IEEE- Interational Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31,2012 222

Designing of FinFET based 5-Stage and 3-Stage

Ring Oscillator High Frequency Generation in
32nm
Lourts Deepak A., Likhitha Dhulipalla, Chaitra S.K., Chand Basha Shaik
Students, M.Sc. in VLSI system design
M. S. Ramaiah School of Advanced Studies, Bangalore, India
E-mail: {lourdu.lourdu.likhitha.ec.chaitrask10.chand.418}@gmail.com
Abstract-In future, as the size of channel length decrease, the
necessity of low power based circuit will be increased. In
nanometer regime, CMOS based circuits may not be used due to
problem in its fundamental material, short channel effect and
high leakage. To achieve low power device in nanometer region
can be obtained by utilizing alternative technologies devices like
FinFET. In most of the electronic circuits, clocks are playing a
critical role to operate the device with the help of oscillatory
circuit and cause the more power dissipation. In this paper, we
designed the 32nm technology 5-stage and 3-stage ring oscillator
to generate high frequencies like 40GHz and 60 GHz respectively
with ultra low power by means of Double Gate FET which is
known as FinFET and result obtained as 39 GHz and 59 GHz
respectively.
Inde Terms-FinFET; Double Gate Field Effect Transistors;
Ring oscillator;
I.
I
NTRODUCTION
R
ing oscillators are the simplest type of oscillator used in
RFIC and electronic circuits. It can be designed for a
fxed fequency and variable fequency operation. Ring
oscillators consists of an odd number of inverters where the
output of the oscillator oscillates between two voltage levels
such as high or low. The inverters are connected in a chain; the
output of the last inverter is fed back into the frst. The ring
oscillator can also be used to measure the effects of voltage
and temperature on a chip.
As the requirement of low power device increases, it's
essential to reduce power dissipation in the ring oscillator,
since it produces more power in the circuit. Low power design
can be achieved by utilizing the alterative solutions instead of
CMOS based design like Double Gate FETs or FinFETs. The
main beneft of the FinFET is good control over leakage
current and suppresses the short channel effects with the help
of another gate which is placed opposite to the traditional gate
and reduces the amount of power dissipation. In this paper, we
modeled FinFET based ring oscillator for 5-stage and 3-stage
to generate the high fequencies like 40 GHz and 60 GHz
respectively. The design calculation for 5-stage and 3-stage
oscillator fequency has been calculated.
In this paper, section II describes about the background
theory of ring oscillator and FinFETs and its mode of
operation. The section III explains about the Inverter design
which is developed using FinFET and section IV explains
about the designing of FinFET based ring oscillator for 5-stage
and 3-stage. Design calculation and Results have been
discussed in section V and VI respectively.
II.
B
ACKGROUND
T
HEORY OF
R
G
O
SCIlLATOR AND
FlNFET's
A. Ring Oscillator (RO):
An oscillator is a device that generates a cyclic signal without
any alterating input signal. It can be expressed as a transfer
fnction of input and output voltages and gain stage as
mentioned in Equation (1).
VOUT/VIN=H(s)/1+H(s)
---------
(1)
If H(s) is -1, then the gain will be infmity amplifcation of
the noise component. For oscillation there are two main
criteria's, frst the total phase shif around the loop should be
180
0
and second criteria is that the feedback system amplifes
its own noise at the fequency of oscillation. These criteria
gives that the returing signal is a negative model of the input
signal, which gives a larger difference between the input signal
and the feedback signal when subtracting. The fndamental
parts of a feedback oscillator are amplifer to amplifing at the
fequency of interest, a resonator- the fequency selective
component, and an output load. The resonator consists of
transformers or other impedance and coupling capacitors. At
initial stage of power supply the supply will not give any
output if the amplifer were noise fee, resonator at the
resonant fequency would be generated. This result will be
applied to the input of amplifer through feedback. The fgure
1 shows the basic feedback ring oscillator system.
ISBN: 978-81-909042-2-3 2012 IEEE
IEEE- Interational Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31,2012 223
VOUI
Figure 1. Ring oscillator circuit with feed back
The amplifed noise resonant fequency frther amplifed at
each and every time and it limits and guarantees the oscillator
output power fnally peaks, generally at the saturated output
power of the amplifer [1]. In following section, will discuss
detailed about the ring oscillator design using FinFET.
Frequency and delay for N stage ring oscillator can be
calculated as:
Freqosc =1/ (2*N*Td) ---------- (2)
Where,
N - No of stages,
Td - Delay of the design circuit in seconds
B. Fin based Field Efect Transistor and its operating
modes:
FinFETs are a non planar double gate transistor built on single
Silicon on Insulator (SOl) substrate. The important
characteristic of the FinFET is that the conducting channel is
enfolding by the thin silicon "fn", which creates the gate of
the device. The thickness of the fn which is measured in the
direction fom source to drain, determines the effective
channel length of the device. The Figure 2 shows the
schematic diagram of a triple gate FINFET device.
Figure 2. Triple gate FinFET based device
Steady miniaturization of transistors with each new
generation of bulk CMOS technology has yielded continual
improvement in the perforance of digital circuits. The
scaling of bulk CMOS, however, faces signifcant challenges
in the fture due to fndamental material and process
technology limits. Primary obstacles to the scaling of bulk
CMOS to deep sub-micron gate lengths include short channel
effects, sub-threshold leakage, gate-dielectric leakage and
device-to-device variations.
It is expected that the use of FinFETs, which provide better
control of short-channel effects, lower leakage and better yield
in aggressively scaled CMOS process, will be required to
overcome these obstacles to scaling. Double-gate devices have
been used in a variety of innovative ways in digital and analog
circuit designs. A parallel transistor pair consists of two
transistors with their source and drain terminals tied together.
In Double-gate (DG) FinFETs, the second gate is added
opposite the traditional (frst) gate, which have been
recognized for their potential to better control short-channel
effects (SCE) and as well as to control leakage current. The
fgure 3 shows the I-V characteristics curve of the double gate
(DGFET's) or FinFET's.
From the above curve we can conclude that linear increment
in current with respect to the input voltage till certain point
which is known as saturation point. The voltage at this point is
known as threshold voltage of the device.
(A) VClTS(j
ll -
,-
I(Fn!)
|J | d | | ` I 0 ` i I ` d
'lULl qV)
Figure 3. I-V Characteristic curve for FinFET 32nm
Four modes of FinFET operation are known as shorted-gate
(SG) mode in which both the gates of transistors tied together,
the independent gate (lG) mode where independent digital
signals are used to drive the two device gates, the low-power
(LP) mode where the back-gate is tied to a reverse-bias voltage
to reduce leakage power and the hybrid (lG/LP) mode, which
employs a combination of LP and IG modes. Here independent
control of font and back gate in DG devices (FinFET) can be
effectively used to improve performance and reduce power
consumption. Independent gate control can be used to merge
parallel transistors (source and drain terminals tied together) in
non-critical paths [2].
III. FIFET
B
ASED
I
NVERTER
D
ESIGN
An inverter is a basic element in electronic devices used to
translate the high input signal to low output signal or low input
signal to high output signal. These inverters are developed
ISBN: 978-81-909042-2-3 20l2 IEEE
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using FinFET based pMOS and nMOS transistors which is
connected in series with each other to share the common input
gate. This inverter is made using short gated mode to improve
the performance. This inverter SPICE code has been
developed and simulated using HSPICE sofware. A FinFET
based inverter offering an extremely good control over short
channel effect compared to CMOS and SOl based inverter.
Vdd
Figure 4. FinFET based Inverter
The inverter is realized by connecting the FinFET based
pMOS nMOS transistors connected serially. By controlling
peak positions of the conductance curve of the FinFET's in the
inverter using another gates situated opposite to FinFET. The
fgure 4 shows the FinFET based inverter schematic diagram.
In the above fgure, the V [ and V __q represent the input and
output of the inverter. V __

GF and GB are the voltages applied

to the power supply terminal and fontlback gate of the two
transistors.
The FinFET based inverter spice code has been developed
and simulated using HSIPCE sofware and result is mentioned
below in fgure 5.
Figure 5. FinFET based Inverter simulation result.
IV.
D
ESIGN OF FTFET BASED 5-ST AGE AND
3
-
S
TAGE
R
G
O
SCILLATOR
FINFET is also known as Multi-gate FET (MuGFET) in which
is an emerging technology for sub-deep micron nodes and it's
receiving consideration as a more scalable alterative to bulk
CMOS. The base of FINFET is Silicon-on-insulator (SOl), the
active silicon flm is etched on the top of SOl which creates
the fns in the isolation layer. The gate oxide has been
developed in both the sidewalls of the silicon fn to make the
double gate FINFET. For Tri-Gate, on the top poly-silicon
material will be deposited and etched to form a strip wrapped
around the silicon fn defning the total MOS channel width.
Using these many advantages of FINFETs in mind, the ring
oscillator has been developed using 32 1 model fle.
Vdd
Ydd Ve
Figure 6. 3-Stage FinFET based Ring oscillator
Ring oscillators have long been used to improve the process
performance, even though it information obtained fom ring
oscillator is limited. It maintains an important evaluation
between process options. The fastest ring oscillator is a
minimally loaded fan out of single inverter. The fgure 6 shows
the schematic diagram of FINFET based 3-stage ring
oscillator, each inverter output is connected to the input as
next inverter and the output of the 3r
d
inverter is feedback to
the input offlfSt inverter to make the oscillation in output [3].
The speed of the inverter has been investigated by
connecting 3 and 5 inverters in series and output of the one
inverter is connected to the next inverter as input. When the
input of the flfSt inverter is driven fom low to high, in which
each signals have been propagated through the chain inverter.
The fgure 6 and 7 shows the result of the 3stage and 5stage
FinFET based ring oscillator circuit respectively.
In an oscillator, the output usually gets shifed by 180

fom
the input. This is due to the presence of phase delay circuit in
the oscillator. These phase shif circuits uses an RC network in
the feedback loop of a tube, transistor, or op-amp to generate
the required phase shif at a particular fequency to sustain
oscillations. They are moderately stable in fequency and
amplitude, and very easy to design and construct. In order to
create and sustain an oscillation at a particular fequency, a
circuit must have a gain higher than unity, and a total
phase shif around the loop of 360 degrees (which is
equivalent to 0 degrees, or positive feedback).
When used with a single-stage inverting amplifcation
element, such as a tube, transistor, or inverting op-amp
confguration, the amplifer itself provides 180 degrees of
phase shif (a gain of -A, where A is the gain of the
amplifcation stage).
ISBN: 978-81-909042-2-3 2012 IEEE
IEEE- Interational Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31,2012 225
Id
Yd I'd Yd I'dd
Figure 7. 5-Stage FinFET based Ring Oscillator
The remaining 180 degrees of phase shif necessary to
provide a total of 360 degrees is provided by an exteral
network of resistors and capacitors. By selecting the
positions of R and C, the phase can be made to lead or
lag the input. An oscillator, the output usually gets shifed by
180
0
fom the input. This is due to the presence of phase delay
circuit in the oscillator. These phase shif circuits uses an RC
network in the feedback loop of a tube, transistor, or op-amp
to generate the required phase shif at a particular fequency to
sustain oscillations. They are moderately stable in fequency
and amplitude, and very easy to design and construct. In order
to create and sustain an oscillation at a particular fequency, a
circuit must have a gain higher than unity, and a total
phase shif around the loop of 360 degrees (which is
equivalent to 0 degrees, or positive feedback).
C1
R2

1 R1
(3) ()
1el
- -
- .
Figure 8. Phase shifer (a) Lead network (b) Lag network
When used with a single-stage inverting amplifcation
element, such as a tube, transistor, or inverting op-amp
confguration, the amplifer itself provides 180 degrees of
phase shif (a gain of -A, where A is the gain of the
amplifcation stage). The remaining 180 degrees of phase
shif necessary to provide a total of 360 degrees is
provided by an exteral network of resistors and capacitors.
The fgure 8 shows the phase shifer diagram for phase
leading and phase lagging circuit. By selecting the positions
of R and C, the phase can be made to lead or lag the
input. For RC phase shif its necessary to identif the value of
the resistor (R) and capacitor (C). Since the impedance is
proportional to the shunt element in the phase shif network 2,
in this case, the resistor, a suitable impedance value must be
chosen before. The input impedance of the network must be
large in comparison to the output impedance of the amplifer,
so as to not load the output appreciably, which would reduce
the gain, possibly to a point where it can no longer sustain
oscillations. A good minimum value is around ten times the
actual output impedance of the amplifcation stage. Since the
input impedance is proportional to the shunt element, and is
approximately twice the value of the shunt element at the
oscillation fequency, the resistance can be chosen to be
around half the required impedance. This resistance will then
determine the value of capacitor necessary to achieve the
desired fequency of oscillation. If output impedance is
assumed to be 10K ohm, a good minimum value for the input
impedance is ten times this value, to prevent loading of the
output stage. Since the resistance value to achieve this
impedance is around half the total impedance, a value of fve
times the output impedance, or 5* lOK = 50K, will work. The
capacitance value is calculated by formula for the fequency of
40 GHz and 60 GHz and tabulated below in table 1.
Table 1. Calculation of Capacitance and Resistance
Freq = 1I21RC Freq = 1I21RC
40G = 1I21* IOK*C 60G = 1I21* IOK*C
C = 4.3 f C = 2.65 f
R = 10K ohm R = 10K ohm
Hence the value of ReSIstor (R) IS gIven as lOK and
calculated value of Capacitor (C) 4.5t and 2.75t for 5stage
and 3stage ring oscillator respectively.
V.
D
ESIGN
C
ALCULATION OF
3
-
S
TAGE A
5
-
S
TAGE
R
G
O
SCIlLATOR
The 5stage and 3stage FinFET based ring oscillator has
been developed, the delay calculation and fequency
calculation has been carried out as per the equation (2) and
mentioned below:
Freqosc
= 1/ (2*N*Td) ------ (2)
A. Frequency calculation for 5stage ring oscillator:
The fequency of oscillator for 5 stages has been calculated as
follows:
No of stages = 5 Stages
Total Delay = Tl + T2 + T3 + T4 + T5
Freqosc
= 0.463+0.483+0.517+0.538+0.560
= 2.561ps
1 / (2 * 5 * 2.561 ps)
1125.61
39GHz
The time delay of each inverter is obtained using the rise
and fall time delay of the each inverter design fom the
simulation result with the help of HSPICE sofware.
ISBN: 978-81-909042-2-3 2012 IEEE
IEEE- Interational Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31,2012 226
B. Frequency calculation for 3stage ring oscillator:
The fequency of oscillator for 3 stages has been calculated as
follows:
No of stages
Total Delay
Freqosc
= 3 Stages
= Tl +T2 +T3
= 0.85 + 0.923+ 1.03
= 2.803 ps
= 1 1(2 * 5 * 2.803 ps)
1/ 16.81
59GHz
The rise time and fall time is used to identif the delay time
of each inverter and it is obtained fom the each inverter
design fom the simulation result with the help of HSPICE
sofware. From this above calculation, with the help of inverter
delay, we obtained 39 GHz and 59 GHz which is nearly
intended fequency 40 GHz and 60 GHz with the help of
5stage and 3stage ring oscillator based on FINFET.
VI.
S
IMULATION
R
ESULTS AND
D
ISCUSSIONS
The spice code for 5stage and 3stage FINFET based ring
oscillator has been developed and simulated using HSPICE
sofware and the simulation result has been placed below. This
simulation has been run through HSPICE simulation tool, to
verif the phase shifing and inversion operation nothing but
oscillation operation.
[ LLtQUt
:1.0
Figure 8. 5-stage FinFET based Ring Oscillator
!
!

t
:
Using this developed spice code, the ring oscillator design
can able to generate the 25 to 30 degree of phase shifing
operation along with its oscillation operations. Other than the
oscillation, with the help of this phase shifing we can make
the delay in the circuit with the help of only one ring oscillator.
The above fgure 8 shows the result of 5stage FINFET based
ring oscillator developed with RC phase shif operation. The
fgure 9 shows the result of the 3stage FINFET based ring
oscillator with RC phase delay operation.
.

.
.
,;, .._'
Figure 9. 3-stage FINFET based Ring Oscillator
VII.
C
ONCLUSION
The FinFET Transistor based ring oscillator circuit to
generate two different high fequencies has been identifed for
5 and 3 different stages in 32nm technology. The delay of each
inverter has been calculated with the help of fall time and rise
time. From these 5 and 3 stages the ring oscillator fequency
has been identifed as 39 GHz and 59 GHz.
FinFET consist of four modes where this paper described
and developed using IG gate mode, since it's faster and
improve the performance of the design. In fture the design
can be developed using any of the other modes of FinFET
operations like IG/LP mode where power plays an important
role.
R
EFERENCES
[ I] J.P. Silver. (2011, September 14
th
) "RF, RFIC and Microwave Theory,
Design-Ring Oscillator Prime". Available: www.rfc.co.uk.
[2] R. V. Joshi, Williams R. Q., Nowak E., Kim K., "FinFET SRAM for
High-Performance Low-Power Applications", in proceedings of 34'h
European Solid State Device Research Conference, Belgium,
September 2004, pp. 69-72.
[3] Mak Kulkarni, Andrew Marshall, Weize Xiong, et, al. (2006,
September), Ring Oscillator Performance and Parasitic Extraction
Simulation in FINFET Technology, IEEE transaction on Solid State
Device, pp. 176-182, September, 2006.
Lourts Oeepak A. was born in Madurai,
Tamilnadu, India, in 1985. Currently He's pursuing
his M.Sc. [Engg.] VLSI System Design in M. S.
Ramaiah School of Advanced Studies, afliated
with Coventry University (UK), Bangalore, India.
He has published 5-International Conference paper
among that, one paper is published in International
Journal and other four are published in IEEE
Proceedings. His current project is dealing with the
development of Hybrid data converters for ultra high frequency based
applications. His current research interests in Nanoelectronics, especially
Carbon Nanotubes (CNTs) based electronics, and Single Electron Transistors
(SET). He is working on development of CNT based analog, mixed signal and
data conversion devices.
He is having 6 years of experience, in which he worked as Senior
Specialist (Integrated Circuit Fabrication) in Global Foundries Pvt. Limited,
Singapore for 3 years. He was even working as a Project head and Junior
Executive - Training and Development in N-Logue Communications Pvt.
Limited, Chennai, which has been run by group of lIT, Madras Professors
Association for 2 years.
ISBN: 978-81-909042-2-3 2012 IEEE
IEEE- Interational Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31,2012 227
Likhitha Dhulipalla was born in Vijayawada, Andhra
Pradesh, India, in 1989. Currently she's doing her
M.Sc. [Engg.] Degree in VLSI System Design in M.
S. Ramaiah School of Advanced Studies, afliated
with Coventry University (UK), Bangalore, India.
She completed her B-Tech in Electronics and
Communication Engineering from Regency Institute
of Technology under Pondicherry University. She
has published 4- International Conference papers, which are publ ished in
IEEE Conference Proceedings. Currently, she is doing her internship in NXP
Semiconductors Pvt. LTD. Her current research interests are in FinFETs,
Carbon Nanotubes (CNTs), and Single Electron Transistors (SET) based
electronics. She is also working on development of CNT based electronic
circuits.
Chaitra S.K. was born Davanagere, Karnataka,
India, in 1987. She has received the B. E. in
Electronics and Communication from G.M.l.T,
Davanagere, affliated by VTU, Karnataka. At
present she is studying M.Sc. [Engg.] Degree in
VLSI System Design in M. S. Ramaiah School of
Advanced Studies, afliated with Coventry
University (UK), Bangalore, India. She has published
3-lnternational Conference paper among that, one paper is published in
International Journal and other 2 published in IEEE international conference.
Currently she is dealing the project titled Design and FPGA Implementation
of Multi-sensor Image Fusion using Wavelet Transform.
Chand Basha Shaik was born in Ongole, Andra Pradesh,
India, in 1989. Currently he's pursuing his M.Sc. [Engg.]
Degree in VLSI System Design in M. S. Ramaiah School
of Advanced Studies, afliated with Coventry University
(UK), Bangalore, India. He has done his B-Tech in
Electronics and Communication Engineering fom
KMCET, afliated by JNTU-Hyderabad, India. He has
published 2-International Conference papers in IEEE. At present he is dealing
with the project titled Design and Implementation of Linear CMOS up
conversion Mixer using I80nm technology for 2.4-2.45GHz fequency based
applications.
ISBN: 978-81-909042-2-3 2012 IEEE