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  • A New Compact SD2 Positive Integer Triangular

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    Sabari Nath V
    6 tayangan2 halaman
    Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems. This paper proposes a novel architecture for a no restoring divisor based on the radix-2 signed-digit (SD2) representation. The proposed divisor architecture is able to achieve a delay of order n, similar to the solution presented by Takagi et al.

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    Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems. This paper proposes a novel architecture for a no restoring divisor based on the radix-2 signed-digit (SD2) representation. The proposed divisor architecture is able to achieve a delay of order n, similar to the solution presented by Takagi et al.

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    6 tayangan2 halaman

    A New Compact SD2 Positive Integer Triangular

    Diunggah oleh

    Sabari Nath V
    Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems. This paper proposes a novel architecture for a no restoring divisor based on the radix-2 signed-digit (SD2) representation. The proposed divisor architecture is able to achieve a delay of order n, similar to the solution presented by Takagi et al.

    Hak Cipta:

    Attribution Non-Commercial (BY-NC)
    Unduh sebagai DOCX, PDF, TXT atau baca online dari Scribd
    Tandai sebagai konten tidak pantas
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    A New Compact SD2 Positive Integer Triangular Array Division Circuit

    Abstract
    Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems; as such drives the demand for efficient hardware division units. Accordingly, this paper proposes a novel architecture for a no restoring divisor based on the radix-2 signed-digit (SD2) representation. This notation has been chosen to achieve fast computation, as proposed by Avizienis (IEEE Transactions on Electronic Computers, vol. EC-10, no.3, pp. 389-400, sep. 1961), but the architecture presented in this paper, due to its structure and the definition of the cell implementing its architecture, saves area as well. The proposed divisor architecture is able to achieve a delay of order n, similar to the solution presented by Takagi et al.(IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, E89-A, no.10,pp.28742881,2006) being considered as the state of the art, instead of other solutions that give o(n2) growth. This is in line with the fact that even if our carry-chains have a less impact on the circuit the basic cell is larger compared to the one proposed by Takagi et al. Our cells are larger that proposed in literature, considering them as single circuit, but considering the overall structure there is a saving of some 40% in the number if gates and a gain of 55% in terms of power saving when compared with the state of the art.

    Name of the candidate: Thara R.S.

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