VLSI Design and Layout Practice Lect5 Stick Diagram & Scalable Design Rules

2012/8/13

IC Layout Concept and Examples

I. II. III.

Stick Diagram Design Rules Layout Verification

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A. Basic Concept

1. Based on the view point of IC layout, the stick diagram can help us understand the circuit function and its geometrical location relative to other circuit blocks.
VDD

Legend: contact metal 2 metal 1 poly ndiff pdiff

in out

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A. Basic Concept

2. Although the stick diagram is an abstract presentation of real layout, it can use graphical symbols or legend to allocate the circuit to 2diomensional plane and reach the aim same as the physical layout does.
3. The stick diagram is similar to a backbone of the real layout but without the real size and aspect ratio of the devices, it still can reflect the real condition to layout of the silicon chip.

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B. Notations of the stick diagram

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Stick Diagram

Intermediate representation between the transistor level and the mask (layout) level. Gives topological information (identifies different layers and their relationship) Assumes that wires have no width. It is possible to translate stick diagram automatically to layout with correct design rules.

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Stick Diagram

1. When the same material (on the same layer) touch or cross, they are connected and belong to the same electrical node.

2. When polysilicon crosses N or P diffusion, an N or P transistor is formed. Polysilicon is drawn on top of diffusion. Diffusion must be drawn connecting the source and the drain. Gate is automatically self-aligned during fabrication.

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Stick Diagram
3. When a metal line needs to be connected to one of the other three conductors, a contact cut (via) is required.

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Stick Diagram

4. Manhattan geometrical rule: When we use only vertical and horizontal lines In orthogonal to describe circuitry. Boston geometrical rule: The stick diagram also allows curves to describe circuitry. 5. In order to describe N/PMOS more completely, to add n-wellP+ selectwell contact and substrate contact are
optional for 4-terminal notation.

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Conclusion

1. Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and layout. 2. Stick diagram uses different lines, colors and geometrical shapes to present circuit nodes, devices, and their relative location. 3. Stick diagram doesnt include information about the accurate coordinates and sizes of device, the length and width of conductors and the real size of well region.
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CMOS Inverter Stick Diagrams

Basic layout

More area efficient layout

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CMOS Inverter Stick Diagrams

CMOS inverter described in other way.

VDD

in

out

VSS

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CMOS Transmission Gate

The transmission gate Circuit schematic Stick diagram

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CMOS Stick Diagrams

NAND/NOR

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CMOS Stick Diagrams

NAND

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< Exercise 1 >

To draw the following circuitry by using a stick diagram

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< Exercise 2 >

To draw the stick diagram and the schematic for the following layout
NWELL NSELECT PSELECT POLY ACTIVE METAL1

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CMOS Stick Diagrams

NOR

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CMOS Inverter Mask Layout

Min. spacing and line width consideration

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Lambda-based Design Rules Lambda design rules are based on a reference metric that has units of um. All widths, spacing and distances are written in the form Value = m Where m is scaling multiplier. <e.g.> = 1um w = 2 =2um s = 3=3um

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Lambda-based Design Rules

Lambda based design: half of technology since 1985. As technology changes with smaller dimensions, a simple change in the value of can be used to produce a new mask set.

3
6 6

All device mask dimensions are based on multiples of , e.g., polysilicon minimum width = 2. Minimum metal to metal spacing = 3
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Active Contact and Surround Rule

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Potential Problem - Misalignment

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Potential Problem Short between Source and Drain

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Design Rule (0)

Due to the photo resolution, concentration, temperature and reaction time of the chemical reagents, the layout should tolerate some errors caused by process environment. In order to avoid the influence from process variation, the layout of the circuit schematics should follow the design Rule

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The purpose of design rules

Ref. Jan M. Rabaey, et. al, Digital Integrated Circuits 2nd Edition Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width

scalable design rules: lambda parameter absolute dimensions (micron rules)

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Design Rules(1)

Layout rules are used for preparing the masks for fabrication. Fabrication processes have inherent limitations in accuracy. Design rules specify geometry of masks to optimize yield and reliability (trade-offs: area, yield, reliability). Three major rules: Wire width: Minimum dimension associated with a given feature. Wire separation: Allowable separation. Contact: overlap rules.

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Design Rules(2)

Two major approaches: Micron rules: stated at micron resolution. rules: simplified micron rules with limited scaling attributes. may be viewed as the size of minimum feature. Design rules represents a tolerance which insures very high probability of correct fabrication (not a hard boundary between correct and incorrect fabrication). Design rules are determined by experience.
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Terminology & Definition

Min. Width : The min. width of the line (layer) <Example> Wpoly(min.) = 0.5um

Min. Space : The min. spacing between lines with same material <Example> Spoly-poly(min.) = 0.5um

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Terminology & Definition

<Min. Extension : The min. extension over different layers <Example> Poly-gate extension over diffusion area = 0.55um

Min. Overlap : The overlap between different layers <Example> Poly1 overlap Poly2 min. = 0.7um

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Terminology & Definition

Max. area of the specific region. <Example> Bonding Pad Area, max. = 100um x 100um

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Conventional Layer Definition

Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

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SCMOS Design Rules

Intra-Layer Design Rules
Same Potential Well 10 Active 3 2 Select 3 Contact or Via Hole 2 2 Metal1 3 0 or 6 Different Potential 9 Polysilicon 2 3 2

Metal2 3

Ref. Jan M. Rabaey, et. al, Digital Integrated Circuits 2nd Edition

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SCMOS Design Rules

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

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SCMOS Design Rules

2 3 1 3 3 2 Select

Substrate

Well

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SCMOS Design Rules

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MOSIS Layout Design Rules

MOSIS design rules (SCMOS rules) are available at http://www.mosis.org. 3 basic design rules: Wire width Wire separation Contact rule

MOSIS design rule examples

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III. Layout Verification

A. Definition DRC Design Rule Check ERC Electrical Rule Check LVS Layout Versus Schematic LPE Layout Parameter Extraction

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Layout Verification

B. DRC(Design Rule Check) => To check the min. line width and spacing based on the design rules. C. ERC(Electrical Rule Check) => To check the short circuit between Power and Ground, or check the floating node or devices.
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Layout Verification

D. LVS(Layout versus Schematic) => To verify the consistency between Schematic and Layout. For exampleto check the amount of transistor numbers, sizes of W/L.

E. LPE or PEX(Layout Parameter Extraction) => From the database of layout, to extract the
devices with parasitics including effective W/L, parasitic capacitances and series resistance. The extracted file is in SPICE format and can be used for Post-Layout Simulation

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Layout Verification
F. Simulations Pre-Layout Simulation - before layout work Post-Layout Simulation after layout work, post layout simulation will reflect more realistic circuit performance.

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Layout Verification
The complete design environment of Fill-Custom Design
Design database Cadence Design Framework II Circuit Editor Text editor/Schematic editor (S-edit, Composer) Circuit Simulator SPICE,TSPICE, HSPICE Layout Editor Cadence Virtuoso, Laker, L-edit Layout Verification Diva, Dracula, Calibre, Hercules

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Concluding Remarks

Milestones technology in silicon era Transistor Integrated Circuits CMOS Technology Key weapons in SOC era Design Automation Design Reuse Breakthrough techniques in design automation Simulation (e.g., SPICE, Verilog-XL, etc.) Automatic Placement and Routing (APR) Logic Synthesis (e.g., Design Compiler) Formal Verification Test Pattern Generation

It is EDA that pushes the IC design technology forward !

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Design rules and Layout

Why we use design rules?

Interface between designer and process engineer Guidelines for constructing process masks

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Design Rules
Minimum length or width of a feature on a layer is 2

Why? To allow for shape contraction

Minimum separation of features on a layer is 2

Why?
To ensure adequate continuity of the intervening

materials.
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Design Rules
Minimum width of PolySi and diffusion line 2 Minimum width of Metal line 3 as metal lines run over a more uneven surface than other conducting layers to ensure their continuity

Metal Diffusion

3 2
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Polysilicon

Design Rules
PolySi PolySi space 2 Metal - Metal space 2 Diffusion Diffusion 3 To avoid the possibility of their associated regions overlapping and conducting current

Metal 2 Diffusion

2
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Polysilicon

Design Rules
Diffusion PolySi To prevent the lines overlapping to form unwanted capacitor Metal lines can pass over both diffusion and polySi without electrical effect. Where no separation is specified, metal lines can overlap or cross

Metal Diffusion

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Polysilicon

Metal Vs PolySi/Diffusion

Metal lines can pass over both diffusion and polySi without electrical effect It is recommended practice to leave between a metal edge and a polySi or diffusion line to which it is not electrically connected
Metal Polysilicon
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Review:
poly-poly spacing

diff-diff spacing 3 (depletion regions tend to spread outward) metal-metal spacing 2

diff-poly spacing

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Note
Two Features on different mask layers can be misaligned by a maximum of 2 on the wafer. If the overlap of these two different mask layers can be catastrophic to the design, they must be separated by at least 2 If the overlap is just undesirable, they must be separated by at least

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When a transistor is formed?

Gate is formed where polySi crosses diffusion with thin oxide between these layers.
Design rules
min. line width of polySi and diffusion 2
drain and source have min. length and width of 2 And

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PolySi extends in the gate region

The polySi of the gate extends 2 beyond the gate area on
to the field oxide to prevent the drain and source from shorting.

diffusion short

Diffusion Problems
no overlap
overlap

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Depletion Transistor
We need depletion implant

An implant surrounding the Transistor by 2

Ensures that no part of the transistor remains in the enhancement mode

A separation of 2 from the gate of an

enhancement transistor avoids affecting the device.

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Depletion Transistor
Implants are separated by 2 to prevent them from merging

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Butting Contact
The gate and source of a depletion device can be connected by a method known as butting contact. Here metal makes contact to both the diffusion forming the source of the depletion transistor and to the polySi forming this devices gate.

Advantage:
No buried contact mask required and avoids
associated processing.
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Butting Contact
Problem: Metal descending the hole has a tendency to fracture at the polySi corner, causing an open circuit. Metal Insulating Oxide
n+ n+

Gate Oxide
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PolySi

Buried Contact
It is a preferred method. The buried contact window defines the area where oxide is to be removed so that polySi connects directly to diffusion.

Contact Area must be a min. of 2*2 to ensure adequate contact area.

Contact Area
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Buried Contact
The buried contact window surrounds this contact by in all directions to avoid any part of this area forming a transistor. Separated from its related transistor gate by to prevent gate

area from being reduced.

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Buried Contact
Here gate length is depend upon the alignment of the buried contact mask relative to the polySi and therefore vary by .

PolySi
2 Channel length

Buried contact

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Contact Cut
Metal connects to polySi/diffusion by contact cut. Contact area: 2*2 Metal and polySi or diffusion must overlap this contact area by so that the two desired conductors encompass the contact area despite any mis-alignment between conducting layers and the contact hole

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Contact Cut apart Contact cut any gate: 2

Why? No contact to any part of the gate. 4
2

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Contact Cut
Contact cut contact cut: 2 apart Why? To prevent holes from merging.

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Rules for CMOS layout

Similar to those for NMOS except No 1. Depletion implant 2. Buried contact

Additional rules
1. Definition of n-well area 2. Threshold implant of two types of transistor

3. Definition of source and drains regions for the NMOS and PMOS.
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Rules for CMOS layout

To ensure the separation of the PMOS and NMOS devices,
n-well supporting PMOS is 6 away from the active area of NMOS transistor.

Why? Avoids overlap of the associated regions

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n+

n-well

Rules for CMOS layout

2
N-well must completely surround the PMOS devices active area by 2

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Rules for CMOS layout

2
The threshold implant mask covers all n-well and surrounds the n-well by

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Rules for CMOS layout

The p+ diffusion mask defines the areas to receive a p+ diffusion. It is coincident with the threshold mask surrounding the PMOS transistor but excludes the n-well region to be connected to the supply.

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Rules for CMOS layout

A p+ diffusion is required to effect the ground connection to the substrate. Thus mask also defines this substrate region. It surrounds the conducting material of this contact by .

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Rules for CMOS layout

Total contact area = 2*4 Neither NMOS nor CMOS usually allow contact cuts to the gate of a transistor, because of the danger of etching away part of the gate

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