EXPERIMENT NO.

3
Aim:
To implement VHDL code for 2:1,4:1and 8:1 Multuplexer.

Tool Required:
a) Mentor Graphics FPGA advantage 8.1 Model Sim 6.3a

Theory:
MULTIPLEXER: In electronics, a multiplexer or mux is a device that selects one of several analogor digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.

a) 2:1 multiplexer A 2:1 multiplexer consists of 2 inputs , 1 selection line and 1 output.

Fig.(3.1) Truth table for 2:1 mux:

Selection Output line S0 Y 0 A 1 B Table (3.1) Logic Equation Y= A.S0+B.S0 b) 4:1 multiplexer A 4:1 multiplexer consists of 4 inputs,2 selection lines and 1 output.

.(3.2)

Truth Table: S0 S1 0 0 0 1 1 0 1 1 Y A B C D Table(3.2) Logic Equation: Y= A.S0.S1+B.S0.S1+C.S0.S1+D.S0.S1 c) 8:1 multiplexer A 8:1 multiplexer consists of 8 inputs,3 selection lines and 1 output. Truth table: S0 S1 S2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Y A B C D E F G H

Table(3.3)

Logic Equation Y=A.S0.S1.S2+B.S0.S1.S2+C.S0.S1.S2+D.S0.S1.S2+E.S0.S1.S2+F.S0.S1.S2+G.S0.S1. S2+H.S0.S1.S2

VHDL code for 2:1 mux

Using data flow modelling

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY mux IS port(i0,i1,s0:in std_logic; y:out std_logic); END ENTITY mux;

-ARCHITECTURE mux_data OF mux IS BEGIN y<= (i0 and(not s0)) or ( i1 and s0); END ARCHITECTURE mux_data;

Using behavioural modelling

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY mux IS port(i0,i1,s0:in std_logic; y:out std_logic); END ENTITY mux; ARCHITECTURE mux_beh OF mux IS

begin process(i0,i1,s0) variable v1,v2:std_logic; begin v1:= (not(s0)and i0); v2:=i1 and s0; y<=v1 or v2; end process; END ARCHITECTURE mux_beh;

Using structural modelling

library ieee; use ieee.std_logic_1164.all; entity Mux_2_to_1 is port( D0, D1, S : in std_logic; F : out std_logic); end Mux_2_to_1; -architecture Func of Mux_2_to_1 is component andGate is port( A, B : in std_logic; F : out std_logic); end component; component orGate is port(A, B : in std_logic; F : out std_logic); end component;

component notGate is port( inPort : in std_logic; outPort : out std_logic); end component;

signal andOut1, andOut2, invOut: std_logic; begin G1: notGate port map(S, invOut); G2: andGate port map(invOut, D0, andOut1); G3: andGate port map(S, D1, andOut2); G4: orGate port map(andOut1, andOut2, F); -- F end Func;

Output:

Result window of 2:1 multiplexer

VHDL code for 4:1 mux Using data flow modelling

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY mux IS port(i0,i1,i2,i3,s0,s1:in std_logic; y:out std_logic); END ENTITY mux; ARCHITECTURE mux_data OF mux IS BEGIN y<= ((i0 and not(s0)and not(s1))or (i1 and not (s0) and s1) or ( i2 and s0 and not(s1)) or (i3 and s0 and s1)); END ARCHITECTURE mux_data;

Using behavioural modelling

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY mux IS port(i0,i1,i2,i3,s0,s1:in std_logic; y:out std_logic); END ENTITY mux;

ARCHITECTURE mux_beh OF mux IS begin process(i0,i1,i2,i3,s0,s1) variable v1,v2,v3,v4:std_logic; begin v1:= (not (s0) and not(s1) and i0); v2:=(not(so) and s1and s1); v3:=(so and not(s1) and i2); v4:=(s0 and s1 amd i3); y<=v1 or v2 or v3 or v4; end process; END ARCHITECTURE mux_beh;

Using if statement

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY mux IS port(i0,i1,i2,i3,s0,s1:in std_logic; y:out std_logic); END ENTITY mux; ARCHITECTURE mux_beh OF mux IS BEGIN process(i0,i1,i2,i3,s0,s1) begin

if(so='0' and s1='0')then y<=i0; elsif(s0='0' and s1='1')then y<=i1; elsif(s0='1' and s1='0')then y<=i2; elsif(s0='1' and s1='1')then y<=i3; end if; end process; END ARCHITECTURE mux_beh;

OUTPUT :

Result window of 4:1 multiplexer

VHDL code for 8:1 mux Using data flow modelling

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY mux is port(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2:in std_logic; y:out std_logic); END ENTITY mux;

-ARCHITECTURE mux_data OF mux IS BEGIN y<=((i0 and not(s0)and not(s1) and not(s2)) or (i1 and not(s0) and not(s1) and s2) or (i3 and not(s0) and s1 and s2) or (i4 and s0 and not(s1) and not(s2))or(i5 and s0 and not(s1) and s2)or (i6 and s0 and s1 and not(s2))or (i7 and s0 and s1 and s2));

END ARCHITECTURE mux_data;

Using behavioural modelling

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY mux IS port(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2:in std_logic; y:out std_logic); END ENTITY mux;

-ARCHITECTURE mux_beh OF mux IS begin process(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2) variable v1,v2,v3,v4,v5,v6,v7,v8:std_logic; begin v1:= (not(s0)and not(s1)and not(s2)and i0); v2:=(not(s0)and not(s1) and s2 and i1); v3:=(not(s0) and s1 and not(s0) and i2); v4:=(not(s0) and s1 and s2 and i3); v5:=(s0 and not(s1) and not(s2) and i4); v6:=(s0 and not(s1) nad s2 and i5); v7:=(s0 and s1 and not(s2) and i6); v8:=(s0 and s1 and s2 and i7); y<=v1 or v2 or v3 or v4 or v5 or v6 or v7or v8; end process; END ARCHITECTURE mux_beh;

OUTPUT

Result window of 8:1 multiplexer

Result: The vhdl code for 2:1, 4:1 and 8:1 multiplexer were simulated and tested