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module mod10_tb();

reg clk,rst;
wire [3:0]cnt1,cnt2;
s
mod10_rtl m1(.clk(clk),.rst(rst),.q(cnt1));
mod10_beh m2(.clk(clk),.rst(rst),.cnt(cnt2));
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
rst =1'b0;
#20 rst=1'b1;
#20 rst=1'b0;
end
always@(*)
begin
if(cn1==cn2)
$display("Success\n");
else
$display("Error Incurred\n");
end
endmodule

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