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`include "pattern_d.

v"
`timescale 1ns/100ps
module pattern_d_tb;
reg reset_n;
reg clk;
reg in;
wire out;
wire [1:0]state;
pattern_d a1
(reset_n,
out,
in,
state,
clk );
always
#10 clk=~clk;
initial
begin
reset_n=0;
clk=0;
in=1;
#5
reset_n=1;
in=0;
#20
reset_n=1;
in=1;
#20
reset_n=1;
in=1;
#20
reset_n=1;
in=0;
#20
reset_n=1;
in=1;
#20
reset_n=1;
in=1;
#20
reset_n=1;
in=0;
#20
$stop;
$finish;
end
endmodule

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