module reg_siso (data, data_next, data_in, shift, reset_n, clk, data_out ); input input input input clk; reset_n;

shift; data_in;

output [3:0]data; output [3:0]data_next; output data_out; wire [3:0]data_next; reg [3:0]data; reg data_out; assign data_next=data>>1; always@(posedge clk or negedge reset_n) begin if(reset_n==0) data<=4'b0; else if (shift==1) begin data<=({data_in,data_next[2:0]}); data_out<=data[0]; end else data<=data; end endmodule