`define

`define
`define
`define
`define
`define
`define
`define

s0
s1
s2
s3
s4
s5
s6
s7

3'd0
3'd1
3'd2
3'd3
3'd4
3'd5
3'd6
3'd7

`define
`define
`define
`define

time_div 4'd0001
load_cnt1 9'd44
load_cnt2 8'd24
load_cnt3 6'd4

module traffic (clk,

reset_n,
MG1,
MG2,
MY1,
MY2,
MR1,
MR2,
SG1,
SG2,
SY1,
SY2,
SR1,
SR2,
MRT1,
MRT2,
SRT1,
SRT2);
input clk;
input reset_n;
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
reg
reg
reg
reg
reg

MG1;
MG2;
MY1;
MY2;
MR1;
MR2;
SG1;
SG2;
SY1;
SY2;
SR1;
SR2;
MRT1;
MRT2;
SRT1;
SRT2;

MG1;
MG2;
MY1;
MY2;
MR1;

reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
wire
wire
wire
wire

MR2;
SG1;
SG2;
SY1;
SY2;
SR1;
SR2;
MRT1;
MRT2;
SRT1;
SRT2;
[3:0]cnt_next;
[8:0]cnt1_next;
[7:0]cnt2_next;
[5:0]cnt3_next;

reg timer1;
reg timer2;
reg timer3;
reg
reg
reg
reg

[3:0]cnt;
[8:0]cnt1;
[7:0]cnt2;
[5:0]cnt3;

wire adv_cnt1;
wire adv_cnt2;
wire adv_cnt3;
wire res_cnt1;
wire res_cnt2;
wire res_cnt3;
reg [2:0] state;
assign cnt_next=cnt+1;
always@(posedge clk or negedge reset_n)
begin
if(reset_n==0)
cnt<=4'd0;
else if(cnt==`time_div)
cnt<=4'd0;
else
cnt<=cnt_next;
end
assign cnt1_next=cnt1+1;
assign adv_cnt1=(timer1==1)&(cnt==`time_div);
assign res_cnt1=(cnt1==`load_cnt1)&(cnt==`time_div);
always@(posedge clk or negedge reset_n)
begin
if(reset_n==0)
cnt1<=9'd0;
else if(res_cnt1==1)
cnt1<=9'd0;
else if (adv_cnt1==1)
cnt1<=cnt1_next;
else

cnt1<=cnt1;
end
assign cnt2_next=cnt2+1;
assign adv_cnt2=(timer2==1)&(cnt==`time_div);
assign res_cnt2=(cnt2==`load_cnt2)&(cnt==`time_div);
always@(posedge clk or negedge reset_n)
begin
if(reset_n==0)
cnt2<=8'd0;
else if(res_cnt2==1)
cnt2<=8'd0;
else if (adv_cnt2==1)
cnt2<=cnt2_next;
else
cnt2<=cnt2;
end
assign cnt3_next=cnt3+1;
assign adv_cnt3=(timer3==1)&(cnt==`time_div);
assign res_cnt3=(cnt3==`load_cnt3)&(cnt==`time_div);
always@(posedge clk or negedge reset_n)
begin
if(reset_n==0)
cnt3<=6'd0;
else if(res_cnt3==1)
cnt3<=6'd0;
else if (adv_cnt3==1)
cnt3<=cnt3_next;
else
cnt3<=cnt3;
end
always@(posedge clk or negedge reset_n)
begin
if(reset_n==0)
begin
MG1<=0;
MG2<=0;
MY1<=0;
MY2<=0;
MR1<=0;
MR2<=0;
SG1<=0;
SG2<=0;
SY1<=0;
SY2<=0;
SR1<=0;
SR2<=0;
MRT1<=0;
MRT2<=0;
SRT1<=0;
SRT2<=0;
timer1<=0;
timer2<=0;
timer3<=0;

state<=`s0;
end
else
case(state)
`s0:
begin
MG1<=1;
MG2<=1;
SR1<=1;
SR2<=1;
MY1<=0;
MY2<=0;
MR1<=0;
MR2<=0;
SG1<=0;
SG2<=0;
SY1<=0;
SY2<=0;
MRT1<=0;
MRT2<=0;
SRT1<=0;
SRT2<=0;
if(res_cnt1==1)
begin
state<=`s1;
timer1<=0;
end
else
begin
state<=`s0;
timer1<=1'b1;
end
end
`s1:
begin
MY1<=1;
MY2<=1;
SR1<=1;
SR2<=1;
MG1<=0;
MG2<=0;
MR1<=0;
MR2<=0;
SG1<=0;
SG2<=0;
SY1<=0;
SY2<=0;
MRT1<=0;
MRT2<=0;
SRT1<=0;
SRT2<=0;
if(res_cnt3==1)
begin

state<=`s2;
timer3<=1'b0;
end
else
begin
state<=`s1;
timer3<=1'b1;
end
end
`s2:
begin
MRT1<=1;
MRT2<=1;
MR1<=1;
MR2<=1;
SR1<=1;
SR2<=1;
MY1<=0;
MY2<=0;
MG1<=0;
MG2<=0;
SG1<=0;
SG2<=0;
SY1<=0;
SY2<=0;
SRT1<=0;
SRT2<=0;
if(res_cnt2==1)
begin
state<=`s3;
timer2<=1'b0;
end
else
begin
state<=`s2;
timer2<=1'b1;
end
end
`s3:
begin
MR1<=1;
MR2<=1;
MY1<=1;
MY2<=1;
MRT1<=0;
MRT2<=0;
SR1<=0;
SR2<=0;
MG1<=0;
MG2<=0;
SG1<=0;
SG2<=0;
SY1<=0;
SY2<=0;

SRT1<=0;
SRT2<=0;
if(res_cnt3==1)
begin
state<=`s4;
timer3<=1'b0;
end
else
begin
state<=`s3;
timer3<=1'b1;
end
end
`s4:
begin
SG1<=1;
SG2<=1;
MR1<=1;
MR2<=1;
MRT1<=0;
MRT2<=0;
MY1<=0;
MY2<=0;
SR1<=0;
SR2<=0;
MG1<=0;
MG2<=0;
SY1<=0;
SY2<=0;
SRT1<=0;
SRT2<=0;
if(res_cnt2==1)
begin
state<=`s5;
timer2<=1'b0;
end
else
begin
state<=`s4;
timer2<=1'b1;
end
end
`s5:
begin
MR1<=1;
MR2<=1;
SY1<=1;
SY2<=1;
SG1<=0;
SG2<=0;
MRT1<=0;
MRT2<=0;
MY1<=0;

MY2<=0;
SR1<=0;
SR2<=0;
MG1<=0;
MG2<=0;
SRT1<=0;
SRT2<=0;
if(res_cnt3==1)
begin
state<=`s6;
timer3<=1'b0;
end
else
begin
state<=`s5;
timer3<=1'b1;
end
end
`s6:
begin
SRT1<=1;
SRT2<=1;
MR1<=1;
MR2<=1;
SR1<=1;
SR2<=1;
SY1<=0;
SY2<=0;
SG1<=0;
SG2<=0;
MRT1<=0;
MRT2<=0;
MY1<=0;
MY2<=0;
MG1<=0;
MG2<=0;
if(res_cnt2==1)
begin
state<=`s7;
timer2<=1'b0;
end
else
begin
state<=`s6;
timer2<=1'b1;
end
end
`s7:
begin
SY1<=1;
SY2<=1;
SR1<=1;

SR2<=1;
MR1<=1;
MR2<=1;
SG1<=0;
SG2<=0;
MRT1<=0;
MRT2<=0;
MY1<=0;
MY2<=0;
MG1<=0;
MG2<=0;
SRT1<=0;
SRT2<=0;
if(res_cnt3==1)
begin
state<=`s0;
timer3<=1'b0;
end
else
begin
state<=`s7;
timer3<=1'b1;
end
end
endcase
end
endmodule