ECE 448 Lecture 9

FSM Examples: Serial Adder, The Arbiter Circuit

ECE 448 FPGA and ASIC Design with VHDL

George Mason University

Required reading
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 8, Synchronous Sequential Circuits Sections 8.5, 8.8

ECE 448 FPGA and ASIC Design with VHDL

Optional Reading
Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 6, Finite State Machines

ECE 448 FPGA and ASIC Design with VHDL

Mixing Design Styles within a Single Architecture

ECE 448 FPGA and ASIC Design with VHDL

Mixed Style Modeling

architecture ARCHITECTURE_NAME of ENTITY_NAME is Here you can declare signals, constants, functions, procedures Component declarations

begin Concurrent statements: Concurrent simple signal assignment Conditional signal assignment Selected signal assignment Generate statement Component instantiation statement Process statement
inside process you can use only sequential statements

Concurrent Statements

end ARCHITECTURE_NAME;

ECE 448 FPGA and ASIC Design with VHDL

Serial Adder

ECE 448 FPGA and ASIC Design with VHDL

Serial Adder block diagram

A a Shift register Adder FSM Shift register b Sum = A + B B Clock s Shift register

ECE 448 FPGA and ASIC Design with VHDL

Serial adder FSM Mealy state diagram

Reset
ab s

11 0 00 0 01 1 10 1 01 0 10 0 11 1

G 00 1 G: carry-in = 0 H: carry-in = 1

ECE 448 FPGA and ASIC Design with VHDL

Left-to-right Shift Register (1)

LIBRARY ieee ; USE ieee.std_logic_1164.all ; -- left-to-right shift register with parallel load and enable ENTITY shiftrne IS GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftrne ;

ECE 448 FPGA and ASIC Design with VHDL

Left-to-right Shift Register (2)

ARCHITECTURE Behavior OF shiftrne IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF E = '1' THEN IF L = '1' THEN Q <= R ; ELSE Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= w ; END IF ; END IF ; END PROCESS ; END Behavior ;
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Serial Adder Entity declaration

1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY serial IS 4 GENERIC ( length : INTEGER := 8 ) ; 5 PORT ( Clock : IN STD_LOGIC ; 6 Reset : IN STD_LOGIC ; 7 A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; 8 Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0)); 9 END serial ;

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder Architecture (2)

10 ARCHITECTURE Behavior OF serial IS 11 12 13 14 15 16 17 COMPONENT shiftrne GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ;

18 SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; 19 SIGNAL s, Low, High, Run : STD_LOGIC ;

20 SIGNAL Count : INTEGER RANGE 0 TO length ;

21 TYPE State_type IS (G, H) ; 22 SIGNAL y : State_type ;

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder Architecture (3)

23
24 25 26 27 28

BEGIN
Low <= '0' ; High <= '1' ; ShiftA: shiftrne GENERIC MAP (N => length) PORT MAP ( A, Reset, High, Low, Clock, QA ) ; ShiftB: shiftrne GENERIC MAP (N => length) PORT MAP ( B, Reset, High, Low, Clock, QB ) ;

ECE 448 FPGA and ASIC Design with VHDL

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Serial adder FSM Mealy state diagram

Reset
ab s

11 0 00 0 01 1 10 1 01 0 10 0 11 1

G 00 1 G: carry-in = 0 H: carry-in = 1

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder Architecture (4)

29 AdderFSM: PROCESS ( Reset, Clock ) 30 BEGIN 31 IF Reset = '1' THEN 32 y <= G ; 33 ELSIF Clock'EVENT AND Clock = '1' THEN 34 CASE y IS 35 WHEN G => 36 IF QA(0) = '1' AND QB(0) = '1' THEN y <= H ; 37 ELSE y <= G ; 38 END IF ; 39 WHEN H => 40 IF QA(0) = '0' AND QB(0) = '0' THEN y <= G ; 41 ELSE y <= H ; 42 END IF ; 43 END CASE ; 44 END IF ; 45 END PROCESS AdderFSM ;

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder Architecture (5)

46 WITH y SELECT 47 s <= QA(0) XOR QB(0) WHEN G, 48 NOT ( QA(0) XOR QB(0) ) WHEN H ; 49 Null_in <= (OTHERS => '0') ; 50 ShiftSum: shiftrne GENERIC MAP ( N => length ) 51 PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ;

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder Architecture (5)

52 Stop: PROCESS 53 BEGIN 54 WAIT UNTIL (Clock'EVENT AND Clock = '1') ; 55 IF Reset = '1' THEN 56 Count <= length ; 57 ELSIF Run = '1' THEN 58 Count <= Count -1 ; 59 END IF ; 60 END PROCESS ; 61 Run <= '0' WHEN Count = 0 ELSE '1' ; -- stops counter and ShiftSum

62 END Behavior ;

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Serial adder FSM Mealy state diagram

Reset
ab s

11 0 00 0 01 1 10 1 01 0 10 0 11 1

G 00 1 G: carry-in = 0 H: carry-in = 1

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder FSM Mealy state table

Present state

Next state ab =00 01 10 11 00

Output s 01 10 11

G H

G G

G H

G H

H H

0 1

1 0

1 0

0 1

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Serial Adder FSM Mealy state-assigned table

Present state y 0 1

Next state ab =00 01 Y 0 0 0 1 0 1 1 1 0 1 10 11 00

Output 01 s 1 0 1 0 0 1 10 11

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder - Mealy FSM Circuit

a b

s Full adder Y carry-out Clock D Q y

Reset

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder FSM Moore state diagram

Reset

00

G0 s = 0 00 00

11

H0 s = 0

01 10

01 10

11

11

01 10

01 10

G1 s = 1

00

H1 s = 1

11

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder FSM Moore state table

Present state

Nextstate

ab =00 G0 G0 G1 G1

01 G1 G1 H0 H0

10 G1 G1 H0 H0

11 H0 H0 H1 H1

Output s

G0 G1 H0 H1

0 1 0 1

ECE 448 FPGA and ASIC Design with VHDL

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Serial Adder FSM Moore state-assigned table

Present state G0 G1 H0 H1

Nextstate ab =00 G0 G0 G1 G1 01 G1 G1 H0 H0 10 G1 G1 H0 H0 11 H0 H0 H1 H1

Output s 0 1 0 1

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Serial Adder FSM Circuit

Sum bit a b Full adder Carry-out Y1 D Q Q y1 s

Y2

Q Q

y2

Clock Reset

ECE 448 FPGA and ASIC Design with VHDL

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The Arbiter Circuit

ECE 448 FPGA and ASIC Design with VHDL

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The Arbiter Circuit

reset

r1 r2 r3

g1

Arbiter

g2 g3

clock
ECE 448 FPGA and ASIC Design with VHDL 27

The Arbiter Circuit Moore state diagram

Reset Idle 0xx 1xx 000

gnt1g1 = 1 x0x
1xx gnt2g2 = 1 xx0 x1x gnt3g3 = 1 xx1
ECE 448 FPGA and ASIC Design with VHDL 28

01x

001

The Arbiter Circuit Alternative description

Reset Idle r1 r1 r 1r 2 r 3

gnt1g1 = 1
r2 r1 gnt2g2 = 1 r3 r2 gnt3g3 = 1 r3
ECE 448 FPGA and ASIC Design with VHDL 29

r 1r 2

r 1r 2 r 3

Incorrect VHDL code for the grant signals

. . . PROCESS( y ) BEGIN IF y = gnt1 THEN g(1) <= '1' ; ELSIF y = gnt2 THEN g(2) <= '1' ; ELSIF y = gnt3 THEN g(3) <= '1' ; END IF ; END PROCESS ; END Behavior ;

ECE 448 FPGA and ASIC Design with VHDL

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Correct VHDL code for the grant signals

. . . PROCESS( y ) BEGIN g(1) <= '0' ; g(2) <= '0' ; g(3) <= '0' ; IF y = gnt1 THEN g(1) <= '1' ; ELSIF y = gnt2 THEN g(2) <= '1' ; ELSIF y = gnt3 THEN g(3) <= '1' ; END IF ; END PROCESS ; END Behavior ;
ECE 448 FPGA and ASIC Design with VHDL 31

Simulation results for the Arbiter Circuit

ECE 448 FPGA and ASIC Design with VHDL

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