Dept. of Electronics and Communications Engg. CITY ENGINEERING COLLEGE BANGALORE 61.
Manual Prepared by: Mrs. Shalini Prasad, Sr. Lecturer, CEC Mr. Vishvakiran RC, Lecturer, CEC
2011
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TABLE OF CONTENTS
Experiments
IC Pin Configurations 1. 2. 3. Boolean Expression realization using Logic gates Half/Full Adder and Subtractor a. Parallel Adder/ Subtractor b. BCD to Excess-3 and Vice-versa 4. 5. 6. 7. 8. 9. Binary to Gray Conversion and vice versa MUX/DEMUX for arithmetic circuits Comparators Decoder Chip for LED Display Priority Encoder Flip-Flop verification
Page No.
2 4 7 10 14 16 21 27 31 33 35 38 50 55 57 59 60
10. Counters 11. Shift Registers 12. Ring Counter/ Johnson Counter 13. Sequence Generator Logic Design Lab Syllabus 10ESL38 Possible Viva Questions
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IC Pin configurations
Inverter (NOT Gate) - 7404LS 2-Input AND Gate - 7408LS
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Decoders/Demultiplexer 74139
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Experiment No. 1
Components Required: -
IC 7408 (AND), IC 7404 (NOT), IC 7432 (OR),IC 7400 (NAND), IC 7402 (NOR),IC 7486 (EX-OR)
Procedure
1. Verify that the gates are working. 2. Construct a truth table for the given problem. 3. Draw a Karnaugh Map corresponding to the given truth table. 4. Simplify the given Boolean expression manually using the Karnaugh Map.
A: Implementation Using Logic Gates 5. Realize the simplified expression using logic gates. 6. Connect VCC and ground as shown in the pin diagram. 7. Make connections as per the logic gate diagram. 8. Apply the different combinations of input according to the truth tables. 9. Check the output readings for the given circuits; check them against the truth tables. 10. Verify that the results are correct.
B. Implementation Using Universal Gates 11. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic. 12. Implement the simplified Boolean expressions using only NAND gates, and then using only NOR gates. 13. Connect the circuits according to the circuit diagrams, apply inputs according to the truth table and verify the results.
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Given Problem:
Truth Table: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1
Switching Expression:
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Y=BC+BD
B C D
1 1 7432 2 7408 3 2
Y=B(C+D)
C B D
1 7400 2 4 7400 5
3 9 7400 6 10 8
7402 3
Y=B(C+D)
Y=BC+BD
C D
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Y=BC+BD
Y=B(C+D)
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Experiment No. 2
Components Required: -
Procedure: -
1. Verify that the gates are working. 2. Make the connections as per the circuit diagram for the half adder circuit, on the trainer kit. 3. Switch on the VCC power supply and apply the various combinations of the inputs according to the respective truth tables. 4. Note down the output readings for the half adder circuit for the corresponding combination of inputs. 5. Verify that the outputs are according to the expected results. 6. Repeat the procedure for the full adder circuit, the half subtractor and full subtractor circuits. 7. Verify that the sum/difference and carry/borrow bits are according to the expected values.
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A B
1 7486 2 1 7408 2
A 0
B 0 1 0 1
S 0 1 1 0
C 0 0 0 1
0 1 1
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A 0 0 1
C
B 0 1 0 1
D 0 1 1 0
B 0 1 0 0
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Experiment No. 3
Components Required: -
Procedure: 1. Connect one set of inputs from A1 to A4 pins and the other set from B1 to B4, on the IC 7483. 2.Connect the pins from S1 to S4 to output terminals. 3. Short S,C0 to XOR gate 1 input and other input take from C4 and obtain the Output Carry Cout (Output Borrow Bout). 4. In order to Perform Addition take S=0. 5. In order to implement the IC 7483 as a subtractor, Take S=1, Apply the B input through XOR gates (essentially taking complement of B). 6. Apply the inputs to the adder/ subtractor circuits as shown in the truth tables. 7. Check the outputs and note them down in the table for the corresponding inputs. 8. Verify that the outputs match with the expected results. IC 7483 Pin Diagram
7483
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Circuit Diagram:
VCC A4 A3 1 3 8 10 16 4 5 14 C4
2 1
Output Carry
7486' S4 S3 S2 S1
3
Cout
Input Data A
A2 A1
1
15 2 6 9
B4 B3 B2 B1
7486
2 4
Data Output
Input Data B
7486
5 9
7483
7486
10 12
7 11 13 C0 12 GND
7486
13
11
S=0
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Circuit Diagram:
A4 A3 1 3 8 10 16 4
5 14 C4
Output Carry
1
7486'
2
Bout
Input Data A
A2 A1
1
15 2 6 9
S4 S3 S2 S1
B4 B3 B2 B1
7486
2 4
Data Output
Input Data B
7486
5 9
7483
7486
10 12
7 11 13 C0 12 GND
7486
13
11
S=1
Input Data B
B3 B2 B1 Bout S4 S3 S2 S1
1 1 0 0 1 0 1 1
0 0 0 0 0 1 1 0
0 0 1 0 1 1 1 1
0 0 0 1 0 0 0 0
0 1 1 0 1 0 1 1
0 0 0 1 0 0 1 1
1 0 0 1 1 1 1 0
0 0 0 1 1 1 1 1
0 0 1 1 1 0 1 1
0 0 1 1 1 0 1 1
1 0 0 0 1 0 1 1
1 0 1 1 1 1 1 0
0 0 0 0 1 1 1 1
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Example 4bit adder operation using 7483 if control input S=0,addition can be performed Ex: If C0=0
A4 A3 A2 A1=1100 B4 B3 B2 B1=0011
then Sum,S4 S3 S2 S1 =1111 and C0 C4 = Cout. 4 bit subtraction operation using 7483 for A>B here S=1 A4 A3 A2 A1= 1001 B4 B3 B2 B1= 1101 (2's complement) of +3=0011 The end around carry is disregarded 1 0110 C0 C4 = Bout = 0 Difference, S4 S3 S2 S1 = 0110 2's complement method of subtraction can be performed, if S=1(i.e. C0=1). Consider the above Example A4 A_A2 A_ 1001 and B4 B3 B2 B1= 0011 3 _ 1= _ 1s Complement of B4 B3 B2 B1 is B4 B3 B2 B1= 1100
_4 A3 A2 A1= A ___
B4 B3 B2 B1=
2s Complement of B input = -B
The end around carry is disregarded 0 1111 (2's complement) of +1 = 0001 C0 C4 = Bout = 1
-1
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C. BCD To Excess-3 And Vice-Versa Conversion Using 7483 Chip I. BCD TO EXCESS-3 CONVERTER
VCC A3 A2 A1 A0
1
Note: S = 0 and B3,B2,B1,B0 = 0011 vary the BCD input at A3,A2,A1,A0. Circuit Diagram:
1 3 8 10 16 4 5 14 C4 E3 E2 E1 E0 X NC
Input Data A
15 2 6 9
B3 = 0
7486
2 4
Data Output
Input Data B
B2 = 0 B1 = 1 B0 = 1
7486
5 9
7483
7486
10 12
7 11 13 C0 12 GND
7486
13
11
S=0
Truth Table :
Consider Constant Value for B3B2B1B0 = 0011 and S=0 BCD Inputs A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 X X X X X X Excess 3 Outputs E2 0 1 1 1 1 0 0 0 0 1 X X X X X X E1 1 0 0 1 1 0 0 1 1 0 X X X X X X E0 1 0 1 0 1 0 1 0 1 0 X X X X X X
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II.
Note: S=1 and B3,B2,B1,B0 = 0011 vary the Excess-3 input at A3(E3),A2(E2),A1(E1),A0(E0).
Circuit Diagram:
A3 A2 A1 A0
1
VCC 1 3 8 10 16 4 5 14 C4 D C B A X NC
Input Data A
15 2 6 9
B3 = 0
7486
2 4
Data Output
Input Data B
B2 = 0 B1 = 1 B0 = 1
7486
5 9
7483
7486
10 12
7 11 13 C0 12 GND
7486
13
11
S=1
Truth Table :
Consider Constant Value for B3B2B1B0 = 0011 and S=1 Excess-3 Inputs E3 0 0 0 0 0 1 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 1 E1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0 A 0 0 0 0 0 0 0 0 1 1 BCD Outputs B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1
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Experiment No. 4
Components Required: -
IC 7486, etc.
Procedure: -
1.Verify that the gates are working properly. 2. Write the proper truth table for the given Binary to Gray converter. 3. Draw Karnaugh maps for each bit of output. Simplify the Karnaugh maps to get simplified Boolean Expressions. 4. Make connections on the trainer kit as shown in the circuit diagram for the Binary to Gray converter. 5. Apply the Binary inputs at B3-B0 pins, according to the truth table. 6. Check the outputs at the G3-G0 pins and note them down in the table for the corresponding inputs. 7. Verify that the outputs match with the expected results. 8. Repeat the procedure to design, test and verify the working of a Grey to Binary Converter.
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Karnaugh Maps:
For G3:
For G2:
G3 = B3
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For G1:
For G0:
Circuit:
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Karnaugh Maps:
For B3:
For B2:
B3 = G3
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For B1:
For B0:
Circuit:
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Experiment No. 5
1.The Pin [16] is connected to + Vcc and Pin [8] is connected to ground. 2. The inputs are applied either to A input or B input. 3.If MUX A has to be initialized, EA is made low and if MUX B has to be initialized, EB is made low. 4. Based on the selection lines one of the inputs will be selected at the output, and thus the truth table is verified. 5.In case of half adder using MUX, apply constant inputs at (I0a, I1a, I2a, I3a)and (I0b, I1b, I2b and I3b) as shown. 6.The corresponding values of select input lines, A and B (S1 and S0) are changed as per table and the output is taken at Za as sum and Zb as carry. 7.In this case, the inputs A and B are varied. Making Ea and Eb zero andthe output is taken at Za, and Zb. 8.In case of Half Subtractor, connections are made according to the circuit, Inputs are applied at A and B as shown, and outputs are taken at Za (Difference) and Zb (Borrow). Verify outputs. 9.In full adder using MUX, the inputs are applied at Cn-1, An and Bn according to the truth table. The corresponding outputs are taken at Sn (pin Za) and Cn (pin Zb) and are verified according to the truth table. 10. In full subtractor using MUX, the inputs are applied at Cn-1, An and Bn according to the truth table. The corresponding outputs are taken at pin Za(Difference) and pin Zb(Borrow) and are verified according to the truth table.
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Truth Table:
Inputs A 0 0 1 1 B 0 1 0 1
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Truth Tables for Full Adder/Subtractor using 74153 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin/Bin 0 1 0 1 0 1 0 1 Full Adder Outputs S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full Subtractor Outputs D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1
Procedure B. For DEMUX IC 74139 1. The Pin [16] is connected to + Vcc and Pin [8] is connected to ground. 2. The inputs are applied either to A input or B input. 3. If DEMUX A has to be initialized, EA is made low and if DEMUX B has to be initialized, EB is made low. 4. Based on the selection lines one of the inputs will be selected at the set of outputs, and thus the truth table is verified. 5. In case of half adder using DEMUX,Ea is set to 0, the corresponding values of select input lines, A and B (S1a and S0a) are changed as per table and the output is taken at Sum and Carry. Verify outputs. 6. In case of Half Subtractor, connections are made according to the circuit, Inputs are applied at A and B as shown, and outputs are taken at Differenceand Borrow. Verify outputs. 7. In full adder using DEMUX, the inputs are applied at Cn-1, An and Bn according to the truth table. The corresponding outputs are taken at Sum and Carry, and are verified according to the truth table. 8. In full subtractor using DEMUX, the inputs are applied at Cn-1, An and Bn according to the truth table. The corresponding outputs are taken at Difference and Borrow as shown, and are verified according to the truth table.
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Truth Tables: Inputs A 0 0 1 1 B 0 1 0 1 Half Adder Outputs Sum 0 1 1 0 Carry 0 0 0 1 Half Subtractor Outputs Diff 0 1 1 0 Borrow 0 1 0 0
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Truth Tables: Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin/Bin 0 1 0 1 0 1 0 1 Full Adder Outputs S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full Subtractor Outputs D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1
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Experiment No. 6
B. Study of IC 7485: 1.Write the truth table for an4-bit comparator. 2. Connect pin 16 to Vcc and pin 8 to GND for the ICs. 3.Apply the two inputs as shown; making sure that the MSB and LSB is correctly connected. 4. Outputs are recorded at pin 2 (A<B), pin 4 (A>B), pin 3 (A=B) pins and are verified as being according to the truth table.
A. One-Bit Comparator: Circuit : Truth Table: 1bit Comparator Inputs A 0 0 1 1 B. Two-Bit Comparator:
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For A=B
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Circuit:
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Truth Table: 4bit Comparator Input A A3 0 0 1 0 0 1 0 1 A2 0 1 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 B3 0 0 1 0 1 1 0 1 Input B B2 0 0 0 1 0 0 1 1 B1 0 1 1 1 0 1 1 1 B0 1 1 0 0 0 1 0 0 A>B 0 1 0 0 0 1 0 1 Output A<B 1 0 0 1 1 0 0 0 A=B 0 0 1 0 0 0 1 0
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Experiment No. 7
Components required: -
Procedure: -
1. Test and verify that all the segments of the LED Display are working. 2. Make the circuit connections as shown in the circuit diagram. 3. Connect Pin 16 to Vcc and Pin 8 to GND. 4. Connect the input pinsof the 7-segment LED Display to the respective pins (A3-A0) of the 7447 BCD to 7-Segment decoder driver chip. 5. Give the different BCD inputs according to the truth table, and observe the Decimal outputs displayed on the 7-segment LCD Display. 6. Verify that the outputs match the expected results in the truth tables.
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Circuit Diagram:
Output Table:
BCD inputs segment outputs display D C B A a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1
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Experiment No. 8
PRIORITY ENCODER
Aim: Tostudy the use of a 10-line-to-4-Line Priority Encoder Chip (IC 74147).
Components Required: -
IC 74147, etc.
Procedure: -
1. Make the connections as shown in the circuit diagram. 2. Connect Pin 16 of the IC to Vcc and Pin 8 to GND. 3. Connect the pins designated Inputs 1 through 9, to the input switches of the trainer kit. 4. Connect the Output pins designated A, B, C, D to the LED indicators of the trainer kit. 5. Provide the inputs to the encoder chip as shown in the truth table. 6. Observe the outputs on the LED indicators, and note down the results for the respective inputs. 7. Verify that the outputs are as shown in the truth table.
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Truth Table:
1 1 0 X X X X X X X X
2 1 1 0 X X X X X X X
3 1 1 1 0 X X X X X X
Decimal Input 4 5 6 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 X 0 1 X X 0 X X X X X X X X X
7 1 1 1 1 1 1 1 0 X X
8 1 1 1 1 1 1 1 1 0 X
9 1 1 1 1 1 1 1 1 1 0
BCD Output D C B A 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0
Decimal Value 0 1 2 3 4 5 6 7 8 9
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Experiment No. 9
STUDY OF FLIP-FLOPS
Aim: To study and verify the truth tables for J-K Master Slave Flip Flop, T-type and DType Flip-Flops.
Components Required: -
Procedure: 1. Make the connections as shown in the respective circuit diagrams. 2. Apply inputs as shown in the respective truth tables, for each of the flip-flop circuits. 3. Check the outputs of the circuits; verify that they match that of the respective truth tables.
Clear
1 0 1 1 1 1
J
X X 0 0 1 1
K
X X 0 1 0 1 35
Clock
X X 1 0 0 1
Status
Set Reset No Change 0 1 1 0 Reset Set Toggle SP,VK
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B. T-Type Flip-Flop
Circuit:
Truth Table :
Preset 1 1
Clear 1 1
T 0 1
Clock
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C. D-Type Flip-Flop
Circuit:
Truth Table:
Preset 1 1
Clear 1 1
D 0 1
Clock 0 1 1 0
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Experiment No. 10
STUDY OF COUNTERS
Aim: Realization of 3-bit counters as a sequential circuit and Mod-N counter Design (7476, 7490, 74192, 74193)
Components Required: -
Procedure: A. Counter Circuits using IC 7476 1. Make the connections as shown in the respective circuit diagrams. 2. Clock inputs are applied one by one at the clock I/P, and the outputs are observed at QA, QB and QC pins of the 7476 ICs. 3. Verify that the circuit outputs match those indicated by the truth tables. B. Study of Counters IC 74192, IC 74193 1. Connections are made as shown in the respective circuit diagrams, except for the connection from the output of the NAND gate to the load input. 2. The data (0011) = 3 is made available at the data input pins designated A, B, C and D respectively. 3. The Load pin is made LOW so that the data 0011 appears at QD, QC, QB and QA respectively. 4. Now, the output of the NAND gate is connected to the Load input pin. 5. Clock pulses are applied to the Count Up pin, and truth table is verified for that condition. 6. Next, the data (1100) =12 (for 12 to 5 counter) is applied at A, B, C and D and the same procedure as explained above, is performed. 7. IC 74192 and IC 74193 have the same pin configurations. 74192 can be configured to count between 0 and 9 in either direction. Starting value can be any number between 0 and 9.
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Circuit Diagram:
Timing Diagram:
QC 0 0 0 0 1 1 1 1 0 0
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QB 0 0 1 1 0 0 1 1 0 0
QA 0 1 0 1 0 1 0 1 0 1
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Circuit Diagram:
Timing Diagram:
QC 1 1 1 1 0 0 0 0 1 1
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QB 1 1 0 0 1 1 0 0 1 1
QA 1 0 1 0 1 0 1 0 1 0
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Circuit:
Timing Diagram:
Truth Table:
Clock 0 1 2 3 4 5
QC 0 0 0 0 1 0
QB 0 0 1 1 0 0
QA 0 1 0 1 0 0
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Circuit:
Timing Diagram:
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Timing Diagram:
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Circuit:
Truth Table:
CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3rdSem, E&C Dept.
QD
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
QC
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
QB
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 44
QA
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SP,VK
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Circuit:
Truth Table
CLK 0 1 2 3 4 5 6 7 8 9 10
QD
0 0 0 0 0 0 0 0 1 1 0
QC
0 0 0 0 1 1 1 1 0 0 0
QB
0 0 1 1 0 0 1 1 0 0 0
QA
0 1 0 1 0 1 0 1 0 1 0
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Circuit:
Truth Table:
Clock 0 1 2 3 4 5 6 7 8 9 10
QD 0 0 0 0 0 0 0 0 1 1 0
QC 0 0 0 0 1 1 1 1 0 0 0
QB 0 0 1 1 0 0 1 1 0 0 0
QA 0 1 0 1 0 1 0 1 0 1 0
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Circuit:
Truth Table:
Clock 0 1 2 3 4 5 6 7 8 9
QD 0 0 0 0 0 0 0 0 0 0
QC 0 0 0 0 1 1 1 1 0 0
QB 0 0 1 1 0 0 1 1 0 0
QA 0 1 0 1 0 1 0 1 0 1
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Circuit:
Truth Table:
Clock 0 1 2 3 4 5 6 7
QD 0 0 0 0 0 1 0 0
QC 0 1 1 1 1 0 0 1
QB 1 0 0 1 1 0 1 0
QA 1 0 1 0 1 0 1 0
Decimal 3 4 5 6 7 8 3 4
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Circuit:
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Experiment No. 11
IC 7495, etc.
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C. Serial In-Serial Out Mode: 1. Connections are made as shown in the SISO circuit diagram. 2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to LOW, and connect clock input to Clk 1(Pin 9). 3. The 4 bits are applied at the Serial Input pin (Pin 1), one by one, with a clock pulse in between each pair of inputs to load the bits into the IC. 4. At the end of the 4th clock pulse, the first data bit, d0 appears at the output pin QD. 5. Apply another clock pulse, to get the second data bit d1 at QD. Applying yet another clock pulse gets the third data bit d2 at QD, and so on. 6. Thus we see the IC 7495 operating in SISO mode, with serially applied inputs appearing as serial outputs.
D. Parallel In-Serial Out Mode: 1. Connections are made as shown in the PISO circuit diagram. 2. Now apply the 4-bit data at the parallel input pins A, B, C, D (pins 2 through 5). 3. Keeping the mode control M on HIGH, apply one clock pulse. The data applied at the parallel input pins A, B, C, D will appear at the parallel output pins QA, QB, QC, QDrespectively. 4. Now set the Mode Control M to LOW, and apply clock pulses one by one. Observe the data coming out in a serial mode at QD. 5. We observe now that the IC operates in PISO mode with parallel inputs being transferred to the output side serially.
E. Parallel In-Parallel Out Mode: 1. Connections are made as shown in the PIPO mode circuit diagram. 2. Set Mode Control M to HIGH to enable Parallel transfer. 3. Apply the 4 data bits as input to pins A, B, C, D. 4. Apply one clock pulse at Clk 2 (Pin 8). 5. Note that the 4 bit data at parallel inputs A, B, C, D appears at the parallel output pins QA, QB, QC, QDrespectively.
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Clock 1
1
Serial I/P 1 0 1 1
QA X X X 1
QB X X 1 0
QC X 1 0 1
QD 1 0 1 1
2 3 4
B. SIPO MODE (Right Shift) Circuit: Truth Table: Clock 1 2 3 4 Serial I/P 1 0 1 1 QA 1 0 1 1 QB X 1 0 1 QC X X 1 0 QD X X X 1
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C. SISO Mode
Circuit:
Truth Table:
Clock 1 2 3 4 5 6 7
QA QB QC 0 1 1 1 X X X X 0 1 1 1 X X X X 0 1 1 1 X
D. PISO Mode
Circuit:
Truth Table:
Mode
Clk
Parallel I/P A
Parallel O/P
B C D QA QB QC QD 0 1 1 1 X X X 0 1 X X 1 0 1 X 1 1 0 1
1 0 0 0
1 2 3 4
1 X X X
X X X X X X X X X
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E. PIPO Mode
Circuit:
Truth Table:
Clk
Parallel I/P
Parallel O/P
A B C D QA QB QC QD 1 1 0 1 1 1 0 1 1
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Experiment No. 12
Components Required: -
Procedure: 1. Make the connections as shown in the respective circuit diagram for the Ring Counter. 2. Apply an initial input (1000) at the A, B, C, D pins respectively. 3. Keep Select Mode = HIGH (1) and apply one clock pulse. 4. Next, Select Mode = LOW (0) to switch to serial mode and apply clock pulses. 5. Observe the output after each clock pulse, record the observations and verify that they match the expected outputs from the truth table. 6. Repeat the same procedure as above for the Johnson Counter circuit and verify its operation.
A. Ring Counter
Circuit:
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B. Johnson Counter
Circuit:
Truth Table:
Mode Clock QA QB QC QD 1 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0
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Experiment No. 13
SEQUENCE GENERATOR
Aim: To design and study the operation of a Sequence Generator.
In order to generate a sequence of length S, it is necessary to use at leastN number of Flip-flops, in order to satisfy the condition . The given sequence length S = 15 Therefore, N = 4 Note: There is no guarantee that the given sequence can be generated by 4 flip-flops. If the sequence is not realizable by 4 flip-flops, we need to use 5 flip-flops, and so on.
Procedure:1. Truth table is constructed for the given sequence, and Karnaugh maps are drawn in order to obtain a simplified Boolean expression for the circuit. 2. Connections are made as shown in the circuit diagram. 3. Mode M is set to LOW (0), and clock pulses are fed through Clk 1 (pin 9). 4. Clock pulses are applied at CLK 1 and the output values are noted, and checked against the expected values from the truth table. 5. The functioning of the circuit as a sequence generator is verified.
Circuit:
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Truth Table:
Karnaugh Map:
Map Value 15 7 3 1 8 4 2 9 12 6 11 5 10 13 14
O/p Clock QA QB QC QD D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1
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Syllabus LOGIC DESIGN LAB (Common to EC/TC/EE/IT/BM/ML) Sub Code :10ESL38 Hrs/ Week : 03 Total Hrs.: IA Marks : 25 Exam Hours : 03 Exam Marks : 50
NOTE: Use discrete components to test and verify the logic gates. LabView can be used for designing the gates along with the above. 1. Simplification, realization of Boolean expressions using logic gates/Universal gates. 2. Realization of Half/Full adder and Half/Full Subtractors using logic gates. 3. (i)Realization of parallel adder/Subtractors using 7483 chip (ii) BCD to Excess-3 code conversion and vice versausing 7483 chip. 4. Realization of Binary to Gray code conversion and vice versa 5. MUX/DEMUX use of 74153, 74139 for arithmetic circuits and code converter. 6. Realization of One/Two bit comparator and study of 7485 magnitude comparator. 7. Use of Decoder chip to drive LED display. 8. Use of IC 74147 as Priority encoder. 9. Truth table verification of Flip-Flops: (i) (ii) (iii) JK Master slave T type D type.
10. Realization of 3 bit counters as a sequential circuit and MOD N counter design (7476, 7490, 74192,74193). 11. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95. 12. Wiring and testing Ring counter/Johnson counter. 13. Wiring and testing of Sequence generator.
http://www.scribd.com/doc/62491691/Logic-Design-Lab-Manual-10ESL38-3rd-sem-2011
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