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LS6410 S3C6410 ARM11 Core Board

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LS6410CORE integrates S3C6410, two 16 bit 128MB mobile DDR, 1GB MLC NAND Flash K9G8G08, power management circuit, Ethernet chip DM9000AEP, audio IC WM9713 of dual input channels/dual output channels, iNand Flash, etc.

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1. Pin Definition
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name KP_COL3 KP_COL4 KP_COL5 KP_COL6 KP_COL7 EINT20 EINT21 PWR_ON_OFF GND CLK_32K SD0_CD SD0_D0 SD0_D1 SD0_D2 SD0_D3 SD0_CLK SD0_CMD XVD0 XVD1 XVD2 XVD3 XVD4 XVD5 XVD6 XVD7 XVD8 XVD9 XVD10 XVD11 XVD12 XVD13 XVD14 XVD15 XVD16 Description Note Additional Function IO IO IO IO IO IO IO

Keypad matrix column scan 3 Keypad Matrix column scan 4 Keypad matrix column scan 5 Keypad matrix column scan 6 Keypad matrix column scan 7 External interrupt 20 External interrupt 21 Power enable, active high Power ground 32.768KHz waveform output SDIO channel 0 enable, active 10K resister pull low up Data line 0 of SDIO channel 0 10K resister pull up Data line 1 of SDIO channel 0 10K resister pull up Data line 2 of SDIO channel 0 10K resister pull up Data line 3 of SDIO channel 0 10K resister pull up Clock of SDIO channel 0 10K resister pull up Command signal of SDIO 10K resister pull channel 0 up Data 0 of LCD signal B0 Data 1 of LCD signal B1 Data 2 of LCD signal B2 Data 3 of LCD signal B3 Data 4 of LCD signal B4 Data 5 of LCD signal B5 Data 6 of LCD signal B6 Data 7 of LCD signal B7 Data 8 of LCD signal G0 Data 9 of LCD signal G1 Data 10 of LCD signal G2 Data 11 of LCD signal G3 Data 12 of LCD signal G4 Data 13 of LCD signal G5 Data 14 of LCD signal R6 Data 15 of LCD signal R7 Data 16 of LCD signal R0 3 / 20

IO or EINT12 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

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35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

XVD17 XVD18 XVD19 XVD20 XVD21 XVD22 XVD23 XHSYNC XVSYNC XVDEN XVCLK CTS1 RXD1 RTS1 TXD1 GND EINT0 EINT1 EINT2 EINT5 EINT6

Data 17 of LCD signal Data 18 of LCD signal Data 19 of LCD signal Data 20 of LCD signal Data 21 of LCD signal Data 22 of LCD signal Data 23 of LCD signal Raw Scan Signal of LCD Column Scan Signal of LCD DE signal of LCD Clock signal of LCD Serial port 1 TTL CTS Serial Port 1 TTL RXD Serial Port 1 TTL RTS Serial Port 1 TTL TXD Power Gound External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 5 External Interrupt 6

R1 R2 R3 R4 R5 R6 R7

Can only triggered by high level

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

56 57 58 59

EINT9 EINT10 EINT11 EINT13

External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 13

60

EINT14

External Interrupt 14

61

EINT15

External Interrupt 15

Used to select NAND during booting Used to select NAND during booting Used to select NAND during booting

IO IO IO IO

IO

IO

62 63 64 65 66 67 68 69 70 71 72

EINT16 EINT17 EINT18 MIC1 HOST_DHOST_D+ PWM1 PWM0 BBP BBN SPKL

External Interrupt 16 External Interrupt 17 External Interrupt 18 Single channel MIC input USB HOST D- pin USD HOST D+ pin PWM output 1 PWM output 0 MIC differential input + MIC differential input Audio output Left channel 4 / 20

IO IO IO

IO IO Connect to GSM audio output Connect to GSM audio output

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73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112

SPKR MIC_MTN MIC_MTP MICP MICN HP_DET LOUT ROUT AC97_W AC97_YAC97_Y+ AC97_XAC97_X+ OM1 OM2 OM3 OM4 XciYDATA0 XciYDATA1 XciYDATA2 XciYDATA3 XciYDATA4 XciYDATA5 XciYDATA6 XciYDATA7 XciCLK XciHREF XciPCLK XciRSTN XciVSYNC RXD0 TXD0 CTS0 RTS0 RXD2 TXD2 RXD3 TXD3 XirSDBW GND

Audio output Right channel Audio output Audio output+

Connect to GSM audio input Connect to GSM audio input

MIC input + MIC input Headphone plug in detection Headphone plug (active low) in detection Headphone Left channel Headphone Right channel Audio IC touch function 5 line touch common pin Audio IC touch YAudio IC touch Y+ Audio IC touch XAudio IC touch X+ Boot configuration pin Refer to boot configuration Boot Configuration pin Refer to boot configuration Boot Configuration pin Refer to boot configuration Boot Configuration pin Refer to boot configuration Camera interface data line 0 Camera interface data line 1 Camera interface data line 2 Camera Interface data line 3 Camera Interface data line 4 Camera Interface data line 5 Camera Interface data line 6 Camera Interface data line 7 Camera Interface Clock Horizontal Sync Clock Pixel Clock Signal Camera module Reset signal Frame Sync Clock Signal Serial port 0 TTL RXD Serial port 0 TTL TXD Serial port 0 TTL CTS Serial port 0 TTL RTS Serial port 2 TTL RXD Serial port 2 TTL TXD Serial port 3 TTL RXD Serial port 3 TTL TXD Infra-red control signal Power Ground 5 / 20

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

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113 114 115

NET_SPEED NET_LINK AVDD25

116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147

NET_TXNET_TX+ NET_RXNET_RX+ SPI0_MISO SPI0_CLK SPI0_MOSI SPI0_CS SPI1_MISO SPI1_CLK SPI1_MOSI SPI1_CS SD1_CD SD1_CLK SD1_CMD SD1_D0 SD1_D1 SD1_D2 SD1_D3 SD1_D4 SD1_D5 DS1_D6 SD1_D7 AIN0 AIN1 AIN2 AIN3 TS_YM TS_YP TS_XM TS_XP IIC0_SCL

Network speed indicator Active Low output Network Link indicator output Active Low 2.5V output To supply the Ethernet transformer Ethernet Differential TXEthernet Differential TX+ Ethernet Differential RXEthernet Differential RX+ SPI channel 0 MISO SPI channel 0 CLK SPI channel 0 MOSI SPI channel 0 CS SPI channel 1 MISO Dual Function: SD2_CMD SPI channel 1 CLK Dual Function: SD2_CLK SPI channel 1 MOSI SPI channel 1 CS SD channel 1 channel selection (active low) SD channel 1 CLK SD channel 1 Command signal SD channel 1 data 0 SD channel 1 data 1 SD channel 1 data 2 SD channel 1 data 3 SD channel 1 data 4 Dual function: SD2_D0 SD channel 1 data 5 Dual function: SD2_D1 SD channel 1 data 6 Dual function: SD2_D2 SD channel 1 data 7 Dual function: SD2_D3 ADC channel 0 ADC precision: 10 bit ADC channel 1 ADC channel 2 ADC channel 3 Touch YTouch Y+ Touch XTouch X+ IIC bus clock Need external 10K pull up 6 / 20

IO or EINT IO or EINT IO or EINT IO or EINT IO or EINT IO or EINT IO or EINT IO or EINT IO IO IO IO IO IO IO IO IO IO IO

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148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170

IIC0_SDA DAC0 DAC1 GND OTG_DOTG_D+ OTG_ID OTGDRV_VBUS DVBUS nRESET VDD_RTC VDD_MAX KP_ROW0 KP_ROW1 KP_ROW2 KP_ROW3 KP_ROW4 KP_ROW5 KP_ROW6 KP_ROW7 KP_COL0 KP_COL1 KP_COL2

IIC bus data TV analog output signal 0 TV analog output signal 1

Need external 10K pull up Connect to TV output Connect to TV output

Power Ground OTG Data OTG Data+ OTG ID signal OTG power output enable signal OTG power input detection signal Reset signal (active low) RTC backup battery input 1.8-3.0V Signal main power input 2.7-6.5V Keypad matrix row scan 0 Keypad matrix row scan 1 Keypad matrix row scan 2 Keypad matrix row scan 3 Keypad matrix row scan 4 Keypad matrix row scan 5 Keypad matrix row scan 6 Keypad matrix row scan 7 Keypad matrix column scan 0 Keypad matrix column scan 1 Keypad matrix column scan 2

IO IO IO IO IO IO IO IO IO IO IO

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2. Core Board Package

Thickness: 2.85mm Length: 60mm Width: 60mm Pin pitch: 1.27mm

Recommended footprint as follows: 1. Add a layer of silkscreen to prevent the core board shots with via on the motherboard.

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2. Add a rectangle opening on the motherboard as shown in the following figure.

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3. PCB Layout
3.1 Core Board PCB normal line width and line interval

1. Normal signal line interval 4 mil. 2. TOP layer: the first line outside BGA has a line interval of 5 mil.

3. Lines under BGA has an interval of 4 mil.

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4. The minimal line width of power and GND is 10 mil, and maxium 20 mil.

3.2 Size of via and distribution of blind and buried via This core board uses blind and buried via. There are no empty via.

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3.3 Core Board Stackup

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3.4 Core Board Impedance Control

3.5 Core board layout

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Power plane separation:

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Components placement:

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