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A

ZZZ2

ZZZ1

ZZZ3

ZZZ4

PCB

LA-7072P

LS-7072P

LS-7073P

M/B
DAZ@

M/B
DA@

LED/B
DA@

TP/B
DA@

11/18
LA-7072P P/N from DA60000LA00 to DA60000LA10
LS-7072P P/N from DA40000Z300 to DA40000Z310
LS-7073P P/N from DA40000Z400 to DA40000Z410
11/22
LS-7073P P/N from DA40000Z410 to DA20000Z410

11/18 ZZZ2 for DAZ P/N:DAZ0IV00101

Compal Confidential
P0VE6 LA7072P Schematics Document

AMD Ontario Processor with DDRIII + Hudson M1


10.1" M/B
2010-11-18
Rev : 1.0

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Cover Page
Size Document Number
Custom

Rev
1.0

P0VE6 Schematics

Date:

Monday, November 22, 2010

Sheet
E

of

36

Compal Confidential

Brazos Platform

Model Name : P0VE6 / P0VH6


File Name : LA-7072P
HDMI
RGB
LVDS

AMD
Ontario FT1

Memory Bus (DDRIII)

Single Channel

APU

204 Pin DDRIII SO-DIMM x1

1.5V DDRIII 800/1066

BANK 0, 1, 2, 3

6.4G/8.5G

BGA 413-Ball
19mm X 19mm

Page 7

100M/133M

Page 4,5,6

HDMI Conn.

D-Sub Conn.

Page 9

Page 10

LVDS Conn.

UMI x4
Gen.1

Page 8

USB Conn.x1
(Right Side)
Port 2

2.5GT/s
per Lane
PWM

Camera

Bluetooth

Port 5

Port 7

Page 24

Page 8

Card Reader
ENE 6250 / 6252
Port 6

Page 19

Page 18
2

Page 26

PCI-Express X3
100MHz

Port 1

PCIE Gen1 2.5GT/S


Port 3

WWAN

WLAN

JMINI1

JMINI2

Media processor
Port 1

(Left Side)
Port 0, 1

Page 24

Fan Circuit

USB Conn.x2

Wireless Card
Port 3

Page 19

Page 20

USB

AMD
Hudson M1

HD Audio

FCH

Port 2

LAN(10/100mbE)

3.3V 48MHz

SATA

3.3V 24MHz

Gen1 1.5GT/S ,Gen2 3GT/S

3G Card

100MHz

BGA 605-Ball
23mm X 23mm

Port 3
Page 19

Page 11,12,13,14,15

AR8152

HDD

Port 2
Page 17

(2.5")
Port 0

LPC

Page 21

33MHz
3

RJ-45
Page 17

HDA Codec+AMP

ENE KB930

CX20584

Small Board

Page 25

LED/B

Page 16

TP BTN/B

LS-7072P

LS-7073P

HP Jack x1
MIC Jack x1
Page 23

RTC Ckt.
Page 11

BIOS ROM
2MB

Power Button

Page 26
Page 22

2010/08/12

Issued Date

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Page 27

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DC/DC Interface Ckt.


B

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
1.0

P0VE6 Schematics
Monday, November 15, 2010

Sheet
E

of

36

Voltage Rails

Power Plane

Description

S1

VIN

Adapter power supply (19V)

N/A

B+

AC or battery power rail for power circuit.

N/A

S5

FCH Hudson-M1
USB Port List

N/A

N/A

USB1.1

N/A

N/A

S3

+APU_CORE

Core voltage for CPU (0.7-1.2V)

ON

OFF

OFF

+APU_CORE_NB

1.0V switched power rail

ON

OFF

OFF

+1.5V

1.5V power rail for CPU VDDIO and DDRIII

ON

ON

OFF

+0.75VS

0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.05VS

1.05V switched power rail for NB VDDC & VGA

ON

OFF

OFF

+1.1VS

1.1VS switched power rail

ON

OFF

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+1.1VALW

1.1V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+1.5VS

1.5VS switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCBATT

RTC power

ON

ON

ON

EC SM Bus1 address
Address

HEX

Device

Address

HEX

Smart Battery

0001-011xb

16H

SB-TSI

1001-100xb

98H

SM Bus Controller 0
Device

SM Bus Controller 1
Device

NC

(FCH_SMB0)

Address

HEX

1001-000xb

90

PCIE1
PCIE2

NC

HDD

SATA1

NC

SATA2

PCIE3

NC

SATA3

NC

Port0

Right USB2

PCIE0

NC

SATA4

NC

Port1

Right USB3

PCIE1

WWAN

SATA5

NC

Port2

Left

PCIE2

LAN

Port3

WWAN

PCIE3

WLAN

Port4

SIM

Port5

USB Camera

Port6

CardReader

Port7

BT

Port8

WiMax

USB1

Port9

NC

Port10

NC

Port11

NC

Port12

NC

Port13

NC

Board ID

H_THERMTRIP# (FCH_ALERT#)

DDR DIMM1 (FCH_SMB0)

NC

Port1

Vcc
Ra

HEX

APU SIC/SID (FCH_SMB3)

Port0

SATA0

Board ID / SKU ID Table for AD channel

(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)

Address

PCIE0

FCH Hudson-M1
SATA Port List

EC SM Bus2 address

Device

Brazos
PCIE Port List

USB2.0

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

APU

FCH

0
1
2
3
4
5
6
7

+3VALW
100K +/- 5%
Rb
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

PCB Revision
0.1
0.2

SMBUS Control Table


Source

BATT

EC_SMB_CK1
EC_SMB_DA1

KB930

EC_SMB_CK2
EC_SMB_DA2

KB930

HDMI_DATA
HDMI_CLK

APU FT1

EDID_DATA
EDID_CLK

APU FT1

FCH_SMDAT0
FCH_SMCLK0

FCH M1

BOM Structure

HDMI@ :
BT@
:
CONN@ :
45@
:
3G@
:
3G_MP@:
CHARGE@:
NONCHARGE@:

HDMI function
BT function
Connetors
45 Level
3G function
3G & Media processor function
Charge BATT
nonCharge BATT

DIMM

MINI Card LCD DDC ROM

APU

V
V
V
4

2010/08/12

Issued Date

V
Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

HDMI DDC ROM

Title

Notes List
Size
B
Date:

Document Number

P0VE6 Schematics
Monday, November 15, 2010

Sheet
E

of

36

Rev
1.0

U1

10/08 Add U1(C50@) SA00004BM30 S IC ONTARIO ZM101034B2238 1G BGA ABO!

R9

10/08 Change U1 P/N to SA00004DF20 S IC ONTARIO ZM121034B1238 1.2G BGA ABO!


10/27 APU P/N update to B0 stepping

1
1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

HDMI_TX1P_C
HDMI_TX1N_C

B9
A9

TDP1_TXP1
TDP1_TXN1

C7
C8

1
1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

HDMI_TX0P_C
HDMI_TX0N_C

D10
C10

TDP1_TXP2
TDP1_TXN2

C4
C5

1
1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

HDMI_CLKP_C
HDMI_CLKN_C

A10
B10

TDP1_TXP3
TDP1_TXN3

<8> LVDS_A2
<8> LVDS_A2#

B5
A5

LTDP0_TXP0
LTDP0_TXN0

<8> LVDS_A1
<8> LVDS_A1#

D6
C6

LTDP0_TXP1
LTDP0_TXN1

<8> LVDS_A0
<8> LVDS_A0#

A6
B6

<8> LVDS_ACLK
<8> LVDS_ACLK#

D8
C8

11/29 Change U1 from SA00004BM80 to SA00004KD40


+3VS
R10
R11
R13
R14
R16
R17

1
1
1
1
1
1

2
2
2
2
2
2

C405 1

HDMI_DATA
HDMI_CLK
APU_PROCHOT#
APU_ALERT#_R
APU_SIC
APU_SID

10K_0402_5%
10K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%

LDT_RST#

2 100P_0402_50V8J

Power Circuit

10/05 Add 100p(C405) on LDT_RST#

<11>
<11>

APU_CLK
APU_CLK#

V2
V1

<11>
<11>

DISP_CLK
DISP_CLK#

D2
D1

<35> APU_SVC
<35> APU_SVD
APU_SIC
APU_SID

9/9 Change R24 from @ to mount R26 from mount to @


9/15 Change R24 from mount to @

<11> FCH_PROCHOT#
<25> EC_PROCHOT#

R23

R27

2 0_0402_5% APU_PROCHOT#
2 0_0402_5%

<13> APU_ALERT#_FCH
<25> APU_ALERT#_EC

Connection to EC, FCH input

Power Circuit
Power Circuit

+3VS

<35> APU_VDD0_RUN_FB_L

2 0_0402_5%

F1

<35> APU_VDDNB_RUN_FB_L

R380 1

2 0_0402_5%

B4
W11
V5

PROCHOT_L
THERMTRIP_L
ALERT_L
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

DP_BLON
DP_DIGON
DP_VARY_BL

G2
H2
H1

TDP1_AUXP
TDP1_AUXN

B2
C2

TDP1_HPD

C1

LTDP0_AUXP
LTDP0_AUXN

A3
B3

EDID_CLK
EDID_DATA

LTDP0_HPD

D3

LTDP0_HPD

DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB
DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA

VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE

R1

H3

DAC_ZVSS

RESET_L
PWROK

DP_ZVSS

DP_ZVSS

mount

TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37

C12
D13
A12
B12
A13
B13

APU_ENBKL <25>
APU_ENVDD <8>
APU_BLPWM <8>
HDMI_CLK
HDMI_DATA

HDMI_CLK <9>
HDMI_DATA <9>

8/25 Pull-up 100k(@ R352) to +3VS


on LTDP0_HPD for eDP

HDMI_DET <9>
EDID_CLK <8>
EDID_DATA <8>
R9

R352 1

2 100K_0402_5%

2 100K_0402_5%

R12

2 150_0402_1%

R15

2 150_0402_1%

R18

2 150_0402_1%

+3VS

DAC_RED <10>
DAC_GRN <10>
DAC_BLU <10>

E1
E2

CRT_HSYNC <10>
CRT_VSYNC <10>

F2
D4

CRT_DDC_CLK <10>
CRT_DDC_DATA <10>

D12 DAC_ZVSS
R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5

eDP

2 150_0402_1%

R19

2 499_0402_1%

TEST15

R20

2 1K_0402_5%

TEST18
TEST19
TEST25_H
TEST_25_L

R21
R22
R25

1
1
1

2 1K_0402_5%
2 1K_0402_5%
2 510_0402_1%

10/01 Remove T1,T3~T7,T11,T12,T31,T32

PAD T2

TEST31
TEST33_H
TEST33_L
TEST35
TEST36
TEST37

PAD T8

C9 1
C10 1
R30

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
1

PAD T13 R386 1

R28
R29

2 51_0402_1%
2 51_0402_1%

1
1

2 1K_0402_5%
2 1K_0402_5%

+1.8VS

9/9 Add R386 (1k@) to +1.8VS on TEST35

VSS_SENSE
TEST38
DMAACTIVE_L

RSVD_1
RSVD_2
RSVD_3

9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend)

K3
T1

ALLOW_STOP# <11>
R31

2 1K_0402_5%

+1.8VS

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !


C30@

8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P

R33

SIC
SID

R379 1

9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L

R32
10K_0402_5%
<BOM Structure>

DISP_CLKIN_H
DISP_CLKIN_L
SVC
SVD

F4
G1
F3

T14PAD

CLKIN_H
CLKIN_L

P3
P4

APU_PROCHOT#
U1
APU_THERMTRIP# U2
APU_ALERT#_R T2
R24 1
@
2 0_0402_5%
R26 1
@
2 0_0402_5%
APU_TDI
N2
APU_TDO
need to pull-down
N1
APU_TCK
P1
APU_TMS
P2
APU_TRST#
M4
T9 PAD
APU_DBRDY
M3
T10PAD
Close to APU
APU_DBREQ#
M1

<35> APU_VDDNB_RUN_FB_H
<35> APU_VDD0_RUN_FB_H

LTDP0_TXP3
LTDP0_TXN3

J1
J2

T3
T4

<11> LDT_RST#
<11> APU_PWRGD

LTDP0_TXP2
LTDP0_TXN2

DP MISC

C2
C3

TDP1_TXP0
TDP1_TXN0

VGA DAC

A8
B8

TEST

<9> HDMI_CLKP
<9> HDMI_CLKN

HDMI_TX2P_C
HDMI_TX2N_C

DISPLAYPORT 1

TEST_25_L
TEST36

2 510_0402_1%
2 1K_0402_5%

1
1

<9> HDMI_TX0P
<9> HDMI_TX0N

.1U_0402_16V7K
.1U_0402_16V7K

DISPLAYPORT 0

R8
R6

APU_SVC
APU_SVD

2 1K_0402_5%
2 1K_0402_5%

1
1

2
2

CLK

R3
R4

<9> HDMI_TX1P
<9> HDMI_TX1N

1
1

SER

C1
C6

CTRL

<9> HDMI_TX2P
<9> HDMI_TX2N

C50@

LVDS

mount

U1B

JTAG

11/03 APU P/N update to SA00004DF60(C30) SA00004BM80(C50)

SA00004KD40

+1.8VS

SA00004DF60

S IC ONTARIO ZMC50AFPB22GT 1G BGA 413P ABO !

Display

R352

1K_0402_5%
B

Q1
1

APU_THERMTRIP#

9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32


H_THERMTRIP# <12>

AMD Debug

MMBT3904_NL_SOT23-3
1
R34

+1.8VS

9/20 Delete R41~R43

2
0_0402_5%

If FCH internal pull-up disabled, level-shifter could be deleted.


Need BIOS to disable internal pull-up!!

APU_TCK

R35

1 1K_0402_5%

APU_TMS

R36

1 1K_0402_5%

APU_TDI

R38

1 1K_0402_5%

APU_PWRGD

R5

1 300_0402_5%

LDT_RST#

R7

1 300_0402_5%

R2

1 300_0402_5%

+1.8VS
+3VS
1

2N7002DW-T/R7
Vgs(th): min 1.0V
Typ 1.6V
Max 2.0V

R39
10K_0402_5%
@

R37

T29PAD

1K_0402_5%
2
1 APU_TRST#

T30PAD

APU_DBRDY
APU_DBREQ#

If Q8 or R429, R432 implemented,


EC side pull-up need to be mounted

APU_TDO

DMN66D0LDW-7_SOT363-6
1

APU_SID
A

EC_SMB_DA

Q2A
1
R49

1
R47
1
R48

2
0_0402_5%
2
0_0402_5%

FCH_SID
EC_SMB_DA2

FCH_SID <12>
EC_SMB_DA2 <25>

T0 FCH
TO EC

2
0_0402_5%

8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

DMN66D0LDW-7_SOT363-6
4

APU_SIC

Q2B

1
R52
5

EC_SMB_CK

1
R50
1
R51

FCH_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%

FCH_SIC <12>
EC_SMB_CK2 <25>

T0 FCH
TO EC

Compal Secret Data

Security Classification
2010/08/12

Issued Date

2012/08/12

Deciphered Date

Compal Electronics, Inc.


FT1 CTRL/DP/CRT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
0_0402_5%

Title

Size Document Number


Custom
Date:

Rev
1.0

P0VE6 Schematics

Monday, November 29, 2010

Sheet
1

of

36

DDR_A_D[0..63]

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

DDR_A_DM[0..7]

U1E

R18
T18
F16

<7> DDR_A_BS0
<7> DDR_A_BS1
<7> DDR_A_BS2

<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

<7>
<7>
<7>
<7>

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

D15
B19
D21
H22
P23
V23
AB20
AA16

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

A16
B16
B20
A20
E23
E22
J22
J23
R22
P22
W22
V22
AC20
AC21
AB16
AC16

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

M17
M16
M19
M18
N18
N19
L18
L17

DDR_RST#
DDR_EVENT#

<7> DDR_RST#
<7> DDR_EVENT#

DDR_CKE0
DDR_CKE1

<7> DDR_CKE0
<7> DDR_CKE1

<7> DDR_A_ODT0
<7> DDR_A_ODT1

<7> DDR_CS0_DIMMA#
<7> DDR_CS1_DIMMA#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

F15
E15

DDR_A_ODT0
DDR_A_ODT1

W19
V15
U19
W15

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

T17
W16
U17
V16

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

<7> DDR_A_RAS#
<7> DDR_A_CAS#
<7> DDR_A_WE#

L23
N17

U18
V19
V17

M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

DDR SYSTEM MEMORY

R17
H19
J17
H18
H17
G17
H15
G18
F19
E19
T19
F17
E18
W17
E16
G15

M_BANK0
M_BANK1
M_BANK2
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

M_RESET_L
M_EVENT_L
M_CKE0
M_CKE1

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1

B14
A15
A17
D18
A14
C14
C16
D16

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

C18
A19
B21
D20
A18
B18
A21
C20

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

C23
D23
F23
F22
C22
D22
F20
F21

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

H21
H23
K22
K21
G23
H20
K20
K23

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

N23
P21
T20
T23
M20
P20
R23
T22

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

V20
V21
Y23
Y22
T21
U23
W23
Y21

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

M23

+MEM_VREF

M22

+M_ZVDDIO

<7>
<7>
<7>

8/22 Delete C11~C18 (No VGA)


9/6 Change PCI-E from FCH to APU
9/6 Update PCI-E port List
9/15 Change PCI-E from APU to FCH

U1A

AA6
Y6
AB4
AC4
AA1
AA2
Y4
Y3
+1.05VS

R53

2
2K_0402_1%

P_ZVDD_10

Y14

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

P_GPP_TXP0
P_GPP_TXN0

PCIE I/F

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

P_ZVDD_10

P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_ZVSS

AB6
AC6
AB3
AC3
Y1
Y2
V3
V4

AA14 P_ZVSS

R54

1.27K_0402_1%

Less than 1"


Less than 1"
AA12
Y12

<11> UMI_RX0P
<11> UMI_RX0N
<11> UMI_RX1P
<11> UMI_RX1N

AA10
Y10

<11> UMI_RX2P
<11> UMI_RX2N

AB10
AC10

<11> UMI_RX3P
<11> UMI_RX3N

AC7
AB7

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

P_UMI_TXP0
P_UMI_TXN0

UMI I/F

P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

AB12
AC12

UMI_TX0P_C
UMI_TX0N_C

C19
C20

1
1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

AC11
AB11

UMI_TX1P_C
UMI_TX1N_C

C21
C22

1
1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

AA8
Y8

UMI_TX2P_C
UMI_TX2N_C

C23
C24

1
1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

AB8
AC8

UMI_TX3P_C
UMI_TX3N_C

C25
C26

1
1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

UMI_TX0P <11>
UMI_TX0N <11>
UMI_TX1P <11>
UMI_TX1N <11>
UMI_TX2P <11>
UMI_TX2N <11>
UMI_TX3P <11>
UMI_TX3N <11>

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !


C30@

M_VREF

M_RAS_L
M_CAS_L
M_WE_L

R55

M_ZVDDIO_MEM_S

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !


C30@

+1.5V

39.2_0402_1%

9/11 Delete DDR Signal link to JDIMM2

+1.5V

+1.5V

R56
1K_0402_1%

2
1K_0402_5%

DDR_EVENT#

+MEM_VREF

R57

R58
1K_0402_1%

C27

C28

1000P_0402_50V7K

0.1U_0402_16V4Z

Place within 1000 mils to APU


20100526

Compal Secret Data

Security Classification
Issued Date

2010/08/12

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


FT1 DDRIII/UMI/PCIE

Size
Document Number
Custom
Date:

Rev
1.0

P0VE6 Schematics

Wednesday, November 17, 2010


E

Sheet

of

36

+APU_CORE
+1.8VS

4500 mA

10U_0603_6.3V6M

1U_0402_6.3V6K
C40

1U_0402_6.3V6K
C39

1U_0402_6.3V6K
C38

.1U_0402_16V7K
C36

C34

180P_0402_50V8J
C35

1U_0402_6.3V6K
C37

L2

10U_0603_6.3V6M

1U_0402_6.3V6K
C51

C49

180P_0402_50V8J
C50

1
FBMA-L11-201209-221LMA30T_0805

8/25 Change +1.0VS to +1.05VS


+1.05VS

L3

10U_0603_6.3V6M

1U_0402_6.3V6K
C60

5500 mA

.1U_0402_16V7K
C59

2
1

180P_0402_50V8J
C58

L4

+VDD_10

1
FBMA-L11-201209-221LMA30T_0805

+3VS

500 mA
+VDD_33

1
1

1U_0402_6.3V6K

A4

VDD_33

10U_0603_6.3V6M
C67

1U_0402_6.3V6K
C66

1U_0402_6.3V6K
C65

.1U_0402_16V7K
C64

2
1

.1U_0402_16V7K
C63

U13
W13
V12
T12

VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

C57

+VDDL_10

R333
2
0_0603_5%

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSSBG_DAC

N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

8/22 Reserve R333 ( 0 ohm 0603 )

C91

9/15 Change C99,C100 to 470U(SGA00003K00)

C98

C97

180P_0402_50V8J

9/15 Remove C101, C113

180P_0402_50V8J

C96

.1U_0402_16V7K

8/25 Change C101 from mount to @

C95

SGA00004L00

.1U_0402_16V7K

C93
220U_D2_2VY_R15M
C94

U1D
A7
B7
B11
B17
B22
C4
D5
D7
D9
D11
D14
B15
D17
D19
E7
E9
E12
E20
F8
F11
F13
G4
G5
G7
G9
G12
G20
G22
H6
H11
H13
J4
J5
J7
J20
K10
K14
L4
L6
L8
L11
L13
L20
L22
M7
N4
N6
N8
N11

9/20 Change C93 to SGA00004L00

.1U_0402_16V7K

C92

10U_0603_6.3V6M

C90

1U_0402_6.3V6K

C83

+1.05VS

+1.5V

U11

VDDPL_10

POWER

10U_0603_6.3V6M

C89

C81

C82

180P_0402_50V8J

C80

180P_0402_50V8J

10U_0603_6.3V6M

C72
C79

1U_0402_6.3V6K

C88

VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !


C30@

1U_0402_6.3V6K

G16
G19
E17
J16
L16
L19
N16
R16
R19
W18
U16

10U_0603_6.3V6M

C87

10U_0603_6.3V6M

C71
C78

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

C70
C77
C86

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

C85

10U_0603_6.3V6M

C69
C76

1U_0402_6.3V6K

10U_0603_6.3V6M

C68

.1U_0402_16V7K

1U_0402_6.3V6K

C75
C84

W = 15 mil / Spcae = 20 mil

DP Phy/IO

DDR3

.1U_0402_16V7K

+VDD_18_DAC

POWER

+1.5V

VDD_18_DAC

PCIE/IO/DDR3 Phy

2000 mA

+1.8VS

W9

C73

+APU_CORE_NB

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22

W = 20 mil / Spcae = 20 mil

+APU_CORE_NB
E8
E11
E13
F9
F12
G11
G13
H9
H12
K11
K13
L10
L12
L14
M11
M12
M13
N10
N12
N14
P11
P13

C61

8000 mA

180P_0402_50V8J
C62

10U_0603_6.3V6M

C33
C48

180P_0402_50V8J

U8
W8
U6
U9
W6
T7
V7

VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_18_5
VDD_18_6
VDD_18_7

.1U_0402_16V7K
C74

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15

1U_0402_6.3V6K

10U_0603_6.3V6M

C30
C47

C56

180P_0402_50V8J

C42

10U_0603_6.3V6M

10U_0603_6.3V6M

C41

E5
E6
F5
F7
G6
G8
H5
H7
J6
J8
L7
M6
M8
N7
R8

.1U_0402_16V7K

1U_0402_6.3V6K

C46
C55

.1U_0402_16V7K

C32

10U_0603_6.3V6M
1U_0402_6.3V6K

C45
C54

.1U_0402_16V7K

C29

10U_0603_6.3V6M
1U_0402_6.3V6K

C44
C53

DIS PLL

.1U_0402_16V7K

10U_0603_6.3V6M

C31
C43
C52

GPU AND NB CORE

DAC

L1
2
1
FBMA-L11-201209-221LMA30T_0805

GND

CPU CORE

1U_0402_6.3V6K

.1U_0402_16V7K

+VDD_18

TSense/PLL/DP/PCIE/IO

2000 mA

U1C

+APU_CORE

POWER

+APU_CORE

8/22 Change C111~C113 from E-Cap to Poly-Cap (SGA20331E10)

SGA20331E10

Near CPU Socket

SGA20331E10

Near CPU Socket

Compal Secret Data

Security Classification

Issued Date

2010/08/12

Deciphered Date

2012/08/12

Title

C110

C109

C108

Compal Electronics, Inc.


P07-FT1 PWR/VSS

Size
C
Date:

SGA20331E10

Near CPU Socket

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C107

C106

180P_0402_50V8J

180P_0402_50V8J

C112
330U_D2_2V_Y

180P_0402_50V8J

180P_0402_50V8J

C116

C111
330U_D2_2V_Y

C115

C117

10U_0603_6.3V6M

C114

+
2

330U_D2_2V_Y

22U_0805_6.3V6M

1
1

C105

.1U_0402_16V7K

+1.8VS

Near CPU Socket

C104

+1.5V

POWER
.1U_0402_16V7K

+APU_CORE_NB

+1.5V

POWER

C103

SGA00003K00

By case (Along split)

9/11 Change C111 to SGA20331E10

.1U_0402_16V7K

.1U_0402_16V7K

C100
470U_X_2VM_R6M
@

10U_0603_6.3V6M

C99
470U_X_2VM_R6M

C102

8/25 Change C111 from poly-cap to E-cap (SF000002Z00)

10U_0603_6.3V6M

Document Number

Rev
1.0

P0VE6 Schematics
Wednesday, November 17, 2010
1

Sheet

of

36

DDR_A_D16
DDR_A_D17
<5> DDR_A_DQS#2
<5> DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<5> DDR_A_CLK0
<5> DDR_A_CLK#0
DDR_A_MA10
<5> DDR_A_BS0
<5> DDR_A_WE#
<5> DDR_A_CAS#
DDR_A_MA13
<5> DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33
<5> DDR_A_DQS#4
<5> DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<5> DDR_A_DQS#6
<5> DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59
R63
10K_0402_5%
1
2

R64
10K_0402_5%

205

G1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

2
2

2
R61
1K_0402_1%

R62
1K_0402_1%
1

DDR_RST# <5>

DDR_A_D20
DDR_A_D21

8/19 Change JDIMM1 to SP07000LT00(LCN_DAN06-K4406-0103_204P)

DDR_A_DM2

9/13 Update JDIMM1 to LCN_DAN06-K4406-0102_204P

DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29

9/23 Reserve R396,R397 on CKE0 & CKE1(S3 hang Issue)


DDR_A_DQS#3 <5>
DDR_A_DQS3 <5>

DDR_A_D30
DDR_A_D31
+1.5V

100_0402_1%
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7

2
DDR_CKE1 <5>

0.1U_0402_16V4Z
2
C120

1
0.1U_0402_16V4Z

C121
1

0.1U_0402_16V4Z
2
C122

1
0.1U_0402_16V4Z

C123
1

0.1U_0402_16V4Z
2
C124

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C125

C126
@

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C127
@

C128
@

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C129
@

C130
@

1
0.1U_0402_16V4Z

C131
@

10/11 Change R396 R397 from @ to mount (For A1 APU,B0 APU no Need)

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

9/11 Change C137 to SGA00004L00


DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>

CRB 0.1u X1

4.7u X1

CRB

DDR_A_BS1 <5>
DDR_A_RAS# <5>
+0.75VS

DDR_A_ODT1 <5>
+VREF_CA

DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

X2

+1.5V

DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>

DDR_A_D36
DDR_A_D37

100U

W=20mil

1
+

C137
220U_D2_2VY_R15M

Place near JDIMM1

DDR_A_DQS#5 <5>
DDR_A_DQS5 <5>

SGA00004L00

8/25 Change C137 from poly-cap to E-cap (SF000002Y00)


8/25 Reserve C381 E-cap (SF000002Y00) on +1.5V

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 <5>
DDR_A_DQS7 <5>
DDR_A_D62
DDR_A_D63

+0.75VS

9/11 Remove C381


DDR_EVENT# <5>
FCH_SMDAT0 <12,19,20>
FCH_SMCLK0 <12,19,20>

206

G2

100 mA

LCN_DAN06-K4406-0102

0.1U_0402_16V4Z

C138

C139

+3VS
A

2.2U_0603_6.3V6K

DDR_A_DM7

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_D14
DDR_A_D15

1
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

+VREF_CA

DDR_A_DM1

0.1U_0402_16V4Z

<5> DDR_A_BS2

+VREF_DQ

DDR_A_D12
DDR_A_D13

R397

100_0402_1%

R60
1K_0402_1%

DDR_A_D6
DDR_A_D7

C133

1
<5> DDR_CKE0

R59
1K_0402_1%

<5>

DDR_A_DQS#0 <5>
DDR_A_DQS0 <5>

R396

DDR_A_DM[0..7]

+1.5V

DDR_A_DM[0..7]

+1.5V

4.7U_0603_6.3V6K

DDR_A_D10
DDR_A_D11

<5>

DDR_A_MA[0..15] <5>

<5> DDR_A_DQS#1
<5> DDR_A_DQS1

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_D4
DDR_A_D5

C136

DDR_A_D8
DDR_A_D9

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

0.1U_0402_16V4Z

DDR_A_D2
DDR_A_D3

DDR_A_D[0..63]

CONN@

C135

DDR_A_DM0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1000P_0402_50V7K

DDR_A_D0
DDR_A_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C132

C119

1000P_0402_50V7K

2
D

0.1U_0402_16V4Z

C118

3500 mA

+1.5V
JDIMM1

+VREF_DQ

0.1U_0402_16V4Z

+1.5V

W=20mil

C134

Compal Secret Data

Security Classification
2010/08/12

Issued Date

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


DDR3 SODIMM-I Socket

Size Document Number


Custom
Date:

Rev
1.0

P0VE6 Schematics

Wednesday, November 17, 2010

Sheet
1

of

36

LCD POWER CIRCUIT

About Camera

9/24 Change Q3 to SB000007H10


11/02 Change Q3 PN to SB934130020

+LCDVDD

Q3

+LCDVDD

J1

+3VS

W=40mils

+3VALW

R67

+3VS

AP2301GN-HF_SOT23-3

W=40mils

+CAM_VCC

JUMP_43X39
@

C161
0.1U_0402_16V4Z

0.1U_0402_16V4Z
C162 1

C163 1
4.7U_0603_6.3V6K

6 +LCDVDD_R

C165

100K_0402_5%
1

W=40mils

R68

2 0.047U_0402_16V4Z

D
Q32A
DMN66D0LDW-7_SOT363-6

2
R69

9/15 Remove D1 L5 R71 R72 C166 C167 for layout spacing


C164
4.7U_0603_6.3V6K

470_0402_5%

9/23 Add D1 L5 R71 R72 C166 C167 for ESD

4.7K_0402_5%

8/31 Change R68.2 link to +3VALW


9/23 Remove D1 C166 C167
9/24 Swap L5

8/26 Change Q4 Q5 to Q32A Q32B (SB00000DH00) Standard Part

0_0402_5%

L5
Q32B
DMN66D0LDW-7_SOT363-6

<4> APU_ENVDD

R70
100K_0402_5%

USB20_P5_1

CMOS & LCD/PANEL BD. Conn.

0_0402_5%

0_0402_5%

1 R310

INVT_PWM <25>

EC

1 R311

APU_BLPWM <4>

APU

W=20mil

8/31 Reserve R353 R354 on LVDS_ACLK

0_0402_5%
0_0402_5%

2
2

1 R353
1 R354

LVDS_ACLK <4>
LVDS_ACLK# <4>

LVDS_A2_R
LVDS_A2#_R

0_0402_5%
0_0402_5%

2
2

1 R327
1 R328

LVDS_A2 <4>
LVDS_A2# <4>

R331

0 ohm

0.1uF

R332

0 ohm

0.1uF

INVT_PWM

R381

0 ohm

0.1uF

LVDS_A0_R
LVDS_A0#_R

0_0402_5%
0_0402_5%

2
2

1 R331
1 R332

EDID_DATA_R
EDID_CLK_R
BKOFF#
INVTPWM
+3VS_LVDS
+LCDVDD_L

0_0402_5%
0_0402_5%

2
2

1 R381
1 R382

BKOFF#

R382

0 ohm

9/7 Reserve R381,R382( 0 ohm)R383(100k@) for eDP

LVDS_A1 <4>
LVDS_A1# <4>
LVDS_A0 <4>
LVDS_A0# <4>
EDID_DATA
EDID_CLK

EDID_DATA <4>
EDID_CLK <4>

C168
220P_0402_50V7K
3G@

BKOFF# <25>
1 R334
+LCDVDD

L6
FBMA-L11-201209-221LMA30T_0805
+LEDVDD

L7 2
2

ACES_88341-3000B001
1

CONN@

+3VS

W=20mil

8/22 Reserve R334(0402 0 ohm)


B+

EDID_DATA_R

R383

1 R329
1 R330

100K_0402_5%
R383 1
@
2

2
2

*
eDP

0_0402_5%
0_0402_5%

LVDS

LVDS_A1_R
LVDS_A1#_R

0_0402_5%

1
R72

Display

EDID_CLK_R
LVDS_ACLK_R
LVDS_ACLK#_R

R73
2.2K_0402_5%

8/22 Reserve R327~R332( 0 ohm) for eDP

camera

R75
2.2K_0402_5%
1
2

10/01 Remove R74,R76

USB20_P5 <12>

10/04 Change C401 on INVTPWM

+3VS

9/13 Add Net Name +3VS_DMIC

USB20_P5

100P_0402_50V8J

9/13 Update LVDS Pin definition, Add R74,R76

+CAM_VCC

USB20_N5 <12>

C401
INVTPWM

8/31 Update JLVDS1 Pin definition Delete R74 R76

USB20_P5_1
USB20_N5_1

USB20_N5

10/04 Add 100p(C401) on INVT_PWM

100K_0402_5%
R387 1
2 INVTPWM

JLVDS1

9/17 Change R387 from @ to mount

8/25 JLVDS1.5 change to INT_MIC0 JLVDS1.6 change to GNDA

0_0402_5%

9/9 Reserve 100k PD to GND on INVTPWM

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
3628
3329
3230

WCM2012F2S-900T04_0805

8/26 Change Q3 to SB934130020 Standard Part

USB20_N5_1

1
R71

0.1uF

100k ohm

C169
1000P_0402_50V7K
3G@

R73

2.2k ohm

For RF

R75

2.2k ohm 100k ohm

W=20mil

FBMA-L11-201209-221LMA30T_0805
1
C170
330P_0402_50V7K
3G@

C171
100P_0402_50V8J
3G@

9/3 Pull-Down 10k(R377) to GND on BKOFF#


BKOFF#

R377 1

2 10K_0402_5%

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

LVDS / Camera
Size
B
Date:

Document Number

Rev
1.0

P0VE6 Schematics
Wednesday, November 17, 2010

Sheet
1

of

36

+5VS

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

R77
R78
R79
R80
R81
R82
R83
R84

HDMI_CLKP
HDMI_CLKN
HDMI_TX0P
HDMI_TX0N
HDMI_TX1P
HDMI_TX1N
HDMI_TX2P
HDMI_TX2N

1
1
1
1
1
1
1
1

HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

+5VS

HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN

+5VS

3
1

HDMIDAT_R

@
D2
BAT54S-7-F_SOT23-3

HDMICLK_R

@
D3
BAT54S-7-F_SOT23-3

HDMI_HPD

@
D4
BAT54S-7-F_SOT23-3

EMI/ESD

+3VS

@ L8
2

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_CLK-_CONN

1
R86

HDMI_TX0+_CONN

WCM-2012-900T_4P

1
R87

HDMI_TX0N

HDMI_TX0+_CONN

HDMI_TX0-_CONN

1
R88

HDMI_TX1+_CONN

1
R89

HDMI_TX1-_CONN

1
R90

HDMI_TX2+_CONN

WCM-2012-900T_4P

1
R91

HDMI_TX2-_CONN

@ L10
1

HDMI_TX1N

1
4

HDMI_TX1+_CONN

HDMI_TX1-_CONN

1
R93

499_0402_1%
499_0402_1%
499_0402_1%

2
3

@
R95
100K_0402_5%

HDMI_TX2+_CONN
HDMI_TX2-_CONN

NEAR CONNECT

D
Q7
SSM3K7002FU_SC70-3

2
G
S

2 0_0402_5%

@
R94

8/19 Change Q9A Q9B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

HDMI@

10/29 Add C409~C412(0.1U) on +5VS_HDMI

10/29 Add C415~C416(0.1U) on +5VS_HDMI_F

HDMI_TX2N

HDMIDAT_R

Q9B
DMN66D0LDW-7_SOT363-6
HDMI@
@
0_0402_5%
1
2
R92

499_0402_1%

+5VS

@ L11
1

<4> HDMI_DATA

WCM-2012-900T_4P
HDMI_TX2P

499_0402_1%

HDMI_TX1P

Q9A
DMN66D0LDW-7_SOT363-6
HDMI@

499_0402_1%
499_0402_1%

HDMICLK_R

499_0402_1%

HDMI_TX0-_CONN

@ L9
HDMI_TX0P

2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@

R85
HDMI_CLKN

<4> HDMI_CLK

HDMI_CLK+_CONN

HDMI_CLKP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

HDMI@
2
1 C410

0.1U_0402_16V4Z

HDMI@
1 C411

0.1U_0402_16V4Z

HDMI@
1 C412

+5VS_HDMI

1 C409

0.1U_0402_16V4Z

0.1U_0402_16V4Z

HDMI@
2
1 C416

+5VS_HDMI_F

1 C415

WCM-2012-900T_4P

8/26 Change Q7 to SB000009610 Standard Part

HDMI@

+5VS

W=60mil

9/20 Add F2 on HDMI


@
R96
0_0805_5%

HDMI@
D5
RB491D_SC59-3
1

10/27 Change D5 P/N from SC1B491D000 to SCS00003H00

HDMI@

10/27 Change F2 P/N from SP04301P120 to SP040001B00

+3VS

HDMI_DET

HDMIDAT_R
HDMICLK_R
HDMI_HPD

HDMI_CLK+_CONN
HDMI_TX0-_CONN

@
R102
100K_0402_5%

HDMI_TX0+_CONN
HDMI_TX1-_CONN

@
R101
200K_0402_5%
R103
100K_0402_5%
HDMI@

HDMI_CLK-_CONN

1
3

R100
1
2
150K_0402_5%
HDMI@

<4>

2
B

JHDMI1
HDMI_HPD
+5VS_HDMI_F

10/28 Change JHDMI1 footprint from


ACON_HMR2E-AK120D_19P-T to ACON_HMR2E-AK120D_19P-S

F2 HDMI@
1.1A_6V_SMD1812P110TF

0_0402_5%
@

C
HDMI@ Q8
MMBT3904_NL_SOT23-3

C172
0.1U_0402_16V4Z
HDMI@
B

HDMI@
R98
2.2K_0402_5%
2

9/20 Change Q8,R100 from @ to HDMI@


R99

2
HDMI@
R97
2.2K_0402_5%

+5VS_HDMI

W=60mil

9/20 Change R99 from HDMI@ to @

10/07 Update JHDMI1 footprint from ACON_HMR2E-AK120D_19P


to ACON_HMR2E-AK120D_19P-T

HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

ACON_HMR2E-AK120D
CONN@
A

8/23 Update JHDMI1 Symbol (SUYIN_100042GR019S268ZR_19P-T)


8/23 Update JHDMI1 Symbol (SUYIN_100042GR019M23DZL_19P-T)
9/7 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P)

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

HDMI Connector
Size Document Number
Custom
Date:

Rev
1.0

P0VE6 Schematics

Wednesday, November 17, 2010

Sheet
1

of

36

D6

Close to CRT CONN for ESD.

D7
@

1
L12
1

<4> DAC_RED

L13
<4> DAC_GRN

<4> DAC_BLU

+5VS

1
C177

CHENG-HANN MBK1005470YZF 0402


2

RED

CHENG-HANN MBK1005470YZF 0402


2

GREEN

CHENG-HANN MBK1005470YZF 0402


2

BLUE

1
1

C178
10P_0402_50V8J

C176

10P_0402_50V8J

R106

10P_0402_50V8J

R105

150_0402_1%
2
1

R104

150_0402_1%
2
1

150_0402_1%
2
1

L14

Change L12. L14, L15 to SM01000C600 2010/04/06

PJDLC05C_SOT23-3

0615

PJDLC05C_SOT23-3

Modify C31- C308 C303 C307 C306 C304 BOM Structure

C173
10P_0402_50V8J
2

C174
10P_0402_50V8J
2

C175
10P_0402_50V8J

JVGA_HS
1
C179

2
0.1U_0402_16V4Z
JVGA_VS

U2

IN A

GND

Vcc

OUT Y

CRT_HSYNC_R

R375 1

+3VS

2 39_0402_5%

TC7SET125FUF_SC70-5

0_0402_5%

8/31 Delete Net Name: CRT_HSYNC_1, CRT_VSYNC_1

CRT_DET

CRT_DET
+5VS

8/21 Change U2 U3 to SA00000RZ00 (TC7SET125FUF_SC70-5)

1
C180

R325 1

R107
10K_0402_5%
@

High: CRT Plugged

9/3 Add R375 R376 for CRT

CRT_DET#

2
0.1U_0402_16V4Z

<4> CRT_HSYNC

Q10
SSM3K7002FU_SC70-3

2
G

U3
1

<4> CRT_VSYNC

Vcc

CRT PORT

IN A

GND

CRT_VSYNC_R

OUT Y

R376 1

2 39_0402_5%

8/26 Change Q10 to SB000009610 Standard Part


8/22 Update JCRT1 Symbol from database (SUYIN_070546FR015M21TZR_15P)

+CRT_VCC
+5VS

TC7SET125FUF_SC70-5

0.1U_0402_16V4Z

D8

8/21 Reserve R325 R326 for CRT buffer cost down

2
R326 1

W=40mils
1

RB491D_SC59-3

8/26 Update D8 P/N to SCS00003H00

+CRT_VCC_F

JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

VGA_DDC_DAT
GREEN

JVGA_VS
CRT4

R108
R110

R111
VGA_DDC_CLK
2.2K_0402_5%
2

2.2K_0402_5%
2

11/01 Add Net CRT4, CRT11 on JCRT.4 , JCRT.11

1.1A_6VDC_FUSE

JVGA_HS
BLUE

2.2K_0402_5%

+CRT_VCC_F 1

CRT11
RED

10/4 Change from +CRT_VCC to +CRT_VCC_F


+3VS

R109

C181
2

0_0402_5%

+3VS

2.2K_0402_5%

F1
1

CRT_DET#
2

R112
100K_0402_5%

VGA_DDC_CLK

<4> CRT_DDC_CLK

VGA_DDC_DAT

Q11B
DMN66D0LDW-7_SOT363-6

16
17

SUYIN_070546FR015M21TZR
CONN@

8/26 Update F1 P/N to SP040001B00


4

<4> CRT_DDC_DATA

G
G

Q11A
DMN66D0LDW-7_SOT363-6

8/19 Change Q11A Q11B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

+CRT_VCC

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

CRT PORT
Size
B
Date:

Document Number

P0VE6 Schematics
Wednesday, November 17, 2010

Sheet
E

10

of

36

Rev
1.0

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
AA22
Y21
AA25
AA24
W23
V24
W24
W25

PCIE_FRX_DTX_P1
PCIE_FRX_DTX_N1
PCIE_FRX_DTX_P2
PCIE_FRX_DTX_N2
PCIE_FRX_DTX_P3
PCIE_FRX_DTX_N3

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N
PCIE_CALRP
PCIE_CALRN
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

9/6 Change PCI-E from FCH to APU


9/15 Change PCI-E from APU to FCH
close to FCH within 1"

8/25 Update JBATT1 Symbol (LOTES_AAA-BAT-019-K01_2P)


<4>
<4>

+RTCBATT1

R125 1
R126 1

DISP_CLK
DISP_CLK#

2 0_0402_5%
2 0_0402_5%

M23
P23

DISP_CLK_R
DISP_CLK#_R

T26
T27
CONN@
JBATT1

<4>
<4>

R127 1
R128 1

APU_CLK
APU_CLK#

2 0_0402_5%
2 0_0402_5%

APU_CLK_R
APU_CLK#_R

N29
N28

LAN

<17> CLK_PCIE_LAN
<17> CLK_PCIE_LAN#

WLAN

<20> CLK_PCIE_WLAN
<20> CLK_PCIE_WLAN#

R134 1
R135 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R

WWAN

<19> CLK_PCIE_WWAN
<19> CLK_PCIE_WWAN#

R348 1
R349 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_WWAN_R M29
CLK_PCIE_WWAN#_R M28

LOTES_AAA-BAT-019-K01

8/23 Add R348 R349 for WWAN PCIE

+CHGRTC

+RTCBATT

9/13 Add NONCHARGE@ for D10 R244

2
1

W=20mil

9/1 Add R372 on CLK_48M_CR


9/7 Change R372 to 22 ohm

C198
22P_0402_50V8J

C199
22P_0402_50V8J
1
2

Y2

GPP_CLK5P
GPP_CLK5N

P29
P28

GPP_CLK6P
GPP_CLK6N

N26
N27

GPP_CLK7P
GPP_CLK7N

T29
T28
L25

1M_0603_5%
25M_CLK_X2
R139

L27

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME_L
LDRQ0_L
LDRQ1_L/CLK_REQ6_L/GPIO49
SERIRQ/GPIO48

GPP_CLK8P
GPP_CLK8N

ALLOW_LDTSTP/DMA_ACTIVE_L
PROCHOT_L
LDT_PG
LDT_STP_L
LDT_RST_L

H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19

10/08 Change R392 from 0 ohm to 1k ohm

10K_0402_5%

R113
2

R136 1

2 0_0402_5%

LPCCLK0 <15>

R137 1
R138 1

2 22_0402_5%
2 0_0402_5%

LPC_CLK0_EC <25>
CLK_PCI_DB <15>

LPC_AD0 <25>
LPC_AD1 <25>
LPC_AD2 <25>
LPC_AD3 <25>
LPC_FRAME# <25>

10/04 Add 100p(C396) on H_PWRGD_L

SERIRQ <25>

G21
H21
K19
G22
J24

ALLOW_STOP# <4>
FCH_PROCHOT# <4>
APU_PWRGD <4>

11/15 Delete net U5_G22

LDT_RST# <4>

14M_25M_48M_OSC

25M_X1

25M_X2

32K_X1

C1

RTC_32KHI

32K_X2

C2

RTC_32KHO

RTCCLK
INTRUDER_ALERT_L
VDDBT_RTC_G

D2
B2
B1

10/07 Change R140 from 560 to 1k ohm


11/01 Add Net U5_G22 on U5.G22
SUSCLK <25>
+RTCBATT_R

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

SA000046HA0

8/25 Change FCH(U5) PN to SA000046H30

10/07 Change R392 from 1k to 0 ohm


3

GPP_CLK4P
GPP_CLK4N

L26

25MHZ_20PF_7A25000012

+RTCBATT

L24
L23
P25
M25

INTE_L/GPIO32
INTF_L/GPIO33
INTG_L/GPIO34
INTH_L/GPIO35

1
+RTCBATT2
R392
CHARGE@

GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N

25M_CLK_X1

+RTCBATT2_R 2
0_0402_5%

GPP_CLK1P
GPP_CLK1N

RTC

9/13 Change Net Name +RTCBATT1 to +RTCBATT2

2 22_0402_5%CLK_48M_CR_R

R372 1

<18> CLK_48M_CR

9/13 Add Net Name +RTCBATT1_RR

GPP_CLK0P
GPP_CLK0N

CPU

+RTCBATT1_R 1
2
R244
1K_0402_5%
BAV70W_SOT323-3
NONCHARGE@
NONCHARGE@
3

SLT_GFX_CLKP
SLT_GFX_CLKN

T25
V25

+RTCBATT1

D10

CPU_HT_CLKP
CPU_HT_CLKN

LPC

9/6 Change D10 to SC600000B00 Standard Part

NB_HT_CLKP
NB_HT_CLKN

11/04 Change U5 PN to SA000046HA0 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA)

1
R140

+RTCBATT
2
1K_0402_5%

W=20mil

C200
2

CLRP1 @
SHORT PADS

for Clear CMOS

BAS40-04_SOT23-3
1

+CHGRTC
CHARGE@
C392
0.1U_0402_16V4Z

11/01 Change R392 from 1k to 0 ohm

Compal Secret Data

Security Classification
2010/08/12

Issued Date

9/13 Add C392,R392,D23(CHARGE@) for RTC Charge Circuit

L29
L28

NB_DISP_CLKP
NB_DISP_CLKN

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

CLOCK GENERATOR

2 0_0402_5%
2 0_0402_5%

R132 1
R133 1

D23

V21
T21
V23
T23

8/21 Delete R130,R131(No VGA)

U29
U28

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0_L
CBE1_L
CBE2_L
CBE3_L
FRAME_L
DEVSEL_L
IRDY_L
TRDY_L
PAR
STOP_L
PERR_L
SERR_L
REQ0_L
REQ1_L/GPIO40
REQ2_L/CLK_REQ8_L/GPIO41
REQ3_L/CLK_REQ5_L/GPIO42
GNT0_L
GNT1_L/GPO44
GNT2_L/GPO45
GNT3_L/CLK_REQ7_L/GPIO46
CLKRUN_L
LOCK_L

PCI I/F

WWAN
LAN
WLAN

<19>
<19>
<17>
<17>
<20>
<20>

PCIE_FTX_DRX_P1
PCIE_FTX_DRX_N1
PCIE_FTX_DRX_P2
PCIE_FTX_DRX_N2
PCIE_FTX_DRX_P3
PCIE_FTX_DRX_N3

AD29
AD28

PAD T17

AA1
AA4
AA3
AB1
AA5
AB2
9/9 Change R117 R122 from mount to @
AB6
9/15 PU PE_GPIO1 100k to +5VALW
AB5
AA6
+5VALW
AC2
AC3
AC4
PE_GPIO1 R117 1
AC1
2 100K_0402_5%
AD1
PE_GPIO0 R122 1
@
AD2
2 100K_0402_5%
AC6
AE2
AE1
AF8
10/11 Change Y1 from SJ100006600 to SJ132P7KW10
AE3
AF1
PE_GPIO0
AG1
Close to FCH
AF2
AE9
PCI_AD23 <15>
@R123
@
R123 20M_0402_5%
AD9
PCI_AD24 <15>
AC11
1
2
PCI_AD25 <15>
AF6
PCI_AD26 <15>
AF4
PCI_AD27 <15>
C196
AF3
RTC_32KHO
AH2
1
2
AG2
Y1
22P_0402_50V8J
AH3
AA8
4 OSC
NC 3
R124
AD5
20M_0603_5%
AD8
1 OSC
NC 2
AA10
32.768KHZ_12.5PF_9H03200413
AE8
C197
AB9
RTC_32KHI
AJ3
1
2
AE7
22P_0402_50V8J
AC5
AF5
AE6
AE4
10/05 PD 10k(R405) on CLKRUN
AE11
+1.8VS
+3VS
AH5
AH4
AC12 GPIO42
PAD T18
R129
AD12
10K_0402_5%
AJ5
PE_GPIO1
AH6
R405
AB12 GPIO46
PAD T19
AB11
1
2
APU_PWRGD
AD7
3
1
H_PWRGD_L <35>
2
10K_0402_5%
AJ6
FDV301N_NL_SOT23-3
C396
AG6
Q12
AG4
100P_0402_50V8J
1
AJ4
1

2
2
2
2
2
2

PCIE_CALRP
PCIE_CALRN

PCI_CLK3 <15>
PCI_CLK4 <15>

V2

1
1
1
1
1
1

590_0402_1%
2K_0402_1%

PCI_CLK1 <15>

C192
C193
C194
C195
C379
C380

PCIE_FTX_C_DRX_P1
PCIE_FTX_C_DRX_N1
PCIE_FTX_C_DRX_P2
PCIE_FTX_C_DRX_N2
PCIE_FTX_C_DRX_P3
PCIE_FTX_C_DRX_N3

1
1

PCIRST_L

PAD T16
PCI_CLK2

2
2

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

W2
W1
W3
W4
Y1

<19>
<19>
<17>
<17>
<20>
<20>

R121
R118

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

+PCIE_VDDAN

AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24

PCIE_RST_L
A_RST_L

Watchdog timer on NB_PWRGD


enable for pull-up
disable for pull-down
20100527

9/27 Change R115 from @ to mount

AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

UMI_RX0P_C
UMI_RX0N_C
UMI_RX1P_C
UMI_RX1N_C
UMI_RX2P_C
UMI_RX2N_C
UMI_RX3P_C
UMI_RX3N_C

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

2
2
2
2
2
2
2
2

R116

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

1
1
1
1
1
1
1
1

2 0_0402_5% P1
2 0_0402_5% L1

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

C184
C185
C188
C186
C187
C189
C190
C191

PCI EXPRESS I/F

9/2 Change R120 from 0603 to 0402


9/16 Change U4,C182 from @ to mount,
R120, R115 from mount to @

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

U5E
R384 1
R385 1

1 33_0402_5%

1U_0402_6.3V6K

2
1

2 0_0402_5%

R119

PCI CLKS

A_RST#

R115
100K_0402_5%

150P_0402_50V8J
2
1 C183

PLT_RST# <17,19,20,25>

NC7SZ08P5X_NL_SC70-5

CHARGE@

+3VS

10K_0402_5%

5
A

PLT_RST#

R120 1

R114
8.2K_0402_5%
@

10/08 Update U5 to SA000046H70 S IC 218-0792006 A13 HUDSON-M1 605P ABO!

9/20 C183.2 link to R119.2 Follow CRB

U4

A_RST#

9/9 Add R384(@ 0 ohm) R385(0 ohm) on PCI-E RST

0.1U_0402_16V4Z
2

+3VALW

C182

Deciphered Date

2012/08/12

Compal Electronics, Inc.


FCH PCIE/PCI/ACPI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

Size Document Number


Custom
Date:

Rev
1.0

P0VE6 Schematics

Wednesday, November 17, 2010

Sheet
E

11

of

36

+3VALW

8/21 Delete Net : KILL_SW#

USB_OC7#
2
10K_0402_5%
EC_LID_OUT#
2
10K_0402_5%
USB_OC5#
2
10K_0402_5%
USB_OC4#
2
10K_0402_5%
USB_OC3#
2
10K_0402_5%

U5A

<25>

PCI_PME#

<25> SLP_S3#
<25> SLP_S5#
<25> PBTN_OUT#

FCH_PWRGD

WWAN_CLKREQ#
2
10K_0402_5%
LAN_CLKREQ#
2
10K_0402_5%
WLAN_CLKREQ#
2
10K_0402_5%
NB_PWRGD
2
4.7K_0402_5%
FCH_SMCLK0
2
2.2K_0402_5%
FCH_SMDAT0
2
2.2K_0402_5%

<25>
<25>
<25>
<25>
+3VALW
150P_0402_50V8J
2
1 C417

R148 1

GATEA20
KB_RST#
EC_SCI#
EC_SMI#

2 10K_0402_5%

<17,19,20> FCH_PCIE_WAKE#
H_THERMTRIP#

<4> H_THERMTRIP#

NB_PWRGD

G1

<25> EC_RSMRST#

8/31 Pull up 10k(R359) to +3VS on WWAN_CLKREQ#


R159 2

11/15 Add C417(150p) on H_THERMTRIP#

1 0_0402_5%

R160 2

<17> LAN_CLKREQ#

1 0_0402_5%

8/31 Delete Net : SATA_DET#

<19> WWAN_CLKREQ#
<20> WLAN_CLKREQ#

P
G

5
2

C202
1 .1U_0402_16V7K

ICH_POK <25>

VGATE

<25,35>

NC7SZ08P5X_NL_SC70-5
U6 @

8/22 Delete Net : R161 R162

USB_OC7#

9/6 Change ODD_DETECT# to USB_OC3#


<24> USB_OC1#
<24> USB_OC0#

FCH_SMCLK1

EC_RSMRST#

R166 1
R168 1

<16> HDA_BITCLK_AUDIO
<16> HDA_SDOUT_AUDIO
<16> HDA_SDIN0

HDA_BITCLK

2 33_0402_5%
2 33_0402_5%

HDA_SDOUT

2 33_0402_5% HDA_SYNC
2 33_0402_5% HDA_RST#

R173 1
R174 1

<16> HDA_SYNC_AUDIO
<16> HDA_RST_AUDIO#

R177

R181

+3VALW

T23
T24

GPIO189
GPIO190
GPIO191
GPIO192
1

F11
E11

USB_HSD11P
USB_HSD11N

E14
E12

USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N

9/15 Update USB Port List


9/1 Update USB Port List
8/23 USB port8 link to SIM

J12
J14
A13
B13
D13
C13
G12
G14
G16
G18

USB_HSD5P
USB_HSD5N

D16
C16

USB_HSD4P
USB_HSD4N

B14
A14

USB_HSD3P
USB_HSD3N

E18
E16

USB_HSD2P
USB_HSD2N

J16
J18

USB_HSD1P
USB_HSD1N

B17
A17

USB20_P9 <19>
USB20_N9 <19>

WWAN

USB20_P8 <20>
USB20_N8 <20>

WiMax

USB20_P7 <19>
USB20_N7 <19>

Bluetooth

USB20_P6 <18>
USB20_N6 <18>

Card Reader

USB20_P5 <8>
USB20_N5 <8>

Camera

USB20_P4 <19>
USB20_N4 <19>

SIM

USB20_P3 <19>
USB20_N3 <19>

WWAN

USB20_P2 <24>
USB20_N2 <24>

USB Conn.(LS) JUSB1

USB20_P1 <24>
USB20_N1 <24>

USB Conn.(RS) JUSB3

USB20_P0 <24>
USB20_N0 <24>

USB Conn.(RS) JUSB2

A16
B16

10/07 Add R406~R410 (GPIO189~190) for Board ID


10/07 Add E6@(R406) & S6@(R407) for Board ID
10/27 Change R408 R410 from @ to mount

PAD
PAD

T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7

GPIO187 E23
GPIO188 E24
F21
G29
GPIO189
GPIO190
GPIO191
GPIO192

D27
F28
F29
E27

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST_L
GBE_PHY_INTR
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2_L/GBE_STAT2/GPIO166
FC_RST_L/GPO160

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

D25
F23
B26
E26
F25
E22
F22
E21

GPIO193
GPIO194

R167 2
R169 2

1 10K_0402_5%
1 10K_0402_5%
FCH_SIC <4>
FCH_SID <4>

EC_PWM2
EC_PWM3

Internal Pull-Up available

G24
G25
E28
E29
D29
D28
C29
C28
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

+3VALW
3

8/31 Change R182 from mount to @


Change R183 from @ to mount

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

EC_PWM3 EC_PWM2

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

10/28 Add R413 R414 on GPIO192 for project ID


11/15 Change R408,R410,R413 P/N from 10k to 1k SD028100280 to SD028100180

R406

R407

mount

mount
B

SPI ROM

NC

NC

Reserved

Reserved

LPC ROM

2010/08/12

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

P0VS6

ROM TYPE

NC

Board ID
P0VE6

EC_PWM3
EC_PWM2

9/15 Change R178 from @ to mount

R413
R407
R408
R410
1K_0402_5% 10K_0402_5% 1K_0402_5% 1K_0402_5%
S6@
2

2 10K_0402_5%

M3
N1
L2
M2
M1
M4
N2
P2

GBE LAN

2 10K_0402_5%

R414
@ R406
R409
@ R411
@
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
E6@

2 10K_0402_5%
2 10K_0402_5%

2 10K_0402_5%

R180

B12
A12

USB_HSD12P
USB_HSD12N

USB_HSD0P
USB_HSD0N

EMBEDDED CTRL

R175 1
R176 1
+3VALW

+3VALW

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

HDA_SDIN0

+3VALW

USB_HSD13P
USB_HSD13N

FCH_SMDAT1

Pull-down for enable high performance mode


20100527 (required for M1)

+3VALW

BLINK/USB_OC7_L/GEVENT18_L
USB_OC6_L/IR_TX1/GEVENT6_L
USB_OC5_L/IR_TX0/GEVENT17_L
USB_OC4_L/IR_RX0/GEVENT16_L
USB_OC3_L/AC_PRES/TDO/GEVENT15_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC0_L/TRST_L/GEVENT12_L

2
11.8K_0402_1%

10K_0402_5%
1
2
R179

USB_OC5#
USB_OC4#
USB_OC3#
USB_OC2#

USB_RCOMP 1

2.2K_0402_5%
2
1
R183

2
10K_0402_5%
2
10K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

<25> EC_LID_OUT#

USB_FSD0P/GPIO185
USB_FSD0N

H9
J8

USB_HSD8P
USB_HSD8N

HD AUDIO

1
R163
1
R164
1
R165
1
R170
1
R171
1
R172

9/6 Change ODD_DA#_FCH to USB_OC4#

J10
H11

USB_HSD9P
USB_HSD9N

USB OC

10/04 Add 100p(C397) on FCH_PWRGD

H3
D1
E4
D4
E8
F7
E7
F8

R146
G19

USB_FSD1P/GPIO186
USB_FSD1N

USB_HSD10P
USB_HSD10N

CLK_REQ4_L/SATA_IS0_L/GPIO64
CLK_REQ3_L/SATA_IS1_L/GPIO63
SMARTVOLT1/SATA_IS2_L/GPIO50
CLK_REQ0_L/SATA_IS3_L/GPIO60
SATA_IS4_L/FANOUT3/GPIO55
SATA_IS5_L/FANIN3/GPIO59
SPKR_GPIO66
SCL0_GPIO43
SDA0_GPIO47
SCL1_GPIO227
SDA1_GPIO228
CLK_REQ2_L/FANIN4_GPIO62
CLK_REQ1_L/FANOUT4_GPIO61
IR_LED_L/LLB_L/GPIO184
SMARTVOLT2/SHUTDOWN_L/GPIO51
DDR3_RST_L/GEVENT7_L
GBE_LED0/GPIO183
GBE_LED1/GEVENT9_L
GBE_LED2/GEVENT10_L
GBE_STAT0/GEVENT11_L
CLK_REQG_L/GPIO65_OSCIN

A10

10K_0402_5%
1
2
R178

C397
100P_0402_50V8J

RSMRST_L

USB 2.0

USB_RCOMP

10mils and <1"

GPIO

<16> FCH_SPKR
<7,19,20> FCH_SMCLK0
<7,19,20> FCH_SMDAT0

+3VS @
C201 .1U_0402_16V7K
1
2

<35> FCH_PWRGD

AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
FCH_SMCLK1
F5
FCH_SMDAT1
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20

USBCLK/14M_25M_48M_OSC

2.2K_0402_5%
2
1
R182

1
R359
1
R155
1
R156
1
R157
1
R149
1
R158

T20PAD
T21PAD
T22PAD

PCI_PME_L/GEVENT4_L
RI_L/GEVENT22_L
SPI_CS3_L/GBE_STAT1/GEVENT21_L
SLP_S3_L
SLP_S5_L
PWR_BTN_L
PWR_GOOD
SUS_STAT_L
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0_L
KBRST_L/GEVENT1_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L
GEVENT5_L
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
IR_RX1/GEVENT20_L
THRMTRIP_L/SMBALERT_L/GEVENT2_L
NB_PWRGD

USB 1.1

9/20 Change R145,R147 from @ to mount

J2
K1
D3
F1
H1
F2
H5
G6
B3
C4
F6
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
AC19

USB MISC

+3VS

1
R142
1
R144
1
R151
1
R152
1
R153

ACPI/WAKE UP EVENTS

USB_OC2#
2
10K_0402_5%
USB_OC1#
2
10K_0402_5%
USB_OC0#
2
10K_0402_5%
FCH_SIC
2
10K_0402_5%
FCH_SID
2
10K_0402_5%
FCH_PCIE_WAKE#
2
10K_0402_5%

1
R141
1
R143
1
R150
1
R145
1
R147
1
R154

Title

FCH HDA/USB/ACPI
Size Document Number
Custom
Date:

Rev
1.0

P0VE6 Schematics

Thursday, November 18, 2010

Sheet
E

12

of

36

U5B

AJ8
AH8

<21> SATA_DTX_C_IRX_N0
<21> SATA_DTX_C_IRX_P0

AH10
AJ10

SATA_TX1P
SATA_TX1N

AG10
AF10

SATA_RX1N
SATA_RX1P

AG12
AF12

SATA_TX2P
SATA_TX2N

AJ12
AH12

SATA_RX2N
SATA_RX2P

AH14
AJ14

SATA_TX3P
SATA_TX3N

AG14
AF14

SATA_RX3N
SATA_RX3P

AG17
AF17
AJ17
AH17
AJ18
AH18
AH19
AJ19

10 mils and < 1"


+AVDD_SATA

R184
R185

2 1K_0402_1%
2 931_0402_1%

1
1

SATA_CALRP
SATA_CALRN

AD11

<21> HDD_LED#
R190 1

25M_SATA_X1 AD16

@ C209
22P_0402_50V8J
@ C210
22P_0402_50V8J
1
2

SATA_TX5P
SATA_TX5N
SATA_RX5N
SATA_RX5P
SATA_CALRP
SATA_CALRN
SATA_ACT_L/GPIO67

25M_SATA_X2 AC16

SATA_X1

SATA_X2

GPIO161

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
ROM_RST_L/GPIO161

SPI ROM

T25 PAD

J5
E2
K4
K9
G2

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

1M_0603_5%
R195

25MHZ_20PF_7A25000012

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174
TEMP_COMM

@
Y3

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

SATA_RX4N
SATA_RX4P

2 10K_0402_5%

+3VS

AB14
AA14

SATA_TX4P
SATA_TX4N

FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146
FC_WE_L/GPIOD148
FC_CE1_L/GPIOD149
FC_CE2_L/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147

HW MONITOR

9/7 Change SATA_CALRN from +1.1VS to +AVDD_SATA

SATA_RX0N
SATA_RX0P

SERIAL ATA

FC_CLK
FC_FBCLKOUT
FC_FBCLKIN

GPIOD

8/21 Delete C205~C208 (No ODD ESATA function)

SATA_TX0P
SATA_TX0N

NC1
NC2

AH28
AG28
AF26

11/01 Add Net U5_AE29 on U5.AE29

AF28
AG29
AG26
AF27
AE29
AF29
AH27

11/15 Delete net U5_AE29

AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

+3VS
2

SATA_ITX_C_DRX_P0 AH9
SATA_ITX_C_DRX_N0 AJ9

@
GPIO56

W5
W6
Y9
W7
V9
W8

R415
10K_0402_5%

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
1

C203
C204

<21> SATA_ITX_DRX_P0
<21> SATA_ITX_DRX_N0

8/21 Delete Net : ODD_EN


8/22 Delete Net : BT_OFF#, WL_OFF#

R416
10K_0402_5%

HDD

10/29 Add R415(@), R416(@) on GPIO56

GPIO56

B6
A6
A5
B5
C7

TEMPIN0 R186 2
TEMPIN1 R187 2
TEMPIN2 R188 2
R189 2

1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

A3
B4
A4
C5
A7
B7
B8
A8

GPIO175
GPIO176
GPIO177
GPIO178
GPIO179
GPIO180
GPIO181
GPIO182

1
1
1
1
1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

9/9 Change R189 from mount to @


9/15 Change R189 from @ to mount
APU_ALERT#_FCH <4>

R191
R192
R193
R194
R196
R197
R198
R199

2
2
2
2
2
2
2
2

VIN6/GBE_STAT3/GPIO181
Enable integrated pull-down/up and leave unconnected

G27
Y2

C406 1

2 100P_0402_50V8J

APU_ALERT#_FCH

10/05 Add 100p(C406) on APU_ALERT#_FCH

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

8/31 remove FCH SPI ROM

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

FCH-SATA/SPI
Size Document Number
Custom
Date:

P0VE6 Schematics

Wednesday, November 17, 2010

Sheet
E

13

of

36

Rev
1.0

.1U_0402_16V7K

C249

C250

2.2U_0603_6.3V6K

L20
2

+VDDAN_11_USB C11
D11

VDDPL_33_USB_S

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

VDDAN_33_HWM_S
VDDXL_33_S

C259 1

L25
2
1
FBMA-L11-160808-221LMT_2P
HWM@

2 2.2U_0603_6.3V6K
HWM@ C260

L25
+VDDPL33
L27
+3VS

2
1
FBMA-L11-160808-221LMT_2P
C262 1

2 2.2U_0603_6.3V6K

58mA

A11
B11

C257

10U_0603_6.3V6M

C238

22U_0805_6.3V6M

C228

C227

1U_0402_6.3V6K

2.2U_0603_6.3V6K

R347
2
0_0603_5%

C223

+3VALW
2

+1.1VALW

46mA

+VDDPL11

65mA

F19

+AVDD_USB

16mA

D6

+VDDAN33_HWM
1

L19
1

+1.1VALW

0_0805_5%

12mA

L21

+VDDXL_33_S

L20

+3VS

FBMA-L11-160808-221LMT_2P

+VDDIO_AZ

+3VALW
+1.5V
1
R209

2
0_0603_5%
1
2
R210
@
0_0603_5%

C258
2.2U_0603_6.3V6K

For 3V AZ device

9/3 Change L26 to L25(NONHWM@)

Compal Electronics, Inc.

Compal Secret Data


2010/08/12

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

10U_0603_6.3V6M

C221

C220

1U_0402_6.3V6K

C219
C226

1U_0402_6.3V6K

.1U_0402_16V7K

+VDDPL33

L22

Issued Date

SD013000080

1U_0402_6.3V6K

C218

+VDDIO_AZ

M21

.1U_0402_16V7K

+VDDCR_11_USB

5mA

.1U_0402_16V7K

C256

C225

.1U_0402_16V7K

15mA

M8

Security Classification

0_0603_5%

NONHWM@

8/25 Change C222 from poly-cap to E-cap (SF000002Z00)

C248

F26
G26

+VDDAN33_HWM
+3VALW

C261

L24
2
1
FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

+VDDPL11
+1.1VALW

C255

C254

1U_0402_6.3V6K

1U_0402_6.3V6K

2 2.2U_0603_6.3V6K

.1U_0402_16V7K

C252 1

22U_0805_6.3V6M

2
1
FBMA-L11-160808-221LMT_2P

SF000002Z00

165mA

L22
2
1
FBMA-L11-201209-221LMA30T_0805

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

C253

+3VS

+1.1VS

.1U_0402_16V7K

.1U_0402_16V7K

C217

+VDDIO_33_S

A21
D21
B21
K10
L10
J9
T6
T8

+AVDD_SATA
+VDDPL_33_SATA

+1.1VS

8/23 Add R346 R347, +VDDIO_33, +VDDIO_33_S

L23

10U_0603_6.3V6M

VDDPL_11_SYS_S

L15 2

FBMA-L11-201209-221LMA30T_0805

C247

VDDPL_33_SYS

PLL

88mA

FBMA-L11-160808-221LMT_2P

M6
P8

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

M10

VDDIO_GBE_S_1
VDDIO_GBE_S_2

VDDIO_AZ_S

C222
330U_2.5V_M

V1

L7
L9

VDDCR_11_S_1
VDDCR_11_S_2

.1U_0402_16V7K

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

.1U_0402_16V7K

C245

C244

.1U_0402_16V7K

1U_0402_6.3V6K

C243

C242

1U_0402_6.3V6K

10U_0603_6.3V6M

C241

A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19

USB I/O

10U_0603_6.3V6M

FBMA-L11-201209-221LMA30T_0805

C246

+AVDD_USB

49mA

CORE S5

L18

+1.1VS

+VDDAN_11_CLK

K28
K29
J28
K26
J21
J20
K21
J22

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

C240

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7

1U_0402_6.3V6K

VDDPL_33_SATA

AJ20
AF18
AH20
AG19
AE18
AD18
AE16

534mA

+1.1VALW

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

+VDDPL_33_SATA AD14

1354mA

+3VALW

U26
V22
V26
V27
V28
V29
W22
W26

382mA

15mA
+AVDD_SATA

VDDPL_33_PCIE

2.2U_0603_6.3V6K

1115mA
+PCIE_VDDAN

AE28

1U_0402_6.3V6K

+VDDPL33_PCIE

+1.1VS
1

C237

C232

C236

C235

VDDRF_GBE_S
VDDIO_33_GBE_S

N13
R15
N17
U13
U17
V12
V18
W12
W18

C239

.1U_0402_16V7K

1U_0402_6.3V6K

C234

C233

2
1
FBMA-L11-201209-221LMA30T_0805

22U_0805_6.3V6M

L17

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

22mA

3.3V_S5 I/O

2
+1.1VS

VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4

GBE LAN

AF22
AE25
AF24
AC22

SERIAL ATA

2
1
FBMA-L11-160808-221LMT_2P

+3VS

0.15mA

PCI EXPRESS

L16

.1U_0402_16V7K

2.2U_0603_6.3V6K

.1U_0402_16V7K

C231

.1U_0402_16V7K

C229

C230

1
R208

0_0402_5%

FLASH I/O

4.7U_0603_6.3V6K

+VDDIO_18_FC

2
0_0603_5%

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

2.2U_0603_6.3V6K

.1U_0402_16V7K

C216

.1U_0402_16V7K

C215

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12

CLKGEN I/O

R207
1

GPIO I/F implemented: tied to +1.8V_S0


GPIO I/F not implemented: tied to
+1.8V_S0 or 0 ohm to ground

+1.8VS

C214

C213

790mA

POWER

U5C
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19

PCI/GPIO I/O

.1U_0402_16V7K

+VDDIO_33

C224

42mA

R346
2
0_0603_5%

CORE S0

22U_0805_6.3V6M

+3VS

C251

Title

FCH PWR
Size Document Number
Custom
Date:

Rev
1.0

P0VE6 Schematics

Wednesday, November 17, 2010

Sheet
E

14

of

36

U5D

VSSXL

P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23

VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13

VSSPL_SYS

PCI_CLK1

PCI_CLK3

PCI_CLK4

LPC_CLK0 CLK_PCI_DB

ALLOW PCIE
GEN2

USE
DEBUG
STRAP

Reserved

internal EC
ENABLE

Internal
CLKGEN
Mode

*
IGNORE
DEBUG
STRAP

internal EC
DISABLE

CLKGEN Mode

Internal

R215
10K_0402_5%
2
1

+3VS +3VALW +3VALW

R213
10K_0402_5%
2
1

+3VS

R212
10K_0402_5%
2
1

+3VS

External
CLKGEN
Mode

R214
10K_0402_5%
2
1

FORCE PCIE
GEN1

PULL
LOW

9/13 Change R211 from mount to @, R216 from @ to mount


9/13 Change R211 from @ to mount, R216 from mount to @

<11>
<11>
<11>
<11>
<11>

PCI_CLK1
PCI_CLK3
PCI_CLK4
LPCCLK0
CLK_PCI_DB

R220
10K_0402_5%
2
1

VSSAN_HWM

M19

PULL
HIGH

Check Internal PU/PD

R219
10K_0402_5%
2
1

EFUSE

REQUIRED STRAPS

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

R218
10K_0402_5%
2
1

Y4
D8

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

R211
10K_0402_5%
2
1

VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28

GND

A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19

VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19

R216
10K_0402_5%
2
1

Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16

R217
10K_0402_5%
2
1

M20

H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

DEBUG STRAPS
FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

ILA
AUTORUN
Enabled

FC PLL
bypassed

Disable I2C
ROM

Required Setting

<11>
<11>
<11>
<11>
<11>

PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

PULL
LOW

BYPASS
PCI PLL

Getting Value
from I2C EPROM

Reserved

Check AD29,AD28 strap function

Issued Date

2010/08/12

Deciphered Date

Compal Electronics, Inc.


2012/08/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

check default
Compal Secret Data

Security Classification

R225
2.2K_0402_5%
2
1

ILA AUTORUN Selects


Disabled
FC PLL

PCI_AD23
Enable ROM Straps

PCI_AD24

R224
2.2K_0402_5%
2
1

USE internal
PLL generated
PLL CLK

PCI_AD25

R223
2.2K_0402_5%
2
1

PULL
HIGH

PCI_AD26

R222
2.2K_0402_5%
2
1

PCI_AD27

R221
2.2K_0402_5%
2
1

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

FCH-VSS/Strap
Size
B
Date:

Document Number

P0VE6 Schematics
Wednesday, November 17, 2010

Sheet
1

15

of

36

Rev
1.0

Int. Speaker Conn.

RA19 1

BEEP#

2 10K_0402_5%

MONO_IN

RA20 1

1
1
1
1

2
2
2
2

JSPK2
SPK_L+
SPK_LSPK_R+
SPK_R-

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

20mil

0.1U_0402_16V4Z

@
CA32
0.1U_0402_16V4Z

CA34
100P_0402_50V8J

JSPK1
DA5
PJDLC05C_SOT23-3
@

SPK_L+
SPK_L-

DA4
PJDLC05C_SOT23-3
@

2 0_0603_5%

CA44
1000P_0402_50V7K

40 mil
10U_0805_10V6K
1

9/25 Add RA54~RA56

+3VS_DVDD

0.1U_0402_16V4Z
1

RA54 1

+5VS
CA19
@

+3VS

RA31 1

20 mil

2
0_0603_5%

1
RA32

CA12
2
RA40
0.1_1206_1%

CA13
10U_0805_10V6K

34
41
42
22

1
CA2
1U_0402_6.3V6K

<23> MIC1_R

MIC1_L

CA38 1

MIC1_R

CA39 1

PORTD_R
SPK_OUT_LPORTE_L
SPK_OUT_R+
PORTE_R
SPK_OUT_RPORTF_L
PORTB_L
PORTF_R
PORTB_R
FLY_P

2 MIC1_C_L
2.2U_0603_6.3V6K
2 MIC1_C_R
2.2U_0603_6.3V6K

35
36
37

+MIC1_VREFO

FLY_N

SDATA_IN
SDATA_OUT

PORTC_L
SYNC
PORTC_R
RESET#
C_BIAS
BIT_CLK

20 mil
+3VS
HP_PLUG#

<23> MIC_PLUG#

2
1
RA34 39.2K_0402_1%

MIC_PLUG#

GND

2
5.11K_0402_1%

MONO_IN
<25> EC_MUTE#

13
12

<25>

SENSEA

1
2
RA29 0_0402_5%

44
43
47
48

9/7 Add 0.1U (CA50) between GND & GNDA

1
2
RA39 0_0402_5%

3
2

SPKL+

16

SPKL-

19

SPKR+
SPKR-

17
39

MIC2_C_L 1

40

MIC2_C_R 1

+AVEE
1

CA10
2
0.1U_0402_16V4Z

24
49

SENSE A
SENSE B

GPIO1/SPK_MUTE#
GPIO2/SPDIF2

4
HP_SENSE

RA41
47K_0402_5%

11/17 Change CA40,CA41,RA16 from mount to @


1

2
33_0402_5%

10

HDA_SYNC_AUDIO

<12>
1

DMIC_CLK_R

1 RA49
2
90.9_0402_1%

AVEE

FILT_1.65

EP_GND

AVDD_3.3

CA58

+LDO_OUT_3.3V

CA11
CX20584-11Z_QFN48_7X7
10U_0805_10V6K

SA000034010

CA6
0.1U_0402_16V4Z 2

RA51 1

2 0_0402_5%

DMIC_CLK <23>

DMIC_DATA0

RA53 1

2 0_0402_5%

DMIC_DATA <23>

CA57

220P_0402_50V7K
2

9/13 Add RA50~RA53 for DMIC


10/01 Remove RA50,R52

0.1U_0402_16V4Z
1
1

+LDO_OUT_3.3V CA1

20 mil

220P_0402_50V7K
2

Layout Note: close to UA1

9/7 Change UA1 Pin1 to GND

30

11/01 Change CA57, CA58 from @ to mount

+3VALW

DMIC_CLK0

1U_0402_6.3V6K

10/28 Reserve CA57 CA58 for EMI

08/31 Reserve CA48(22P) on HDA_SDOUT_AUDIO

HDA_BITCLK_AUDIO <12>

9/13 Add RA49 for DMIC

+FILT_1.65V

HDA_SDIN0 <12>

1
2 CA48
22P_0402_50V8J
2 CA36
22P_0402_50V8J

+FILT_1.8V

@
CA4
1U_0402_6.3V6K

COM_MIC

HDA_RST_AUDIO# <12>
HDA_BITCLK_AUDIO_R 1
2
RA28
0_0402_5%
1
2 CA31
22P_0402_50V8J
@

32

QA2A
DMN66D0LDW-7_SOT363-6

9/1 Add CA49 RA41 on HP_SENSE

1
RA27

HDA_SDOUT_AUDIO <12>

COM_MIC

@
1
2
RA9
10K_0402_5%

2
G

QA1
BSS138_NL_SOT23-3S
@

100_0402_1%

+B_BIAS

46
45

1
2
2
RA10 20K_0402_5% G
1
CA49
0.1U_0402_16V4Z

9/13 Remove Analog MIC circuit

20 mil
FILT_1.8

RA16

HDA_SDIN0_AUDIO

GPIO0/EAPD#
SPDIFO

1000P_0402_50V7K

<23> HP_SENSE

CA47

MIC2_R
2 CA40 @
2.2U_0603_6.3V6K
2 CA41 @
2.2U_0603_6.3V6K

38

11

QA2B
DMN66D0LDW-7_SOT363-6

CA18
10U_0805_10V6K

9/6 UA1 Pin 1 link to GNDA

EAPD

20 mil

6
14

1
2
RA18 10K_0402_1%

COM_MIC_PLUG# 2
@
1
RA33 20K_0402_1%

2
0.1U_0402_16V4Z

DMIC_CLK0
EXT_MUTE#
DMIC_1/2

11/17 Change RA33 from mount to @

1
CA50

PCBEEP

CA16

10/26 Remove SPKR+ SPKR- function

HP_PLUG#

RA7
1

SPK_OUT_L+

20

15

18
RPWR5.0

31

29

21

PORTD_L

B_BIAS
23

CA15

CA8
CA7

CA9

2
0.1U_0402_16V4Z

11/17 Change RA12,RA14,CA25 from mount to @

10U_0805_10V6K
1
1

33

PORTA_R

28

9/3 Change RA17 from 1k to 0 ohm

<23> MIC1_L

@
1
2
RA11 20K_0402_5%

10U_0805_10V6K

CLASSDREF

27

PORTA_L

LPWR5.0

26

AVDD_5V

<23> HP_RIGHT

HP_RIGHT

AVDD_HP

<23> HP_LEFT

25

DVDD_3.3

UA1
HP_LEFT

CA17

VDD_IO

CA22

0.1U_0402_16V4Z
1

CA14
2 0.1U_0402_16V4Z

CA23
10U_0805_10V6K

VAUX_3.3

CA46

+3VS_VAUX

0.1U_0402_16V4Z
1
1

+CLASSD_5V
1

20 mil

Combo Jack

RA12
@
1
2
2.2K_0402_5%

RA26
2

2 0_0603_5%

COM_MIC_PLUG#

0.1U_0402_16V4Z
RA56 1

G1
G2

10/12 Change RA40 to 0.1 ohm (1206)

60 mil
+3VS

3
4

11/17 Change RA11, RA9, CA4, QA1 from mount to @

10/11 Change RA40 to 0 ohm (1206)

CA24
2
0.1U_0402_16V4Z

1
2

9/6 Update QA2 symbol

Combo Jack

CA3

9/3 Change CA38~ CA43 from 4.7U to 2.2U


Change RA16 from 1k to 100 ohm

1
2

ACES_88266-02001
CONN@

1000P_0402_50V7K

10/28 Add DA4 CA46 CA47 RA23 RA24

1000P_0402_50V7K
1
CA45

10/28 Add JSPK1 (2 pin)

0.1U_0402_16V4Z
1
1

+5VS_AVDD

+VDD_IO

1U_0402_6.3V6K

2
0_0603_5%

10/26 Remove DA4 CA46 CA47 RA23 RA24

2 0_0805_5%

08/25 Change CA5,CA8,CA11,CA13,CA17,CA18,CA19,CA23,CA25,CA26 to SE000004880 Standard Part

60 mil
1

+1.5VS

CA21
CA20
2
2
0.1U_0402_16V4Z

5
6

G1
G2

2
1

RA21
10K_0402_5%

RA55 1

1
2
3
4

ACES_88266-04001
CONN@

08/21 Follow PAV70


+3VS

1
2
3
4

2 10K_0402_5%
1

<12> FCH_SPKR

RA22
RA25
RA23
RA24

SPKL+
SPKLSPKR+
SPKR-

11/04 Change RA19 RA20 from 47k to 10k


CA33

<25>

08/19 Follow NTUC0

Headphone jack (jack shared with S/PDIF)


Internal MIC (mono or stereo)
Microphone/LI/LO jack
Line Out jack (Optional)
Line In jack (Optional)
Not used.
Internal stereo speakers
Internal stereo digital mic (Optional)
S/PDIF (jack shared with headphone)

A:
B:
C:
D:
E:
F:
G:
J:
H:

Port Configuration
Port
Port
Port
Port
Port
Port
Port
Port
Port

10K_0402_5%
+LDO_OUT_3.3V

CA5
10U_0805_10V6K

RA14
@
1
1K_0402_5%

COM_MIC_R

2
1

08/25 Add UA1 PN:SA000034010

COM_MIC

COM_MIC <23>

RA35 0_0402_5%
1
2
@

+B_BIAS

@
CA25
10U_0805_10V6K

10/11 Update UA1 PN:SA000034020

1
2
RA36 0_0402_5%

10/12 Update UA1 PN:SA000034010


1
2
RA37 0_0402_5%

08/25 Change CA1,CA2,CA3,CA4 to SE000000K80 Standard Part

GND

2010/08/12

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GNDA
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1
2
RA38 0_0402_5%

Title

Audio Codec CX20584


Size Document Number
Custom
Date:

Rev
1.0

P0VE6 Schematics

Wednesday, November 17, 2010

Sheet
1

16

of

36

8/23 Reserve 4.7k(RL15) to +3V_LAN on PLT_RST#


Reserve 4.7k(RL16) to +3V_LAN on LAN_CLKREQ#_R

+3V_LAN
LAN_CLKREQ#_R
PLT_RST#

UL1
30

TX_P

LED_ACT#

38

LAN_ACTIVITY#

29

TX_N

LED_LINK10_100#

39

LAN_SK_LAN_LINK#

<11> PCIE_FTX_C_DRX_P2

35

RX_P

<11> PCIE_FTX_C_DRX_N2

36

RX_N

TRXP0
TRXN0
TRXP1
TRXN1

11
12
14
15

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

RBIAS

10

2
CL9

CLK_PCIE_LAN
CLK_PCIE_LAN#

<11> CLK_PCIE_LAN
<11> CLK_PCIE_LAN#

LAN_CLKREQ#_R
2
0_0402_5%
PLT_RST#

1
RL12

<12> LAN_CLKREQ#

33
32

<11,19,20,25> PLT_RST#

23

1
RL14

<12,19,20> FCH_PCIE_WAKE#

2
0_0402_5%

LAN_X1
LAN_X2

LAN_X1

DL8

LAN_X2

LAN_CLKREQ#

25MHZ_20PF_7A25000012

LAN_CLKREQ#_R

2
CL10
27P_0402_50V8J

10/11 Change DL8 to SCS00000Z00

2 CL3

0.1U_0402_16V4Z

2 CL4

0.1U_0402_16V4Z
D

RL5 keep away other singal (25mil)

W=40mils

* If SWR mode applied,


Mount LL1, CL30, CL14, CL2, CL13 and CL27. No mount RL11 and CL26.
Place LL1 close to LAN Pin40.

W=40mils
+VDDCT_REG

+VDDCT

* If LDO mode applied,


DVDDL
DVDDL_REG

XTLO
XTLI

16
17
18
19
20
21
13

CL11
27P_0402_50V8J

+3V_LAN
+LX

5
4

VDDCT
VDDCT_REG

TEST_RST
TESTMODE
GND

7
8

RB751V-40_SOD323-2

@
1

SMCLK
SMDATA

28
27
41

Change YL1 to SJ100003300 2010/04/06

49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%

WAKE#

25
26

9/9 Change RL14 from @ to mount

2
2
2
2

W=40mils

40

LX

1
1
1
1

1 RL5 2.37K_0402_1%

VDD33
PERST#

2010.08.21 Follow PAWGC

YL1

CLKREQ#

LAN_WAKE#

<25> LAN_WAKE#

REFCLK_P
REFCLK_N

close to Lan chip

RL1
RL2
RL3
RL4

AVDDH
AVDDH_REG

NC
NC
NC
NC
NC
NC
NC

AVDDL
AVDDL
AVDDL_REG

24
37

+DVDDL

W=40mils

22
9

+AVDDH

W=40mils

31
34
6

+AVDDL

Mount CL30, CL2, RL11, CL26 and CL27. No mount LL1, CL14 and CL13.

+LX

W=40mils

SWR@
1

LL1

4.7UH_1008HC-472EJFS-A_5%_1008
CL30

2
AR8152-AL1E

9/23 Reserve DL8 on LAN_CLKREQ#

LDO@
1
2
RL11
0_0603_5%

+VDDCT

CL14

SWR@
2

CL2

CL13

AR8152L PN:SA00003JW30
C

close to Lan pin5

8/25 Change UL1 P/N to SA00003JW30

LAN Power circuit refer to NAU00

SWR@
2

+VDDCT_REG

CL26
LDO@

close to Lan pin40

CL27

0.1U_0402_16V4Z

CL6

<11> PCIE_FRX_DTX_N2

1U_0402_6.3V6K

0.1U_0402_16V4Z

PCIE_C_RXP1
.1U_0402_16V7K
PCIE_C_RXN1
1
.1U_0402_16V7K

<11> PCIE_FRX_DTX_P2

10U_0603_6.3V6M

1 4.7K_0402_5%
1 4.7K_0402_5%

1000P_0402_50V7K

@
@

0.1U_0402_16V4Z

RL15 2
RL16 2

close to Lan pin4

Change CL17, CL21, CL24, CL26 to SE000000K80 2010/04/06

W=40mils

close to Lan pin6

close to Lan pin31

+AVDDL

+AVDDH

+DVDDL

close to Lan pin34

close to Lan pin9

1
CL17
2

close to Lan pin22

1
CL18
2

close to Lan pin37

1
CL19
2

0.1U_0402_16V4Z

1
CL23

0.1U_0402_16V4Z

1
CL22

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CL34

1
CL16

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CL1

0.1U_0402_16V4Z

1
CL20

1U_0402_6.3V6K

CL7

1U_0402_6.3V6K

CL8

10U_0603_6.3V6M

CL5

1
CL12

close to Lan pin24

10U_0603_6.3V6M

AP2301GN-HF_SOT23-3

CL21

1
1U_0402_6.3V6K

QL1

0.1U_0402_16V4Z

1000P_0402_50V7K

+3VALW

CL24

1A

2 0_0603_5%

1U_0402_6.3V6K

+3V_LAN
RL13 1

close to JRJ45

close to LAN Pin 1


RL18 1
2

2 10K_0402_5%

@
2
1
CL28
470P_0402_50V7K

EN_WOL# <25>

CL41
JRJ45

LAN_MDI1+
LAN_MDI1-

1
2
3
4
5
6
7
8

+VDDCT_L

close to TL1

AR8152
LED[0]

LED[1]

Pin No. PU/PD


38

un-overclocking

overclocking

39

H
5

Description

RX+
RXCT
NC
NC
CT
TX+
TX-

16
15
14
13
12
11
10
9

RJ45_MIDI1+
RJ45_MIDI1RJ45_CT0
RJ45_CT1
RJ45_MIDI0+
RJ45_MIDI0-

RL7
1

RL6
1

2 75_0402_5%

CL15
1000P_1206_2KV7K

350uH_NS0013LF

For EMI.

RJ45_GND

SP050003N00

@
2
1
CL32
470P_0402_50V7K

+3V_LAN

LAN_SK_LAN_LINK#

9/2 Reserve DL2~7 for EMI(Need Update)


9/2 Change R399 to RL17

9/7 Update DL2~DL5 symbol from database


@
2

DL6

DL2

RJ45_MIDI1+

SMF10A_SOD-123FL2
@
DL3
2
1 RJ45_MIDI1SMF10A_SOD-123FL2
@
DL4
2
1 RJ45_MIDI0+
SMF10A_SOD-123FL2
@
DL5
2
1 RJ45_MIDI0SMF10A_SOD-123FL2

LDO mode

9/3 Remove RL17

RJ45_CT0

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

SHLD1

2
1
CL33
470P_0402_50V7K
RJ45_GND

Issued Date

LANGND

2012/08/12

Deciphered Date

DL1
PJDLC05C_SOT23-3

LANGND

Compal Secret Data


2010/08/12

LANGND

Green LED-

CL38
1000P_1206_2KV7K
1
2

9/2 Change RJ45_GND to LANGND on DL1


Security Classification

14

Green LED+

SANTA_130452-3
CONN@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SWR mode

PR1+

LAN_SK_LAN_LINK#_1 9
1 RL8
511_0402_1%
10

9/1 Add DL1, CL38~40,LL3 for EMI

RJ45_CT1

B88069X9231T203_4P5X3P2-2
@

PR3+

RJ45_MIDI1+

9/2 Reserve R399(0 ohm) on LAN_SK_LAN_LINK#

9/9 Update DL6~DL7 symbol from database


DL7

13

PR3-

B88069X9231T203_4P5X3P2-2
@

DETECT PIN1
PR2-

15

PR4+

6
5

2 75_0402_5%

SHLD1
PR4-

CL39

CL29

CL36

CL31

0.1U_0402_16V4Z

1000P_0402_50V7K

0.1U_0402_16V4Z

1000P_0402_50V7K

CL25

CL35

1U_0402_6.3V6K

RD+
RDCT
NC
NC
CT
TD+
TD-

Yellow LED-

RL10
5.1K_0402_5%

TL1

LAN_MDI0+
LAN_MDI0-

close to LL2

RJ45_MIDI1-

9/25 Change QL1 to SB000007H10


LL2
+VDDCT
2
1
MURATA_BLM18AG601SN1D_0603

9/21 Change QL1 from SB934130000 to SB934130020

Yellow LED+

9/2 Change R374 to RL18, C387 to CL41 Q36 to QL1

11
12

8/26 Change TL1 P/N to SP050003N00

LAN_ACTIVITY#_R
1
511_0402_1%

2
RL9

CL40

LAN_ACTIVITY#

9/2 Reserve Q36, R374, C387 for EN_WOL#

Title

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

LL3

MCK3225201YZF_2P

Compal Electronics, Inc.


LAN AR8152

Size Document Number


Custom
Date:

Rev
1.0

P0VE6 Schematics

Wednesday, November 17, 2010

Sheet
1

17

of

36

UC1
1

+3VS

RC1

11/15 Change RC16 P/N from SD028000080 to SM010009E00

0_0603_5%

+3VALW

RC2

UC1 close to JREAD1


+3VS_READER

SA00003FJ00

0_0603_5%

091020 change JUMP J2/J3 to RC1/RC2 0ohm

RC3
12K_0402_1%
1
2

1
CC1
10U_0603_6.3V6M

CC2
0.1U_0402_16V4Z
2 @

28
29
30
31
33

CrdVcc
SysVcc
Vcc33O
Vcc18O
Thermo Pad

REXT

14
13
12
8

D+
DRref
EClkin

CARD_D0
CARD_D1
CARD_D2
CARD_D3
CARD_D4
CARD_D5
CARD_D6
CARD_D7

17
18
20
21
19
4
5
6

xDData0
xDData1
xDData2
xDData3
xDData4
xDData5
xDData6
xDData7

+VCC_4IN1
+3VS_READER
+VCC33
+VCC18

6250@

8/25 Co-lay UB6252 (6252@)


D

+VCC33

UC1

UB6250NF-A1-110_QFN32_5X5

20mils

@
2

<12>
<12>

USB20_P6
USB20_N6
XTLI

Clock from M/B

VddA
VccA

15
10

xDCeZ
xDCle
xDAle
xDBsyZ

7
23
24
22

xDWeZ
xDReZ
xDWpZ
SdCdZ
xDCdZ

3
25
32
26
27

SMCEZ_C
SMCLE
SMALE_CLK_R 1
2 SMALE_CLK
SMBSYZ_SDCMD
FBMA-11-100505-900T 0402
PIN3
RC16
SMREZ_C
SMWPZ
SDCDZ
SMCDZ_MSINSZ

CARD_LED_R#

LedZ

ResetZ

+VCC33

RC4
4.7K_0402_5%
@

16
11
9

VssA
GndA
NC

XTLO

UB6252NF-A1-110_QFN32_5X5
6252@

8/26 Change UC1 to UB6252 (SA00003K010)

CC4 close to UC1.28


CC9 close to UC1.15
+VCC_4IN1

+VCC18

20mils

If use external crystal (YC1),


UC1 will change to UB6252

20mils

8/24 Card_LED# Follow PAV70


+VCC33

@
RC11
10K_0402_5%

@
RC12
0_0402_5%

@
RC13
0_0402_5%
1
2

+VCC33

@
RC10
10K_0402_5%

RC6
10K_0402_5%

0_0402_5%
RC5
2

+3VS

+VCC33

CC6
4.7U_0603_6.3V6K

@
CC5
0.1U_0402_16V4Z

CC4
10U_0603_6.3V6M

+VCC_4IN1

@
CC3
10P_0402_50V8J

20mils

DC1
3

CARD_LED_R#

CARD_LED# <21>

RB751V-40_SOD323-2
2

@
CC7
0.01U_0402_16V7K

1
CC8
0.1U_0402_16V4Z

QC1
SSM3K7002FU_SC70-3

CC9
4.7U_0603_6.3V6K

0_0402_5%
RC7
@

ByPass Capacitors

8/26 Change DC1 to SCS00002G00 Standard Part


8/26 Change QC1 to SB000009610 Standard Part

Card Reader Connector


B

JREAD1
+VCC_4IN1

RC8
1

<11> CLK_48M_CR

6250@
2
0_0402_5%
CC11
2

1
@
2

CC13
22P_0402_50V8J

30
29
28
27
26
25
24
23

PIN3
SMWPZ
SMALE_CLK
SMCDZ_MSINSZ
SMBSYZ_SDCMD
SMREZ_C
SMCEZ_C
SMCLE

33
32
34
39
38
37
36
35

Only UB6252
need to use XTLI and XTLO

31
40

XD10-D0
XD11-D1
XD12-D2
XD13-D3
XD14-D4
XD15-D5
XD16-D6
XD17-D7
XD07-WE
XD08-WP
XD06-ALE
XD01-CD
XD02-R/B
XD03-RE
XD04-CE
XD05-CLE

CC15

41
42

XTLO

11
18

SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3
SD2-CMD
SD-CD
SD-WP

9
4
3
21
19
16
1
2

10/08 Change DC1 to SCS00000Z00


+VCC_4IN1
SMALE_CLK
CARD_D0
CARD_D1
CARD_D2
CARD_D3
SMBSYZ_SDCMD
SDCDZ
PIN3

2
4.7P_0402_50V8J

CC10
0_0402_5%
RC14

11/15 Change CC10 P/N from 22p to 4.7p SE071220J80 to SE07147AC80

6
13

11/15 Change P/N CC12, RC15 from mount to @.


@

MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3
MS6-INS
MS2-BS
MS1-VSS
MS10-VSS

XD GND
XD GND

SD CD/WP GND
SD CD/WP GND
T-SOL_144-1300302600_NR

18P_0402_50V8J
6252@

SD4-VDD
MS9-VCC

SD6-VSS
SD3-VSS

0911 change YC1 to SJ100005900


1

EMI

CARD_D0
CARD_D1
CARD_D2
CARD_D3
CARD_D4
CARD_D5
CARD_D6
CARD_D7

XD-VCC

18P_0402_50V8J
6252@
YC1
12MHZ_16PF_7A12000026
6252@

RC9
33_0402_5%

XTLI

22

SMALE_CLK
CARD_D0
CARD_D1
CARD_D2
CARD_D3
SMCDZ_MSINSZ
PIN3

17
10
8
12
15
14
7
5
20

1
CC12

2
22P_0402_50V8J

0_0402_5%
RC15
SMCDZ_MSINSZ

10/28 Add RC14 RC15(@) RC16 on SMALE_CLK for EMI

CONN@

11/04 Change RC15 from @ to mount

2010.08.19 Copy Symbol from NCQF0

1
CC14
0.1U_0402_16V4Z

11/04 Change CC10 CC12 from 4.7p to 22p

9/2 Change CC11 CC15 from 27P to 18P

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

CARD READER UB6250/6252


Size Document Number
Custom
Date:

Rev
1.0

P0VE6 Schematics

Wednesday, November 17, 2010

Sheet
1

18

of

36

C263
2

W=40mil

8/22 Reserve R335 (0 ohm 0805) Add net +1.5VS_WWAN

C269

0.1U_0402_16V4Z

3G_MP@

3G_MP@

0.1U_0402_16V4Z
1
C270

8/25 Change C269,C275 to SE000004880 Standard Part

C266

+3VS

8/31 Change MCP@ to 3G_MP@

3G_MP@

C268

+3VS_WWAN

3G_MP@

3G_MP@

1
C265

2
1

C271
0.01U_0402_25V7K

R226
C272
47P_0402_50V8J <20,25> BT_ON#

+3VS_WWAN

R374
0_0603_5%
@

1
R227

2
0_1206_5%

C274

<12,17,20> FCH_PCIE_WAKE#

1
3
5
7
9
11
13
15

WWAN_CLKREQ#

<12> WWAN_CLKREQ#

<11> CLK_PCIE_WWAN#
<11> CLK_PCIE_WWAN

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

<11> PCIE_FRX_DTX_N1
<11> PCIE_FRX_DTX_P1
<11> PCIE_FTX_C_DRX_N1
<11> PCIE_FTX_C_DRX_P1
+3VS_WWAN

C275 10U_0805_10V6K 3G_MP@


1
2
WWAN_WAKEUP_R#

9/9 Remove D9

53
55

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1
NC

BT@

+
2

0.1U_0402_16V4Z
+3VS_BT

150U_B_6.3VM_R40M

2
0_0402_5%

BT@
C273

+3V_BT

Close to WWAN CONN

JMINI1
@
1
R412

+3VS_BT

Q13

AP2301GN-HF_SOT23-3

9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE#


FCH_PCIE_WAKE#

11/02 Change Q3 PN to SB934130020

+3VS_WWAN

+3VALW
@
1
R228

2
0_1206_5%

C402
100P_0402_50V8J

R378
0_0603_5%

10/27 Add R412 (0 ohm) on FCH_PCOE_WAKE#

BT MODULE CONN

10K_0402_5%

1
+3VS

9/25 Change Q13 to SB000007H10

+3VALW +3VS

06/29

9/3 Reserver +3VALW for BT (R378 R374)

C267 BT@
0.1U_0402_16V4Z

BT@

10U_0805_10V6K
BT@

Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T

10/04 Add 100p(C402) on BT_ON#

3G_MP@

+1.5VS_WWAN

3G_MP@
C264

2
0_0805_5%

0.1U_0402_16V4Z

1
R335

4.7U_0603_6.3V6K

3G_MP@

47P_0402_50V8J

3G_MP@

+1.5VS

+1.5VS_WWAN

W=40mil

0.01U_0402_25V7K

8/26 Change Q13 to SB934130020 Standard Part

JBT1

+1.5VS_WWAN

+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

USB20_P7
USB20_N7

<12> USB20_P7
<12> USB20_N7

10/04 Add 100p(C398) on UIM_RST

1
2
3
4

R230
1
1
R231

WLAN_LED#_R

0_0402_5%
2
2
0_0402_5%
USB20_MINI_N
USB20_MINI_P

1
R232

54
56

GND2
NC

2 0_0402_5%

2
0_0402_5%

G1
G2

5
6

ACES_88266-04001
CONN@

10/06 Remove C398


WXMIT_OFF#
R229 1

1
2
3
4

WXMIT_OFF# <25>
PLT_RST# <11,17,20,25>

9/1 Change R230 R231 from NON3G@ to mount


FCH_SMCLK0 <7,12,20>
FCH_SMDAT0 <7,12,20>

WWAN_LED# <20,21>
WLAN_LED# <20,21>

8/22 Update JBT1 Symbol from database (ACES_88266-04001_4P)

USB20_MINI_N
USB20_MINI_P

(9~16mA)

@
1
R417
@
1
R418
1
R419
1
R420

2
2 0_0402_5%
0_0402_5%
2
2 0_0402_5%
0_0402_5%

USB20_N3 <12>
USB20_P3 <12>
USB20_N9 <12>
USB20_P9 <12>

11/01 Change R417 R418 from mount to @


Change R419 R420 from mount to @ SW request (P0VE6-0045)

10/31 Add R417~R420 for co-lay USB port3 & port9

BELLW_80052-1021
CONN@

9/1 Change R234 from mount to @


W=20mil

JSIM1

Modifiy 05/11

1
3G@

3G@
1

C285

1
3G@ C282
3G@

R234
10K_0402_5%

3G@

@
2

56P_0402_50V8

TAITW_PMPAT7-08GLBS1N14H0
CONN@

C284
56P_0402_50V8

@
10K_0402_5%

+UIM_PWR

C283
0.1U_0402_16V4Z

10
11

1U_0402_6.3V6K

GND
GND

C281

D+
D-

22P_0402_50V8J

8
9

+3VALW

22P_0402_50V8J

USB20_P4
USB20_N4

+UIM_PWR
UIM_RST
UIM_CLK

1
2
3

22P_0402_50V8J
C280

<12>
<12>
R233

VCC
RST
CLK

22P_0402_50V8J

1
C277

C276
56P_0402_50V8

3G@ 1

GND
VPP
I/O
DET

C279

4
5
6
7

UIM_VPP
UIM_DATA

100P_0402_50V8J C278

<25> WWAN_WAKEUP#

1
R235

WWAN_WAKEUP_R#
2
0_0402_5%

10/06 Change C278 to 100p


Reserve for SIM card does not meet rise time
and pull-up is needed.
8/22 Update JP1 Symbol from database (TAITW_PMPAT7-08GLBS1N14H0_9P)

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Mini-Card/BT CONN
Size

Document Number

Rev
1.0

P0VE6 Schematics
Date:

Wednesday, November 17, 2010

Sheet
E

19

of

36

Mini-Express Card for WWAN


D

EC_TX_P80_DATA
EC_RX_P80_CLK

<25> EC_TX_P80_DATA
<25> EC_RX_P80_CLK

R236 0_0402_5%
1
2 EC_TX_P80_DATA_R
1
2 EC_TX_P80_CLK_R
R237
0_0402_5%

Mini-Express Card for WLAN

W=40mil

+3VS_WLAN

1
C286
4.7U_0603_6.3V6K

W=40mil

+1.5VS_WLAN

1
C287
0.1U_0402_16V4Z

1
C288
47P_0402_50V8J

1
C289
4.7U_0603_6.3V6K

1
C290
0.1U_0402_16V4Z

1
R336

+1.5VS

2
0_0805_5%

+1.5VS_WLAN

C291
47P_0402_50V8J

8/22 Reserve R336 (0 ohm 0805) Add net +1.5VS_WLAN


C

9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE#


JMINI2

<11> CLK_PCIE_WLAN#
<11> CLK_PCIE_WLAN

<11> PCIE_FRX_DTX_N3
<11> PCIE_FRX_DTX_P3
<11> PCIE_FTX_C_DRX_N3
<11> PCIE_FTX_C_DRX_P3
+3VS_WLAN
B

EC_TX_P80_DATA_R
EC_TX_P80_CLK_R
1

C292
10U_0603_6.3V6M

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
54

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
G2

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G3
G4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
55
56

+3VS
+1.5VS_WLAN

WL_OFF# <25>
PLT_RST# <11,17,19,25>
R393
1
1
R394

0_0402_5%
2
2
0_0402_5%

FCH_SMCLK0 <7,12,19>
FCH_SMDAT0 <7,12,19>
USB20_N8 <12>
USB20_P8 <12>

WWAN_LED#_R

9/17 Remove R239,R240


B

1 R241
2
0_0402_5%
R242

9/20 Add R393 R394 for SMBus

WWAN_LED# <19,21>

0_0402_5%

(9~16mA)

BELLW_80052-1021
CONN@

WLAN_LED# <19,21>

R243
100K_0402_5%

1
3
5
7
9
11
13
15

2 R238
1
@ 0_0402_5%

<19,25> BT_ON#
<12> WLAN_CLKREQ#

J2
JUMP_43X79
@
1 1
2 2

<12,17,19> FCH_PCIE_WAKE#

+3VS_WLAN

5/12
6/1
6/12
6/26
7/01

Update WLAN connector(the same as KAV60)


Revised 37 39 41 42 43 to NC
Update connector to DC040006S00
Update JMINI1 footprint
update pin 23,25,31,33

Compal Electronics, Inc.


Title
WLAN
Size
Document Number
CustomP0VE6 Schematics
Date:
5

WLAN
Rev
1.0

LA-6222P

Wednesday, November 17, 2010

Sheet
1

20

of

36

+3VS

Y
A

NC7SZ08P5X_NL_SC70-5

ACES_85201-1205N
CONN@

1
3

2
<13> HDD_LED#

13
14

GND
GND

HDD_LED#

U8
2

<18> CARD_LED#

+3VS

<19,20> WWAN_LED#
<19,20> WLAN_LED#

2
G

W=40mil

MEDIA_LED#

8/24 Update JLED1 Symbol from database (ACES_85201-1205N_12P) & Update pin definition

MEDIA_LED#

R373
10K_0402_5%

+3VS

PWR_LED#
PWR_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#

1
2
3
4
5
6
7
8
9
10
11
12

Q34
SSM3K7002FU_SC70-3

2
G

1
2
3
4
5
6
7
8
9
10
11
12

+3VALW
<25>
<25>
<25>
<25>

8/22 Update JP2 Symbol from database (ACES_85201-1605N_16P)

JLED1

W=40mil

LED PCB CONN

Q35
SSM3K7002FU_SC70-3

9/1 Add LED Circuit (LED2~4(SC597UDB000)LED5(SC5191NB000), R360~R369, Q33)


9/1 Change All LED power to 5V
9/1 Add R373, Q34, Q35 for MEDIA_LED#

9/9 Change LED2~4 footprint to LED_HT-297DQ-GQ_4P

9/11 Remove LED portion

9/1 Change Q33 to SB000009610(SSM3K7002FU_SC70-3)

SATA HDD Conn.


8/22 Reserve R337 R338 Add net +3VS_HDD,+5VS_HDD
JHDD1
<13> SATA_ITX_DRX_P0
<13> SATA_ITX_DRX_N0
<13> SATA_DTX_C_IRX_N0
<13> SATA_DTX_C_IRX_P0

SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_P0

1
2
3
4
5
6
7

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

SATA_DTX_IRX_N0
2 C293
0.01U_0402_16V7K
SATA_DTX_IRX_P0
2

C294
0.01U_0402_16V7K

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS_HDD

+5VS_HDD
0.1U_0402_16V4Z
1

C295

C296

10U_0805_10V6K
1

1
C297

+5VS_HDD

C298

1000P_0402_50V7K

1U_0402_6.3V6K

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND GND
V12
V12
GND
V12

W=40mil
+3VS

1
R337

2
0_0805_5%

+5VS

1
R338

2
0_0805_5%

+3VS_HDD

+5VS_HDD

W=100mil

24
23

SUYIN_127043FR022G263ZR_NR
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

8/22 Change C298 from 10U 6.3V to 10U 10V

2010/08/12

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title
Size
B

SATA CONN./LED/B CONN./BATT CONN.


Document Number

Rev
1.0

P0VE6 Schematics

Date:

Wednesday, November 17, 2010


G

Sheet

21
H

of

36

ON/OFF Button
8/26 Change D11 to SC600000B00 Standard Part
3

SW1

4
ON/OFFBTN#
+3VALW
2

EVQPLMA15 SPST PANASONIC H1.5

9/20 Remove R245,R248,D12

R247

100K_0402_5%
D11

FOR EMI

ON/OFF#

ON/OFFBTN#

ON/OFF# <25>

51_ON#

51_ON# <28>

BAV70W_SOT323-3
PWR_LED1#

C299 1

2 @ 100P_0402_50V8J

ON/OFFBTN#

C301 1

2 @ 100P_0402_50V8J

C300

1
EC_ON

EC_ON

Q14
SSM3K7002FU_SC70-3

2
G

<25>

1000P_0402_50V7K
1

R249

10K_0402_5%

8/26 Change Q14 to SB000009610 Standard Part


9/6 Change D13 from mount to @
10/05 Remove D13

9/1 Remove LED2 LED3 circuit, Change 70@ to mount

9/24 Change U9 to SA00001TC00

9/20 Add LED2 LED3 Circuit


9/21 Remove LED2 LED3 Circuit

LID Switch
W=20mil

+3VS

+3VALW

(BLUE)

C302
0.1U_0402_16V4Z

51_0402_5%
R251

VDD

AH180WG-7_SC59-3

GND

3
1

U9
C303

PWR_LED1#

10P_0402_50V8J

LID_SW# <25>

OUTPUT
LED1
HT-191NB5-DT BLUE 0603

PWR_LED1# <25>

10mil

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/12

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

ON/OFF / PWR SW/ LID SW


Document Number

P0VE6 Schematics
Wednesday, November 17, 2010

Sheet

22

of

36

Rev
1.0

To TP/B Conn.
8/22 Update JP3 Symbol from database (ACES_85201-0605N_6P)
8/22 Reserve R339 (0 ohm 0402) Add Net name +5VS_TP

INT_KBD Conn.

KSO[0..15] <25>

<25> TP_DATA
<25> TP_CLK
+5VS
0_0402_5%

JKB1

KSI0

C304 1

100P_0402_50V8J

KSO4

C305 1

100P_0402_50V8J

KSI1

C306 1

100P_0402_50V8J

KSO5

C307 1

100P_0402_50V8J

KSI2

C308 1

100P_0402_50V8J

KSO6

C309 1

100P_0402_50V8J

KSI3

C310 1

100P_0402_50V8J

KSO7

C311 1

100P_0402_50V8J

KSI4

C312 1

100P_0402_50V8J

KSO8

C313 1

100P_0402_50V8J

KSI5

C314 1

100P_0402_50V8J

KSO9

C315 1

100P_0402_50V8J

KSI6

C316 1

100P_0402_50V8J

KSO10

C317 1

100P_0402_50V8J

KSI7

C318 1

100P_0402_50V8J

KSO11

C319 1

100P_0402_50V8J

KSO0

C320 1

100P_0402_50V8J

KSO12

C321 1

100P_0402_50V8J

KSO1

C322 1

100P_0402_50V8J

KSO13

C323 1

100P_0402_50V8J

KSO2

C324 1

100P_0402_50V8J

KSO14

C325 1

100P_0402_50V8J

KSO3

C326 1

100P_0402_50V8J

KSO15

C327 1

100P_0402_50V8J

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

KSI0
KSI1
KSI2
KSO0
KSO1
KSO2
KSI3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSI4
KSO9
KSI5
KSI6
KSO10
KSO11
KSI7
KSO12
KSO13
KSO14
KSO15

G2
G1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

TP_DATA
TP_CLK
2
1
R339

JTP1

1
2
3
4
5
6

+5VS_TP

<25>

KSO[0..15]

KSI[0..7]

W=20mil

1
2
3
4
G1
G2
ACES_85201-0405N
CONN@

D14
@

PJDLC05C_SOT23-3

KSI[0..7]

8/24 Update JTP1 Symbol from database (ACES_85201-0405N_4P)


& Update pin definition
C

ACES_85202-24051
CONN@

8/22 Update JKB1 Symbol from database (ACES_85202-24051_24P)


8/23 Update KB pin definition
10/06 Change Jacks GND to GNDA

Headphone Out
(combo jack)

11/01 Change DA8 from @ to mount


CA51

2 39_0402_1%

HPOUT_L_1

2 39_0402_1%

HPOUT_R_1

330P_0402_50V7K
1

COM_MIC

HPOUT_L_2
2
FBMA-L11-160808-700LMT_2P
HPOUT_R_2
2
FBMA-L11-160808-700LMT_2P

1
LA1
1
LA2

10/01 Change RA42 RA43 to 39 ohm 1%

HP_SENSE

+5VS

2
2
4
1K_0603_5%
5

1
RA44

DA7
RB751V-40_SOD323-2

CONN@

MIC JACK

+MIC1_VREFOL

+MIC1_VREFOR

SINGA_2SJ2326-001111

DA1

JMIC1

RA47

RA48

1
6

AZ5125-02S.R7G_SOT23-3

MIC1_R RA46 1

2 MIC1_R_1
100_0402_5%

3K_0402_5%
MIC1_L_R

MIC1_R_R

10/29 Reserve DA8(SCA00001100) on COM_MIC

+3VS

9/13 Change AMIC to DMIC

DMIC_CLK
DMIC_DATA

<16> DMIC_CLK
<16> DMIC_DATA

SM010004010 300ma 70ohm@100mhz DCR 0.3

JMIC2

1
2
3
4

1
2
3
4

CA53

G1
G2

220P_0402_50V7K

5
6

MIC_PLUG#

CA54

@
DA2
PJDLC05C_SOT23-3

22P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data


2010/08/12

Issued Date

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

DA3
PJDLC05C_SOT23-3

9/17 Update JMIC1 to DC230004K00(SINGA_2SJ-A960-C01_6P)

Security Classification

9/14 Update JMIC1 to DC230007700(SUYIN_010030HR006G129ZR_6P)

CA56

SINGA_2SJ-A960-C01
CONN@

220P_0402_50V7K
2

CA55
22P_0402_50V8J

ACES_88266-04001
CONN@

<16> MIC1_R

LA3 1
2
FBMA-L11-160808-700LMT_2P
LA4 1
2
FBMA-L11-160808-700LMT_2P

MIC1_L RA45 1 100_0402_5%


2 MIC1_L_1

<16> MIC1_L

3K_0402_5%
@
DA8
PJDLC05C_SOT23-3

10/08 Change DA6,DA7 to SCS00000Z00

DA6
RB751V-40_SOD323-2

MIC_PLUG#

<16> MIC_PLUG#

COM_MIC

<16> COM_MIC

+MIC1_VREFO

3
6

RA42 1

HP_RIGHT RA43 1

330P_0402_50V7K

HP_LEFT

JHP1

<16> HP_RIGHT

9/13 Combine LS-7071PR01_USB_0908.DSN Audio Jack Portion

CA52

<16> HP_LEFT

HP_SENSE

<16> HP_SENSE

9/28 Change Jacks AGND to GND

Title

KB Conn/TP/CR Conn
Size
B
Date:

Document Number

Rev
1.0

P0VE6 Schematics
W ednesday, November 17, 2010

Sheet
1

23

of

36

USB Charge Follow PAWGC


8/25 Remove Charge USB Circuit

9/1 Add R370 R371 for OC circuit

Left Side USB CONN.

+USB_VCCC

W=80mils

+USB_VCCC

SGA00002N80

C389
150U_B2_6.3VM_R35M

9/15 remove R370 R371 for OC circuit

+
2

C390
470P_0402_50V7K

+5VALW

1 C394

0.1U_0402_16V4Z

USB_OC0# <12>

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4

D21

L31

USB_ON#

C388
@ 1000P_0402_50V7K

PJDLC05C_SOT23-3

USB20_P1_1

USB20_N0_1

USB20_P0_1

R390
0_0402_5%
@
2

C391
470P_0402_50V7K

D22

1
2
3
4

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4

10/29 Add C413~C414(0.1U) on +USB_VCCC

WCM-2012-900T_4P
@
1
2
R391
0_0402_5%

10/28 Change R388,R389,R390,R391,R257,R258 from mount to un-mount

PJDLC05C_SOT23-3

<12> USB20_P0

SUYIN_020133GB004M25MZL
CONN@

9/11 Change C340 C389 to SGA00002N80

<12> USB20_N0
JUSB2

USB20_N0_1
USB20_P0_1
3

1 C414

L32
2

+USB_VCCC
1 C413

USB20_N1_1

@
1
2
R389
0_0402_5%

W=80mils

9/11 Combine USB/B circuit

9/28 Swap L31 L32

+USB_VCCC

+USB_VCCC

9/29 Add C394,C395(0.1U) Close to U18

0.1U_0402_16V4Z

WCM-2012-900T_4P

0.1U_0402_16V4Z

<12> USB20_P1

SA00003XM00

<12> USB20_N1

SUYIN_020133GB004M25MZL
CONN@

AP2301MPG-13_MSOP8
1

1 C395

8
7
6
5

VOUT
VOUT
VOUT
FLG

1
2
3
4

EPAD

1 C387

GND
VIN
VIN
EN

0.1U_0402_16V4Z

1
2
3
4

U18

USB20_N1_1
USB20_P1_1

W=80mils
+USB_VCCC

JUSB3

W=80mils

0.1U_0402_16V4Z

R388
0_0402_5%
@
2

9/24 Change U11,U18 to SA00003XM00

10/28 Change L28,L31,L32 (SM070000K00) from un-mount to mount


9/27 Change L28,L31,L32 to SM070000K00

+5VALW

1
2
3
4

USB_ON#

GND
VIN
VIN
EN

EPAD

<25>

W=80mils

U11

C338
0.1U_0402_16V4Z

Right Side USB CONN.

+USB_VCCC1

W=80mils

VOUT
VOUT
VOUT
FLG

8
7
6
5

+USB_VCCC1

USB_OC1# <12>

AP2301MPG-13_MSOP8
1

9/28 Swap L28

W=80mils
C339
@ 1000P_0402_50V7K

1
C340
150U_B2_6.3VM_R35M

SA00003XM00

+
2

C341

R257
0_0402_5%
@
2

470P_0402_50V7K
L28

8/25 Change C340 from poly-cap to E-cap (SF000001500)

USB20_N2_1
USB20_P2_1

1
2
3
4
5
6
7
8

D17
USB20_N2_1

+USB_VCCC1

CH3

Vp

CH4

@
CH2

Vn

CH1

<12> USB20_N2

JUSB1

SGA00002N80

VCC
DD+
GND

<12> USB20_P2

2
3

USB20_N2_1

USB20_P2_1

WCM-2012-900T_4P

GND1
GND2
GND3
GND4

1
R258

2
0_0402_5%

SUYIN_020133GB004M25MZL
CONN@

USB20_P2_1

CM1293-04SO_SOT23-6

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

USB PORTS
Size
B
Date:

Document Number

Rev
1.0

P0VE6 Schematics
Wednesday, November 17, 2010

Sheet
E

24

of

36

+3VS

11/15 Change L29,L30 P/N from SM010015410 to SM010004010

8/23 Pull up 10k (R345) to +3VALW on USB_ON#

8/21 Change R262 from 0 ohm 0805 to 0 ohm 0603

EC_SMI#

R266
R272

2 2.2K_0402_5%

2 2.2K_0402_5%

GATEA20
KB_RST#_R
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

LPC_CLK0_EC
PLT_RST#
EC_RST#
EC_SCI#

12
13
37
20
38

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

11/02 Change C353 to 10p R275 to 22 ohm

C353
R275
10P_0402_50V8J 22_0402_5%
2
1
1
2

8/23 Change R271 R279 from mount to @

Reserve for EMI please close to U12

<23>

KSI[0..7]

<23>

KSO[0..15]

KSI[0..7]
KSO[0..15]

+3VS
+3VALW

2 2.2K_0402_5% EC_SMB_CK2

R277

2 2.2K_0402_5% EC_SMB_DA2

R279

2 10K_0402_5% EC_SCI#

R276

9/5 Change R276 R277 from mount to @

8/31 EC_SCI# Pull up to +3VALW


8/25 Delete KSO16 KSO17
8/23 Delete R280

EC_SMB_CK1
Battery<29>
<29> EC_SMB_DA1

APU
C407 1

2 100P_0402_50V8J

<4> EC_SMB_CK2
<4> EC_SMB_DA2
APU_ALERT#_EC

SLP_S3#_R
SLP_S5#_R
EC_SMI#
APU_ALERT#_EC

10/05 Add 100p(C407) on APU_ALERT#_EC

EC_XCLK1

EC_XCLK0

OSC

OSC

NC

NC

2
1
1

R284
8.2K_0402_5%

8/21 Change R283 from 100k to 0 ohm

SUSCLK

R282
@

EC_XCLK1
EC_XCLK0
0_0402_5%

122
123

8/31 Add 100k(R358) pull-down on SUSCLK

MISC
AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PS2 Interface

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

<12> SLP_S3#

<12> PBTN_OUT#

C351 2

BATT_TEMP

SPI Flash ROM

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

GPI

XCLK1
XCLK0

V18R

EN_FAN1
IREF
CHGVADJ

EN_FAN1 <26>
IREF
<30>
CHGVADJ <30>

EC_MUTE#
USB_ON#
PWR_LED1#
TP_CLK
TP_DATA

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK
EC_SPICS#/FSEL#

110
112
114
115
116
117
118

VGATE
APU_ENBKL
EAPD
EC_PROCHOT#
SUSP#
PBTN_OUT#_R
WWAN_WAKEUP#

124

V18R

R278

1 100K_0402_5%

+3VALW

100P_0402_50V8J

<12,35>

Project ID

R398
0_0402_5%

Rb

WWAN_WAKEUP# <19>

AD_PID0
1

C393
0.1U_0402_16V4Z

9/9 Change R323 from mount to @


+3VALW

R281
100K_0402_5%

R322
10K_0402_5%

PME Follow PAWGC

C356

9/21 Change Q29 from SB000008J00 to SB000009610

4.7U_0603_6.3V6K

8/31 Change EC_FAN_PWM from pin 34 to pin 26

1 R341

SLP_S5#_R

8/31 Change PWR_SUSP_LED from pin 36 to pin 34

0_0402_5%

1 R342

PBTN_OUT#_R

8/31 Change EC_PME# from pin 118 to pin 103

0_0402_5%

1 R343

KB_RST#_R

1
R323

<17> LAN_WAKE#

10/27 Change C356 from 10V_0805 to 6.3V_0603

0_0402_5%

+3VS

10K_0402_5%

+3VALW

Ra

APU_ENBKL <4>

SLP_S3#_R

R274

100p(C400) on VR_ON

1
R324

+3VALW

Compal Secret Data


2012/08/12

Deciphered Date

Title

EC_PME#

2
0_0402_5%
2
@ 0_0402_5%

<12> PCI_PME#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

0_0402_5%

Change Net Name from BATT_GRN_LED# to BATT_BLUE_LED#

BKOFF# <8>
WL_OFF# <20>
WXMIT_OFF# <19>

1 R340

2010/08/12

ICH_POK <12>
@

LID_SW#

EC_RSMRST# <12>
EC_LID_OUT# <12>
EC_ON <22>

Issued Date

2
2

9/25 Change VLDT_EN to VLDT_EN#

20mil

Security Classification

@
RB751V_SOD323

R273

EAPD
<16>
EC_PROCHOT# <4>
SUSP# <27,32,33>

BATT_AMB_LED# <21>
10/04 Add
PWR_LED# <21>
SYSON <27,32>
VR_ON <35>
C400

0_0402_5%

8/22 Add R340~R343 (0 ohm)

ICH_POK_EC

8/23 Delete W_DISABLE#_2

VGATE

<30>

0_0402_5%

D19

8/31 Add EN_FAN1 on U12.70

VR_ON
EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_PME#
ICH_POK_EC
BKOFF#
WL_OFF#
WXMIT_OFF#

ACIN

Follow PAWGC

9/17
FSTCHG <30>
BATT_BLUE_LED# <21>

BATT_AMB_LED#
PWR_LED#
SYSON
VR_ON
EC_ACIN

100
101
102
103
104
105
106
107
108

L30
ECAGND 2
1
FBMA-L11-160808-800LMT_0603

SA00003QQ10

R395

EC_SI_SPI_SO <26>
EC_SO_SPI_SI <26>
EC_SPICLK <26>
EC_SPICS#/FSEL# <26>

FSTCHG
BATT_BLUE_LED#

<30>

PWR_LED1# <22>
TP_CLK <23>
TP_DATA <23>

EN_WOL# <17>
VLDT_EN# <27>
LID_SW# <22>

1
RB751V-40_SOD323-2
2
1 100P_0402_50V8J

C352

EC_MUTE# <16>
USB_ON# <24>

EN_WOL#
VLDT_EN#
LID_SW#

KB930QF A1 LQFP 128P

EC_ACIN

8/23 Delete DAC_BRIG


8/25 Delete CHG_ON#

97
98
99
109

73
74
89
90
91
92
93
95
121
127

D18

BATT_TEMP <29>
ADP_I

1 200K_0402_5%

2
2

1 100P_0402_50V8J ECAGND

ADP_I
AD_BID0
AD_PID0

+3VALW

100P_0402_50V8J
BEEP#
<16>
EC_FAN_PWM <26>
ACOFF <30>

BEEP#
EC_FAN_PWM
ACOFF

SPI Device Interface

10/11 Change R282 R358 from mount to @

C357
0.1U_0402_16V4Z

PWM Output

2 R358
1
@
100K_0402_5%

<12> KB_RST#
1

ACOFF
21
23
26
27

9/23 Reserve R395 on ACIN


10/08 Change D18 to SCS00000Z00

C399

1
A

Q29
SSM3K7002FU_SC70-3
@

Rb

<11>

<12> SLP_S5#

AD_BID0

4.7K_0402_5%

Ra

Analog Board ID definition,


Please see page 3.

R283
0_0402_5%

10/04 Add 100p(C399) on ACOFF

10/11 Change C354,C355, X1 from @ to mount

Board ID
A

INVT_PWM
FAN_SPEED1
BT_ON#
EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF#
PWR_SUSP_LED#

<8> INVT_PWM
<26> FAN_SPEED1
<19,20> BT_ON#
<20> EC_TX_P80_DATA
<20> EC_RX_P80_CLK
<22> ON/OFF#
<21> PWR_SUSP_LED#

15P_0402_50V8J

8/23 Change R282 from mount to @


X1 C354 C355 from @ to mount
8/26 Change R282 from @ to mount
X1 C354 C355 from mount @
+3VALW

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

8/24 Delete Net FAN_SPEED1

C355

X1
32.768KHZ_12.5PF_Q13MC14610002

8/26 Change D18 to SCS00002G00 Standard Part

9/23 Update EC pin definition follow P5WE6

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

GND
GND
GND
GND
GND

1
1

15P_0402_50V8J

<12> EC_SMI#
<4> APU_ALERT#_EC

C354

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &

EC_SMB_DA1
EC_SMB_CK1

R264

KSO2

2 1K_0402_5%

TP_DATA

2 47K_0402_5%

<11> LPC_CLK0_EC
<11,17,19,20> PLT_RST#
<12> EC_SCI#

4.7K_0402_5%

1 10K_0402_5%

R271

R270

R263

TP_CLK

10/1 ENE Recommand


KSO1

<11> SERIRQ
<11> LPC_FRAME#
<11> LPC_AD3
<11> LPC_AD2
<11> LPC_AD1
<11> LPC_AD0

2 47K_0402_5%

R345

1 10K_0402_5%

<12> GATEA20

+3VALW

R269

USB_ON#

R268

0.1U_0402_16V4Z

C348
0.1U_0402_16V4Z

AGND

C350 2

+5VS

EC_RST#

69

1 47K_0402_5%

11
24
35
94
113

R267 2

+3VALW

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

U12

ECAGND

9
22
33
96
111
125

C347
1000P_0402_50V7K

C346
1000P_0402_50V7K

C345
0.1U_0402_16V4Z

LPC_CLK0_EC

C344
0.1U_0402_16V4Z

C343
0.1U_0402_16V4Z

@R265
@
R265
33_0402_5%
2
1

C342
0.1U_0402_16V4Z

R259

R399
8.2K_0402_5%

+3VALW_EC
1

@C349
@
C349
22P_0402_50V8J
2
1

L29
W=20mils
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
1

W=40mils

67

R262
+3VALW 0_0603_5%
1
2

+3VALW

8/31 Change EC_MUTE# Pull-up to +3VS(@)

EC_MUTE#

Compal Electronics, Inc.


EC ENE-KB930

Size Document Number


Custom

Rev
1.0

P0VE6 Schematics

Date:

Wednesday, November 17, 2010

Sheet
1

25

of

36

+3VALW

9/2 Change EC_SPICLK to EC_SPICLK_R

2MB SPI ROM


Share ROM.

2 SPI_WP#
3.3K_0402_5%

R201 1

8/31 Remove EC ROM , Add SPI ROM

EC_SPICLK_R

2SPI_HOLD#
3.3K_0402_5%
1

R202 1

R200
33_0402_5%
@

W=20mil

+3VALW
C212
1
2
EC_SPICS#/FSEL#
EC_SI_SPI_SO

CS#
SO
WP#
GND

VCC
HOLD#
SCLK
SI

8
7
6
5

SPI_HOLD#
0_0402_5% R206
EC_SPICLK_R 1
2 EC_SPICLK
EC_SPI_SI
1
2 EC_SO_SPI_SI

MX25L1605AM2C-12G_SO8

SA00003FO00

Layout Note:
R204 close to U7

C211
22P_0402_50V8J
@

0.1U_0402_16V4Z

U7

EC_SPICS#/FSEL#_R 1
EC_SPI_SO
2
SPI_WP#
3
33_0402_5%
4
R204

EC_SPICLK <25>
EC_SO_SPI_SI <25>

EMI

33_0402_5% R205

Layout Note:
R203 R205 R206 close to U12

FAN Conn.

+5VS

+5VS

D20
DAN217_SC59

2.2U_0603_10V6K
2

C382
1

<25> EC_SPICS#/FSEL#
<25> EC_SI_SPI_SO

R203
0_0402_5%
1
2
1
2

2 C383

U17
H2
H_3P2

H3
H_3P2

3P2 x 3 (APU)

EN_FAN1

9/15 Update the Screw Hole


@

1
R355

GND
GND
GND
GND

4.7U_0603_6.3V6K

APL5607KI-TRG_SO8
1

9/20 Add H20 (H_3P4X3P2N)

+VCC_FAN1
EN_FAN1_R
2
330_0402_5%

<25>

EN
VIN
VOUT
VSET

4.7U_0603_6.3V6K
@
C384 1
2

8
7
6
5

@
2

C385
1000P_0402_50V7K
1
2

@
+3VS

C386
0.01U_0402_16V7K

40mil
1

H1
H_3P2

1
2
3
4

+VCC_FAN1
R290
10K_0402_5%

H8
H_2P6

H9
H_2P6

H10
H_2P6

+5VS

1
R289

H11
H_2P8

H12
H_2P8

H13
H_2P8

+VCC_FAN1

EC_FAN_PWM 1
0_0402_5%

2
R356

@
1

2P6 x 5

+VCC_FAN1
2
0_0603_5%
<25> FAN_SPEED1
1
<25> EC_FAN_PWM
C360
@
10U_0805_10V6K
2

H7
H_2P6

40mil
H6
H_2P6

10/07 Change H13 from GND to LANGND


1

2P8 x 3

JFAN1
1 1
2 2
EC_FAN_PWM_R 3
3
4 4
5 G5
R357
6 G6
0_0402_5%
ACES_85205-04001
CONN@

8/24 Update JFAN1 Symbol from database (ACES_85205-03001_3P) & Update pin definition
8/24 Delete R290

10/07 Change H13 from LANGND to GND

8/25 Update JFAN1 Symbol from database (ACES_85205-04001_4P) & Update pin definition
8/25 Add R290 10k pull-up tp +3VS
8/31 Reserve U17,C382~C386, R355~R357, D20 (Fan Drive Circuit)
H_3P2X3P7N x 1

H19
H_3P2X3P7N

FM2

H20
H_3P4X3P2N

FM4
@

FIDUCIAL_C40M80

H_3P4X3P2N x 2
1

3P3N x 1

H18
H_3P4X3P2N

FM3
@

H16
H_3P3N

FM1

H17
H_3P2X3P5N

H_3P2X3P5N x 1

H15
H_3P2N

3P2N x 1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/12

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Screw / EC ROM /FAN


Size
B
Date:

Document Number

Rev
1.0

P0VE6 Schematics
Wednesday, November 17, 2010

Sheet

26

of

36

+3VALW TO +3VS

2
G

+5VS_GATE_R
1

C370
0.1U_0603_25V7K

SUSP

2
G
Q20

+3VS_GATE 1 R350

2+3VS_GATE_R
1

9/27 Change Q21.2 from SUSP# to SUSP

SUSP# 2
G
Q21

2
1

100K_0402_5%

2 +1.1VS_ON#
G
Q22 @

SSM3K7002FU_SC70-3 S

SUSP

R400
100K_0402_5%

0_0402_5%
2

0_0402_5%

+1.1VS_GATE_R
1

<34>

SUSP

SUSP

VLDT_EN#

SYSON#

10/04 Add 100p(C403) on SUSP


10/06 Remove C403

VLDT_EN# <25>

R403
0_0402_5%
2 100P_0402_50V8J

@
R303
100K_0402_5%

2
G
Q30

<25,32,33> SUSP#
C408 1

2 100P_0402_50V8J

10/06 Change C404 on +1.1VS_ON#

R404
10K_0402_5%

D
SYSON

<25,32> SYSON
S
SSM3K7002FU_SC70-3

@
2
G
Q31
SSM3K7002FU_SC70-3

2
1
3

1
C404 1

R302
100K_0402_5%

9/28 Remove C372

10/04 Add 100p(C404) on VLDT_EN#

+1.1VS_GATE 2 R351
D

1
R402

R304
47K_0402_5%

+1.1VS_ON# 2
G
Q24

+1.1VS_ON#

SB00000GV00

+VSB

+5VALW

R300
470_0603_5%
@

9/25 Change Q15 to SB000007H10

9/28 Change R296.1 from +VSB to +5VALW

C376
1U_0603_10V6K
2

C375
10U_0805_10V6K
2

+5VALW

10/29 Change R298 from 0 ohm to 100k

C373
0.1U_0402_16V4Z

8/26 Change Q15 to SB934130020 Standard Part

C374
10U_0805_10V6K

SUSP

10/31 Change C373 from 0603_25V to 0402_16V

9/28 Change U19 to Q15(SB934130020)


1

+5VALW

+1.5VS_GATE_R
1

S SSM3K7002FU_SC70-3

10/12 Change R400 R403 from @ to mount

+1.5VS_GATE 2 R298
D

9/28 Change Q21.2 from SUSP to SUSP#

U16
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
6
3
5

10/12 Change R402 from mount to @

2
G

Q18
SSM3K7002FU_SC70-3 S

9/27 Change Q15 to U19(SB00000GV00)


+1.1VS

R291
470_0603_5%

R296
200K_0402_5%

11/18 Change R295 from 200k to 120k

C371
0.1U_0603_25V7K

C363
1U_0603_10V6K

SB934130020

2 SUSP
G
Q17 @
SSM3K7002FU_SC70-3

9/27 Change R296.1 from +5VALW to +VSB

+1.1ALW to +1.1VS+1.1VALW

+5VALW

0_0402_5%

SSM3K7002FU_SC70-3

2 10U_0805_10V6K

20K_0402_5%
SSM3K7002FU_SC70-3
Q19

1
C362
10U_0805_10V6K
2

2
1

1
@

1
R295
120K_0402_5%

R297
+5VS_GATE 1

R293
470_0603_5%
@

C361

SB00000GV00

2 SUSP
G
Q16 @
SSM3K7002FU_SC70-3

1
G

+VSB

1
R294
82K_0402_5%

C369
1U_0603_10V6K

SB00000GV00

R292
470_0603_5%
@

3
1
C368
10U_0805_10V6K
2

1 2

1 2

+VSB

SUSP

1
C367
10U_0805_10V6K

C366
1U_0603_10V6K

10U_0805_10V6K

1
C365
10U_0805_10V6K
2

10/27 Change R291 Q18 from @ to mount


Q15
+1.5VS
AO3413L_SOT23-3

+1.5V

+3VS

U15
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
6
3
5

C364

U14
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
6
3
5

+1.5V to +1.5VS

+3VALW

+5VS

+5VALW

+5VALW TO +5VS

C378
0.1U_0603_25V7K

10/27 Add C408(100P) on SUSP# close to PR70


9/27 Change R302 from @ to mount, remove R301
8/19 Change Q16~Q22 Q24~Q28 toSB000009610(SSM3K7002FU_SC70-3)

SSM3K7002FU_SC70-3

10/12 Change R294 to 100k

9/27 Change R304.1 from +5VALW to +VSB

10/12 Change R295, R296 to 200k

10/12 Change R304 to 47k


10/12 Change R294 to 82k
10/12 Change R297 to 20k
+1.8VS

+1.5V

+1.05VS

8/19 Change Q29 Q30 to Q23A Q23B (SB00000DH00 S TR DMN66D0LDW-7 2N SOT363-6)

10/31 Change C361 C362 from mount to @


3

8/21 Change U14~U16 to SB548000310 (SI4800BDY-T1-E3_SO8)


8/23 Remove R305 R299 Add R350 R351 for Sequence
8/24 Change Q23A Q23B to Q30 Q31(@) (SB000009610 SSM3K7002FU_SC70-3)

+0.75VS

2
G
Q26 @
SSM3K7002FU_SC70-3

1
R309
470_0603_5%
@

8/25 Change C361,C362,C364,C365,C367,C368,C374,C375 to SE000004880 Standard Part


8/26 Change U14, U15, U16 to SB00000GV00 Standard Part

D
SUSP

2
G
Q25 @
SSM3K7002FU_SC70-3

1 2

D
SYSON#

D
SUSP

R308
470_0603_5%
@

2
G
Q27 @
SSM3K7002FU_SC70-3

SUSP

R307
470_0603_5%
@

1 2

1
R306
470_0603_5%
@

1 2

1 2

8/25 Change C363,C366,C369,C376 to SE080105K80 Standard Part

2
G
Q28 @
SSM3K7002FU_SC70-3

9/3 Delete C377(DIS@)


9/23 Reserve R400~403, Q36 for VLDT_EN
9/25 Remove R401 Q36 on VLDT_EN
9/25 Add 10k(R404) PD on SUSP#

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/12

Issued Date

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DC Interface
Size Document Number
Custom
Date:

Rev
1.0

P0VE6 Schematics
Sheet

Thursday, November 18, 2010


E

27

of

36

VIN

PD1
1

RLS4148_LL34-2

N1

RLS4148_LL34-2

VS

1
PR3
100K_0402_1%

1
2

PC6
0.22U_0603_25V7K

1
2

1
2

PC4
100P_0402_50V8J

PC3
1000P_0402_50V7K

1
2

PC2
100P_0402_50V8J

4
3
2
1

GND 4
GND 3
2
1

PC1
1000P_0402_50V7K

6
5

<BOM Structure>

PR2
68_1206_5%
2

PD2

BATT+

SP02000GC00
PJP1

PR1
68_1206_5%

DC_IN_S1

PQ1

TP0610K-T1-E3_SOT23-3

VIN

PL1
HCB2012KF-121T50_0805
1
2

PC5
0.1U_0603_25V7K

PR4
<22>

ACES 88266-04001
CONN@

51_ON#

22K_0402_1%

PR5
0_0603_5%
1
2

+CHGRTC

+3VLP

PBJ1
2

PR141
+RTCBATT2P

PR142

560_0603_5%

+RTCBATT2

560_0603_5%

ML1220T13RE
45@

PJ1

@ PJ2
1

JUMP_43X118

+3VALW

+1.1VALW P

JUMP_43X118
PC241
.1U_0402_16V7K

+1.1VALW
1

PC242
.1U_0402_16V7K

+3VALW P

@ PJ4
1

+1.05VSP

+5VALW

2
2

+1.05VS
PC244
.1U_0402_16V7K

@ PJ6
1

JUMP_43X39

+VSB
1

PC243
.1U_0402_16V7K

@ PJ5
+VSBP

JUMP_43X118

JUMP_43X118

PJ3

+0.75VSP

JUMP_43X79
PC245
.1U_0402_16V7K

+0.75VS
1

PC246
.1U_0402_16V7K

+5VALW P

@ PJ7
2

+1.8VS

JUMP_43X118

+1.8VSP

PC247
.1U_0402_16V7K

@ PJ9
2

JUMP_43X118

+1.5V

+1.5VP

PC249
.1U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/12

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DCIN/VIN DECTOR
Size
Date:

Document Number

Rev
1.0

W ednesday, November 17, 2010


D

Sheet

28

of

36

VMB

PL2
HCB2012KF-121T50_0805
1
2

PJP2
VMB

1
2
3
4
5
6
7
8
9
10

BATT+

EC_SMCA

PR6
1K_0402_1%

PC8
0.01U_0402_25V7K

PC7
1000P_0402_50V7K

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 72 degree C

EC_SMDA

B/I
TS
1

VL

@ PR10
100K_0402_1%

<31> MAINPW ON

PU1

PR8
22.1K_0402_1%

VCC TMSNS1

GND RHYST1

OT1 TMSNS2

PR11
15K_0402_1%

OT2 RHYST2

+3VALW

PR14
1K_0402_1%
2
1

PR13
100_0402_1%
1
2

PR12
100_0402_1%
1
2

G718TM1U_SOT23-8

@ PR15
47K_0402_1%
1

BATT_TEMP <25>
1

PR9
6.49K_0402_1%
2
1

PR7
10K_0402_1%

VL

PC9
0.1U_0402_10V7K

@
SUYIN_200275MR008G15QZR

1
2
3
4
5
6
7
8
GND
GND

PH2 @
EC_SMB_CK1 <25>

PH1

100K_0402_1%_NCP15W F104F03RC
2

100K_0402_1%_NCP15W F104F03RC

EC_SMB_DA1 <25>

PQ2
TP0610K-T1-E3_SOT23-3
3

B+

+VSBP

1
PR18
100K_0402_1%

PR17

1
2

1
2

VL

PC10
0.22U_0603_25V7K

2
1
PR16
100K_0402_1%

PC11 @
0.1U_0603_25V7K

22K_0402_1%

PR19
<31,33>

POK

PQ3
SSM3K7002FU_SC70-3

2
G

PC12
.1U_0402_16V7K

0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/12

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

BATTERY CONN / OTP


Size
Date:

Document Number

Rev
1.0

W ednesday, November 17, 2010


D

Sheet

29

of

36

1
2
EN

CSON

22

PR34 2

18

LX_CHG

6251VREF

VREF

UGATE

17

DH_CHG

.1U_0402_16V7K

6251VREF 1

6251ACLIM

4
1
3

CHLIM

BOOT

16

PR42
BST_CHG 1
2
0_0603_5%

10

ACLIM

VDDP

15

6251VDDP

11

VADJ

LGATE

14

DL_CHG

12

GND

PGND

13

1
2

20K_0402_1%

1 1

2
1

4.7K_0402_1%

PR46

1
2

0.01U_0402_25V7K

1
PC31

ACOFF

PR44
100K_0402_1%
2

<25>

PQ12
DTC115EUA_SC70-3
ACOFF
2

PR43

PL4
8.2UH_VMPI0703AR-8R2M-Z01_4A_20%
CHG
1
2
1

PC27
BST_CHGA 2
1
0.1U_0603_25V7K
PD5
RB751V-40_SOD323-2
1
2 6251VDD

PR45
PC32
4.7U_0603_6.3V6M

PR38

BATT+
4

2
@ PR41
4.7_1206_5%

3
0.05_1206_1%

PHASE

@ PC28
680P_0603_50V7K

ICM

2
2_0402_5%

19

3
2
1

CSIP

IREF

1 20_0402_5%

PC25
0.1U_0603_25V7K
1
PR36

PC26
1
2

PR39
62K_0402_1%
2
1

VCOMP

<25>

1
2
47K_0402_1%

ADP_I

6
PR37

PQ10
AON7408L_DFN8-5

PR40
47K_0402_1%
1
2

20

@
PC21
2200P_0402_50V7K

CSOP

PQ11
AON7408L_DFN8-5

<25>

10K_0402_1%

0.01U_0402_25V7K

CSIN

6800P_0402_25V7K

CSON

PR35

ICOMP

5
G

PACIN

PC24
1
2

CSOP

PQ9B
DMN66D0LDW -7_SOT363-6

CELLS

21

PR32 20_0402_5%
1
2
PC22
0.047U_0402_16V7K
1
2
PR33
20_0402_5%

3
2
1

PC23
1
2

PR27
100K_0402_1%
1
2BATT_ON

PQ9A
DMN66D0LDW -7_SOT363-6

PQ7
DTC115EUA_SC70-3

PC204
10U_0805_25V6K

PR28
14.3K_0402_1%

0.1U_0603_25V7K
ACPRN

2
G

ACSETIN

PC205
10U_0805_25V6K
2
1

23

VIN

PC30
10U_0805_25V6K
2
1

ACSET ACPRN

47K_0402_1%

PC29
10U_0805_25V6K
2
1

PR25
10K_0402_1%

24

PR21

2
DCIN

6251_EN

PC20
DCIN 2

VDD

100K_0402_1%

PC19
1000P_0402_25V8J
2
1

1 1

PR31

PR30
150K_0402_1%

PQ8
DTC115EUA_SC70-3

6251VDD

PU2
1

PQ6
DTA144EUA_SC70-3

PR29
10K_0402_1%
2
1

FSTCHG

<25>

PR26
10_1206_5%

PR24
191K_0402_1%

PD4
RB751V-40_SOD323-2

BATT_ON

PC18
2.2U_0603_6.3V6K

ACSETIN

PC17
0.1U_0603_25V7K
2
1

PR23
200K_0402_1%

VIN
PC13
5600P_0402_25V7K

PC234
10U_0805_25V6K
2
1

CSIP

1
2

PR22
200K_0402_1%

PQ5
SI7121DN-T1-GE3_POW ERPAK8-5
1
2
3

CSIN

CHG_B+

PL3
HCB2012KF-121T50_0805
2
1

PC16
4.7U_0805_25V6-K
2
1

PC15
4.7U_0805_25V6-K
2
1

B340A_SMA2

PC14
4.7U_0805_25V6-K
2
1

1
2
3

PC251
10U_0805_25V6K

B+

PR20
0.05_1206_1%
1
4

PC250
10U_0805_25V6K
2
1

VIN

P3

PQ4
SI7121DN-T1-GE3_POW ERPAK8-5

P2

PD3

PC237
10U_0805_25V6K
2
1

CP = 85%*Iada ; CP = 1.789A
ADP_I = 19.9*Iadapter*Rsense

PC238
10U_0805_25V6K
2
1

Iada=0~2.105A(40W/19V=2.105A)

4.7_0603_5%

G5209S31U_SSOP24

<25> CHGVADJ

PR47
1

CV mode

PR48
31.6K_0402_1%

CC=0.25~3.52A

Vth,rise(typical) = ((191K/14.3K)+1)*1.26
6251VDD

= 18.089V

BATT Type

15.4K_0402_1%

Charging Voltage
(0x15)

Vth,fall(typical) = ((191K/14.3K)+1)*1.26 -3.4uA*191K

IREF=0.7224*Icharge
12.60V

IREF=0.43V~3.24V

12600mV

= 17.44V

Normal 3S LI-ON Cells

PR49
47K_0402_1%
2

PR50
10K_0402_1%

ACIN

<25>

PACIN

Ki
Vchlim=Iref*(PR39/(PR39+PR44))
=Iref*(100K/(80.6K+100K))
=Iref*0.617
Ichanrge=(165mV/PR38)*(Vchlim/3.3V)
=(165m/50m)*(1/3.3V)*Iref*0.617
=0.617*Iref
Iref=1.62*Ichanrge =>Ki=1.62

PR51
10K_0402_1%
1
2

PQ13
DTC115EUA_SC70-3
2

PR52
14.3K_0402_1%

ACPRN

Kv
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv
A=Vref*(R/(R+514K))=0.052
Kv=9.451

2010/08/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

CHARGER
Size
Date:

Document Number

Rev
1.0

W ednesday, November 17, 2010

Sheet
1

30

of

36

2VREF

PC33
1U_0402_6.3V6K

UGATE1

21

LX_3V

11

PHASE2

PHASE1

20

LX_5V

LG_3V

12

LGATE2

LGATE1

19

LG_5V

PC37
0.1U_0603_25V7K
2
1

PC240
4.7U_0805_25V6-K
2
1

PL7
4.7UH_FDVE0630-H-4R7M=P3_5.5A_20%
1
2

1
+

PC46 @
680P_0603_50V7K

PC44
220U_6.3V_M

PQ17
FDMC7692S_MLP8-5

3
2
1

VL
PC48
4.7U_0603_6.3V6K

B++

PQ18B
DMN66D0LDW -7_SOT363-6

PR64

+5VALWP

NC
RT8205EGQW _W QFN24_4X4

2VREF

PC49
0.1U_0603_25V7K

PR65

VL

<29,33>

PC42
2 0.1U_0603_25V7K

PR62 @
4.7_1206_5%

18

17

16

13

3
2
1

UGATE2

PC40
4.7U_0805_25V6-K
2
1

10

POK

PQ15
AON7408L_DFN8-5

2
S

DMN66D0LDW -7_SOT363-6

FB1

UG_3V

PR60
BST_5V 1
2
0_0603_5%
UG_5V

EN
D

5
G

ENTRIP1

22

1
2

REF

BOOT1

VREG5

BOOT2

VIN

ENTRIP2

ENTRIP1

BST_3V

1
2
3
2

PC47
1U_0402_6.3V6K
B

PQ18A

TONSEL

23

GND

24

PGOOD

PR63
499K_0402_1%
1
2

B+
PQ16
FDMC7692S_MLP8-5

ENTRIP2

VO1

VREG3

100K_0402_5%

2
PC45 @
680P_0603_50V7K

6
ENTRIP2

VO2

PR58
143K_0402_1%
1
2

4.7_1206_5%

B++

PR61 @

PC43
220U_6.3V_M

P PAD

15

PR59
1
2
0_0603_5%

+3VALWP

PL6
4.7UH_FDVE0630-H-4R7M=P3_5.5A_20%
1
2

25

1
2
3

PC41
0.1U_0603_25V7K

PU3

SKIPSEL

PR57
130K_0402_1%
1
2

14

PC38

PQ14
AON7408L_DFN8-5

PR56
19.1K_0402_1%
1
2

4.7U_0603_6.3V6K

PC36
2200P_0402_50V7K
2
1

PC239
4.7U_0805_25V6-K
2
1

PC35
4.7U_0805_25V6-K
2
1

PC34
0.1U_0603_25V7K
2
1

+3VLP

PR55
20K_0402_1%
1
2
ENTRIP1

B+

PL5
HCB2012KF-121T50_0805
1
2

PR54
30K_0402_1%
1
2

FB2

B++

+5VALW Vo= (2*30K/19.1K)+2=5.141V

PR53
13.7K_0402_1%
1
2

PC39
2200P_0402_50V7K
2
1

+3VALW Vo= (2*13.7K/20K)+2=3.37V

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)


(2)SMPS2=375KHZ (+3VALWP)

1
1

100K_0402_1%
<29> MAINPW ON
PR66
1
2
100K_0402_1%

1
2

PC50

0.1U_0402_10V7K

PR67

2
42.2K_0402_1%

VS

PQ19
DTC115EUA_SC70-3

+3.3VALWP
Imax=4.214A ; Ipeak=6.02A ; Iocp=1.2*Ipeak=7.224A
f=375KHz, L=4.7UH,Rentrip2=130K ohm
Rdson=14.5~17.9m ohm (IRFH3707)
1/2Delta I = 1/2 *(19-3.3)*(3.3/19)/(375KHz*4.7UH)=0.773A
Vtrip2=(10*10^-6*150Kohm/9)-24mV=0.143V
Ilimit=0.143/(17.9m*1.2)~0.143/(14.5m)=6.642A~9.839A
Iocp=7.415A~10.613A (7.415A>7.224A -> OK)

+5VALWP
Imax=4.9A ; Ipeak=7A ; Iocp=1.2*Ipeak=8.4A
f=300KHz, L=4.7UH,Rentrip1=143K ohm
Rdson=14.5~17.9m ohm (IRFH3707)
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vtrip1=(10*10^-6*162Kohm/9)-24mV=0.156V
Ilimit=0.156/(17.9m*1.2)~0.156/(15m)=7.263~10.759A
Iocp=8.569~12.065A (8.569>8.4 -> OK)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/12

Issued Date

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

3VALWP/5VALWP
Size

Document Number

Rev
1.0

Date:

Wednesday, November 17, 2010

Sheet
1

31

of

36

FB

1
PC55
2

200K_0402_1%
PC56

PR72

0.22U_0402_10V6K

FB_1.8VS

PR71
10K_0402_1%

<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR69/PR71)=0.6*(1+20.5K/10K)=1.83V
Ipeak=2A, Imax=1.4A

499K_0402_1%

PR69
20.5K_0402_1%

PC54
22U_0805_6.3VAM

1
2

NC

FB=0.6Volt

NC

TP

11

2 EN_1.8VS

PR68

1
PR70

<25,27,33> SUSP#

+1.8VSP
1

PC51
22U_0805_6.3VAM

EN

SVIN

PC53
22U_0805_6.3VAM

LX

LX_1.8VS

PVIN

PC52
68P_0402_50V8J
2
1

JUMP_43X39

LX

PVIN

10

680P_0603_50V7K

4.7_1206_5%

+5VALW

PL8
1UH_FDV0630-1R0M-P3_10.3A_20%

PU4
SY8033BDBC_DFN10_3X3
@ PJ10

PG

14
BST

VFB=0.75V

FB

PGOOD

13

DH_1.5V
LX_1.5V

LX

12

ILIM

11

VDD

10

DL

PR73
1
2
15K_0402_1%

PC61
0.1U_0603_25V7K
2
1

PC62
2200P_0402_50V7K
2
1
1

+1.5VP

@ PR79
4.7_1206_5%

+5VALW

DL_1.5V

+ PC65
330U_2.5V_M

PC67
4.7U_0603_6.3V6K

PQ21
FDMC7692S_MLP8-5

@ PC66
680P_0603_50V7K

G5603RU1U_TQFN14_3P5X3P5

4
2

PGND
8

AGND

PC58
4.7U_0603_6.3V6K

0.1U_0603_25V7K
1

VCC

DH

PL10
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

PC64
1
2

OUT

BST_1.5V-1

100_0603_5%

0_0603_5%

PR78

TON

+5VALW

15

EN_SKIP

PU5

TP

PC63 @
.1U_0402_16V7K

PR76
30K_0402_5%

B+

3
2
1

BST_1.5V

0_0402_5%

PR77

3
2
1

PR75

<25,27> SYSON

PC60
4.7U_0805_25V6-K
2
1

PR74
255K_0402_1%
1
2

PQ20
AON7408L_DFN8-5

PC59
4.7U_0805_25V6-K
2
1

PL9
HCB2012KF-121T50_0805
1
2

PR80

5.36K_0402_1%
PR81
5.1K_0402_1%
2

<Vo=1.5V> VFB=0.75V
V=0.75*(1+5.36K/5.1K)=1.538V
Cout ESR=25m ohm
Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707)
Ipeak=6.5A, Imax=4.55A, Iocp > 7.8A

G5603

Temperature
Compensated

RT8209B

-1180ppm/

1600ppm/

TPS51117

4500ppm/

OCP setting

RT8209B

TPS51117

RT8209M

6.821A

7.235A

8.000A

8.178A

RT8209M

4800ppm/

Vtrip_min (SPEC)

30mV

50mV

30mV

50mV

Vtrip_max (SPEC)

200mV

200mV

200mV

200mV

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/12

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

G5603

Title

1.8VSP/1.5VP
Size Document Number
Custom
Date:

Rev
1.0

W ednesday, November 17, 2010


D

Sheet

32

of

36

PR82
255K_0402_1%
1
2

2
PR88
13K_0402_1%

DL_1.1VALW

DL

4
1

PGND
8

AGND
7

PC75
4.7U_0603_6.3V6K

+5VALW

G5603RU1U_TQFN14_3P5X3P5

PC76
4.7U_0603_6.3V6K

PC71
2200P_0402_50V7K

1
2

PC70
0.1U_0603_25V7K
2
1

1
2

PC74
330U_2.5V_M

10

G5603

RT8209B

TPS51117

RT8209M

5.799A

6.183A

6.845A

6.976A

+1.1VALW P

OCP setting

@ PR86
4.7_1206_5%

11

BST
ILIM
VDD

0.1U_0603_25V7K

@ PC77
680P_0603_50V7K

PGOOD

LX_1.1VALW

VFB=0.75V

DH_1.1VALW

12

FB

13

LX

PQ23
FDMC7692S_MLP8-5

VCC

14

15

DH

OUT

3
2
1

TON

+5VALW

PL12
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

PC73
1

PR87
100_0603_1%
1
2

TP

PU6

EN_SKIP

PC72
.1U_0402_16V7K
@

PR84
30K_0402_5%
@

Cout ESR=25m ohm


Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707)
Ipeak=4.02A, Imax=2.814A, Iocp > 4.824A

PQ22
AON7408L_DFN8-5

BST_1.1V ALW

POK

PR85
0_0603_5%
1
2

<29,31>

PR83
0_0402_5%
1
2

B+

<Vo=1.1V> VFB=0.75V
V=0.75*(1+4.99K/10K)=1.124V

3
2
1

PC69
4.7U_0805_25V6-K

PC68
4.7U_0805_25V6-K

PL11
HCB2012KF-121T50_0805
1.1VALW _B+ 2
1

1
+
2

PR89
4.99K_0402_1%
1
2
2

PR90
10K_0402_1%
2

PL13
HCB2012KF-121T50_0805

G5603RU1U_TQFN14_3P5X3P5

PC86
4.7U_0603_6.3V6K

PC80
0.1U_0603_25V7K
2
1

PC79
4.7U_0805_25V6-K
2
1

PC81
2200P_0402_50V7K

+1.05VSP

PC84
220U_D2_2VY_R15M

DL

PGND
8

PGOOD

AGND

6
2

PC85
4.7U_0603_6.3V6K

@ PR97
4.7_1206_5%

DL_1.05VALW

+5VALW

@ PC87
680P_0603_50V7K

PR96
15K_0402_1%

10

VDD

LX_1.05VALW
1

ILIM

11

15

14

12

0.1U_0603_25V7K

PQ25
FDMC7692S_MLP8-5

FB

LX

VCC

VFB=0.75V

13

OUT

DH_1.05VALW

DH

3
2
1

PL14
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

PC83
1

PR95
100_0603_1%
1
2

+5VALW

TON

B+

PQ24
AON7408L_DFN8-5

BST_1.05V ALW

BST

2
3

TP

PU7

EN_SKIP

PC82
.1U_0402_16V7K

PR94
30K_0402_5%
@

<25,27,32> SUSP#

4
PR93
0_0603_5%
1
2

3
2
1

PR92
200K_0402_1%
1
2

1
2

5
PR91
255K_0402_1%
1
2

PC78
4.7U_0805_25V6-K

1.05VALW _B+ 2

1
+

<Vo=1.05V> VFB=0.75V
V=0.75*(1+3.57K/8.25K)=1.074V

Cout ESR=25m ohm


Rdson(max)=17.9m ohm Rdson(typ)=14.5 mohm.(IRFH3707)
Ipeak=5.5A, Imax=3.85A, Iocp > 6.6A

PR98
3.57K_0402_1%
1
2

OCP setting

RT8209B

TPS51117

RT8209M

6.524A

7.003A

7.768A

7.881A

PR99
8.25K_0402_1%

G5603

G5603
Temperature
Compensated

RT8209B

-1180ppm/

1600ppm/

TPS51117

4500ppm/

RT8209M

4800ppm/

30mV

50mV

30mV

50mV

Vtrip_max (SPEC)

200mV

200mV

200mV

200mV

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Vtrip_min (SPEC)

2010/08/12

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

1.1VALWP/1.0VSP
Size Document Number
Custom
Date:

Rev
1.0

W ednesday, November 17, 2010


D

Sheet

33

of

36

PJ11
JUMP_43X118
@

PU8
1
2
1

GND

NC

VREF VCNTL

+3VALW

8
7
6

PC89
1U_0402_6.3V6K

PR100
1K_0402_1%

NC

VOUT

PC88
4.7U_0603_6.3V6K

VIN

+1.5V

NC
TP

5
9

PQ26
SSM3K7002FU_SC70-3

+0.75VSP

PR102
1K_0402_1%

PC90
.1U_0402_16V7K
2
1

PC91
10U_0603_6.3V6M

PC92
.1U_0402_16V7K

2
G

PR101
300K_0402_5%
1
2

SUSP

<27>

APL5336KAI-TRL_SOP8P8

For shortage changed

Compal Secret Data

Security Classification
2010/08/12

Issued Date

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


0.75VSP

Size
Date:

Document Number

Rev
1.0

Wednesday, November 17, 2010

Sheet
1

34

of

36

PL15
HCB2012KF-121T50_0805

CPU_B+
PC93
33P_0402_50V8J
2
1

PR124
0_0402_5%

PR126
26.1K_0402_1%
2
1

6
7
8

SVC

PGND0
LGATE0

RBIAS

PVCC

OCSET

LGATE1

VDIFF0

PGND1

35

BOOT0

34

UGATE0

33

PHASE0

32

PC99
68U_25V_M_R0.44

PC98
2200P_0402_50V7K
2
1

PC97
0.1U_0603_25V7K
2
1

PC96
4.7U_0805_25V6-K
2
1

PC103
220U_D2_2VY_R15M

1
1 2

PC110
2200P_0402_50V7K
2
1

PC109
0.1U_0603_25V7K
2
1

PC108
4.7U_0805_25V6-K
2
1

PC107
4.7U_0805_25V6-K
2
1

PC106
4.7U_0805_25V6-K
2
1

3
2
1

+5VALW

30
29
28

PQ30
FDMC7692S_MLP8-5

PR123
6.98K_0402_1%

@PC112
@PC112
680P_0603_50V7K

PC113
2
1
0.1U_0603_16V7K

PC114
1U_0603_16V6K

2
LGATE0

27

PR127
1.87K_0402_1%

26

TP

25

49

ISN1
24

ISP1
23

VW1
22

COMP1
21

FB1
20

VDIFF1
19

VSEN1
18

RTN1

BOOT1

ISN0

ISP0

PR130
0_0402_5%
2
1

17

14

PR129
0_0402_5%

10_0402_1%

<4> APU_VDD0_RUN_FB_H

VSEN1

13

VSEN1
PR128
+APU_CORE

@ PR122
4.7_1206_5%

LGATE0

31

+APU_CORE

ISP0
ISN0

RTN0

UGATE1

VW0

VSEN0

COMP0

ISP0

12

PHASE1

16

11

FB0

PC111
0.22U_0603_10V7K

PHASE0

36

PL17
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

UGATE0

SVD

ISL6265CHRTZ-T_TQFN48_6X6

PR118
2.2_0603_1%
BOOT0 1
2 1

38

39

40

41

PWROK

15

10

37
UGATE_NB

PHASE_NB

LGATE_NB

PGND_NB

42

43

44

45

46

BOOT0

BOOT_NB

BOOT_NB

PGOOD

ENABLE

ISN0

PR125
90.9K_0402_1%
2
1

VR_ON

@ PC104
680P_0603_50V7K

ISP0

100P_0402_50V8J

1 2

2
PR121
0_0402_5%2

+APU_CORE_NB

PHASE0

3
2
1

<4>

PQ29
AON7408L_DFN8-5

@ PC124
@PC124
2
1

OFS/VFIXEN

OCSET_NB

ISN0

<25>

PC123
100P_0402_50V8J
2
1

ISL6265_PWROK

<4> APU_SVD
APU_SVC

2
@ PR119 100K_0402_5%
2
PR120 100K_0402_5%

RTN_NB

VSEN_NB

<11> H_PWRGD_L

FSET_NB

<12> FCH_PWRGD

FB_NB

VCC

VGATE

COMP_NB

47

48
VIN

PU9

@PR107
4.7_1206_5%

CPU_B+

UGATE0
@ PR117
105K_0402_1%

PQ28
FDMC7692S_MLP8-5

PHASE_NB

@ PR114
105K_0402_1%

<12,25>

<4>

APU_VDDNB_RUN_FB_L <4>

UGATE_NB

@
PR116
10K_0402_1%

PR115
105K_0402_1%

PC102
0.22U_0603_10V7K
4

APU_VDDNB_RUN_FB_H

PR113
0_0402_5%

LGATE_NB

PL16
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

PR139
10_0402_5%
100P_0402_50V8J
2
1
1
2
PR111
0_0402_5% PR112
PHASE_NB
2
1
23.7K_0402_1%
LGATE_NB

+3VS

PR108
10_0402_5%
1
2 +APU_CORE_NB

@ PC122
2
1

PC105
0.1U_0603_25V7K

PHASE_NB
PR105
2.2_0603_1%
BOOT_NB
1
2 1

B+

PR109
2_0603_5%

+3VS

+5VS

3
2
1

UGATE_NB

PR106
22K_0402_1%
2
1
PR110
0_0402_5%
2
1
@ PC121
100P_0402_50V8J
2
1

PC101
0.1U_0603_16V7K

CPU_B+

PC100
1000P_0402_50V7K
2
1
1

+5VALW

PC95
4.7U_0805_25V6-K
2
1

PR104
2_0603_5%
1
2

PC94
1000P_0402_50V7K

3
2
1

PR103
44.2K_0402_1%

2
PQ27
AON7408L_DFN8-5

VSEN0
2

@ PC119
@PC119
100P_0402_50V8J
2
<4> APU_VDD0_RUN_FB_L
2

PR131
10_0402_1%
1

@ PC120
@PC120
100P_0402_50V8J
1 RTN0

0_0402_5%
PR132
DIFF_0

VW0

PR134
PC115
255_0402_1% 4700P_0402_25V7K
2
1 2
1

COMP0

PC116
100P_0402_50V8J

PR135
1K_0402_5%
2
1

PR136
2

PC118
2
1

+3VS

7.87K_0402_1%
PR133
2
1

6.49K_0402_1%
PR140
2
1

PC117
1000P_0402_50V7K

PR137
6.81K_0402_1%
2
1

54.9K_0402_1% 1200P_0402_50V7K

Compal Secret Data

Security Classification
PR138
36.5K_0402_1%

2010/08/12

Issued Date

2012/08/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


CPU_CORE

Size
Date:

Document Number

Rev
1.0

Wednesday, November 17, 2010

Sheet
E

35

of

36

Version change list (P.I.R. List)


Item

Page 1 of 1 for PWR

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Date

Phase

Modify CP point for 40W adapter (40W*0.85=34W)

30

Change PR43 from SD034249280 (S RES 1/16W 24.9K +-1%


0402) to SD034470180 (S RES 1/16W 4.7K +-1% 0402)

20101011

EVT

Modify Outpot current sensor follow PAV70 design

30

Change PR38 from SD012200D80 (S RES 1/2W 0.02 +-1%


1206) to SD00000CI10 (S RES 1/2W 0.05 +-1% 1206 )

20101011

EVT

30

Change PR39 from SD034309380 (S RES 1/16W 309K +1%


0402) to SD034620280 (S RES 1/16W 62K +-1% 0402)

20101011

EVT

32

Change PR73 from SD034787180 (S RES 1/16W 7.87K +-1%


0402) to SD034150280 (S RES 1/16W 15K +-1% 0402)

20101011

EVT

33

Change PR88 from SD034100280 (S RES 1/16W 10K +-1%


0402) to SD034130280 (S RES 1/16W 13K +-1% 0402)

20101011

EVT

33

Change PR96 from SD034140280 (S RES 1/16W 14K +-1%


0402) to SD034150280 (S RES 1/16W 15K +-1% 0402)

20101011

EVT

20101011

EVT

20101011

EVT

Modify KI =1.62 follow PAV70 design

Modify 1.5V OCP


(there is only one dimm for 10.1")

Modify 1.1V OCP for G5603

Modify 1.05V OCP for G5603

Modify +APU CORE OCP setting

35

Change PR123 to 6.98K ohm , PR127 to 1.87K ohm,


PR125 to 90.9K ohm, PR126 to 26.1K ohm

+APU CORE power sequence concern

35

change PR116

Modify RTC schematic

28

add PR141 & PR142 =560 ohm

20101011

EVT

10

Modify SY8033B Enable pin pull down resistor

32

Change PR72 to non-pop

20101011

EVT

11

Modify 1.8VS power sequence

32

Change PR70 to 200K ohm , add PC56 =0.22uF

20101012

EVT

12

Modify 1.05VSP power sequence

33

Change PR92 to 200K ohm , add PC82 =0.1uF

20101012

EVT

13

Modify 0.75VSP power sequence

34

Change PR101 to 300K ohm , add PC92 =0.1uF

20101012

EVT

to non-pop

14
B

15

16
17
18
19
20
21
22
A

23

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/12

Deciphered Date

2012/08/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PIR (PWR)
Size Document Number
Custom
Date:

Monday, November 15, 2010

Rev
1.0
Sheet
1

36

of

36

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