CMOS
Outline Part I
The MOS transistor: quick summary
The MOS transistor DC characteristics Important formulas
2
AICS
y z x
iD S g
G S
Transconductance
3
n+
n+
LINEAR REGION (Low VDS): Electrons (in light blue) are attracted to the SiO2 Si Interface. A conductive channel is created between source and drain. We have a Voltage Controlled Resistor (VCR).
n+
n+
SATURATION REGION (High VDS): When the drain voltage is high enough the electrons near the drain are insufficiently attracted by the gate, and the channel is pinched off. We have a Voltage Controlled Current Source (VCCS).
Iout I RS
5
AICS
2.5E-05
2.0E-05
IDS [ A ]
Output conductance
1.5E-05
1.0E-05
5.0E-06
0.0E+00 0.0
VDS [ V ]
6
CMOS
Figure 5
Figure 5 shows a cross section of a CMOS chip illustrating how the PMOS and NMOS transistors are fabricated. Observe that while the NMOS transistor is implemented directly in the p-type substrate, the PMOS transistor is fabricated in a specially created n region, known as an n well. The two devices are isolated from each other by a thick region of oxide that functions as an insulator.
AICS
Circuit Symbol
NMOS
PMOS
AICS
Saturation region :
where, iD
Drain current
n
Cox W L vGS VT
=
= = = = =
Electron mobility
Capacitance per unit area Width Length Gate-source voltage Threshold voltage
AICS
Linear region,
Saturation region,
AICS
Gm and Ro (NMOS)
Transconductance for NMOS transistor in saturation,
AICS
Slide 11 of 34
Linear region,
Saturation region,
AICS
Gm and Ro (PMOS)
Transconductance for PMOS transistor in saturation,
AICS
Slide 13 of 34