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Code: 9D57101 M.TECH - I Semester Regular and Supplementary Examinations, April/May 2012 VLSI TECHNOLOGY (Common to VLSIS, VLSISD, VLSI, VLSID and ES) Time: 3 hours Max Marks: 60 Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) 2 (a) (b) 3 (a) (b) 4 (a) (b) 5 (a) (b) 6 (a) (b) 7 (a) (b) 8 (a) (b) Discuss the various process of CMOS fabrication. Tabulate the comparison of MOS and CMOS technologies. Discuss the electrical properties of Bi CMOS circuits. Discuss the function latch-up in CMOS circuits. Explain scaling models and scaling factors. Write short notes on sheet resistance.

Discuss the features of low power gates. Explain the role of inductive interconnect delays.

Explain the features of Interconnect design. List the salient features of gate and network testing.

Explain the role of power optimization in sequential system. Discuss various parasitic elements in MOS transistor. Explain the features of memory cells in sequential systems. Discuss the features of off-chip connection. Explain the steps involved in layout synthesis. Write short notes on scheduling and printing.

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