ME 6405: Mechatronics

Analog to Digital Converters

Erik Lee
Gabriel Ramirez
Siddharth Doshi

February 13, 2008

Georgia Institute of Technology

George W. Woodruff School of Mechanical Engineering
 Analog to Digital Converter
Overview
•Signals
•ADC
•ADC Properties

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 What is an Analog Signal
•Continuous in nature
•Has a value at every instant in time

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 What is a Discrete Signal
•Non-continuous
•No knowledge of values between
samples

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 What is an ADC?
•Converts an analog signal to discrete
values
•Most cases it’s a voltage signal to some
physical parameter (temp,pressure,etc.)

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 ADC Properties
•Quantization
–Saturation
•Sampling
–Aliasing

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 Quantization
•The process of converting a voltage
value to a binary word.
•Dependent on resolution of Analog to
Digital converter
•Can range from 6 to 18 bits
1.2

0.8

0.6

0.4

0.2

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George W. Woodruff School of Mechanical Engineering
 Quantization

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Quantization Resolution
∆V fs RV = Voltage Resolution
RV = ∆V fs = Full-Scale Voltage Range
2n n = Number of Bits of ADC

Increase Resolution

⇒
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 Resolution and Saturation
•To increase resolution always use a input
voltage range that is equal to ADC
voltage range
•Can amplify signal to increase resolution
•Saturation Example
–ADC full-scale range is 0V to 10V
–What if our analog signal is oscillation
between 10V and 11V?

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George W. Woodruff School of Mechanical Engineering
 Sampling Frequency
1
Fs = Ts = Sampling Period
Ts

Ts
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 Sampling
•At each sampling period the voltage
value at that time will be quantized
•The sampling frequency is limited by the
ADC
•Can vary from 1000 Hz to the MHz range

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George W. Woodruff School of Mechanical Engineering
 Aliasing
•Must satisfy Nyquist Criterion if we are
going to try to reconstruct the signal

f sample > 2 f signal

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 Aliasing
•Frequencies will show up as a lower
frequency

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 Filtering
•No matter how fast one samples, can’t
guarantee there is no aliasing
•Low-pass filters can be used to prevent
aliasing
–Butterworth
•Better attenuation
•Larger phase shift
–Bessel

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George W. Woodruff School of Mechanical Engineering
 Filtering/Sampling
•Cutoff at 0.5
•1st order Butterworth filter
Example:
ω samp = 1000 Hz
ω cutoff = 500 Hz
Frequencies down to
200Hz will still be
attenuated.

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George W. Woodruff School of Mechanical Engineering
 Types of ADC
• Flash ADC
• Delta-Sigma ADC
• Dual Slope (integrating) ADC
• Successive Approximation ADC

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 Types of ADC
• Comparison

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 Types of ADC
• Flash
–Most high-speed
oscilloscopes

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 Types of ADC
• Flash
Advantages
• Simplest in terms of
operational theory
• Most efficient in terms
of speed, very fast
• limited only in terms of
comparator and gate
propagation delays
Disadvantages
• Lower resolution
• Expensive
• For each additional
output bit, the number
of comparators is
doubled
• i.e. for 8 bits, 256
comparators needed

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George W. Woodruff School of Mechanical Engineering
 Types of ADC
• Sigma Delta ADC
– resolution as fine as 24 bits
–Audio frequency signals

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 Types of ADC
• Sigma Delta ADC

Advantages Disadvantages
• High resolution • Slow due to oversampling
• No precision external
components needed

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 Types of ADC
• Dual Slope (integrating) ADC
–Superior noise rejection
–DMMs

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George W. Woodruff School of Mechanical Engineering
 Types of ADC
• Dual Slope ADC
Advantages Disadvantages
• Input signal is • Slow
averaged • High precision
• Greater noise external components
immunity than other required to achieve
ADC types accuracy
• High accuracy

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 Successive Approximation
ADC
•Binary search through all quantization
levels.
•From MSB to LSB.
•MSB initialized as 1.
•Closed-Loop.

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 Successive Approximation
ADC
•Circuit

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 Successive Approximation
ADC
•Example
• 10 bit resolution or
0.0009765625V of
Vref
• Vin= .6 volts
• Vref=1volts
• Find the digital value
of Vin

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George W. Woodruff School of Mechanical Engineering
 Successive Approximation
ADC
• MSB (bit 9)
Divided Vref by 2
Compare Vref /2 with Vin
If Vin is greater than Vref /2 , turn MSB on (1)
If Vin is less than Vref /2 , turn MSB off (0)
Vin =0.6V and V=0.5
Since Vin>V, MSB = 1 (on)

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George W. Woodruff School of Mechanical Engineering
 Successive Approximation
ADC
• Next Calculate MSB-1 (bit 8)
Compare Vin=0.6 V to V=Vref/2 + Vref/4= 0.5+0.25 =0.75V
Since 0.6<0.75, MSB is turned off
Calculate MSB-2 (bit 7)
Go back to the last voltage that caused it to be turned on
(Bit 9) and add it to Vref/8, and compare with Vin
Compare Vin with (0.5+Vref/8)=0.625
Since 0.6<0.625, MSB is turned off

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George W. Woodruff School of Mechanical Engineering
 Successive Approximation
ADC
•This process continues for all the remaining
bits.

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 Successive Approximation
ADC
Advantages Disadvantages

• Capable of high speed • Higher resolution

and reliable successive approximation
• Medium accuracy ADC’s will be slower
compared to other ADC • Speed limited to ~5Msps
types
• Good tradeoff between
speed and cost
• Capable of outputting the
binary number in serial
(one bit at a time) format.

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 A/D on HC11
• Components (Block Diagram)
• Features
• Options Register
• A/D Control Register
• A/D Results Registers
• Conversion Timing
• Example Program
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 A/D Converter on HC11
PE0
AN0 8-BIT CAPACITIVE DAC WITH VRH
PE1 SAMPLE AND HOLD
AN1 VRL
PE2
AN2 SUCCESSIVE APPROXIMATION
REGISTER AND CONTROL
PE3
AN3
ANALOG RESULT
PE4 MUX
AN4

PE5
AN5
INTERNAL
PE6 DATA BUS
AN6

SCAN
MULT
CCF

CD
CC
CB
CA
PE7
AN7

ADCTL A/D CONTROL

RESULT REGISTER INTERFACE

ADR 1 ADR 2 ADR 3 ADR 4

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 Simplified Diagram
Pin: 7 6 5 4 3 2 1 0

Port E (analog input)

ADCTL ADR1 - result 1

Analog Multiplexer
ADR2 - result 2
Result
A/D Converter Register ADR3 - result 3
Interface
ADR4 - result 4

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 Features
• Charge Redistribution SAR ADC
• 8 input channels, can convert 4 in one
procedure, +/-0.5LSB Accuracy
• Analog Input between 0-5V
• Resolution = 8 bits = 256 Discrete Values
= Steps of (VRH-VRL)/256
• VRL Æ #$00, VRHÆ #$FF

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Analog Input translation Table

Bit 7 6 5 4 3 2 1 Bit 0

%
50% 25% 12.5% 6.25% 3.12% 1.56% 0.78% 0.39%
(VRH-VRL)

VRH= 5V
2.500 1.250 0.625 0.3125 0.1562 0.0781 0.0391 0.0195
VRL= 0V

VRH= 3.3V
1.65 0.825 0.4125 0.2063 0.1031 0.0516 0.0258 0.0129
VRL= 0V

Page 41, Programming Reference guide

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George W. Woodruff School of Mechanical Engineering
Option Control Register
OPTION Register ($1039)

7 6 5 4 3 2 1 0

ADPU CSEL IRQE DLY CME CR1 CR0

Reset: 0 0 0 1 0 0 0 0

ADC concerned with :

ADPU – A/D power up

CSEL – A/D Charge Pump Clock select
DLY – Oscillator Startup Delay (4000 clock cycles)

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George W. Woodruff School of Mechanical Engineering
Option Control Register

ADPU - A/D Charge Pump Power Up

0: Turn off the A/D
1: Turn on the A/D (by enabling the charge pump)
Note: Wait 100 microseconds before using the ADC to allow charge
pump and comparator circuits to stabilize.

CSEL - A/D Charge Pump Clock select

0: Use the E-clock for the A/D
1: Use internal RC oscillator that runs at around 2MHz
Note: If the E-clock is 750KHz or higher, CSEL should be 0.
Otherwise CSEL should be 1.

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 A/D Control Register
ADCTL Register ($1030)
7 6 5 4 3 2 1 0

CCF SCAN MULT CD CC CB CA

Reset: 0 0 Indeterminate after Reset
MULT - Single or multiple channel
0: Sample a single channel (four times)
1: Sample four channels
CD,CC,CB,CA - Channel selection
If MULT is 0, then CC-CA bits specify the channel
If MULT is 1, then CC specifies the group:
0: Sample AN0-AN3, 1: Sample AN4-AN7
CD is reserved for factory test use
CCF - Conversion Complete Flag
Set when all four conversions are complete
Cleared by writing to ADCTL - starts the next conversion
SCAN - Continuous scan mode
0: Take one set of four conversions and stop
1: Continually perform new conversions
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A/D Control Register
Conversion Combinations

Single Channel Multiple Channel

(MULT = 0) (MULT = 1)
Single 1 channel. 4 channels.
Conversion Converted 4 times. Converted once.
Results in ADR1-4. Results in ADR1-4.
(SCAN = 0)
1 channel. 4 channels.
Continuous
Conversion Converted Converted
continuously. continuously.
(SCAN = 1)
ADR1-4 overwritten ADR1-4 overwritten

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 A/D Control Register
Channel Selection

CD CC CB CA Channel Signal If Mult =1, ADR

0 0 0 0 PE0 ADR1
0 0 0 1 PE1 ADR2
0 0 1 0 PE2 ADR3
0 0 1 1 PE3 ADR4
0 1 0 0 PE4 ADR1
0 1 0 1 PE5 ADR2
0 1 1 0 PE6 ADR3
0 1 1 1 PE7 ADR4
1 0 0 0 Reserved ADR1
1 0 0 1 Reserved ADR2
1 0 1 0 Reserved ADR3
1 0 1 1 Reserved ADR4
1 1 0 0 VH ADR1
1 1 0 1 VL ADR2
1 1 1 0 1/2 VH ADR3
1 1 1 1 Reserved ADR4

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 A/D Results Registers
ADR1-ADR4 Registers

Read: 7 6 5 4 3 2 1 0

Write:

Reset: Indeterminate after Reset

ADR1 = $1031 Read Only.

ADR2 = $1032 Writes to these register
have no effect.
ADR3 = $1033
ADR4 = $1034

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George W. Woodruff School of Mechanical Engineering
Conversion Sequence/Timing
E Clock cycles:

Sample (12) Bit 7 (4) 6 (2) _ (2) 0 (2) End

(2)
ADCTL
Successive approximation
write (1)

CCF
1st, ADR1 2nd, ADR2 3rd, ADR3 4th, ADR4
0 32 64 96 128 total

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 Stop & Wait Modes

Enter wait/stop mode

– conversion sequence suspended
Exit wait/stop mode
– channel re-sampled / conversion
resumed
– For stop mode, A/D circuitry requires time
to stabilize (10 ms or DLY bit in OPTION)

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 Program Example
ORG $1040
LDAA #$80 OPTION
STAA $1039 ADPU=1,CSEL=0
LDY #$30
Delay for charge pump
LOOP DEY
BNE LOOP to stabilize 100µs

LDAA #$00 ADCTL

STAA $1030 SCAN=0,MULT=0,
CHAN=000
LDX #$1030
WAIT BRCLR 0,X #$80 WAIT Wait until CCF or bit 7=“1”

LDAA $1031
PSHA Read and store result
SWI
END

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George W. Woodruff School of Mechanical Engineering
 ADC Examples
•ADC0808/ADC0809
– 8-Bit µP Compatible A/D Converters with
8-Channel Multiplexer

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 ADC Examples

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 ADC Examples
•Vehicles
–ECU
•Temp Sensor
•Oxygen Sensor
•RPM
•TV Tuner Card

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 ADC Examples
•Oscilloscope

•Music Recording

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 ADC Examples
•Analog signal needs to be processed,
stored or transported in digital form.

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George W. Woodruff School of Mechanical Engineering