1

Chapter 10
Operational-Amplifier Circuits
C.-Y. Su(2011) 2
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Outline
The Two-Stage CMOS Op Amp
The Folded-Cascode CMOS Op Amp
The 741 Op-Amp Circuit
DC Analysis of the 741
Small-Signal Analysis of the 741
Gain, Frequency Response, and Slew Rate
of the 741
Modern Techniques for the Design of BJT Op
Amps
3
TheTwo-StageCMOSOp
Amp
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+
_
V
GS3
V
ICM
+
_
V
SG5
Two-StageCMOSOP Amp
tp OV tn SS ICM
V V V V V + + >
3
V
GS3
1 5 SG OV DD ICM
V V V V s
C.-Y. Su(2011) 5
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VoltageGainandR
o
) // )( // (
: gain dc
//
2
: gain dc
//
) 2 / ( 2
7 6 4 2 6 1
2 2 1 1 2 1
2 2 2
7 6 2
6
6
6 2
1 1 1
4 2 1
2 1 1
o o o o m m
m m v
m
o o o
ov
D
m m
m
o o
ov
m m m
in
r r r r g g
R G R G A A A
R G A
R r r R
V
I
g G
R G A
r r R
V
I
g g G
R
=
= =
=
= =
= =
=
=
= = =
=
C.-Y. Su(2011) 6
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FrequencyResponse
C
m
C m
m m P v t
C
G
C R G R
R G R G f A f
2 2
1
1
2 2 1
2 2 1 1 1
= = ~
C
m
Z
m
P
C m
P
C
G
f
C
G
f
C R G R
f

2
2
2
1
2
2
2
2
2 2 1
1
~
~
~
To achieve the goal of a uniform -20 dB/decade
gain rolloff down to 0 dB, the f
t
The design must satisfy
2 1
2 1
2
and
2 2
and
m m
C
m
C
m
z P t
G G
C
G
C
G
f f f
< <
<

C.-Y. Su(2011) 7
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PhaseMargin
) / ( tan ) / ( tan 90
1
2
1
Z t P t total
f f f f

+ + =
|
|
.
|

\
|
=
|
|
.
|

\
|
=

Z
t
Z
P
t
P
f
f
f
f
1
2
1
2
tan
tan

Excess phase shift

The phase lag at f=f
t
will be
Thus the phase margin will be
) / ( tan ) / ( tan 90
180
1
2
1
Z t P t
total
f f f f

=

C.-Y. Su(2011) 8
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ProvidingAdditional PhaseLag
2 2
2
1
i m
C
i
V G
sC
R
V
=
+
|
|
.
|

\
|
= R
G
C s
m
C
2
1
/ 1
Setting V
o
=0 gets
Thus the new transmission zero is at
1. Selecting R=1/G
m2
, we can place the zero at infinite frequency.
2. Selecting R greater than 1/G
m2
place the zero at a negative real-axis
location where the phase it introduces adds to the phase margin.
) / ( tan ) / ( tan 90
margin phase
1
2
1
Z t P t
f f f f

=
=0 =0
C.-Y. Su(2011) 9
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SlewRate
) from (pulled current a sink will
on, off,
4
1 1 2
C
D
C I Q
I I Q Q =
OV t OV t
t
m
C
C
o
V V f
f
g
I
C
I
SR
t
C
I
t v

= = = =
=
2
2
) (
1
(G
m1
=g
m1
=I/V
OV1
)
10
TheFolded-CascodeCMOS
OP AMP
C.-Y. Su(2011) 11
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Structureof theFolded-CascodeCMOS
OP AMP
I
B
-I/2
I
B
-I/2
C.-Y. Su(2011) 12
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A MoreCompleteCircuit
R
o4
~(g
m4
r
o4
)(r
o2
//r
o10
)
R
o6
~(g
m6
r
o6
)r
o8
C.-Y. Su(2011) 13
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VoltageGain
Dc open-loop gain:
)} //( )] // ( {[
) // (
8 6 6 10 2 4 4 1
6 4 1
o o m o o o m m
o o m
o m v
r r g r r r g g
R R g
R G A
=
=
=
The folded-cascode op amp is simply a transconductance
amplifier with an infinite input resistance, a transconductance G
m
and an output resistance R
o
. The amp is given the name
operational transconductance amplifier (OTA).
C.-Y. Su(2011) 14
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FrequencyResponse
p
o
o L
o m
L
o m
id
o
s
A
R sC
R G
sC
R G
V
V

+
=
+
= =
1
1
)
1
// (
o L
P
R C
f
2
1
=
Thus, the dominant pole has a frequency f
p
,
And the unity-gain frequency f
t
will be
L
m
P o m P v t
C
G
f R G f A f
2
= = =
The value of C
L
should be such that at f=f
t
the excess phase
resulting from nondominant poles is small enough to permit the
required phase margin to be achieved.
C.-Y. Su(2011) 15
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SlewRate
Slewing occurs when a large differential input signal is applied.
Assume that a large v
id
is applied so that Q
2
cuts off and Q
1
conducts
the current I.
I
B
I
B
-I
I
B
-I
I
B
-I
I
L L
o
C
I
SR t
C
I
t V = = ) (
C.-Y. Su(2011) 16
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IncreasingtheInput Common-ModeRange: Rail-to-Rail
Input Operation
An NMOS and a PMOS differential pair placed in parallel
would provide an input stage with a common-mode range that
exceeds the power supply voltage in both directions. This is
known as rail-to-rail input operation.
V
id
>0
G
m
(V
id
/2)
V
o
=2G
m
R
o
V
id
A
v
=2G
m
R
o
C.-Y. Su(2011) 17
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IncreasingtheOutput VoltageRange: TheWide-Swing
Current Mirror
Cascode current mirror
Wide-Swing current mirror
1
2 3
4
V
omin
=V
t
+2V
ov
1
2
3
4
V
omin
=2V
ov
V
t
>V
ov
Q
4

18
The741OP-AMP Circuit
C.-Y. Su(2011) 19
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741OP-AMP Circuit

C.-Y. Su(2011) 20
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ClassABOutput Stage
Class A Class B
Class AB
21
DCAnalysisof the741
C.-Y. Su(2011) 22
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ReferenceBiasCurrent
5
11 12
) (
R
V V V V
I
EE BE EB CC
REF

=
-V
EE
V
CC
I
REF
=0.73 mA
C.-Y. Su(2011) 23
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Input-StageBias
. obtain can we , and ng Substituti
ln
get we , that Assuming
10 4
4 10
10
11 10
4 10 10 11
C REF
C
C
REF
T
S S
C BE BE
I R I
R I
I
I
V
I I
R I V V
=
=
=
Widlar current source
I
C10
=19 A
C.-Y. Su(2011) 24
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Input-StageBias
1 1
2
2
3
5
6
4
If |
P
>>1, I
C9
~2I=I
C10
.
I
C10
=19 A
I
C9
=19 A
I
C1
=I
C2
~I
C3
=I
C4
=9.5 A
C.-Y. Su(2011) 25
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Input- StageBias
1
2
3
4
5
S
T BE
BE
N
E C
I
I
V V
R
IR V I
I I
ln
2
6
3
2 6
7 7
=
+
+ = ~

Substituting I
S
=10
-14
and
I=9.5 A results in
V
BE6
=517 mV
Thus, I
C7
=10.5 A
5
6
I
C7
I
E7
C.-Y. Su(2011) 26
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Second-StageBias
0.75 I
REF
0.25 I
REF
I
C13B
~0.75 I
REF
=550 A
I
C17
=I
C13B
=550 A
A 2 . 16
mV 618 ln
9
8 17 17
17 16 16
17
17
=
+
+ = ~
= =
R
R I V
I I I
I
I
V V
E BE
B E C
S
C
T BE
I
B17
C.-Y. Su(2011) 27
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Output-StageBias
I
C13A
~0.25 I
REF
=180 A
I
C23
~I
E23
=I
C13A
=180 A
If V
BE18
=0.6V, I
R10
=15 A.
Thus, I
E18
=180-15=165 A
I
C18
~I
E18
=165 A
I
B18
=I
C18
/|=0.8 A
I
C19
~I
E19
=I
B18
+I
R10
=15.8 A
A 154
in results A 10 3 ng Substituti
ln ln
V 118 . 1 530 588
mV 530 ln
20 14
14
20 14
20
20
14
14
19 18
19
19
= =
= =
+ =
= + = + =
= =

C C
S S
S
C
T
S
C
T BB
BE BE BB
S
C
T BE
I I
I I
I
I
V
I
I
V V
V V V
I
I
V V

+
_
V
BB
1
2
+
_
V
BE18
3
28
Small-Signal Analysisof the
741
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TheInput Resistanceof theInput Stage
O = + =
+ =
O = = =
=
M 1 . 2 63 . 2 ) 1 200 ( 4
) 1 ( 4
k 63 . 2
A 9.5
mV 25
4
e N id
E
T
e
e
i
e
r R
I
V
r
r
v
i

C.-Y. Su(2011) 30
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TheTransconductanceof theInput Stage
G
m1
=i
o
/v
i
=2oi
e
/v
i
=o/2r
e
Substituting
r
e
=2.63 kO and
o~1 results in
G
m1
=1/5.26 mA/V
e
i
e
r
v
i
4
=
C.-Y. Su(2011) 31
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TheOutput Resistanceof theInput Stage
(virtual
ground)
R
o4
R
o6
R
o1
=R
o4
//R
o6
R
o4
~[1+g
m4
(r
e2
//r
4
)]r
o4
=10.5 MO
R
o6
~[1+g
m6
(R
2
//r
6
)]r
o6
=18.2 MO
R
o1
=R
o4
//R
o6
~6.7 MO
Ground assumed
C.-Y. Su(2011) 32
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Small-Signal Equivalent Circuit Model for
theInput Stage
6 4 1
1
//
2 /
) 1 ( 4
o o o
e m
e N id
R R R
r G
r R
=
=
+ =

C.-Y. Su(2011) 33
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TheSecondStage
O = =
+ ~
=
=
+ + =
+
=
+
=
O ~
+ + + + =
k 81 90.9//787
)] // ( 1 //[
//
mA/V. 5 . 6
) )( 1 (
) // (
) // (
M 4
)] )( 1 //( )[ 1 (
17 17 8 17 13
17 13 2
2
17
2
8 17 17 17
16 17 9
17 9
2 17
8 17
17
17
8 17 17 9 16 16 2
o m B o
o B o o
i
c
m
e i
e i
i
i b
e
b
c
e e i
r r R g r
R R R
v
i
G
R r R
r R R
R R
v v
R r
v
i
R r R r R

C.-Y. Su(2011) 34
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Small-Signal Equivalent Circuit Model of
theSecondStage
Norton form
Thvenin form
C.-Y. Su(2011) 35
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TheOutput Stage
v
omax
=V
CC
-V
CEsat
-V
BE14
v
omin
=-V
EE
+V
CEsat
+V
EB23
+V
EB20
v
o2
=-G
m2
R
o
v
i2
R
in3
~|
23
(|
20
R
L
//r
o13A
)
=50[(502k)//280k]
=3.7 MO
G
vo3
=v
o
/v
o2
|
RL=
~1
+
_
V
CEsat
+
_
V
CEsat

C.-Y. Su(2011) 36
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TheOutput Resistanceof theOutput Stage
37
Gain, FrequencyResponse,
andSlewRateof the741
C.-Y. Su(2011) 38
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Small-Signal Gain
dB 107.7
V/V 243147 97 . 0 ) 5 . 526 ( 1 . 476
) )( // (
3 2 2 2 1 1
2 2
2 2
0
=
= =
+
=
=
out L
L
vo o m i o m
o
o
i
o
i
i
i
o
R R
R
G R G R R G
v
v
v
v
v
v
v
v
A
C.-Y. Su(2011) 39
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FrequencyResponse
C
C
=30 pF
C
in
=C
C
(1+|A
2
|)=15480 pF
R
t
=R
o1
//R
i2
=2.5 MO
MHz 1 1 . 4 243147
Hz 1 . 4
2
1
0
~ = =
= =
P t
t in
P
f A f
R C
f

3 2
3
2 2
2
3
2
2
2
3
2
) (
in o
in
o m
o
i
i
o
i
i
R R
R
R G
v
v
v
v
v
v
A
+
= =
C.-Y. Su(2011) 40
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SlewRate
Modeling the second stage as an ideal integrator results in the above
model.
C
C
o
C
I
SR
t
C
I
t v
2
2
) (
=
=
For the 741, I=9.5 A and C
C
=30 pF, resulting in SR=0.63 V/s.
41
ModernTechniquesfor the
Designof BJT OpAmps
C.-Y. Su(2011) 42
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Special PerformanceRequirements
Single power supply
Low value of V
cc
C.-Y. Su(2011) 43
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Rail-to-Rail Input Common-ModeRange
Modern BJT op amps can operate over an input
common-mode voltage range that extends a fraction of a
volt beyond its two supply rails.
C.-Y. Su(2011) 44
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BiasDesign
|
|
.
|

\
|
=
=
1
2
2
2 2 1
ln
S
S T
R BE BE
I
I
R
V
I
I V V
C.-Y. Su(2011) 45
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Designof theInput StagetoObtainRail-
to-Rail V
ICM
(a) V
ICMmin
= 0.1 V
(b) V
ICMmin
= V
RC
-0.6V
V
RC
=0.2~0.3V,
V
ICMmin
=-0.4~-0.3V
V
ICMmax
= V
CC
-0.1-0.7
= V
CC
-0.8
C.-Y. Su(2011) 46
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V
RC
=0.3V,
-0.3V sV
ICM
sV
CC
-0.8
V
RC
=0.3V,
0.8V sV
ICM
sV
CC
+0.3
C.-Y. Su(2011) 47
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Input StagewithRail-to-Rail Input Common-ModeRange
andaFolded-CascodeStage
npnpnp
0.8V sV
ICM
sV
CC
-0.8
C.-Y. Su(2011) 48
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Common-ModeFeedbacktoControl the
dcVoltage
C.-Y. Su(2011) 49
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TheSecondStageof anOp-AmpCircuit
C.-Y. Su(2011) 50
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A Buffer/ Driver Stage
C.-Y. Su(2011) 51
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A MoreCompleteVersionof theOutput
Stage