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# Digital Logic circuits

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## Subject: Digital Logic Circuits UNIT I

Using K-map simplify the expression Y (A, B, C, D) = m 1+m 3+m 5+ 1. m 7+m 8+m 9+ m 0+m 2+m 10+m 12+m 13. Indicate the prime implicants, essential and non-essential prime implicants. Realize the logic circuit using AND -OR-INVERT gates and also by using NAND gates. (16) Obtain the simplified function for the Boolean function Y (A, B, C, D) = 2. m 1+m 3+m 5+ m 7 +m 8+m 9+ m 0+m 2+m 10+m 12+m 13 using Quine McClusky method. Obtain the NAND and NOR implementation of the simplified expression. (16) Obtain the minimum SOP using Quine McClusky method and verify 3. using K- map
4. 5. F= m0 + m2+m4+m8+m9+m10+m11+m12+m13. (16) Determine the prime implicants of the following function and verify using K-map F(A,B,C,D) = (3,4,5,7,9,13,14,15). (16) Simplify using K-map to obtain a minimum POS expression for the function F = (A + B + C + D) (A + B+ C + D) (A + B + C + D) (A + B + C + D) (A+ B + C + D)(A + B + C + D). (8) Write short notes on i) alphanum eric codes and ii) Error detection and correction methods (6) i. Simplify F (A,B ,C,D ) = m ( 1,3,5,8,9,11,15) + d (2,13).If dont care conditions are not taken into care what will be the simplified Boolean function? Write your comments on it. Implement both circuits using logic gates. (12) ii. Add 26 and 39 using Excess-3 code. (4) Simplify using five variable mapping F =(8,9,10,11,13,15,16,18,21,24,25,26,27,30,31) (16)

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9. State and prove De - Morgans theorems using two variables. (6) 10. Realize the functions of NOT, AND, OR and NAND gates only with NOR gates. (8) 11. i. Convert the decimal 65 to BCD, Excess-3 and Gray code (4) ii. Encode data bits 1001 into a seven bit even parity Hamming code. (4) 12. Simplify the following Boolean function in SOP and POS form using K-map F ( A,B,C,D) = m( 3,4,9,13,14,15) + d ( 2,5,10,12) (8) 13. Simplify the following function using K map and tabular methods. Compare the methods. F ( A,B,C,D) = m(4,5,6,7,8) + d (11,12,13,14,15).Implement the result using NAND gates. (16) 14. Obtain the minimum SOP using Quine Mc Cluskys method for the function m(0,1,2,8,9,15,17,21,24,25,27,31) (7) 15. What are codes? Explain the different codes with examples. (16) 16. Prove the following Boolean identities i) x + xyz + yzx + wx + wx + xy = x + y ii) (X1 + X2) (X1 X3 + X3) (X2 + X1X3) = X1X2 (6) 17. The state of 12 cell register is 010110010111.What is its contents if it represents a) Three decimal digits in BCD b) Three decimal digits in Excess- 3 code. c) Three decimal digits in 2421 code d) Three decimal digits in 84-2-1 code. (8)
18. Implement the following expression with 2 - input NAND NOT gates. Assume that only true values of the inputs are available = (AB + AB) (CD + CD).Also

use a multiple level implementations to reduce the number of gates. Hint Use a two level AND OR implementation plus NOT gates on the inputs as needed. Then convert to NAND NOT gates. (16) 19. Simplify the following switching function F(A,B,C,D,E) = m(1,3,6,10,11,12,14,15,17,19,20,22,24,29,30) (16) 20. i) Perform the following arithmetic using twos complement (+27) + (-61), (-27) + (+61) and (-27) + (-61). (6) ii) Generate the parity bits for 8421 BCD code in an odd parity system. (2) 21. Perform the following using 12 bit twos complement arithmetic i. 8 - 7 ii. -8 -7 iii. - 8+7 (6) 22. Given F = ABE + BCDE + BCDE+ ABDE + BCDE, BE +BDE is the simplified version of the expression. Are there any dont care conditions, if so what are they? (8) 23. Simplify the function F(w,x,y,z) = m(2,3,12,13,14,15) using tabulation method. Implement the simplified function using gates. (8) 24. Obtain a four level NAND network for F (A, B, C, D) = (AB + C) D + EF (8) 25. Simplify the function F(w,x,y,z) = m(1,4,6,7,8,9,10,11,15) using tabulation method. Implement the simplified function using gates. (8) 26. Explain the term Prim e Implicants. Write notes on computer aided minim ization procedure. (10) 27. Simplify the five variable switching function F(E,D,C,B,A)=m(3,5,6,8,9,12,13,14,19,22,25,30) (16) 28. Determine the Prime Implicants and Essential Prime Implicants of the function F(w,x,y,z) = m(1,4,6,7,8,9,10,11,15) using tabulation method. (16) 29. Realise F(A,B,C,D) = m(0,3,4,5,8,9,10,14,15) using three input NOR gates. (16) 30. Find the MSP form of F (w, x, y, z) = m(1 3, 5-10,12 14) using the Quine Mc Clusky method. (16)
31. Perform the following: i) (-105)10 + (-120)10 using ones and twos complement. Comment

on the result. ii) Divide 100000110.1 by 101 and perform 100000 0.11 using ones complement, iii) (34)10 + (19)10 using excess 3 code. iv) Determine whether single error has occurred and if so, corrects the error using Hamming code, for 1100010. (16) 32. Compare ones complement and twos complement representation of signed binary numbers. (16) 33. Obtain the minimum SOP using Quine MC Cluskys method and using K -map. F = m0+ m2 + m4 + m8 + m9 +m10 + m11 + m12 + m13 (16) 34. Reduce the following using tabulation method. F = m2 + m3 + m4 + m6 + m7 +m9 + m11 + m13. (16) 35. Using Quine Mc Clusky method find all the prime implicants and the minimum SOP for the function F ( a, b, c, d) = m(0,4,5,7,8,11,12,15) (16) 36. Convert the decimal number 342.75 to binary, octal and hexa decimal. (6) 37. Draw and explain the working of 4 bit adder subtractor circuit. 38.Design a 4 bit BCD to Excess- 3 code converter. 39.Design a 4 bit Binary to gray code converter. 40.Design a two bit magnitude Comparator (8) (10) (10) (8)

41.The inputs to a circuit are the four bits of the binary number D3 D2 D1 D0. The circuit produces a one if and only if all of the following conditions hold, i. MSB is 1 or any of the other bits are a 0. 2

D2 is a 1 or any other bits are a 0. ii. iii. Any of the 4 bits are 0 Obtain a minimal expression for the output. (8) 42. i) Design a Half subtractor using NAND- NAND logic (6) ii) Design a four bit gray to binary code converter. (10) 43.Explain the working of carry look ahead generator (10) 44. A majority gate is a digital circuit whose output is equal to 1 if majority of its inputs are 1s.The output is 0 otherwise. Using a truth table, find the Boolean function implemented by a 3-input majority gate. Simplify the function and implement it with logic gates. (8) 45. i) Construct a BCD to Excess -3 code converter using full adders (8) ii) Design an 8421 to gray code converter. (8) 46. i) Design and implement a full adder circuit using logic gates and also by using half adders. (8) 47. i. Design a logic circuit to simulate the function f (A, B, C) = A (B + C) by using only NAND gates. (4) ii. Explain with truth table and gate level circuits diagram for a full adder. (12) 48. i. What is a decoder? How is it different from encoder? (6) ii. Implement the following function with a Multiplexer f (a, b, c, d) = ( 0, 1, 3, 4, 8, 9, 15) (10) 49.Using 8 to 1 multiplexer, realize the following Boolean function T = f (w,x,y,z) = (1,1,2,4,5,7,8,9,12,13) (16) 50. i. Implement full adder circuit using, a) Decoder b) Multiplexer (12) ii. How can you convert a decoder into a de-multiplexer? (4) 51. i. Using 8 to 1 multiplexer, realize the Boolean function T = f (w, x, y, z) = m (0, 1, 2, 4, 5, 7, 8, 9, 12, 13) (8) ii. Realize the function given in (i) using Decoder and external gates. (8) 52. Implement the function Y (A, B, C, D) = m (1, 3, 5, 7, 8, 9, 0, 2, 10, 12, 13) using 4:1MUX. (16) 53. i. Implement the logic function Y(A,B,C) = m ( 1, 2, 7) using 74151A and 74153 (8) ii. Implement a 3 to 8 line decoder. (8) 54. Which of the following statements refer to a decoder, encoder, a MUX or a DEMUX? a) Has more inputs than outputs. b) Can be used in parallel to serial conversion. c) Produces a binary code at its output. d) Only one of its outputs can be active at one time. e) Can be used to route an input signal to one of several possible outputs. f) Can be used to generate arbitrary logic functions. (6) 55. Implement the following multiple output combinational logic circuit using a 4 16 line decoder. F1 = m (1, 2, 4, 7, 8, 11, 12, 13) F2 = m (2, 3, 9, 11) (16) F3 = m (10, 12, 13, 14) F4 = m (2, 4, 8) 56. Design a 4 bit BCD to Excess- 3 code converter using Binary Parallel Adder (BPA). What is the drawback in BPA and how can it be rectified. (10) 57. Implement the function Y (A, B, C, D) = m (1, 4, 6, 7, 8, 9, 10, 11, 15) using 4:1 MUX (16) 58.Design and explain the working of a 4 x 1 MUX . (8) 59.Explain how a 4 to 16 line decoder can be built using 2 to 4 line decoder. (8)

60. State the advantages of complex MSI devices over SSI gates. 61. Implement the switching function F (A, B, C) = m (1, 2, 4, 5) using the DEMUX 74156.

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62. Design a BCD to seven segment code conversion and representing the system 63. Design the following function F = m (0, 1, 3, 5, 6, 8, 10, 13, 14) using a multiplexer and a decoder. UNIT II

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1. Design a MOD 10 synchronous counter using JK flip-flops. Write the excitation table and state table. (16) 2. i. Compare Moore and Mealy circuits. (4) ii. Draw and explain the block diagram of Mealy circuit. (12) 3. Using SR flip-flops, design a synchronous counter which counts in the sequence 000, 111, 101, 110, 001, 010, 000, (16) 4. Design a mod 5 synchronous counter using JK flip flops with separate logic circuitry for each J and K input. Construct a timing diagram and determine the duty cycle of the output of the most significant stage. (16) 5. Design a synchronous counter using JK flip-flop to count the following sequence 7, 4, 3, 1, 5, 0, 7. (16) 6. Design a sequential circuit with four flip-flops ABCD. The next states of B, C, and D are equal to the present states of A, B, C respectively. The next state of A is equal to the EX- OR of present states of C and D. (16) 7. i. Show that the characteristic equation of Q ( t+1) of JK flip flop is Q (t+1) = JQ + KQ (4) ii. A sequential circuit has one flip-flop Q, two inputs x and y, and one output S. It consists of a full adder circuit connected to a D flip-flop, as shown below. Derive the state table and state diagram of the sequential circuit. (12)

8. i. Reduce the number of states in the following state table and tabulate the reduced state table. (8) Present Next State Output state x=0 x=1 x=0 x=1 a F b 0 0 b D c 0 0 c F e 0 0 d G a 1 0 e D c 0 0 f F b 1 1 g G h 0 1 h G a 1 0 ii. Starting from state a, and the input sequence 01110010011, determine the output sequence for the given and reduced state stable. (8) 9. Design a synchronous decade counter using D flip flop. (16) 10. i. Explain the working of a master slave JK flip flop. State its advantages. (6)
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ii. For a four bit even parity bit generator, inputs come serially. The four bits of the input sequence are to be examined by the circuit and circuit produces a parity bit 4

which is to be added in the original sequence. The circuit should get ready for receiving another four bits after producing a parity bit for the last sequence. Draw the state diagram and write down the state transition table. (10) 11. A sequential circuit has four flip- flops ABCD and an input x is describe the following State equations. A (t + 1) = (CD + CD) x + (CD + CD) x B (t + 1) = A C (t + 1) = B D (t + 1) = C a. Obtain the sequence of states when x = 1 starting from ABCD = 0001 b. Obtain the sequence of states when x = 0 starting from ABCD = 0000 (16) 12. A sequential circuit with 2 D flip- flops A and B and input X and output Y is specified by the following next state and output equations. A (t + 1) = AX + BX B (t + 1) = AX Y = (A + B) X i. Draw the logic diagram of the circuit ii. Derive the state table Iii.Derive the state diagram (16) 13. Design a Mod-14 up-down counter using T flip-flops. (16) 14. Design a mod- 7 counter using JK flip-flops. (6) 15. Design a BCD Up / Down counter using S R flip-flops. (10) 16. Design an asynchronous decade counter using JK flip-flops. (16) 17. Draw a four state switch tail ring counter. Show the count sequence. What is the modification to be used to prevent lock out? (16) 18. Design a synchronous counter with states 0, 1, 2, 3, 0, 1 using JK flip-flops. (16) 19. Write notes on state minimization. (8) 20. Design the clocked sequential circuit using JK flip-flops whose state diagram is given below. (16)

## Reduce the state diagram.

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22. Design 4 bit synchronous counter using X-OR gate as well as JK Flip-flop to count from 0 to 15. (16) 23. Distinguish between synchronous and asynchronous sequential circuits. (6) 24. Consider the follow ing synchronous sequentia l circuit. Determ ine its state table. What does the circuit do? (16)

25. Explain the meaning of Mealy and Moore machines. (6) 26. Show that if a sequential machine is strongly connected, then it is reversible but that the converse is not always true. 27. Design a four state down counter using type T design procedures. 28. Design a 4 bit synchronous 8421 decade counter with ripple carry. 29. Explain the working of JK flip- flop. What is race around condition? How is it overcome? Explain these concepts with relevant timing diagrams. 30. Design a 4 bit up / down counter using JK flip flops and Explain its working with timing diagrams. 31. For the given Moore model sequential circuit, find the state table, state diagram, flips input and output equations.

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UNIT III 1. Develop the state diagram and primitive flow table for a logic system that has two inputs S and R and a single output Q. The device is to be an edge triggered SR flip-

flop but without a clock. The device changes state on the rising edges of the two inputs. Static input values are not to have any effect in changing the Q output (16) 2. Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output Z. The output is to remain a 0 as long as X1 is a 0. The first change in X2 that occurs while X1 is a 1 will cause a Z to be a 1. Z is to remain a 1 until X1 returns to 0. Construct a state diagram and flow table. Determine the output equations. (16) 3. Construct the state diagram of a Mealey Pattern detector that can detect a serial string of 4 inputs,where each input is a four bit code. If the string of four bit codes is correctly received,then an output is generated. An incorrect input code pattern is to generate a second output.The second output is to be asserted only after receiving the sequence of four bit codes. (16) 4. An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are Y1=x1 +x1y2 ' +x2y1 Y2=x2 +x1y1' y2+x1y1 (i) Draw the logic diagram of the circuit. (ii) Derive the transition table and output map. (ii) Obtain a flow table for the circuit. 5. An asynchronous sequential circuit is described by the excitation and output functions Y = x1x2' +(x1+x2' ) y and Z =y (i) Draw the logic diagram of the circuit with a NOR SR latch. (ii)Derive the transition table and output map (iii)Obtain a two-state flow table. 6. Define the following: i) asynchronous sequential circuits, ii) Cycles, iii) critical race, iv) non- critical race
7. Draw the state diagram and obtain the primitive flow table for a circuit with two inputs x 1 and x2 and two outputs z1 and z2 that satisfies the following conditions. When x1 x2 = 00 output z1 z2 = 00, when x1= 1 and x2 changes from 0 to 1 the output z1 z2 = 01, when x2= 1 Z= x2+y1

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and x1 changes from 0 to 1 the output z1 z2 = 10 otherwise output does not change. (16) 8. Design an asynchronous binary toggle circuit that changes state with each rising edge of clock input. Assume the initial output as zero. (16) 9. Write notes on the following giving one example for each. (8) Stable state,Unstable state,Cycles,Race 10.Analyze the Boolean expression, K- Map, transition and state table and primitive flow table of the following asynchronous sequential circuits. (16)

11. How will you minimize the number of rows in the primitive state table of an incompletely specified sequential machine? (12) 12. State the restrictions on the pulse width in a pulse mode asynchronous sequential machine. (4) UNIT IV 1. Draw the circuit diagram and explain the working of TTL inverter with tristate output (8) 2. Explain the concept and implementation of ECL logic family. (8) 3. (i) Explain the operation of TTL NAND gate with a neat circuit diagram. (8) ii) Draw the circuit of CMOS NOR gate and explain its operation. Mention any two points about the advantages of CMOS over the other digital logic families. (8) 4. (i) Using ROM, design a combinational circuit which accepts 3 bit number and generates an output binary number equivalent to the square of input number. (8) (ii) A combinational circuit is defined by the functions F 1 (A, B, C) = m (3, 5, 6, 7), F2 (A, B, C) = m (0, 2, 4, 7). Implement the circuit using PLA. (8) 5. Discuss the working of the following programmable logic devices: (16) i. PROM ii. FPGA iii. PLD 6. Explain the working of 3 input totem pole TTL NAND gate. (10) 7. Draw a PLA circuit to implement the logic functions ABC + ABC + AC and ABC + BC (6) 8. Compare various digital logic families based on any five suitable parameters (10) 9. Write notes on ROM and its types. (16) 10. Write short notes on TTL, ECL and CMOS digital logic families. (16) 11. Explain EPROM and PLA. (8) 12. Define the terms Fan-out, tri-state gates, Fan-in. (6) 13. Draw the circuits of two input NAND and two input NOR gates using CMOS. (8) 14. Illustrate the ROM and PLA design for the following functions W(A,B,C,D) = m(3,7,8,9,11,15) X(A,B,C,D) = m(3,4,5,7,10,14,15) Y (A, B, C, D) = m (1, 5, 7, 11, 15) (16) 15. Draw and explain the circuit diagram of an ECL OR / NOR gate. (8) 16. Draw a neat sketch showing the implementation of Z1 = abde + abcde + bc + de Z2 = ace Z3 = bc + de + cde + bd and Z4 = ace + ce using a 5 x 8 x 4 PLA. (12) 17. Generate the following Boolean functions with a PAL with 4 inputs and 4 outputs. Y3 = ABCD + ABCD + ABCD + ABCD Y2 = ABCD + ABCD + ABCD Y1 = ABC + ABC + ABC + ABC Y0 = ABCD (16) 18. Discuss about the TTL parameters. (10) 19. Draw the TTL inverter circuit. (6) 20. Name and explain the characteristics of TTL logic family. (8) 21. Draw the internal circuits of TTL inverter and AND gate. (8) 22. Discuss the concept of working and applications of the following memories: ROM, EPROM, PLA (16) 23.Explain the characteristics and implementation of the following digital logic families.

i. CMOS, ii. ECL 24. Write short notes on memory based design

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UNIT V 1. Explain in words the operations specified by the following register transfer notation: (a) R2 R2 +1, R1R2 (b) R3R3-1 (c) If(T=1) then (R0R1) else if (T2=1) then (R0R2) (16)

2. Show a BCD to Gray code converter can be designed using a 16 words X 4 bits ROM. (16) 3. Write a VHDL code for a full subtractor, using logic equations. Assume that the full subtractor has a 5-ns delay. (16) 4. Write a VHDL code for a serial adder. (16) 5. Write a VHDL code for a T flip-flop with a active-low asynchronous clear. (16) 6. What are the different HDL descriptions of a design problem. (16) 7. Draw the circuit represented by the following CHDL statements: (16) F<=E and I; I<=G or H; G<=A and B; H<=not C and D; 8. Write a VHDL module that implements a full adder using an array of bit-vectors to represent the truth table. (16) 9. Write HDL program for full adder and 4 bit comparator (16) 10. Write HDL behavioral description of JK flipflop using if- else statement based on value of present state. (8) 11. Draw the logic diagram for the following module. module seqcrt (A,B,C,Q,CLK); input A,B,C,CLK; output Q: reg Q,E; always @ (Posedge CLK) begin E<= A&B; Q <= E / C; end end module (8) UNIT I PART A 1. State two absorption properties of Boolean algebra. 2. State De- Morgans laws. 3. Show how bubbled AND gate works as NOR gate. 4. Why NAND and NOR gates are called as universal gates? 5. Why digital circuits are more frequently constructed with NAND and NOR gates than with AND and OR gates?

6. Distinguish between completely specified function and incompletely specified function. 7. Simplify the Boolean function F = (A + (BC)) 8. Minimize the expression using Boolean theorems F= xy + xyz + xz + xyz. Draw

the logic diagram for the minimized function. 9. If A and B are Boolean variables and if A= 1 and (A+B) = 0, find B. 10. Realize the function F (A, B) = AB + AB using NAND gates only. 11. How many inputs and gates are required for the expression W = ABD + ACD + EF 12. Name two canonical forms of Boolean algebra. 13. What is a prime implicant? 14. Express the function f(x,y,z) = x + yz as a sum of minterms. 15. For the given function write the Boolean expression in product of maxterms form f( a,b,c) = m (2,3,5,6,7). 16. Plot the expression in K- map F (w, x, y) = (0, 1, 3, 5, 6) + d (2, 4) 17. Show the Karnaugh map with the encircled groups for the Boolean function, F = C+ AD + ABD. 18. Simplify: x + xy 19. Express the function f(B,A) = A in terms of minterms. 20. Minimize the expression XY + XYZ + YZ using Boolean theorem. 21. Find the decimal equivalent of (123)9. 22. Show that the NOR connective is not associative. 23. What happens when all the gates in a two level AND OR gate network are replaced by NOR gates? 24.State two significant features of tabular method of minimization of Boolean functions. 25.What is two state operation? 26.What is the value of b if 41b = 5? 27. List out the differences between half adder and full adder. 28.Write down the truth table of a full adder. 29. Implement half adder circuit using logic gates. 30. Implement half subtractor circuit using logic gates. 31. What will be the maximum number of outputs for a decoder with a 6 bit data word? 32. List out the differences between decoder and encoder. 33. What is a multiplexer? Give its applications. 34. What is a demultiplexer? Give its applications. 35. Mention the differences between DMUX and MUX. 36. Implement the function f = m (0, 1, 4, 5, 7) using 8 to 1 multiplexer. 37. Design a half subtractor using 2 to 4 decoder. 38. Draw a 1 to 2 demultiplexer and 2 to1 multiplexer. 39. Implement a NAND gate using 4:1 Multiplexer. 40. Give the circuit of a half adder subtractor. 41. What is data selector? 42. Mention the use of decoders. UNIT II PART A 1. Write the excitation tables of JK and D flip-flops. 2. Draw the logic diagram of three bit ring counter. 3. Write the characteristic equation of JK and D flip-flop. 4. Convert an SR flip-flop to D flip-flop. 5. Define glitch.

6. Draw the block diagram of SR Flip flop and give its truth table. 7. List out the limitations of SR flip-flop. 8. Convert a D flip flop into a T flip flop.

9. If a serial in serial out shift register has N stages and if the clock frequency is f, what will be the time delay between input and output? 10. Distinguish between combinational and sequential circuits. 11. Describe the behaviour of SR flip-flop by means of a table. 12. How many flip-flops are required to build a counter of modulus 14 and modulus 8? 13. What is a race condition? 14. How can the race conditions be avoided in flip-flops? 15. What is a Mealy machine? Give an example. 16. Differentiate between Moore and Mealey type sequential circuits. 17. What is a state? 18. What are state diagrams and state table? 19. What are shift register counters? List two widely used shift register counters. 20. Why is state reduction necessary? 21. Derive the characteristic equation of T flip-flop. 22. What is edge triggering? 23. What is the difference between serial and parallel transfer. What type of register is used in each case? 24. When a sequential machine is said to be trivial? 25. If the input frequency of a T flip flop is 1600 KHz, what will be the output frequency? Give reason for your answer. UNIT III PART A 1. When a sequential machine is said to be trivial? 2. List out the differences between a flip-flop and a latch. 3. Why a serial counter is referred to as asynchronous. 4. Why parallel counter is faster than ripple counter? 5. Define fundamental-mode operation. 6. Define Hazard. 7. Why critical race is said to be harmful and how it is avoided in asynchronous sequential Circuits? 8. What are cycles in asynchronous sequential circuits? 9. What are races? 10. Define static Hazard. 11. What is dynamic hazard? 12. What is critical race? UNIT IV PART A 1. What is FPGA? 2. Define Noise margin. 3. Define Fan-in and Fan out? 4. Why CMOS is preferred to TTL? 5. Compare PLA and PAL 6. What are the basic parameters to be noted before selecting an IC?

7. How does the architecture of PLA different from PROM? 8. What is the effect of increasing supply voltage on the propagation delay of the CMOS gates?