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http://o penco res.o rg/o r2k/Instructio n_set

Instruction set
T his chapter describes the OpenRISC 2000 instruction set.

Features
T he OpenRISC 2000 instruction set includes the f ollowing principal f eatures: Dual-length instruction f ormat 32-bit and 16-bit wide instructions aligned on 16-bit boundaries in memory Floating Point co-processor instructions Custom co-processor instructions

Overview Instruction groups

Basic - base set of supported instructions. Mandatory. Extension - set of instructions providing additional f unctionality. Not mandatory. Entirety to be implemented if at all. F loating point - set of instructions implementing f loat point support. Not mandatory. Co-processor - Co-processor/custom instructions. Not mandatory. DSP - DSP related instructions. Not mandatory.

Instruction f ormats
32-bit f ormat s
R3 type 31 32bit 1 bit 30 . . . 26 25 . . rD 5 bits . 21 20 . . rA 5 bits . 16 15 . . rB 5 bits . 11 10 . 8 7 . . . . . . 0

Opcode 5 bits

reserved 3 bits

Function 8 bits

I type 31 32-bit 1 bit 30 . . . 26 25 . . rD 5 bits . 21 20 . . rA 5 bits . 16 15 . . . . . . . . . . . . . . 0

Opcode 5 bits

Immediate 16 bits

K type 31 32-bit 1 bit 30 . . . 26 25 . . rD 5 bits . 21 20 . . rA 5 bits O type 31 32-bit 1 bit 30 . . . 26 25 . . . . . . . . . . . . . . . . . . . . . . . . 0 . 16 15 . . . . . . 8 7 . . . . . . 0

Opcode 5 bits

Immediate 8 bits

Function 8 bits

Opcode 5 bits

Immediate 26 bits

16-bit f ormat s
R2 type 15 16-bit 1 bit 14 . . 11 10 . rD 4 bits LSSP type 15 16-bit 1 bit 14 . . 11 10 . . 7 6 . . 3 2 . Len 3 bits 0 . 7 6 . rA 4 bits . 3 2 . 0

Opcode 4 bits

Function 3 bits

Opcode 4 bits

Start Reg 4 bits J type

S.P of f set 4 bits

15 16-bit 1 bit

14

11

10

. rD

Opcode 4 bits

Immediate 7 bits

4 bits

Instruction groups
Basic - base set of supported instructions. Mandatory. Extension - set of instructions providing additional f unctionality. Not mandatory. Entirety to be implemented if at all. F loating point - set of instructions implementing f loat point support. Not mandatory. Co-processor - Co-processor/custom instructions. Not mandatory. DSP - DSP related instructions. Not mandatory.

Instruction set overview

Mnemonic l.j l.nop l.seq l.sne l.slts l.sltu l.sgts l.sgtu l.sles l.sleu l.sges l.sgeu l.add l.sub l.and l.or l.xor l.sll l.srl l.sra l.ror l.mul l.mulu l.div l.divu l.f f 1 l.f l1 l.cmov lf .add.d lf .add.s

16bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type O O R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3

Opcode 0x00 0x?? 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x02 0x02

Function

Description PC <= PC + exts(Imm26<<1) No operation, Imm26 f or simulation purpose

Group b b b b b b b b b b b b b b b b b b b b e e e e e e e e f f

0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x00 0x01

rD <= rA==rB ? 1 : 0 rD <= rA!=rB ? 1 : 0 rD <= rA < rB ? 1 : 0 rD <= rA < rB ? 1 : 0 rD <= rA > rB ? 1 : 0 rD <= rA > rB ? 1 : 0 rD <= rA =< rB ? 1 : 0 rD <= rA =< rB ? 1 : 0 rD <= rA >= rB ? 1 : 0 rD <= rA >= rB ? 1 : 0 rD <= rA + rB rD <= rA - rB rD <= rA & rB rD <= rA OR rB rD <= rA ^ rB rD <= rA << rB rD <= rA >> rB rD <= rA >>> rB rD <= rotate(rA,rB) rD <= rA * rB rD <= rA * rB rD <= rA / rB rD <= rA / rB rD <= rA[0] ? 1 : rA[1] ? 2 ... rA[31] ? 32 : 0 rD <= rA[31] ? 32 : rA[30] ? 31 ... rA[0] ? 1 : 0 rD <= rB==0 ? rA : rD rf D <= rf A + rf B rf D <= rf A + rf B

lf .sub.d lf .sub.s lf .mul.d lf .mul.s lf .div.d lf .div.s lf .rem.d lf .rem.s lf .f toi.d lf .f toi.s lf .itof .d lf .itof .s lf .seq.d lf .seq.s lf .sge.d lf .sge.s lf .sgt.d lf .sgt.s lf .sle.d lf .sle.s lf .slt.d lf .slt.s lf .sne.d lf .sne.s

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3

0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x03 0x04 0x05

0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19

rf D <= rf A - rf B rf D <= rf A - rf B rf D <= rf A * rf B rf D <= rf A * rf B rf D <= rf A / rf B rf D <= rf A / rf B rf D <= rf A % rf B rf D <= rf A % rf B rD <= f toi(rf A) rD <= f toi(rf A) rf D <= itof (rA) rf D <= itof (rA) rD <= rf A == rf B ? 1 : 0 rD <= rf A == rf B ? 1 : 0 rD <= rf A >= rf B ? 1 : 0 rD <= rf A >= rf B ? 1 : 0 rD <= rf A > rf B ? 1 : 0 rD <= rf A > rf B ? 1 : 0 rD <= rf A =< rf B ? 1 : 0 rD <= rf A =< rf B ? 1 : 0 rD <= rf A < rf B ? 1 : 0 rD <= rf A < rf B ? 1 : 0 rD <= rf A != rf B ? 1 : 0 rD <= rA != rB ? 1 : 0 Co-processor DSP

f f f f f f f f f f f f f f f f f f f f f f f f c d

l.seqi l.snei l.sltsi l.sltui

0 0 0 0

I I I I

0x06 0x07 0x08 0x09

rD <= rA == exts(Imm16) ? 1 : 0 rD <= rA != exts(Imm16) ? 1 : 0 rD <= rA < exts(Imm16) ? 1 : 0 rD <= rA < exts(Imm16) ? 1 : 0

b b b b

l.sgtsi l.sgtui l.slesi l.sleui l.sgesi l.sgeui l.addi l.andi l.ori l.xori l.xnori l.movhi l.slli l.srli l.srai l.rori

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I I I I I I I I I I I I K K K K K K K K K K K K K K K K K K K

0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x00 0x01 0x02 0x03 ... 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d

rD <= rA > exts(Imm16) ? 1 : 0 rD <= rA > exts(Imm16) ? 1 : 0 rD <= rA =< exts(Imm16) ? 1 : 0 rD <= rA =< exts(Imm16) ? 1 : 0 rD <= rA >= exts(Imm16) ? 1 : 0 rD <= rA >= exts(Imm16) ? 1 : 0 rD <= rA + exts(Imm16) rD <= rA & extz(Imm16) rD <= rA OR extz(Imm16) rD <= rA ^ exts(Imm16) rD <= !(rA ^ exts(Imm16)) rD <= extz(Imm16) << 16 rD <= rA << Imm8 rD <= rA >> Imm8 rD <= rA >>> Imm8 rD <= rotate(rA,Imm8)

b b b b b b b b b b b b b b b e b

l.lbs l.lbz l.lhs l.lhz l.lws l.lwz l.ld

0 0 0 0 0 0 0 0

rD <= exts([rA + exts(Imm8)][7:0]) rD <= extz([rA + exts(Imm8)][7:0]) rD <= exts([rA + exts(Imm8)][15:0]) rD <= extz([rA + exts(Imm8)][15:0]) rD <= exts([rA + exts(Imm8)][31:0]) rD <= extz([rA + exts(Imm8)][31:0]) rD <= [rA + exts(Imm8)][63:0]

b b b b b b b b

l.sb l.sh l.sw l.sd lf .ss lf .sd

0 0 0 0 0 0

[rD + exts(Imm8)][7:0] <= rA[7:0] [rD + exts(Imm8)][15:0] <= rA[15:0] [rD + exts(Imm8)][31:0] <= rA[31:0] [rD + exts(Imm8)][63:0] <= rA[63:0] [rD + exts(Imm8)][31:0] <= rf A[31:0] [rD + exts(Imm8)][63:0] <= rf A[63:0]

b b b b f f

lf .ls lf .ld l.ll

0 0 0

K K K

0x16 0x16 0x16

0x8e 0x8f 0x90

rf D[31:0] <- [rA + exts(Imm8)][31:0] rf D[63:0] <- [rA + exts(Imm8)][63:0] rD <= exts([rA + exts(Imm8< SPR_LLADR <= rA + exts(Imm8<<wordof f )

f f e

l.sc

0x16

0x91

if (SPR_LLADR==(rD+exts(Imm8< exts([rD + exts(Imm8< rA <= 1 else rA <= 0

0 l.jr l.jalr 0 0

K K K

0x16 0x16 0x16

... 0xf 8 0xf 9 PC <= rA PC <= rA LR <= PC + 4 b b

l.rf e

0 0

K K K K K

0x16 0x16 0x16 0x16 0x16 0x17 0x18

0xf a ... 0xf d 0xf e 0xf f

PC <= EPCR

b b

l.csync l.msync l.psync

0 0 0 0 0

Context sync. Memory/cache sync. Pipeline sync.

e e e

l.jal

0x19

PC <= PC + exts(Imm26<<1) LR <= PC + 4

l.be l.bne lf .be.d lf .be.s lf .bne.d lf .bne.s l.mtspr l.mf spr l.sys l.trap

0 0 0 0 0 0 0 0 0 0

I I I I I I I I

0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23

PC <= rD == rA ? PC + exts(Imm16<<1) : PC + 4 PC <= rD != rA ? PC + exts(Imm16<<1) : PC + 4 PC <= rf D == rf A ? PC + exts(Imm16<<1) : PC + 4 PC <= rf D == rf A ? PC + exts(Imm16<<1) : PC + 4 PC <= rf D != rf A ? PC + exts(Imm16<<1) : PC + 4 PC <= rf D != rf A ? PC + exts(Imm16<<1) : PC + 4 spr(rD OR Imm16) <= rA rD <= spr(rA OR Imm16) System call Trap

b b f f f f b b e e

s.sub s.add s.and s.or s.xor s.sll s.srl s.sra s.addi s.andi s.ori s.xori s.xnori s.slli s.srli s.srai s.lbz s.lbzinc s.lhz s.lhzinc s.lwz s.lwzinc s.ldz s.ldzinc s.sb s.sbinc s.sh s.shinc s.sw s.swinc s.sd

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

R2 R2 R2 R2 R2 R2 R2 R2 J J J J J J J J R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2

0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0xa 0xa 0xa 0xa 0xa 0xa 0xa

0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7

rD <= rD - rA rD <= rD + rA rD <= rD & rA rD <= rD OR rA rD <= rD ^ rA rD <= rD << rA rD <= rD >> rA rD <= rD >>> rA rD <= rD + exts(Imm7) rD <= rD & extz(Imm7) rD <= rD OR extz(Imm7) rD <= rD ^ extz(Imm7) rD <= !(rD ^ extz(Imm7)) rD <= rD << Imm7 rD <= rD >> Imm7 rD <= rD >>> Imm7

b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b

0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6

rD <= extz([rA][7:0]) rD <= extz([rA++][7:0]) rD <= extz([rA][15:0]) rD <= extz([rA++][15:0]) rD <= extz([rA][31:0]) rD <= extz([rA++][31:0]) rD <= [rA][63:0] rD <= [rA++][63:0] [rD] <= [rA][7:0] [rD++] <= [rA][7:0] [rD] <= [rA][15:0] [rD++] <= [rA][15:0] [rD] <= [rA][31:0] [rD++] <= [rA][31:0] [rD] <= [rA][63:0]

s.sdinc s.lsp s.ssp s.bz s.bnz s.trap

1 1 1 1 1 1

R2 LSSP LSSP J J J

0xa 0xb 0xc 0xd 0xe 0xf

0x7

[rD++] <= [rA][63:0] f or (N=Start Reg;N<Start Reg+(Len+1);N++) rN <= [SP + (Of f set<<2) + ((N-Start Reg)<<2)] f or (N=Start Reg;N<Start Reg+(Len+1);N++) [SP + (Of f set<<2) + ((N-Start Reg)<<2)] <= rN PC <= rD==0 ? PC + exts(Imm7<<1) : PC + 2 PC <= rD!=0 ? PC + exts(Imm7<<1) : PC + 2 Trap

b b b b b e

Instructions
l.add: Add signed
31 32bit 1 bit Format l.add rD,rA,rB Description T he contents of general-purpose register rA are added to the contents of general-purpose register rB to f orm the result. T he result is placed into general-purpose register rD. 32-bit implementation rD[31:0] rA[31:0] + rB[31:0] SR[CY] carry SR[OV] overow 64-bit implementation rD[63:0] rA[63:0] + rB[63:0] SR[CY] carry SR[OV] overow Exceptions Range exception 30 . . . 26 25 . . D 5 bits . 21 20 . . A 5 bits . 16 15 . . B 5 bits . 11 10 . 8 7 . . . . . . 0

opcode 0x0 5 bits

reserved 3 bits

f unction 0x10 8 bits

s.add: Add signed

15 16-bit 1 bit Format

14

11

10

. D

. A

opcode 0x0 4 bits

f unction 0x1 3 bits

4 bits

4 bits

s.add rD,rA Description T he contents of general-purpose register rA are added to the contents of general-purpose register rD to f orm the result. T he result is placed into general-purpose register rD. 32-bit implementation rD[31:0] rA[31:0] + rD[31:0] SR[CY] carry SR[OV] overow 64-bit implementation rD[63:0] rA[63:0] + rD[63:0] SR[CY] carry SR[OV] overow Exceptions Range exception