Training LG 50pa4500-Dm 50pa4510-Dj CH - Pb23a

Internal Use Only
North/Latin America Europe/Africa Asia/Oceania http://aic.lgservice.com http://eic.lgservice.com http://biz.lgservice.com
PLASMA TV SERVICE MANUAL

CHASSIS : PB23A
CAUTION
MODEL : 50PA4500 MODEL : 50PA4510
50PA4500-DM 50PA4510-DJ
BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL67483007 (1205-REV00)
Printed in Korea
CONTENTS
CONTENTS . ............................................................................................. 2 SAFETY PRECAUTIONS ......................................................................... 3 SPECIFICATION........................................................................................ 4 ADJUSTMENT INSTRUCTION................................................................. 5 BLOCK DIAGRAM. .................................................................................. 12 EXPLODED VIEW .................................................................................. 13 SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright LG Electronics. Inc. All rights reserved. Only for training and service purposes
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LGE Internal Use Only
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.
General Guidance
An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks. It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation. If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified. When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB. Keep wires away from high voltage or high temperature parts.
Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet. Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to 0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.
Leakage Current Hot Check circuit
Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock. With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 M and 5.2 M. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.
AC Volt-meter
Leakage Current Cold Check(Antenna Cold Check)
To Instrument's exposed METALLIC PARTS
Good Earth Ground such as WATER PIPE, CONDUIT etc.
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NOTE : Specifications and others are subject to change without notice for improvement.
SPECIFICATION
1. Application range
This spec sheet is applied all of the PDP TV with PB23A chassis.
2. Requirement for Test
Each part is tested as below without special appointment. (1) Temperature: 25 C 5 C(77 F 9 F), CST: 40 C 5 C (2) Relative Humidity: 65 % 10 % (3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models. (4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. (5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test method
(1) Performance: LGE TV test method followed (2) Demanded other specification - Safety : CE, IEC specification - EMC : CE, IEC
4. Model General Specification

No 1 Item Receiving System 1) DVB-T / NTSC Specification Remark 42/50PA4500-DF 42/50PA4510-DC 42/50PA4900-DD 50/60PA6500-DA 42/50PA4500-DM 42/50PA4510-DJ 42/50PA4900-DK, 50/60PA6500-DG 42/50PA4500-DF 42/50PA4510-DC 42/50PA4900-DD 50/60PA6500-DA 42/50PA4500-DM 42/50PA4510-DJ 42/50PA4900-DK, 50/60PA6500-DG
Available Channel
1) VHF : 02~13 2) UHF : 14~69 3) DTV : 14~69 (UHF) 4) CATV : 02~125
3 4 5
Input Voltage Market Screen Size
1) AC 100 ~ 240V 50/60Hz Brazil / chile / Peru / Venezuela / Costarica / Uruguay Colombia / Panama 42 inch Wide(1024 768) 50 inch Wide(1024 768) 50 inch Wide(1920 1080) 60 inch Wide(1920 1080) 16:9 FS PDP42T4#### PDP50T4#### PDP50R4#### PDP60R4#### (1024 768) (1024 768) (1920 1080) (1920 1080) 42PA4 all model 50PA4 all model 50PA6 all model 60PA6 all model 42PA all model 50PA4 all model 50PA6 all model 60PA6 all model
6 7 8
Aspect Ratio Tuning System Module
9 10
Operating Environment Storage Environment
1) Temp : 0 deg ~ 40 deg 2) Humidity : ~ 80 % 1) Temp : -20 deg ~ 60 deg 2) Humidity : ~ 85 %
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ADJUSTMENT INSTRUCTION
1. Application Range
This spec. sheet applies to PB23A chassis applied PDP TV all models manufactured in TV factory.
4. PCB Assembly Adjustment

4.1. Using RS-232C
Adjustment sequence
Order 1. I nter the Adjustment mode 2. C hange the Source 3. Start Adjustment 4. R eturn the Response 5. R ead Adjustment data 6. Confirm Adjustment ( main ) ad 00 20 ( main ) ad 00 30 ad 00 99 command aa 00 00 a 00 OK00x Set response
- A djust 3 items at 3.1. PCB assembly adjustments " 4.1. Adjustment sequence" one after the order.
2. Specification
(1) Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation transformer will help protect test instrument. (2) Adjustment must be done in the correct order. But it is flexible when its factory local problem occurs. (3) T he adjustment must be performed in the circumstance of 25 C 5 C of temperature and 65 % 10 % of relative humidity if there is no specific designation. (4) The input voltage of the receiver must keep AC 100-240 V~, 50/60 Hz. (5) Before adjustment, execute Heat-Run for 5 minutes. A fter Receive 100% Full white pattern (06CH) then process Heat-run (or 8. Test pattern condition of Ez-Adjust status) How to make set white pattern 1) Press Power ON button of Service Remocon 2) Press ADJ button of Service remocon. Select 10. Test pattern and, after select White using navigation button, and then you can see 100% Full White pattern. * In this status you can maintain Heat-Run useless any pattern generator * Notice: i f you maintain one picture over 20 minutes (Especially sharp distinction black with white pattern 13Ch, or Cross hatch pattern 09Ch) then it can appear image stick near black level.
XB 00 40 XB 00 60 ad 00 10
b 00 OK40x (Adjust 480i Comp1 ) (Adjust 1080p Comp1) b 00 OK60x (Adjust 1080p RGB)
OKx ( Success condition ) NGx ( Failed condition ) (main : component1 480i, RGB 1080p) 000000000000000000000000007c007b006dx (main : component1 1080p) 000000070000000000000000007c00830077x NG 03 00x (Failed condition) NG 03 01x (Failed condition) NG 03 02x (Failed condition) OK 03 03x (Success condition) d 00 OK90x
7. End of Adjustment
ad 00 90
< See ADC Adjustment RS232C Protocol_Ver1.0 > Necessary items before Adjustment items Pattern Generator : (MSPG-925FA) Adjust 480i comp1 (MSPG-925FA:model :209, pattern :65) - comp1 Mode Adjust 1080p comp1 (MSPG-925FA:model :225 , pattern :65) - comp1 Mode Addjust RGB (MSPG-925FA:model :225 , pattern :65) - RGB-Pc Mode * If you want more information then see the below Adjustment method (Factory Adjustment) Adjustment sequence aa 00 00: Enter the ADc Adjustment mode. xb 00 40: change the mode to component1 (No actions) ad 00 10: Adjust 480i comp ad 00 10: Adjust 1080p comp xb 00 60: change to RGB-Pc mode(No action) ad 00 10: Adjust 1080p RGB xb 00 90: Endo of Adjustmennt
3. Adjustment items
3.1. PCB Assembly adjustment
Adjust 480i Comp1 Adjust 1080p Comp1/RGB If it is necessary, it can adjustment at Manufacture Line You can see set adjustment status at 9. ADJUST CHECK of the In-start menu
3.2. Set Assembly Adjustment
EDID (The Extended Display Identification Data ) Color Temperature (White Balance) Adjustment Make sure RS-232C control Selection Factory output option
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5. Factory Adjustment
-> PB23A : USE INTERNAL ADC(LM1) : using internal pattern.
5.1. Auto Adjust Component 480i/1080p RGB 1080p
Summary : A djustment component 480i/1080i and RGB 1080p is Gain and Black level setting at Analog to Digital converter, and compensate the RGB deviation Using instrument A djustment remocon, 801GF(802B, 802F, 802R) or MSPG925FA pattern generator ( I t can output 480i/1080i horizontal 100% color bar pattern signal, and its output level must setting 0.7V0.1V p-p correctly)
* caution : Set Volume 0 after adjustment
5.2. Use Internal ADC(S7R)

< Adjustment pattern : 480i / 1080p 60Hz Pattern > You must make it sure its resolution and pattern cause every instrument can have different setting Adjustment method 480i Comp1, Adjust 1080p Comp1/ RGB (Factory adjustment) ADC 480i Component1 adjustment - Check connection of Component1 - MSPG-925FA -> Model: 209, Pattern 65 Set Component 480i mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to NORMAL ADC 1080p Component1 / RGB adjustment - Check connection both of Component1 and RGB - MSPG-925FA -> Model: 225, Pattern 65 Set Component 1080p mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to NORMAL After get each the signal, wait more a second and enter the IN-START with press IN-START key of Service remocon. After then select 7. External ADC with navigator button and press Enter. After Then Press key of Service remocon Right Arrow (VOL+) You can see ADC Component1 Success Component1 1080p, RGB 1080p Adjust is same method. C omponent 1080p Adjustment in Component1 input mode RGB 1080p adjustment in RGB input mode If you success RGB 1080p Adjust. You can see ADC RGB-DTV Success
- A DJ(EZ ADJUST) -> 6.ADC Calibration -> ADC Calibration(START) * E DID (The Extended Display Identification Data)/DDC (Display Data Channel) Download. Summary It is established in VESA, for communication between PC and Monitor without order from user for building user condition. It helps to make easily use realize Plug and Play function. For EDID data write, we use DDC2B protocol. - Auto Download After enter Service Mode by pushing ADJ key, Enter EDID D/L mode. Enter START by pushing OK key. * Caution: - N ever connect HDMI & D-sub Cable when the user downloading . - Use the proper cables below for EDID Writing
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It only needs to PCM EDID D/L for North America Product.
EDID data (Model name = LG TV) - RGB HD 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 58 - South Centural America _2D_HD HDMI 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F 02 03 25 F1 4D 10 1F 04 93 05 14 03 02 12 20 22 15 01 26 15 07 50 09 57 07 67 03 0C 00 10 00 80 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 34
* Edid data and Model option download(RS232) NO Item CMD 1 CMD 2 Data 0 Enter download MODE download Mode In A A 0 0 When transfer the Mode In, Carry the command. EDID data Model option download download A E 00 10 Automatically download (The use of a internal pattern)
- Manual Download Write HDMI EDID data Using instruments - Jig. (PC Serial to D-Sub connection) for PC, DDC adjustment. - S/W for DDC recording (EDID data write and read) - D-sub jack - Additional HDMI cable connection Jig. Preparing and setting. - Set instruments and Jig. Like pic.5), then turn on PC and Jig. - Operate DDC write S/W (EDID write & read) - It will operate in the DOS mode.
< For write EDID data, setting Jig and another instruments >
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- South Centural America _2D_HD HDMI 2 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F 02 03 25 F1 4D 10 1F 04 93 05 14 03 02 12 20 22 15 01 26 15 07 50 09 57 07 67 03 0C 00 10 00 80 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 24
- Adjustment Color Temperature(White balance) Using Instruments Color Analyzer: CA-210 (CH 10) - Using LCD color temperature, Color Analyzer (CA210) must use CH 10, which Matrix compensated (White, Red, Green, Blue compensation) with CS2100. See the Coordination bellowed one. Auto-adjustment Equipment (It needs when Auto-adjustment It is availed communicate with RS-232C : Baud rate: 115200) V ideo Signal Generator MSPG-925F 720p, 216Gray (Model: 217, Pattern 78) Connection Diagram (Auto Adjustment) Using Inner Pattern
- South Centural America _2D_HD HDMI 3 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F 02 03 25 F1 4D 10 1F 04 93 05 14 03 02 12 20 22 15 01 26 15 07 50 09 57 07 67 03 0C 00 10 00 80 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 14
Using HDMI input
< connection Diagram for Adjustment White balance > White Balance Adjustment If you cant adjust with inner pattern, then you can adjust it using HDMI pattern. You can select option at Ez-Adjust Menu 7. White Balance there items NONE, INNER, HDMI. It is normally setting at inner basically. If you cant adjust using inner pattern you can select HDMI item, and you can adjust. In manual Adjust case, if you press ADJ button of service remocon, and enter Ez-Adjust Menu 7. White Balance, then automatically inner pattern operates. (In case of Inner originally Test-Pattern. On will be selected in The Test-Pattern. On/Off. Connect all cables and equipments like Pic.5) S et Baud Rate of RS-232C to 115200. It may set 115200 orignally. Connect RS-232C cable to set Connect HDMI cable to set
- See Working Guide if you want more information about EDID communication.
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When Color temperature (White balance) Adjustment (Automatically) - Press Power only key of service remocon and operate automatically adjustment. - Set BaudRate to 115200. You must start wb 00 00 and finish it wb 00 ff. If it needs, then adjustment Offset. White Balance Adjustment (Manual adjustment) Test Equipment: CA-210 - Using PDP color temperature, Color Analyzer (CA-210) must use CH 10, which Matrix compensated (White, Red, Green, Blue compensation) with CS-2100. See the Coordination bellowed one. Manual adjustment sequence is like bellowed one. - Turn to Ez-Adjust mode with press ADJ button of service remocon. - Select 10.Test Pattern with CH+/- button and press enter. Then set will go on Heat-run mode. Over 30 minutes set let on Heat-run mode. - Let CA-210 to zero calibration and must has gap more 10cm from center of PDP module when adjustment. - Press ADJ button of service remocon and select 7.White-Balance in Ez-Adjust then press button of navigation key. (When press button then set will go to full white mode) - Adjust at three mode (Cool, Medium, Warm) - If cool mode Let B-Gain to 192 and R, G, B-Cut to 64 and then control R, G gain adjustment High Light adjustment. - If Medium and Warm mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - All of the three mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - With volume button (+/-) you can adjust. - After all adjustment finished, with Enter ( key) turn to Ez-Adjust mode. Then with ADJ button, exit from adjustment mode * Attachment: W hite Balance adjustment coordination and color temperature. Using CS-1000 Equipment. - COOL : T=11000K, uv=0.000, x=0.276 y=0.283 - MEDIUM : T=9300K, uv=0.000, x=0.285 y=0.293 - WARM : T=6500K, uv=0.000, x=0.313 y=0.329
RS-232C Command (Commonly apply) RS-232C COMMAND [CMD ID DATA] wb wb wb wb wb wb 00 00 00 00 00 00 00 10 1f 20 2f ff Meaning White Balance adjustment start. Start of adjust gain (Inner white pattern) End of gain adjust Start of offset adjust (Inner white pattern) End of offset adjust End of White Balance adjust (Inner pattern disappeared) wb 00 00: Start Auto-adjustment of white balance. wb 00 10: Start Gain Adjustment (Inner pattern) jb 00 c0 : wb 00 1f: End of Adjustment * If it needs, offset adjustment (wb 00 20-start, wb 00 2fend) wb 00 ff: End of white balance adjustment (inner pattern disappear) Adjustment Mapping information RS-232C COMMAND [CMD ID DATA] Cool R Gain G Gain B Gain R Cut G Cut B Cut jg jh ji Mid Ja Jb Jc Warm jd je jf 00 00 00 M I N CENTER (DEFAULT) Cool 184 187 192 64 64 64 Mid 192 183 161 64 64 64 Warm 192 159 95 64 64 64 192 192 192 127 127 127 M A X
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6. GND and ESD Testing

When tester will measure on Cool condition, adjust W30 on TV display menu.
6.1. Prepare GND and ESD Testing.
Check the connection between set and power cord
6.2. Operate GND and ESD auto-test.

When tester will measure on medium condition, adjust 0 on TV display menu.
When tester will measure on warm condition, adjust W30 on TV display menu. Using CA-210 Equipment. (10 CH) - Contrast value: 216 Gray Color temperature COOL MEDIUM WARM Item Min Typ Max Unit Remark cd/m - 100% Window White Pattern - 100IRE(255Gray) - Picture: Vivid(Medium) 49 60 +20 % - 85IRE(216Gray) 100% Window White Pattern - Picture: Vivid(Medium) Test Equipment CA-210 CA-210 CA-210 White average brightness Color Coordination x 0.276 0.002 0.285 0.002 0.313 0.002 y 0.283 0.002 0.293 0.002 0.329 0.002
Fully connected (Between set and power cord) set enter the Auto-test sequence. Connect D-Jack AV jack test equipment. Turn on Auto-controller(GWS103-4) Start Auto GND test. If its result is NG, then notice with buzzer. If its result is OK, then automatically it turns to ESD Test. Operate ESD test If its result is NG, then notice with buzzer. If its result is OK, then process next steps. Notice it with Good lamp and STOPER Down.
6.3. Check Items.
- Brightness spec. Brightness uniformity -20
Test Voltage GND: 1.5KV/min at 100mA Signal: 3KV/min at 100mA Test time: just 1 second. Test point GND test: Test between Power cord GND and Signal cable metal GND. ESD test: Test between Power cord GND and Live and neutral. Leakage current: Set to 0.5mA(rms)
6.4. POWER PCB Assy Voltage adjustment

6.4.1. Test equipment : D.M.M 1EA 6.4.2. Connection Diagram for Measuring
: refer to fig.1 <XPOWER4 50R4/T4 PSU> (Va, Vs voltage adjustment)
5.3. Test of RS-232C control.
- Press In-Start button of Service Remocon then set the 4.Baud Rate to 115200. Then check RS-232C control and
5.4. Selection of Country option.
- Selection of country option is allowed only North American model (Not allowed Korean model). It is selection of Country about Rating and Time Zone. Models: All models which PU11A Chassis (See the first page.) Press In-Start button of Service Remocon, then enter the Option Menu with PIP CH- Button Select one of these three (USA, CANADA, MEXICO) depends on its market using Vol. +/-button. * Caution : Dont push The INSTOP KEY after completing the function inspection. * Caution : Inspection only PAL M / NTSC
(fig.1) PCB Assy Voltage adjustment
6.4.3. Adjustment method
6.4.3.1. Vs adjustment (refer fig.1) (1) Connect + terminal of D.M.M. to Vs pin of P811, connect -terminal to GND pin of P811 (2) After turning VR901, voltage of D.M.M adjustment as same as Vs voltage which on label of panel left/top ( deviation ; 0.5V) 6.4.3.2. Va adjustment (refer fig.1) (1) After receiving 100% Full White Pattern, HEAT RUN. (2) Connect + terminal of D.M.M. to Va pin of P811, connect -terminal to GND pin of P811 (3) After turning VR502,voltage of D.M.M adjustment as same as Va voltage which on label of panel left/top (deviation; 0.5V)
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7. Default Service option.

7.1. ADC-Set.
R-Gain adjustment Value (default 128) G-Gain adjustment Value (default 128) B-Gain adjustment Value (default 128) R-Offset adjustment Value (default 128) G-Offset adjustment Value (default 128) B-Offset adjustment Value (default 128)
Select download file (epk file)
7.2. White balance. Value.

Center(Default) COOL R Gain G Gain B Gain R Cut G Cut B Cut 192 192 192 64 64 64 Mid 192 192 192 64 64 64 Warm 192 192 192 64 64 64
7.3. Temperature Threshold

Threshold Down Low Threshold Up Low Threshold Down High Threshold Up High 20 23 70 75
8. USB DOWNLOAD(*.epk file download)

Put the USB Stick to the USB socket Press Menu key, and move OPTION
After download is finished, remove the USB stick. Press IN-START key of ADJ remote control, check the S/W version.
9. Tool option
Press FAV Press 7 times Tool option 1 Tool option 2 Tool option 3 Tool option 4 Tool option 5 Country code Country Group Country 50PA4500-DM 36864 22794 3825 54342 10 10 TW CO 50PA4510-DJ 36864 22794 3825 54342 10 10 TW CO
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BLOCK DIAGRAM
- 12 -
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.
300
310
303
304
305
208
209
520
601
540
301
580
206
201
200
302
204
205
207
202
203
501
240
590
120
LV1
910 900
- 13 LGE Internal Use Only
400
A2
A10
A9
A12
+5V
Full SCART
E +3.3V DUP_DVB ISA1530AC1 Q103-*1 C E AV/SC1_DET R105 1K EU R129 0 EU SC1_SOG_IN 23 AV_DET 22 COM_GND 21 SYNC_IN 20 SYNC_OUT 5% 1/16W 19 SYNC_GND2 18 SYNC_GND1 17 RGB_IO 16 R_OUT 15 RGB_GND 14 R_GND 13 D2B_OUT 12 G_OUT 11 D2B_IN 10 G_GND 9 ID 8 B_OUT 7 AUDIO_L_IN 6 B_GND 5 AUDIO_GND 4 AUDIO_L_OUT 3 AUDIO_R_IN 2 AUDIO_R_OUT 1 C107 5600pF 50V EU C108 5600pF 50V EU R138 2K EU Q101 MMBT3904(NXP) EU C113 10uF 16V EU C114 27pF 50V EU R145 6.8K EU R107 75 SC1_B+/COMP1_Pb+ R116 470K EU R124 10K EU R127 12K EU AV/SC1_R_IN R108 75 R115 470K EU SC1_G+/COMP1_Y+ AV/SC1_L_IN R121 10K EU R126 12K EU R106 75 R114 10K EU SC1_R+/COMP1_Pr+ R119 75 EU SC1_FB R123 33 EU EU MMBD6100 D112 A2 SC1_ID R120 2.7K EU DUP_DVB D112-*1 KDS184 A2 C A1 R113 75 EU R118 470K EU R117 75 EU C109 27pF 50V EU C106 EU 0 C111 220pF 50V EU AV/SC1_CVBS_IN Q100 MMBT3904(NXP) EU E B R136 330 EU DUP_DVB 2SC3052 Q100-*1 C B C C Q103 MMBT3906(NXP) EU R144 470 EU B DUP_DVB 2SC3052 Q104*-1
E L103 120-ohm EU L103-*1 CB1608UA121T DUP_DVB
B C
EU JK100 PSC008-02
SHIELD
R104 10K EU
R146 18K EU C B
PDP GP4 S7LR3 EAX64696601
SC1_VOUT
R134 100 1/4W EU R135 0 EU R141 220 EU
E Q104 MMBT3904(NXP) EU R143 180 EU
R147 10K EU
C116 10uF 16V EU
DTV/MNT_VOUT E DUP_DVB 2SC3052 Q106-*1 C E B DUP_DVB 2SC3052 Q105-*1 C
E EU MMBT3904(NXP) Q106 EU C 12K R160
EU 1K R158 B SC_RE1 E EU 1K R157 SC_RE2
REC_8
C A1 E EU MMBT3904(NXP) B Q107 C
EU MMBT3904(NXP) B Q105 C EU 12K R159
EU 7.5K R156
E DUP_DVB 2SC3052 Q107-*1 C
EU R155 3K B
P_17V IC101 AZ4580MTR-E1 P_17V

OUT1 R149 15K EU 1 8 VCC
IN1-
OUT2
R137 2K EU
IN1+ SCART1_Lout R154 5.6K EU VEE
IN2EU 5.6K R153
IN2+
SCART1_Rout
B C115 27pF 50V EU R139 2K EU C112 10uF 16V EU R148 15K EU R152 6.8K EU
DTV_R_OUT
+3.3V_ST
Q102 MMBT3904(NXP) EU
EU R189 10K SCART1_MUTE
R140 2K EU
EU CI_OE AR105
33 /PCM_OE /PCM_WE /PCM_IORD /PCM_IOWR
CI SLOT
+5V_CI_ON
CI_WE CI_IORD CI_IOWR AR106 EU 33
C100 22uF 10V EU
C101 0.1uF 16V EU
CI_ADDR[12] CI_ADDR[13] CI_ADDR[14] REG
PCM_A[12] PCM_A[13] PCM_A[14] /PCM_REG EU BUF2_FE_TS_DATA[0-7] BUF2_FE_TS_DATA[0] AR108 33 EU BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3]
+5V
BUF2_FE_TS_DATA[1] 33 PCM_A[8] PCM_A[9] PCM_A[10] PCM_A[11] BUF2_FE_TS_DATA[2] BUF2_FE_TS_DATA[3]
R151 10K EU /CI_CD1 CI_TS_DATA[4] CI_TS_DATA[5] CI_TS_DATA[6] CI_TS_DATA[7] AR100
R102 100 EU EU
JK102 10067972-000LF EU 35
36 37 33 38 39 40 41 42 R111 10K EU 43 44 45 46 47 48 49 READY R112 0 50 51 52 53 54 R109 10K EU 55 56 57 58 59 60 61 62 63 R110 0 READY 64 65 66 67 68 2 G2 69 G1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 R128 READY 0 EU
CI_ADDR[8] CI_ADDR[9] AR103 33 PCM_D[3] PCM_D[4] PCM_D[5] PCM_D[6] PCM_D[7] R130 33 EU 1/16W R1315% 33 EU R133 10K EU /PCM_CE CI_ADDR[10] CI_ADDR[11]
AR107
AR109 33 EU BUF2_FE_TS_DATA[4] BUF1_FE_TS_DATA[4] BUF2_FE_TS_DATA[5] BUF1_FE_TS_DATA[5] BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7] BUF2_FE_TS_DATA[6] BUF2_FE_TS_DATA[7]
+3.3V_CI +3.3V_CI
EU R165 10K
BUF1_FE_TS_DATA[0-7]
BUF1_FE_TS_DATA[0-7] CI_ADDR[10] CI_ADDR[11] CI_ADDR[9] CI_ADDR[8] CI_ADDR[13] CI_ADDR[14] CI_WE CI_DET PCM_A[0] CI_ADDR[7]
1A2 1OE 1
CI_OE
CI_IORD CI_IOWR BUF2_FE_TS_SYN BUF2_FE_TS_DATA[0-7] BUF2_FE_TS_DATA[0] BUF2_FE_TS_DATA[1] BUF2_FE_TS_DATA[2] BUF2_FE_TS_DATA[3]
IC100 TC74LCX244FT
20 VCC
EU C105 0.1uF 16V
AR110 33 BUF1_FE_TS_SYN BUF1_FE_TS_VAL_ERR BUF1_FE_TS_CLK
EU
BUF2_FE_TS_SYN BUF2_FE_TS_VAL_ERR BUF2_FE_TS_CLK
EU
1A1
19
2OE
2Y4
18
1Y1
CI_ADDR[0]
2A4
R132
100 EU
PCM_A[1]
2Y3
17
PCM_A[7]
1Y2
/PCM_IRQA
CI_ADDR[6]
1A3
16
CI_ADDR[1]
2A3
PCM_A[2]
2Y2
15
PCM_A[6]
1Y3
CI_ADDR[5] BUF2_FE_TS_VAL_ERR BUF2_FE_TS_CLK CI_ADDR[12] CI_ADDR[7] CI_ADDR[6] CI_ADDR[5] CI_ADDR[4] CI_ADDR[3] CI_ADDR[2]
1A4
14
CI_ADDR[2]
2A2
BUF2_FE_TS_DATA[4] BUF2_FE_TS_DATA[5] BUF2_FE_TS_DATA[6] BUF2_FE_TS_DATA[7] PCM_RST /PCM_WAIT REG CI_TS_CLK CI_TS_VAL CI_TS_SYNC AR102 33 EU AR101 33 EU R100 EU 33 R101 EU 33
PCM_A[3]
2Y1
13
PCM_A[5]
1Y4
CI_ADDR[4]
GND
12
CI_ADDR[3]
2A1
10
11
PCM_A[4]
CI POWER ENABLE CONTROL

+5V
L100-*1 CB1608UA121T DUP_DVB Q114 ZXMP3F30FHTA L100 EU 120-ohm EU D +5V_CI_ON
BUF2_FE_TS_DATA[0-7]
5% 1/16W
CI_ADDR[1] EU AR104 33 CI_ADDR[0] PCM_D[0] PCM_D[1] PCM_D[2] CI_ADDR[0-14]
R184 10K READY
R187 10K EU
C131 0.1uF 16V READY
C104 0.1uF 16V EU
R198 10K READY
AO3407A S D
3.3V_CI
+3.3V
CI_TS_DATA[0] CI_TS_DATA[1] CI_TS_DATA[2] CI_TS_DATA[3] R150 10K EU +5V /CI_CD2
L101-*1 CB1608UA121T +3.3V_CI DUP_DVB L101 120-ohm EU
C PCM_D[0-7] PCM_5V_CTL PCM_D[0-7] B R181 10K EU
MULTI Q114-*1 Q113 MMBT3904(NXP) EU
R103 100 EU
E DUP_DVB 2SC3052 Q113*-1
C136 0.1uF 16V READY B
C137 0.1uF 16V EU
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes
GP4_S7LR3 SCART,CI Slot
2011-12-01 1 7
SPDIF HDMI_1
+5V SHIELD 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CK+ D0D0_GND D0+ D0+_HDMI1 D1D1-_HDMI1 D1_GND D1+ D1+_HDMI1 D2D2-_HDMI1 D2_GND D2+ D2+_HDMI1 2 1 3 5 4 6 JP202 R208 33 HDMI_1 R281 10K HDMI_1 E DUP_DVB 2SC3052 Q200-*1 C
JK200-*1
SIDE_HDMI_1
+5V B BODY_SHIELD 20 19 18 17 16 15
20
SIDE_HDMI_2
+5V B BODY_SHIELD C B R203 10K SIDE_HDMI_1 HPD2 20 19 18 17 DDC_SDA_2 DDC_SCL_2 16 15 14 CEC_REMOTE CK-_HDMI2 13 12 11 10 9 8 D0+_HDMI2 7 6 5 D1+_HDMI2 4 3 2 D2+_HDMI2 1 CK+ JP208 R288 10K SIDE_HDMI_2 5V_DET_HDMI_3 R240 1K SIDE_HDMI_2
JK204 JST1223-001 B 1 Fiber Optic
DUP_AT
JK204-*1 DUP_DVB 2F01TC1-CLM97-4F 1 Fiber Optic GND
GND
For CEC
R209 10K SIDE_HDMI_2 HPD3
+5V
R200 1K HDMI_1
HDMI1_NON Screw DATA2+ 1
C B JP201
R202 10K HDMI_1 R217 10K HDMI_1
C B
5V_DET_HDMI_1
YKF45-7058V
DATA2_SHIELD DATA2DATA1+ DATA1_SHIELD
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
R226 1K SIDE_HDMI_1
5V_DET_HDMI_2
VCC C219 0.1uF 16V R285 100 SPDIF_OUT C220 10pF 50V
VCC
JP204
DATA0+ DATA0_SHIELD DATA0CLK+ CLK_SHIELD CLKCEC NC SCL
JP207
R201 1.8K HDMI_1
R286 10K SIDE_HDMI_1
FIX_POLE
DDC_SDA_1 DDC_SCL_1
SDA DDC/CEC_GND +5V_POWER HPD
SHIELD
14 13 12 11 10 9 8 7 CK+
JP205
R232 33 SIDE_HDMI_1
R246 33 SIDE_HDMI_2
DDC_SCL_3 R268 100
CEC_REMOTE CK-_HDMI1
CEC_REMOTE CK-_HDMI3
CEC_REMOTE
CEC_REMOTE_S7 PEN_TOUCH +5V_ST D225 B140A 40V

1A SPEC
IC207 AP2337SA-7
SIDE USB
CK+_HDMI3 D0-_HDMI3
CK+_HDMI1 D0-_HDMI1
CK+_HDMI2 D0D0-_HDMI2 D0_GND D0+ D1D1-_HDMI2 D1_GND D1+ D2D2-_HDMI2 D2_GND D2+
PEN_TOUCH VIN 3 1 GND
+3.3V
2 VOUT
SWITCH ADDED
IC204 AP2191SG-13
SHIELD
Q200 MMBT3904(NXP) HDMI_1 E R204 3.3K HDMI_1 R207 R282 33 10K HDMI_1 HDMI_1
HPD1
DATA1-
R227 1.8K SIDE_HDMI_1
Q201 MMBT3904(NXP) SIDE_HDMI_1 E R230 3.3K R231 R287 SIDE_HDMI_1 33 10K SIDE_HDMI_1 SIDE_HDMI_1
R237 10K SIDE_HDMI_1
Q202 R241 MMBT3904(NXP) 1.8K SIDE_HDMI_2 SIDE_HDMI_2
R250 10K SIDE_HDMI_2 E R244 3.3K R289 SIDE_HDMI_2 R245 10K 33 SIDE_HDMI_2 SIDE_HDMI_2 DDC_SDA_3
VINPUT
VIN
+3.3V +5V
D0D0_GND D0+ D0+_HDMI3 D1D1-_HDMI3 D1_GND 1 USB DOWN STREAM D1+ D1+_HDMI3 D2D2-_HDMI3 D2_GND D2+ D2+_HDMI3
R264 10K
NC
GND
R270 10K
OUT_2
IN_1
JK209 3AU04S-305-ZC-(LG)
$0.11
OUT_1 6 3 IN_2
C212 0.1uF 16V
C213 10uF 10V USB1_OCD
R258 33
FLG
EN
R271 33 SIDE_USB_DM
USB1_CTL
SIDE_USB_DP
JK200 HDMI_1
JK201 SIDE_HDMI_1
JK202 SIDE_HDMI_2
10mm
JK211 PPJ239-01 NON_EU 6H 5H 4H 5G 4F 5F 7F 5E 7E 4D 5D 6D 6N 5N 4N 5M 5L 7L 5K 7K 4J 5J 6J [RD1]E-LUG [RD1]O-SPRING_2 [RD1]CONTACT_2 [WH1]O-SPRING [RD1]CONTACT_1 [RD1]O-SPRING_1
COMPONENT2
RS232C
ETHERNET
+2.5V
JK210 XRJV-01V-0-D12-080
JK208 PPJ234-02 EU 6A [GN]O-SPRING 5A [GN]CONTACT 4A [BL]E-LUG-S 7B [BL]O-SPRING COMP2_Pb+ 5B [RD]E-LUG-S 7C [RD]O-SPRING_1 5C [RD]CONTACT_1 4C R253 75 COMP2_Pr+ R267 1K R252 75 R265 10K COMP2_DET [GN]E-LUG R251 75 COMP2_Y+
+3.3V
R259 10K
JK210-*1
TP
2
BS-R430051
1 ET_NET_UDE
R266 1K
AV2_DET
3
TN
4
RP
5
ET_NET 5
RN
7
8 9
+3.3V_ST
JP241
R283 R284
22 22
PM_TXD
+3.3V_ST
PM_RXD C229 0.1uF 16V
9 9
C200 0.1uF 16V ET_NET
D204 D200 5.6V 5.6V ET_NET ET_NET
D205 5.6V ET_NET
D206 5.6V ET_NET
[RD1]E-LUG-S
5D 4E 5E [WH]O-SPRING [RD]CONTACT_2 [RD]O-SPRING_2 [RD]E-LUG R255 470K R254 470K
R256 10K R262 12K R257 10K R263 12K
COMP2_L_IN
JK203 SPG09-DB-009
1
R278 10K
R279 10K VCC
IC206 MAX3232CDR
16 1 C1+ C228 0.1uF 16V C225 0.1uF 16V
[BL1]O-SPRING [BL1]E-LUG-S [GN1]CONTACT [GN1]O-SPRING [GN1]E-LUG
COMP2_R_IN 2
6 R276 100 +5V_ST GND 15 2 V+
R273 0 ET_NET R280 0 ET_NET
R291 0 ET_NET R290 0 ET_NET
6E
7 3 8 4
R277 100
DOUT1
14
C1-
R228 10K USA TX R229 100K USA B R233 100K USA
RIN1
13
C2+ C226 0.1uF 16V
9 5 10 Q204 MMBT3904(NXP) USA
ROUT1
12
C2-
DIN1
11
V-
DIN2
10
DOUT2
ROUT2
RIN2
[RD2]E-LUG [RD2]O-SPRING_2
NON_EU NON_EU R234 10K R235 470K R236 12K NON_EU
E DUP_AT 2SC3052 Q204*-1 C AV/SC1_R_IN
C227 0.1uF 16V B
[RD2]CONTACT [WH2]O-SPRING [RD2]O-SPRING_1
NON_EU R239 10K NON_EU NON_EU R238 470K R242 12K AV/SC1_L_IN
RGB PC
JK205 SPG09-DB-010
+5V_ST
PC AUDIO
JK206 PEJ027-04 3 6A DSUB_R+ 7A R215 75 R205 33 R216 75 RGB_DDC_SDA DSUB_G+ DSUB_HSYNC DSUB_B+ 7B C202 10pF 50V C203 10pF 50V DSUB_VSYNC R224 10K R225 1K DSUB_DET RGB_DDC_SCL PC_SER_DATA R212 10 PC_SER_CLK 7B 6B B_TERMINAL2 TX T_TERMINAL2 R210 10 USA 4 5 R_SPRING T_SPRING R213 0 NON_USA 6B 4 5 E_SPRING T_TERMINAL1 B_TERMINAL1 R_SPRING T_SPRING B_TERMINAL2 T_TERMINAL2 R221 10K PC_L_IN R219 470K R223 12K 6A 7A R220 10K PC_R_IN 1/16W 5% R218 470K R222 12K JK207 PEJ027-04 USA 3 E_SPRING T_TERMINAL1 IR B_TERMINAL1
SC1_R+/COMP1_Pr+
R297 10K
R298 10K
[RD2]E-LUG-S
1
6 11 7 2
SC1_B+/COMP1_Pb+
RED_GND GND_2 RED GREEN_GND DDC_DATA R214 75
[BL2]O-SPRING [BL2]E-LUG-S
+3.3V
12 8
GREEN BLUE_GND H_SYNC
WIRED IR
3 9 4
COMP1_DET NON_EU R248 10K
13
BLUE NC V_SYNC R206 33
+3.3V
[GN2]CONTACT [GN2]O-SPRING
NON_EU R249 1K
14 10
GND_1 SYNC_GND DDC_CLOCK
5
SC1_G+/COMP1_Y+
15
DDC_GND
16
R211 10 SHILED
[GN2]E-LUG
GND
GP4_S7LR1
JACK INTERFACE
2011-12-1 2 7
TUNER
G201D_NON_DEMODE TU302-*1 TDSS-G201D
BUF1_FE_TS_DATA[0-7] FE_TS_DATA[0] FE_TS_DATA[1] FE_TS_DATA[2] FE_TS_DATA[3] FNIM R324 FNIM 0 R326 FNIM R325 FNIM 0 R323 BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3]
0 FE_TS_DATA[4] FE_TS_DATA[5] FE_TS_DATA[6] FE_TS_DATA[7] FE_TS_DATA[0-7] R331 FE_TS_SYN FE_TS_VAL_ERR FE_TS_CLK 0 0 0

+B2[1.8V] NC_3 IF_AGC DIF[P] DIF[N]
TUNER TDSS-G201D TDSS-H201F TDSH-T101F TDSN_B001F TDSN_G301D
OPT1 DVB-T/C ATSC
OPT2 HNIM HNIM
OPT3 X X RF_SW RF_SW X

12
1 2 3 4 5 6
NC_1 RESET SCL SDA +B1[3.3V] NC_2
FNIM R328 FNIM R330 FNIM 0 0R329 FNIM 0 FNIM FNIM FNIM
R327
BUF1_FE_TS_DATA[4] BUF1_FE_TS_DATA[5] BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7]
R333 R332
BUF1_FE_TS_SYN BUF1_FE_TS_VAL_ERR BUF1_FE_TS_CLK
DVB-T_SCA HNIM SBTVD DVB_T2 FNIM FNIM
7 8 9 10 11
RF_SWITCH R310 1K
SHIELD
RF_SWITCH_CTL C307 0.1uF 16V RF_SWITCH
Close to Tuner Pin TU304 TDSN-G301D

DVB_T2 1 2 3 4 5 6 7 8 9 10 11 NC_1 RESET SCL SDA +B1[3.3V] SIF +B2[1.8V] CVBS NC_2 NC_3 NC_4 +B3[3.3V] +B4[1.23V] NC_5 GND ERROR SYNC VALID MCLK D0 D1 D2 D3 D4 D5 D6 D7 28 SHIELD SBTVD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 RF_S/W_CTL RESET SCL SDA +B1[3.3V] SIF +B2[1.8V] CVBS NC_1 NC_2 NC_3 +B3[3.3V] +B4[1.23V] NC_4 GND ERROR SYNC FE_TS_SYN VALID FE_TS_VAL_ERR MCLK D0 D1 D2 D3 D4 D5 D6 D7 FE_TS_CLK FE_TS_DATA[0] FE_TS_DATA[1] FE_TS_DATA[2] FE_TS_DATA[3] FE_TS_DATA[4] FE_TS_DATA[5] FE_TS_DATA[6] FE_TS_DATA[7] FE_TS_DATA[0-7] C312 10pF 50V READY R334 C313 10pF 50V READY 0 A_DEMODE TU_CVBS 12 SHIELD 12 SHIELD 12 SHIELD
TU303 TDSN_B001F
DVB_T/C
TU302 TDSS-G101D ATSC 1 2 3 4 5 6 7 8 9 10 11 NC RESET SCL SDA +3.3V SIF +1.8V CVBS IF_AGC DIF[P] DIF[N]
TU301 TDSS-H201F
TU300 TDSH-T101F DVB_T_SCA
+3.3V_TU
+3.3V_TU
+1.8V_TU
+2.5V_TU
1 2 3 4 5 6 7 8 9 10 11
NC_1 RESET SCL SDA +B1[3.3V] NC_2 +B2[1.8V] NC_3 IF_AGC DIF[P] DIF[N]
1 2 3 4 5 6 7 8 9 10 11
RF_S/W_CTL RESET SCL SDA +B1[3.3V] SIF +B2[1.8V] CVBS IF_AGC DIF[P] DIF[N] DVB_T2 16V 0.1uF C306 C302 0.1uF 16V C303 10uF 16V 16V 0.1uF C310 C304 68pF 50V
R308 R301 2.2K 100 R307 22
R309 2.2K
R311 10K TUNER_RESET
TU_SCL TU_SDA
R306 22 C305 68pF 50V
C311 0.1uF 16V
DVB_T2 0 H_NIM 0
R302 R303 IF_AGC_MAIN
Close to Tuner Pin
IF_P_MSTAR IF_N_MSTAR
+1.25V_TU
C300 10uF 6.3V FNIM
12 13 C301 0.1uF 16V FNIM 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SHIELD
R320
2K +5V NON_A_DEMODE 430 R322 C308 0.1uF 16V
Close to Tuner Pin
NON_A_DEMODE 430 R319
NON_A_DEMODE
R316 470 A_DEMODE E
A_DEMODE R317 82 TU_SIF
R312 4.7K A_DEMODE A_DEMODE
MMBT3906(NXP) Q301 C A_DEMODE
Close to Tuner Pin
TUNER
Tuner block
6
+3.3V
LGE2111B
MODEL OPTION
1K PCM_D[0-7] PCM_D[0]
IC400
CI_TS_CLK
MODEL OPTION PIN NAME

FHD
PIN NO. AB3 F4 AB2
LOW FHD
HIGH HD
Close to MSTAR
R442 100 H_NIM C468 0.1uF H_NIM DVB_T_SCA C483 100pF R443 100 H_NIM C469 0.1uF H_NIM
DTV_IF
IF_P_MSTAR
PCM_D[1] PCM_D[2] PCM_D[3] PCM_D[4] PCM_D[5] PCM_D[6] PCM_D[7] PCM_A[0-14] PCM_A[0]
AB17 MAIN IC AB19 Y16 AD15 AE15 AD14 AB15 AC16 Y17 AA16 AB16 AD16 Y18 AE20 Y19 AC20 AB18 AD17 AC15 AE17 AA19 AA18 AC19 AE18
AA11 PCMDATA0/GPIO126 PCMDATA1/GPIO127 PCMDATA2/GPIO128 PCMDATA3/GPIO120 PCMDATA4/GPIO119 PCMDATA5/GPIO118 PCMDATA6/GPIO117 PCMDATA7/GPIO116 PCMADR0/GPIO125 PCMADR1/GPIO124 PCMADR2/GPIO122 PCMADR3/GPIO121 PCMADR4/GPIO99 PCMADR5/GPIO101 PCMADR6/GPIO102 PCMADR7/GPIO103 PCMADR8/GPIO108 PCMADR9/GPIO110 PCMADR10/GPIO114 PCMADR11/GPIO112 PCMADR12/GPIO104 PCMADR13/GPIO107 PCMADR14/GPIO106 TS1DATA0/GPIO88 TS1DATA1/GPIO89 TS1DATA2/GPIO90 TS1DATA3/GPIO91 TS1DATA4/GPIO92 TS1DATA5/GPIO93 TS1DATA6/GPIO94 TS1DATA7/GPIO95 PCMREG_N/GPIO123 PCMOE_N/GPIO113 PCMWE_N/GPIO197 PCMIORD_N/GPIO111 PCMIOWR_N/GPIO109 NF_WPZ/GPIO198 NF_CEZ/GPIO137 NF_CLE/GPIO136 NF_REZ/GPIO139 NF_WEZ/GPIO140 PCMCE_N/GPIO115 PCMIRQA_N/GPIO105 PCMCD_N/GPIO130 PCMWAIT_N/GPIO100 PCM_RESET/GPIO129 GPIO_PM[0]/GPIO6 PM_UART_TX/GPIO_PM[1]/GPIO7 GPIO_PM[2]/GPIO8 PCM2_CE_N/GPIO131 PCM2_IRQA_N/GPIO132 PCM2_CD_N/GPIO135 PCM2_WAIT_N/GPIO133 PCM2_RESET/GPIO134 GPIO_PM[4]/GPIO10 PM_UART_RX/GPIO_PM[5]/GPIO11 PM_SPI_SCZ1/GPIO_PM[6]/GPIO12 L5 GPIO_PM[8]/GPIO14 UART1_RX/GPIO44 UART1_TX/GPIO43 UART2_RX/GPIO64 UART2_TX/GPIO65 GPIO_PM[9]/GPIO15 PM_SPI_SCZ2/GPIO_PM[10]/GPIO16 GPIO_PM[11]/GPIO17 A5 PM_SPI_SCK/GPIO1 I2C_SDAM2/DDCR_DA/GPIO71 I2C_SCKM2/DDCR_CK/GPIO72 PM_SPI_CZ0/GPIO_PM[12]/GPIO0 PM_SPI_SDI/GPIO2 PM_SPI_SDO/GPIO3 DDCA_DA/UART0_TX DDCA_CK/UART0_RX D3 B5 B4 R480 33 R478 33 R479 33 L6 B3 L4 ERROR_DET /FLASH_WP 5V_ON J4 D5 C4 RL_ON PM_RXD NF_ALE/GPIO141 NF_RBZ/GPIO142 M5 D4 L7 100 R477 R476 Y9 AA10 Y10 AB10 AC9 AD10 AC10 AR400 100 22 OS AC_DET PM_TXD DISP_EN R481 1K AR401 22 OS TS1CLK/GPIO98 TS1VALID/GPI96 TS1SYNC/GPIO97 Y14 AA14 AD13 Y13 AA13 AD12 AC12 W10 BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3] BUF1_FE_TS_DATA[4] BUF1_FE_TS_DATA[5] BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7] TS0DATA0/GPIO77 TS0DATA1/GPIO78 TS0DATA2/GPIO79 TS0DATA3/GPIO80 TS0DATA4/GPIO81 TS0DATA5/GPIO82 TS0DATA6/GPIO83 TS0DATA7/GPIO84 AB13 AC14 W13 TS0CLK/GPIO87 TS0VALID/GPIO85 TS0SYNC/GPIO86 AB12 AD11 W9 AE11 AB11 AE12 AC13 AB14 CI_TS_DATA[0] CI_TS_DATA[1] CI_TS_DATA[2] CI_TS_DATA[3] CI_TS_DATA[4] CI_TS_DATA[5] CI_TS_DATA[6] CI_TS_DATA[7] Y11 AC11
CI_TS_VAL CI_TS_SYNC CI_TS_DATA[0-7]
MODEL_OPT_0
MODEL_OPT_1 RF_SWITCH_CTL
R409
MODEL_OPT_1 MODEL_OPT_2
from CI SLOT
IF_N_MSTAR DVB_T_SCA C486 100pF
1K
2D
1K HD
A_DEMODE A_DEMODE 47 C458 0.1uF R446 C459 0.1uF R447 47 A_DEMODE
PCM_A[1] TU_SIF PCM_A[2] PCM_A[3] PCM_A[4] PCM_A[5] PCM_A[6] PCM_A[7] PCM_A[8] PCM_A[9] PCM_A[10] PCM_A[11] PCM_A[12] PCM_A[13] PCM_A[14] IF_AGC_MAIN NON_A_DEMODE C488 0.047uF 25V H_NIM +5V
R405
R410
IC400 LGE2111B
A_DEMODE
ANALOG SIF Close to MSTAR

+3.3V
BUF1_FE_TS_CLK BUF1_FE_TS_VAL_ERR BUF1_FE_TS_SYN BUF1_FE_TS_DATA[0-7]
CK+_HDMI2 CK-_HDMI2 D0+_HDMI2 D0-_HDMI2 D1+_HDMI2 D1-_HDMI2 D2+_HDMI2 D2-_HDMI2 DDC_SDA_2 DDC_SCL_2 HPD2 CK+_HDMI3 CK-_HDMI3 D0+_HDMI3 D0-_HDMI3 D1+_HDMI3 D1-_HDMI3 D2+_HDMI3 D2-_HDMI3 DDC_SDA_3 DDC_SCL_3 HPD3 CK+_HDMI1 CK-_HDMI1 D0+_HDMI1 D0-_HDMI1 D1+_HDMI1 D1-_HDMI1 D2+_HDMI1 D2-_HDMI1 DDC_SDA_1 DDC_SCL_1 HPD1 CEC_REMOTE_S7 DSUB_HSYNC DSUB_VSYNC DSUB_R+ DSUB_G+ DSUB_B+ R412 R413 R424 R425 R426 R427 R428 R406 10K R411 2.4K R429 22 22 33 68 33 68 33 68 C407 C408 C409 C410 C411 C412 C413
MAIN H3 IC H2 J1 J2 K1 J3 K3 K2 F4 F5 G5 AD6 AE6 AD7 AC6 AD8 AC7 AC8 AE8 AE5 AC5 AD5 E3 E2 F1 F2 G1 F3 G3 G2 G7 G6 G4 R6
AC3 A_RXCP A_RXCN A_RX0P A_RX0N A_RX1P A_RX1N A_RX2P A_RX2N DDCDA_DA/GPIO24 DDCDA_CK/GPIO23 HOTPLUGA/GPIO19 C_RXCP C_RXCN C_RX0P C_RX0N C_RX1P C_RX1N C_RX2P C_RX2N DDCDC_DA/GPIO28 DDCDC_CK/GPIO27 HOTPLUGC/GPIO21 D_RXCP D_RXCN D_RX0P D_RX0N D_RX1P D_RX1N D_RX2P D_RX2N DDCDD_DA/GPIO30 DDCDD_CK/GPIO29 HOTPLUGD/GPIO22 AUL1 CEC/GPIO5 AUR1 AUL3 HSYNC0 VSYNC0 RIN0P RIN0M GIN0P GIN0M BIN0P BIN0M SOGIN0 AUVRM AA4 AUVAG HSYNC1 VSYNC1 RIN1P RIN1M GIN1P GIN1M BIN1P BIN1M SOGIN1 RN TN RIN2P RIN2M GIN2P GIN2M BIN2P BIN2M SOGIN2 HWRESET IRIN/GPIO4 K4 LED0/GPIO55 LED1/GPIO56 C6 A3 C3 COMP1_DET AV/SC1_DET R440 49.9 RP TP A2 B1 EARPHONE_OUTL EARPHONE_OUTR B2 C2 AUVRP AA9 AB9 C456-*1 1uF DUP_DVB Y5 AUOUTL2 AUOUTR2 AA5 C454 4.7uF C456 1uF DUP_AT AUR3 AUL4 AUR4 AB4 AB5 Y3 AA2 AA1 AA3 W3 Y2 C447 C448 C449 C450 C451 C452 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF I2S_OUT_BCK/GPIO156 I2S_OUT_MCK/GPIO154 I2S_OUT_SD/GPIO157 I2S_OUT_WS/GPIO155 USB1_DM USB1_DP C10 I2S_IN_BCK/GPIO150 I2S_IN_SD/GPIO151 I2S_IN_WS/GPIO149 A9 B8 C9 A8 B10 B9 R473 22 USB0_DM USB0_DP AE9 AD9 SPDIF_IN/GPIO152 SPDIF_OUT/GPIO153 D1 D2 I2C_SCKM1/GPIO75 I2C_SDAM1/GPIO76 AE4 XIN XOUT B6 M7 R474 22 R437 AD4 1M X400 24MHz IF_AGC SIFP SIFM AC2 IP IM AD1 AD3 AD2
L403 BLM18PG121SN1D H_NIM L403-*1 CB1608UA121T DUP_DVB H_NIM C470 0.1uF H_NIM R448 10K
NON_A_DEMODE AGC 1.25V 100 OHM SERIAL A_DEMODE 0ohm

R449 100
Internal demod out
TUNER_I2C
AE3 AE2 TU_SCL TU_SDA C461 30pF
R449-*1 0 A_DEMODE
/PCM_REG /PCM_OE /PCM_WE /PCM_IORD EU R456 10K R457 10K EU /PCM_IOWR
AE14 AD19 AD18 AC18 AC17
/PF_WP /PF_CE0 /PF_CE1 /PF_OE /PF_WE PF_ALE /F_RB
Close to MSTAR
C462
30pF
/PCM_CE /PCM_IRQA /PCM_WAIT PCM_RST
AD20 AE21 W16 EU C495 0.1uF 16V AA17 AA20 AB22 Y21 AB20 Y20 E5
P_SDA SPDIF_OUT
EU SIDE_USB_DM SIDE_USB_DP SUB_SDA SUB_SCL P_SCL /CI_CD1 /CI_CD2 R454 R455 EU 22 22 USB1_OCD USB1_CTL
to delete CI or gate for I2S_I/F

AUD_SCK AUD_MASTER_CLK AUD_LRCH AUD_LRCK
UART_RXD UART_TXD PM_RXD PM_TXD
E4 U24 U25 AB21 AA21 R466 R467 22 22 H5 H4 AA22 PWM0 PWM1 COMP2_DET SC_RE2 Y22 V24 U23 T22 C7 LED_RED E7 KEY1 KEY2 D7 J6 F6 C1 AMP_MUTE
SPI_SCK /SPI_CS SPI_SDI SPI_SDO
for SYSTEM EEPROM (IC104) AUDIO IN
I2C_SDA I2C_SCL RGB_DDC_SDA
AV/SC1_L_IN AV/SC1_R_IN COMP2_L_IN COMP2_R_IN PC_L_IN PC_R_IN
RGB_DDC_SCL
for SERIAL FLASH

+1.10V_VDDC
IC400 LGE2111B
PWM0/GPIO66 PWM1/GPIO67 PWM2/GPIO68 PWM3/GPIO69 PWM4/GPIO70 PWM_PM/GPIO199 SAR0/GPIO31 SAR1/GPIO32 SAR2/GPIO33 SAR3/GPIO34 SAR4/GPIO35 MAINU17 IC P17 R17 R18 T17 T18 U18 J9 J11 P8 R8 U11 V10 P18 DVDD_DDR J14 J15 AVDD_DDR0_C AVDD_DDR0_D_1 AVDD_DDR0_D_2 AVDD_DDR0_D_3 J16 K16 R19 AVDDLV VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 GND_80 GND_81 GND_82 GND_83 GND_84 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND_100 GND_101 AVDD_DDR1_C AVDD_DDR1_D_1 AVDD_DDR1_D_2 AVDD_DDR1_D_3 AVDD2P5 AVDD25_PGA AVSS_PGA AA8 AVDD2P5_DADC AB1 AB2 Y8 AVDD25_LAN AB8 AVDD_MOD C496 1uF Y4 DVDD_NODIE AA6 VDD33 W6 Y6 AVDD_AU33 AVDD_DVI_USB_MPLL AVDD_PLL VDDP W5 AVDD_DMPLL AVDD_NODIE K8 TEST J8 GND_EFUSE V4 GND_85 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 AVDD25_PGA AVSS_PGA GND_102 GND_103 GND_104 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 R23 T23 U5 U6 V11 V15 V16 V17 V18 V19 V20 V21 W11 W15 W17 W18 W20 W21 W22 Y7 AA7 AB6 AB7 A15 A17 A20 B14 B16 B18 B21 C11 C12 C13 C20 C23 C25 D23 E17 E18 E20 E23 F18 G10 G12 G15 G16 G19 G20 G24 H10 H12 H13 H14 H15 H16 H19 H25 J12 J13 J19 J20 J24 K12 K13 K14 K15 K18 K19 K25 L8 L12 L13 L14 L15 L18 L19
R5 R4 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF N1 N2 M1 M3 L2 L3 M2 T3 T2
DSUB
AUDIO OUT
SCART1_Lout SCART1_Rout L404 C463 0.1uF C466 10uF BLM18SG121TN1D
DUP_DVB L404-*1 CIS10P121AC DUP_AT
SCART1_RGB/COMP1
SC1_ID SC1_FB SC1_R+/COMP1_Pr+ SC1_G+/COMP1_Y+ SC1_B+/COMP1_Pb+ SC1_SOG_IN COMP2_Pr+ COMP2_Y+ COMP2_Pb+ R430 R415 R416 R417 R418 R419 R420 0 33 68 33 68 33 68 R431 R432 R433 R434 R435 R436 33 68 33 68 33 68 C414 C415 C416 C417 C418 C419 C420 NON_EU C421 C422 C423 C424 C425 C426 C427 A_DEMODE R421 33 EU R422 R423 33 33 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF
R3 T1 R2 R1 N3 P2 P3 W1 W2 V1 V3 U2 U3 V2 T5 T4 T6 T7
RP TP RN TN R441 49.9 R444 49.9 R445 49.9
+3.3V
+1.10V_VDDC AVDD_MIU
COMP2
*H/W opt : ETHERNET
1K OS
<CHIP Config(LED_R/BUZZ)> Boot from SPI CS1N(EXT_FLASH) Boot from SPI_CS0N(INT_FLASH)
1b0 1b1
R462
<CHIP Config> (I2S_OUT_BCK,I2S_OUT_MCK,PAD_PWM1PAD_PWM0)

B51_no_EJ SB51_WOS SB51_WS MIPS_SPE_NO_EJ MIPS_SPI_EJ_1 MIPS_SPI_EJ_2 MIPS_WOS MIPS_WS : : : : : : : : 4b0000 4b0001 4b0010 4b0100 4b0101 4b0110 4b1001 4b1010 Boot from 8051 with SPI flash Secure B51 without scramble Secure B51 with scramble Boot from MIPS with SPI flash Boot from MIPS with SPI flash Boot from MIPS with SPI flash Secure MIPS without scramble Scerur MIPS with SCRAMBLE 1K 1K
J17 L16 L17 LED_RED AUD_SCK AUD_MASTER_CLK PWM1 PWM0 M16
C460 0.1uF
C471 0.1uF
CVBS In/OUT
TU_CVBS AV/SC1_CVBS_IN COMP2_Y+ DTV/MNT_VOUT
A_DEMODE C428 0.047uF EU C429 C430 0.047uF 0.047uF
CVBS0 CVBS1 CVBS2 TX CVBSOUT2 SOC_RESET
1K
1K
L421
R414
68
C406
0.047uF
U4 R459 R461 R463 VCOM
NON_OS
R470
Close to MSTAR
L405-*1 CB1608UA121T DUP_DVB +2.5V AVDD2P5 AVDD2P5:172mA C4001 IS CAP FOR REPAIR SHOULD BE BOTTOM SIDE
R472
1K
W7
SOC_RESET
+3.3V_ST
DDR3 1.5V
L402-*1 CB1608UA121T DUP_DVB L402 BLM18PG121SN1D R408 10 SOC_RESET 0.1uF C432 DUP_AT 0.1uF C4003 C4004 0.1uF 0.1uF C436 10uF C442 C444 C445 C446 DUP_AT 1uF 0.1uF 0.1uF C446-*1 1uF DUP_DVB AVDD_MIU DECAP READY FOR TEST DECAP FOR SOC (HIDDEN - UCC) READY C453 0.1uF 4V
L405 BLM18PG121SN1D DUP_AT
Normal 2.5V
AVDD_NODIE +3.3V W4
C485 0.1uF NON-UCC L406-*1 CB1608UA121T AVDD25_PGA DUP_DVB L406 BLM18PG121SN1D DUP_AT C477 0.1uF L407 BLM18SG121TN1D AVSS_PGA DUP_DVB Close to IC with width trace L407-*1 CIS10P121AC DUP_AT
UCC C489 0.1uF 4V
READY C4001 0.1uF 4V
AVDD_DDR0:55mA
+1.5V_DDR
IC400 LGE2111B
DECAP FOR SOC (HIDDEN - UCC)
C497 22uF 16V D400-*1 KDS181 D400 BAW56 GEANDE R403 100K DUP_DVB DUP_AT
R482 R483 3.3K 3.3K
R450 R451 3.3K 3.3K
5V_DET_HDMI_1 R452 2.2K R453 2.2K I2C_SDA I2C_SCL P_SDA P_SCL UART_RXD UART_TXD AMP_RESET_N TUNER_RESET PCM_5V_CTL CI_DET AMP_SCL AMP_SDA MODEL_OPT_1 RF_SWITCH_CTL 22 5V_DET_HDMI_2 5V_DET_HDMI_3
MAIN N5 IC A6 M6 R7 P5 D6 M4 C8 C5 R438 EU E6 H6 K5 B7 J7 J5
AC25 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO45 GPIO46 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 LVB0P LVB0M LVB1P LVB1M GPIO73 GPIO74 LVB2P LVB2M LVBCKP LVBCKM LVB3P LVB3M LVB4P LVB4M LVA0P LVA0M LVA1P LVA1M LVA2P LVA2M LVACKP LVACKM LVA3P LVA3M LVA4P LVA4M V23 W24 W25 W23 Y25 Y24 Y23 AA24 AA23 AB24 AB25 AB23 RXB4+ RXB4RXB3+ RXB3RXBCK+ RXBCKRXB2+ RXB2RXB1+ RXB1RXB0+ RXB0AC24 AD25 AD24 AE24 AC23 AE23 AD23 AC22 AD22 AC21 AD21 RXA4+ RXA4RXA3+ RXA3RXACK+ RXACKRXA2+ RXA2RXA1+ RXA1RXA0+ RXA0-
L20 L24 M8 M12 M13 M14 M15 M17 M18 M19 M24 N7 N13 N14 N15 N16 N17 N18 N19 N20 N25 P13 P14 P19 P21 P24
C402 0.1uF
AVDD_DDR1:55mA
C453 IS CAP FOR REPAIR SHOULD BE BOTTOM SIDE
Normal Power 3.3V

0.1uF NON-UCC 0.1uF NON-UCC 0.1uF NON-UCC
STby 3.3V
AVDD_NODIE:7.362mA AVDD_NODIE +3.3V_ST
+3.3V
VDD33
READY
DECAP FOR SOC (HIDDEN - UCC) +1.10V_VDDC
0.1uF NON-UCC
0.1uF NON-UCC
0.1uF NON-UCC
0.1uF NON-UCC
0.1uF NON-UCC
0.1uF NON-UCC
VDDC 1.05V
C467-*1 1uF DUP_DVB C472-*1 1uF DUP_DVB DUP_AT C474 0.1uF 10uF 10uF
+1.10V_VDDC VDDC : 2026mA UCC 0.1uF 4V UCC 0.1uF DECAP FOR SOC (HIDDEN - UCC) UCC READY READY READY 0.1uF C4000 0.1uF 4V 4V C4005 0.1uF C4006 0.1uF
AV2_DET DSUB_DET
L401 BLM18PG121SN1D 0.1uF 10uF C435 10uF DUP_AT L401-*1 CB1608UA121T DUP_DVB
0.1uF
AB3 SC_RE1 SCART1_MUTE R468 EU 22 AC4
10uF
L400 BLM18PG121SN1D DUP_AT L400-*1 CB1608UA121T DUP_DVB C401 0.1uF
1uF
DUP_AT C472 1uF
4V
4V
C440
C4002
C434
C438
C441
C455
C431
C457
C465
C478
C480
C467
C482
C484
C487
C490
C492
C4002 SHOULD NEAR MAIN IC C4000,C4005,C4006 IS CAP FOR REPAIR SHOULD BE BOTTOM SIDE
C491
C493
4V
GP4_S7LR MAIN
2011-10-20 4 6
A1
A2 KDS184 D500-*1
DUP_AT
Key/IR
+3.3V_ST P501 12507WS-08L USA IR R515 4.7K R518 100 C517 10pF 50V DUP_DVB R540 10K KEY1 R516 100 KEY2 C535 0.1uF 16V LED_RED +3.3V_ST ZD500 R542 10K R517 100 5.48VTO5.76V 1 DUP_DVB ZD502
LVDS
+5V R512 4.7K R513 4.7K E DUP_DVB 2SC3052 Q500-*1 C A1 A2 2
NAND Flash 1GBit

NC_1 +3.3V NC_2 NC_3 NC_4 NC_5
IC504 H27U1G8F2BTR-BC
+3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC_29 NC_28 NC_27 PCM_A[0-7] NC_26 I/O7 I/O6 I/O5 I/O4 NC_25 NC_24 NC_23 VCC_2 VSS_2 NC_22 NC_21 NC_20 I/O3 I/O2 I/O1 I/O0 NC_19 NC_18 NC_17 NC_16 C554 10uF 10V
+5V
+3.3V_ST
R577 4.7K
AR518 22
PCM_A[7] PCM_A[6] PCM_A[5] PCM_A[4]
LD500 3 DUP_DVB ZD501 C534 0.1uF 16V R514 22 ZD503 DUP_DVB C520 10pF 50V D500 MMBD6100 DUP_DVB
C
R565 1K /F_RB
R568 4.7K
NC_6 R/B
2K R579
E Q500 MMBT3904(NXP) DUP_AT
RE /PF_OE CE /PF_CE0 NC_7 NC_8
5
P503 TF05-51S
P500 104060-8017
1 2
47K R578
R538 4.7K SUB_SCL
DUP_DVB
R539 4.7K R519 100
1 2 3 4 5 6 7 8 9 RXA0RXA0+ RXA1RXA1+ RXA2RXA2+ RXACKRXACK+ RXA3RXA3+ RXA4RXA4+ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RXB0RXB0+ RXB1RXB1+ RXB2RXB2+ RXBCKRXBCK+ RXB3RXB3+ RXB4RXB4+ 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 RXA0RXA0+ RXA1GND
C550 0.1uF R536 R537 22 22 UART_RXD UART_TXD
VCC_1 VSS_1 NC_9 NC_10 CLE
3 4 5
ZD507 ZD506 DUP_DVB
SUB_SDA
ZD504 DUP_DVB
C522 10pF R520 50V 100 READY C523 10pF 50V READY
C555 0.1uF
8 9
6 7 8 9 10 11 12 13
/PF_CE1 ALE PF_ALE WE /PF_WE WP /PF_WP NC_11 R556 3.3K R567 1K NC_12 NC_13 NC_14 NC_15
AR519 22
PCM_A[3]
IC504-*1 K9F1G08U0D-SCB0
+3.3V_ST
PCM_A[2] PCM_A[1] PCM_A[0]
SS NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 R/B RE CE NC_7 NC_8 VCC_1 VSS_1 NC_9 NC_10 CLE ALE WE WP NC_11 NC_12 NC_13 NC_14 NC_15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC_29 NC_28 NC_27 NC_26 I/O7 I/O6 I/O5 I/O4 NC_25 NC_24 NC_23 VCC_2 VSS_2 NC_22 NC_21 NC_20 I/O3 I/O2 I/O1 I/O0 NC_19 NC_18 NC_17 NC_16
C547 0.1uF 16V ZD505 DUP_DVB
14 15 16 17 18 19 20 21 22 23
ZD503-*1 5.6B DUP_AT
ZD505-*1 ZD504-*1 5.6B DUP_AT 5.6B DUP_AT
ZD506-*1 ZD502-*1 ZD501-*1 5.6B DUP_AT 5.6B DUP_AT 5.6B DUP_AT
24 25 26 HD 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
SERIAL FLASH 8MBit

+3.3V_ST +3.3V_ST +3.3V_ST
IC505 W25Q80BVSSIG
IC505-*1 MX25L8006EM2I-12G
MX CS#
R564 10K /SPI_CS
R569 4.7K READY
CS
VCC
C556 0.1uF
VCC
SO/SIO1
HOLD#
DO[IO1] SPI_SDO
HOLD[IO3]
FHD
WP#
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
SCLK
RXA1+ RXA2RXA2+ RXACKRXACK+ RXA3RXA3+ RXA4RXA4+
SI/SIO0
%WP[IO2] /FLASH_WP GND
CLK SPI_SCK R575 DI[IO0] 33 SPI_SDI
RXB0RXB0+ RXB1RXB1+ RXB2RXB2+

IC503-*1 R1EX24256BSAS0A
A0h
EEPROM 1MBit
+3.3V
RXBCKRXBCK+ RXB3RXB3+ RXB4VSS Renesas_IC503 A0 1 A1 8 VCC
C552 0.1uF
WP
A2
SCL
IC503 AT24C256C-SSHL-T
A0 VCC
RXB4+
SDA
A1
WP
ATMEL_IC503
A2 3 6 SCL
R573 22 I2C_SCL R574 22 I2C_SDA
P_SDA DISP_EN P_SCL PC_SER_DATA PC_SER_CLK
GND
SDA
81
HDCP EEPROM 8KBit

+3.3V
Addr:10101--
IC502 CAT24C08WI-GT3-H-RECV(TV)
R563 4.7K READY
NC_1 NC_2
1 2
8 7
VCC WP SCL SDA
R570 4.7K READY R571 22 READY R572 22 READY I2C_SCL I2C_SDA
A2 3 VSS 4
READY
6 5
* LCI: LVDS Connection Indicator
GP4_S7LR
Memory.LVDS,IR
2011-10-20 5 6
P_17V
P600 SMAW200-H18S1 L600-*1 MLB-201209-0120P-N2 DUP_DVB L600 120 DUP_AT C606 0.1uF 16V R609 100 ERROR_DET +5V_ST C608 10uF 10V C610 0.1uF 16V R1 R617 59K 1% C620 10uF 25V C621 0.1uF 50V R661 10K
+3.3V Multi
C642 0.01uF
P_17V
DCON_EN
Power Wafer
1.5V DDR / 1.24V Core
L606-*1 MLB-201209-0120P-N2 +5V
1 3 5 +3.3V_ST 7 9 R600 10K RL_ON 5V_ON 11 13 15 17
2 4 6 8 10 12 14 16 18 C607 0.1uF 16V AC_DET
V7V
FB2
SS2
EN2
1 THERMAL
+3.3V
VBST
C632 4.7uF 10V
DUP_AT
EN
VIN
CMP2
C634 10uF 16V
L606 CIS21J121 +5V
LOW_P
RLIM2
DCON_EN
IC603 TPS54327DDAR [EP]GND
C636
R639 3300pF 10K
R648 120K
R650 33K R634 56K
DUP_DVB
VFB
R670 4.7 READY C655 0.047uF 25V C609 3300pF READY
21
20
19
18
17
16
VREG5
SW
C628 4700pF 50V
L605 NR5040T2R2N 2.2uH C650 10uF 16V C629 10uF 16V C630 0.1uF 16V
15
R2
R656 47K 1% C656 22uF 16V C651 22uF 16V
19 R2 R619 17.4K 1% C624 1uF 10V SS 4 5 GND
V3V GND_1
22 23 24 25 26 27 28 1 2 3 4 5 6 7
14 13 12
BST2 VIN2 LX2_2 LX2_1 LX1_2 LX1_1 VIN1

C653 10uF 25V C654 10uF 25V L608 NR5040T3R3N L607 NR5040T3R3N
C626 3300pF 50V
PGOOD GND_2 GND_3
R657 43K 1%
C666 0.022uF 16V +1.5V_DDR
IC605 TPS65253RHDR
THERMAL 29
11 10 9 8
R1
Vout=0.765*(1+R1/R2)
GND_4 GND_5
+1.10V_VDDC C683 22uF 16V C657 22uF 16V R653 6.8K 1% R654 51K 1% R655 100K 1% C661 0.022uF 16V
3.3Vst
+5V_ST IC600 AP2121N-3.3TRE1 VIN 3 C600 10uF 10V C601 0.1uF 16V 1 GND 2 VOUT C604-*1 1uF 10V DUP_AT C604 1uF 6.3V DUP_DVB +3.3V_ST
2.5V Multi/2.5_TU
L613-*1 CB1608UA121T +3.3V IC601 TJ3940S-2.5V-3L VIN 3 1 GND 2 VOUT +2.5V DUP_DVB L613 120-ohm 2A DVB_T2 R612 1 C612 10uF 6.3V +2.5V_TU
1.25V_TU
+3.3V IC602 AP1117EG-13 FNIM IN OUT R620 1 FNIM C625 10uF 6.3V FNIM +1.25V_TU
3.3V_TU /1.8V_TU
+3.3V +3.3V_TU IC604 R2 AZ1117BH-ADJTRE1 220 100 R614 R613 5% 5% +1.8V_TU
R1 R2
RLIM1
ROSC
CMP1
BST1
FB1
SS1
EN1
[EP]GND
C652 0.047uF 25V
L604 120-ohm 2A DUP_AT
INPUT C627 10uF 6.3V
ADJ/GND
0.01uF
ADJ/GND C671 10uF 10V DVB_T2 C682 0.1uF 16V DVB_T2 C617 10uF 6.3V FNIM
OUTPUT
R630 3K 1% R631 390K 1% R621 1 C631 10uF 6.3V
R635 3300pF 10K
R647 100K
R2
R615 1 FNIM
R1
R618 240 FNIM
DUP_DVB
C645
C649
DCON_EN
R649 33K
L604-*1 CB1608UA121T
R1
R662 56K
C611 3300pF 50V READY R666 4.7 READY
Vout=1.25*(1+R2/R1)
Vout=1.25*(1+R2/R1)
Vout=0.8*(1+R1/R2)
+3.3V
500-ohm L601
Audio AMP
R628 10K READY R627 10K C B R636 0 READY
EMI GND
R608 0 R607 0
AMP_MUTE READY
Q600 MMBT3904(NXP) E READY R637 0 C643 0.1uF 50V
EAPD/OUT4B TWARN/OUT4A VDD_DIG_1 GND_DIG_1
19 20 21 22 23 24 25 26 27Close-by 28 29 30
18 17 16 15 14 13 12 11
OUT3A/FFX3A OUT3B/FFX3B CONFIG VDD GND_REG

39 R685 R686 39 C660 0.1uF 50V
R605 0 R606 0
EMI_GND1
AC_DET R625 2.2 22 R638
PWRDN VDD_PLL
R604 0 L609 10.0uH C672 0.22uF 50V C674 0.22uF 50V C678 1000pF 50V 4 R602 0
EMI_GND2
OUT1A GND1 VCC1 OUT1B OUT2A VCC2 GND2

P_17V
C664 1uF C665 C662 1uF C663
C633 0.1uF 16V R626 0 AUD_MASTER_CLK
C637 4700pF 50V
C647 680pF 50V
FILTER_PLL GND_PLL
25V C669 0.1uF 50V 330pF 50V
READY AUD_SCK READY AUD_LRCK READY AUD_LRCH READY AMP_RESET_N
C635 22pF 50V C639 22pF 50V C640 22pF 50V C644 22pF 50V
Close-by
10 9 8 7
L610 10.0uH
C675 0.22uF 50V
C679 1000pF 50V
SMAW250-H04R P601
R629 2K
R601 0 R603 0
EMI_GND3
22 R640 22 R641 22 R642 22 R643 22 R644
XTI BICKI LRCKI SDI RESET INT_LINE SDA SCL
C670 25V 330pF 50V 39 R687
L611 10.0uH C673 0.22uF 50V
2 C676 0.22uF 50V C677 0.22uF 50V C680 1000pF 50V C681 1000pF 50V
0.1uF 50V
R688 39
EMI_GND4 GND
Close-by
31 32 THERMAL 33 37 34 35 36 Close-by 6 5 4 3 2 1
L612 10.0uH C667 0.1uF 50V C668 68uF 35V
OUT2B VCC_REG VSS TEST_MODE SA GND_SUB

C659 0.1uF 50V
R623
2K AMP_SDA
R645 22 R646 22
R624
2K AMP_SCL
R633 10K C638 0.1uF 50V C687 330pF 50V C684 330pF 50V C685 330pF 50V C686 330pF 50V C646 0.1uF 50V
GND_DIG_2 VDD_DIG_2 [EP]GND
STA368BWG IC606
GP4_S7LR
Power,AMP
2011-04-01 6
AVDD_DDR0
AVDD_DDR0
AVDD_DDR0
AVDD_DDR0 R1227 +1.5V_DDR L1202 CIC21J501NE 1uF DUP_AT C1219 1uF DUP_AT C1238 AVDD_DDR0 C1218-*1 1uF DUP_DVB 1uF DUP_AT C1241 1uF DUP_AT C1219-*1 1uF DUP_DVB C1238-*1 1uF DUP_DVB C1241-*1 1uF DUP_DVB
R1201
R1204
R1224
1K 1%
1K 1%
OS 1K 1%
OS 1000pF
0.1uF
1000pF
OS 1000pF
0.1uF
1000pF
0.1uF
C1250 OS 1%
A-MVREFCA
0.1uF
A-MVREFDQ 1% R1205
B-MVREFCA
B-MVREFDQ C1248 OS 1K 1% R1225 C1247
OS 1K 1%
1%
R1228
R1202
C1249
C1201
C1202
C1204
C1203
1K
OS
1K
OS
1K
L1202-*1 CB2012PK501T
DUP_DVB
CLose to DDR3
CLose to Saturn7M IC
CLose to Saturn7M IC
CLose to DDR3
EAN61828901
C1251
C1218
DUP_AT 10uF
EAN61828901
IC1201 H5TQ1G63DFR-H9C
DDR_1333_HYNIX A-MVREFCA M8 VREFCA A0 A1 A-MVREFDQ R1203 240 1% B2 C1205 C1207 C1208 C1210 C1211 C1212 C1213 C1214 C1215 C1216 OS 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A1 A8 C1 C9 D2 E9 F1 H2 H9 J1 J9 L1 L9 A-MA14 T7 NC_1 NC_2 NC_3 NC_4 NC_6 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL7 D7 C3 C8 C2 A7 A2 B8 A3 DML DMU E3 F7 F2 F8 H3 H8 G2 H7 DQSU DQSU E7 D3 C7 B7 F3 G3 A-MDQSL A-MDQSLB A-MDQSU A-MDQSUB
N3 P7 P3 N2 P8 P2 R8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 M7 NC_5 M2 N8 M3 J7 BA0 BA1 BA2 VDDQ_1 CK CK CKE L2 K1 CS ODT RAS CAS WE T2 RESET NC_1 NC_2 NC_3 F3 G3 DQSL DQSL NC_4 NC_6 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 B1 VSSQ_1 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B9 D1 D8 E2 E8 F9 G1 G9 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 DQSU DQSU E7 D3 DML DMU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 T2 RESET A1 A8 C1 C9 D2 E9 F1 H2 H9 L2 K1 J3 K3 L3 CS ODT RAS CAS WE NC_1 NC_2 NC_3 NC_4 NC_6 J7 K7 K9 CK CK CKE VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 M2 N8 M3 BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 M7 NC_5 ZQ L8 VREFDQ H1 VREFCA
IC400 LGE2111B
IC1202 H5TQ1G63DFR-H9C
DDR_1333_HYNIX N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 NC_5 B-MBA0 OS B-MBA1 56 R1237 1% B-MBA2 M2 N8 M3 J7 K7 B-MCKE K9 L2 B-MODT AVDD_DDR0 R1232 10K OS B-MDQSL B-MDQSLB B-MDQSL B-MDQSU B-MDQSUB B-MDQSU B-MDML B-MDMU B-MDML B-MDQL0 B-MDQL1 B-MDQL2 B-MDQL3 B-MDQL4 B-MDQL5 B-MDQL6 B-MDQL7 B-MDQU0 B-MDQU1 B-MDQU2 B-MDQU3 B-MDQU4 B-MDQU5 B-MDQU6 B-MDQU7 B-MDQU0 B-MDQU1 B-MDQU2 B-MDQU3 B-MDQU4 B-MDQU5 B-MDQU6 B-MDQU7 B-MDQL0 B-MDQL1 B-MDQL2 B-MDQL3 B-MDQL4 B-MDQL5 B-MDQL6 B-MDQL7 B-MDMU B-MDQSUB B-MDQSLB F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 NC_5 M2 N8 M3 J7 K7 K9 L2 K1 J3 K3 L3 T2 RESET CS ODT RAS CAS WE NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 E3 F7 F2 F8 H3 H8 G2 H7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 E7 D3 DML DMU NC_4 NC_6 CK CK CKE BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 F3 G3 C7 B7 DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 T2 RESET A1 A8 C1 C9 D2 E9 F1 H2 H9 L2 K1 J3 K3 L3 CS ODT RAS CAS WE NC_1 NC_2 NC_3 NC_4 NC_6 J7 K7 K9 CK CK CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 M2 N8 M3 BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 M7 NC_5 ZQ L8 VREFDQ H1 VREFCA SS_1G_1333 SS_2G_1333
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 NC_5 M2 BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 CS ODT RAS CAS WE T2 RESET CK CK CKE L2 K1 J3 K3 L3 J7 K7 K9 N8 M3
A-MA0 A-MA1
Hynix_1G_1600
A_MA0 A_MA1
IC1201-*1 H5TQ1G63DFR-PBC
N3 P7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 M7 A15 M2 N8 M3 J7 BA0 BA1 BA2 VDDQ_1 CK CK CKE L2 K1 CS ODT RAS CAS WE T2 RESET NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 D7 VSSQ_1 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL NC_4 NC_6 J3 K3 L3 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8 VREFDQ H1 VREFCA P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M8
F9 E10 G9 C14 F11 A14 F10 C15 D11 C16 G13 E11 F12 B15 D10 B12 G11 B13 B17 C17 F13 A11 B11 A12 E9 G8 A_DDR3_ODT A_DDR3_RASZ A_DDR3_CASZ A_DDR3_WEZ A_DDR3_MCLK A_DDR3_BA0 A_DDR3_BA1 A_DDR3_BA2 A_DDR3_A0 A_DDR3_A1 A_DDR3_A2 A_DDR3_A3 A_DDR3_A4 A_DDR3_A5 A_DDR3_A6 A_DDR3_A7 A_DDR3_A8 A_DDR3_A9 A_DDR3_A10 A_DDR3_A11 A_DDR3_A12 A_DDR3_A13 A_DDR3_A14
MAIN IC E22
B_DDR3_A0 B_DDR3_A1 B_DDR3_A2 B_DDR3_A3 B_DDR3_A4 B_DDR3_A5 B_DDR3_A6 B_DDR3_A7 B_DDR3_A8 B_DDR3_A9 B_DDR3_A10 B_DDR3_A11 B_DDR3_A12 B_DDR3_A13 B_DDR3_A14 D25 B_DDR3_BA0 B_DDR3_BA1 B_DDR3_BA2 H23 B_DDR3_MCLK B_DDR3_MCLKZ B_DDR3_MCLKE C24 B_DDR3_ODT B_DDR3_RASZ B_DDR3_CASZ B_DDR3_WEZ E21 A_DDR3_RESET B_DDR3_RESET P25 A_DDR3_DQSL A_DDR3_DQSBL B_DDR3_DQSL B_DDR3_DQSBL N24 A_DDR3_DQSU A_DDR3_DQSBU B_DDR3_DQSU B_DDR3_DQSBU L23 A_DDR3_DQML A_DDR3_DQMU B_DDR3_DQML B_DDR3_DQMU P23 A_DDR3_DQL0 A_DDR3_DQL1 A_DDR3_DQL2 A_DDR3_DQL3 A_DDR3_DQL4 A_DDR3_DQL5 A_DDR3_DQL6 A_DDR3_DQL7 B_DDR3_DQL0 B_DDR3_DQL1 B_DDR3_DQL2 B_DDR3_DQL3 B_DDR3_DQL4 B_DDR3_DQL5 B_DDR3_DQL6 B_DDR3_DQL7 N21 A_DDR3_DQU0 A_DDR3_DQU1 A_DDR3_DQU2 A_DDR3_DQU3 A_DDR3_DQU4 A_DDR3_DQU5 A_DDR3_DQU6 A_DDR3_DQU7 B_DDR3_DQU0 B_DDR3_DQU1 B_DDR3_DQU2 B_DDR3_DQU3 B_DDR3_DQU4 B_DDR3_DQU5 B_DDR3_DQU6 B_DDR3_DQU7 P22 L22 R21 P20 R22 M22 N22 L25 R24 K23 T25 J23 T24 K24 R20 M23 N23 B25 D24 F22 H24 M20 A_DDR3_MCLKZ A_DDR3_MCLKE K22 E25 G21 F20 E24 K20 F24 J21 F23 H22 G23 L21 G22 J22 G25 H20
B-MA0 B_MA0 B_MA1 B_MA2 B_MA3 B_MA4 B_MA5 B_MA6 B_MA7 B_MA8 B_MA9 B_MA10 B_MA11 B_MA12 B_MA13 B_MA14 B_MBA0 B_MBA1 B_MBA2 B-MCK B-MCKB B_MCKE B-MCKB B_MODT B_MRASB B_MCASB B_MWEB B_MRESETB B-MRASB B-MCASB B-MWEB B-MRESETB B-MA1 B-MA2 B-MA3 B-MA4 B-MA5 B-MA6 B-MA7 B-MA8 B-MA9 B-MA10 B-MA11 B-MA12 B-MA13
M8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 BA0 BA1 BA2 VDDQ_1 CK CK CKE CS ODT RAS CAS WE VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 NC_1 RESET NC_2 NC_3 NC_4 NC_6 J9 L1 L9 T7 A1 A8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ 240 1% L8 VREFDQ OS R1226 H1 VREFCA
B-MVREFCA
H1 VREFDQ
A2 A3 A4 A5 ZQ A6 A7 A8 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 A9 A10/AP A11 A12/BC A13
A-MA2 A-MA3 A-MA4 A-MA5 A-MA6 A-MA7 A-MA8 A-MA9 A-MA10 A-MA11 A-MA12 A-MA13
A_MA2 A_MA3 A_MA4 A_MA5 A_MA6 A_MA7 A_MA8 A_MA9 A_MA10 A_MA11 A_MA12 A_MA13 A_MA14 A_MBA0
B-MVREFDQ
Hynix_1G_1600
IC1202-*1 H5TQ1G63DFR-PBC
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 M7 A15 M2 N8 M3 BA0 BA1 BA2 J7 K7 K9 CK CK CKE VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 CS ODT RAS CAS WE T2 RESET NC_1 NC_2 NC_3 F3 NC_4 DQSL DQSL C7 B7 DQSU DQSU VSS_1 VSS_2 VSS_3 DML DMU E3 F7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 D7 C3 C8 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 NC_6 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8 VREFDQ H1 VREFCA M8
L8
AVDD_DDR0
K7 K9
AVDD_DDR0 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
L7 R7 N7 T3
D9 G7 K2 K8 N1 N9 R1 R9
C1227 OS C1228 OS C1229 OS C1230 OS C1231 OS C1232 OS C1233 OS C1234 OS C1235 OS C1236
L2 K1 J3 K3 L3
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
E3 F7 F2 F8 H3 H8 G2 H7
G3
E7 D3
C3 C8 C2 A7 A2 B8 A3
F2 F8 H3 H8 G2 H7
C2 A7 A2 B8 A3
R1235 56
A-MBA0 A-MBA1 A-MBA2
A-MCK
SS_1G_1600
1%
IC1201-*2 K4B1G1646G-BCK0
N3 M8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 M7 NC_5 M2 N8 BA0 BA1 BA2 J7 K7 K9 CK CK CKE L2 K1 J3 K3 L3 T2 RESET CS ODT RAS CAS WE NC_1 NC_2 NC_3 NC_4 DQSL DQSL C7 B7 DQSU DQSU E7 D3 E3 DML DMU DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 D7 C3 C8 C2 A7 A2 B8 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 NC_6 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8 VREFDQ H1 VREFCA
A_MBA1 A_MBA2 A-MCK A-MCKB A_MCKE A_MODT A_MRASB A_MCASB A_MWEB A_MRESETB A-MDQSL A-MDQSLB A-MDQSU A-MDQSUB
B-MCK OS C1240 0.01uF 50V
SS_1G_1600
C1209 0.01uF 50V 1%
P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3
R1236 56
IC1202-*2 K4B1G1646G-BCK0
N3 P7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 M7 NC_5 M2 N8 M3 J7 BA0 BA1 BA2 VDDQ_1 CK CK CKE L2 K1 CS ODT RAS CAS WE T2 RESET NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 NC_4 NC_6 J3 K3 L3 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8 VREFDQ H1 VREFCA P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M8
56 R1238
C1 C9 D2 E9 F1 H2 H9
A-MCKE A-MCKB A-MODT A-MRASB AVDD_DDR0 A-MCASB R1231 A-MWEB 10K A-MRESETB
M3
OS 1%
K1 J3 K3 L3 T2
K7 K9
F3 G3
F7 F2 F8 H3 H8 G2 H7
A3
B22 C22 A21 C21 B20 D17 B23 B19 A23 C19 B24 C18 A24 A18 D15 F17 F14 E16 D14 D16 E14 F16
B-MA14
SS_1G_1333
SS_2G_1333
IC1201-*3 K4B1G1646G-BCH9
M8 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
IC1201-*4 K4B2G1646C
M8 VREFCA
A-MDML
H1
VREFDQ
A-MDMU A-MDQL0 A-MDQL1 A-MDQL2 A-MDQL3 A-MDQL4 A-MDQL5 A-MDQL6 A-MDQL7 A-MDQU0 A-MDQU1 A-MDQU2 A-MDQU3 A-MDQU4 A-MDQU5 A-MDQU6 A-MDQU7
IC1202-*3 K4B1G1646G-BCH9
M8
IC1202-*4 K4B2G1646C
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8 VREFDQ H1 VREFCA M8
L8 ZQ
A-MDML A-MDMU A-MDQL0 A-MDQL1 A-MDQL2 A-MDQL3 A-MDQL4 A-MDQL5 A-MDQL6 A-MDQL7 A-MDQU0 A-MDQU1 A-MDQU2 A-MDQU3 A-MDQU4 A-MDQU5 A-MDQU6 A-MDQU7
R2 T8 R3 L7 R7 N7 T3
B2 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 D9 G7 K2 K8 N1 N9 R1 R9
A10/AP A11 A12/BC A13
K7 K9
J3 K3 L3
C7 B7
E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3
AR1224
22
AR1217
22
AR1211
22
AR1206
22
A-MA12 A-MBA1
A_MA12 A_MBA1
A-MA13 A-MA9
A_MA13 A_MA9
B-MA12 B-MBA1
B_MA12 B_MBA1
B-MA13 B-MA9
B_MA13 B_MA9
AR1223
22
AR1216
22
AR1207
22
AR1210
22
A-MA10 A-MCKE
A_MA10 A_MCKE
A-MA0 A-MWEB
A_MA0 A_MWEB
B-MA10 B-MCKE
B_MA10 B_MCKE
B-MA0 B-MWEB
B_MA0 B_MWEB
AR1222
22
AR1214
22
AR1203
22
AR1205
22
A-MA6 A-MA4
A_MA6 A_MA4
A-MA5 A-MA7
A_MA5 A_MA7
B-MA6 B-MA4
B_MA6 B_MA4
B-MA5 B-MA7
B_MA5 B_MA7
AR1221
22
AR1218
22
AR1212
22
AR1209
22
A-MA11 A-MA8
A_MA11 A_MA8
A-MRESETB A-MA2
A_MRESETB A_MA2
B-MA11 B-MA8
B_MA11 B_MA8
B-MRESETB B-MA2
B_MRESETB B_MA2
AR1220
22
AR1213
22
AR1202
22
AR1225
22
A-MRASB A-MODT
A_MRASB A_MODT
A-MCASB A-MBA0
A_MCASB A_MBA0
B-MRASB B-MODT
B_MRASB B_MODT
B-MCASB B-MBA0
B_MCASB B_MBA0
AR1219
22
AR1215
22
AR1204
22
AR1208
22
A-MA1 A-MA14
A_MA1 A_MA14
A-MBA2 A-MA3
A_MBA2 A_MA3
B-MA1 B-MA14
B_MA1 B_MA14
B-MBA2 B-MA3
B_MBA2 B_MA3
GP4L_S7LR2 DDR_256
2011/06/03 12
GP2R, LM1 Training Manual
Table of contents
1. PCB layout. 2. GP2R vs LM1 3. GP2R. (Block, Power, I2C) 4. LM1. (Block, Power, I2C) 5. LM1 SOC Power sequence. 6. Memory test. 7. Pen touch overview.
1. PCB Layout.
GP2R (206 x 183)
LM1 (206 x 141.5)
LM1 use internal EDID&HDCP. (LM1 is Removing the EEPROM for EDID&HDCP) LM1 is optimizing Power block. (LM1 is reducing DC/DC, LDO, power application)
2. GP2R vs GP4 LM1.

Difference PDP Module Tool PCB VSC Main IC Jack Layout Sub Assy PSU SW JIG Power Wafer Stand by 3.5V 12V_secondary
GP2R 50PZ550
R3(FHD) PZ Tool 206x183 S7R
LM1 50PA6500
R4(FHD) PA Tool 206x141.5 S7LR New module. 50R4 Initial model. 12 years New tool.
Changes
change PCB Size. (smaller than GP2R.) Internal sub-Micom .(PM block)
Slim Depth PZ Tool 50R3 XP5 Bd GP2R GP2R . 18P O X
Slim Depth PA Tool 50R4 UP1 Bd LM1 LM1 . 18P O X
Same. GP2R 15pin, LM1 8pin Reduce power on time. PDP only code. Support DFT JIG. Develop new WAFER and CABLE. (12 years) Stand by 0.3W Stand by 3.5V . Not use 12V.
IR Wafer
15P
8P
LM1 not support 3D.
USB Memory
O DDR3
O DDR3
SIDE USB. DDR3 1Gbit . 2ea LGE Internal Use Only
3. GP2R Power measure Summary

Power Line +5V_ST +5V_ST_EN +3.3V_AVDD +2.5V_AVDD +1.5V_DDR_IN +1.26V_VDDC +3.3V_ST +17V +5V_TU +5V +3.3V_TU +1.2V_TU Voltage Spec [V] 4.845~5.355 4.845~5.355 3.14~3.6 2.38~2.62 1.425~1.575 1.2~1.32 3.234~3.366 16.15~17.85 4.75~5.25 4.845~5.355 3.15~3.46 1.20~1.32 Voltage [V] 5.01 5.00 3.31 2.53 1.57 1.27 3.30 17.03 4.99 5.03 3.26 1.27 None None None 0.5 1.5V +/-5% 0.5 Ripple spec [Vpp] Ripple [mV] 86 17 15 20 20 30 19 1.09A 20 57 26 21 Current [A] 0.009 0.710 0.285 0.200 0.310 0.770 0.024 1.420 0.170 2.600 0.320 0.300 Remark
3-1. GP2R Power Block Diagram

5Vst
L603 MAX 3A +5V_ST
C619 100u 16V C627 0.1u 16V C219 0.1u 16V
IC205 AT24C02BN RGB EDID
C654 22u 16V
C655 0.01u 25V
+5V_ST_EN Q600 C657 RTR030P02 C656

100u 16V 0.1u 16V
C600 0.1u 16V
IC600 AZ1085S 3.3V
C607 22u 6.3V
C608 0.1u 16V
L602 2A
+3.3V_AVDD
C615 0.1u 16V
2A/3ea
10u 2ea 0.1u 13ea
S7_3.3V_AVDD
NAND Flash/HDCP/EEPROM
IC604 TJ3964 C616

22u 6.3V
C623 0.1u 16V
+2.5V_AVDD 2A 2A/2ea
10u 1ea 0.1u 4ea
2.5V_AVDD
C609 10u 16V
C611 0.1u 16V
IC602 TPA54319
+1.5V_DDR_IN
C637 10u 10V C647 10u 10V C650 0.1u 16V 10u 2ea 0.1u 32ea
DDR
2A/2ea
10u 4ea
0.1u 10ea
S7 AVDD_DDR
C610 10u 16V
C612 0.1u 16V
IC603 TPA54319
+1.26V_VDDC
C651 10u 10V C652 10u 10V C653 0.1u 16V
2A/2ea
10u 2ea 10u 1ea
0.1u 2ea 0.1u 8ea
DVDD VDDC IC203 MAX3232CDR
C601 0.1u 16V
IC601 AP2121N 300mA
+3.3V_ST
C605 100u 16V C606 0.1u 16V C552 0.1u 16V
S7_MPLL IC503(S-FLASH) MX25L8005M2I-15G SUB ASSY
+17V
17V
C634 4.7u 50V
C635 4.7u 50V
C636 0.01u 50V
IC605 TPA54319
+5V_TU
C641 10u 16V C642 10u 16V
L610 2A
C304 22u 10V
C307 0.1u 16V
5V_TU
C341 68u 35V
C344 68u 35V
C340 0.1u 50V
IC303 Audio AMP STA338BWG13TR
3-2. GP2R Power Block Diagram

+5V
L604 3A L605 3A +5V
C621 100u 16V C624 100u 16V C628 0.1u 16V C631 22u 16V
L101 2A
C103 22u 10V
C104 0.1u 16V
+5V_CI_ON IC205 AT24C02 EDID USB
IC206 AP2191
C223 100u 16V
C222 0.1u 16V C235 0.1u 16V
SPDIF
L708 2A
C725 10u 16V
C728 0.1u 16V
IC704 TPS54319
C746 10u 10V
C747 10u 10V
C748 0.1u 16V
L709 2A
L710 2A
0.1u 16V 13ea
1.0V_LTX 1.0V
C750 0.1u 16V
IC706 AZ1085S
C753 22u 16V
C754 0.1u 16V
L708 2A
+3.3V_3D
C751 0.1u 16V
IC707 AZ1117ST C752 L705 2A L706 2A L707 2A

22u 16V
C755 0.1u 16V C789 10u 16V C753 10u 16V C805 100p 50V C754 100p 50V
R834 01/10W
C735 0.1u 16V 0.1u 16V 33ea
IC702 MX25L4005
1.8V
0.1u 16V 0.1u 16V 0.1u 16V
7ea
3.3V_LTX 3.3V_VDD 3.3V_PLL
7ea
3ea
C658 0.1u 16V
IC606 AZ1085S
C659 22u 6.3V
C660 0.1u 16V
L601 2A
C661 0.1u 16V
C126 0.1u 16V
L100 2A
C128 0.1u 16V C120 0.1u 16V C332 0.1u 50V
+3.3V_CI
IC101 74LCX244
IC303 Audio AMP
+3.3V_TU L300 2A
C302 0.1u 16V C309 22u 10V
+3.3V_TU
C313 0.1u 16V
IC301 AZ1117H
+1.2V_TU
C325 22u 10V C322 0.1u 16V C300 0.1u 16V
+1.2V_TU
3-3. LDO/DC-DC Start up

IC600 (+3.3V_AVDD/AZ1085S) IC602 (+1.5V_DDR_IN/TPS54319)
Vin Vout Vin Ve n Vo Io
IC604(+2.5V_AVDD/TJ3964S)
IC603 (+1.26V_VDDC/TPS54319)
Vin Vout Ve n Vo Io
Vin
3-4. LDO/DC-DC Start up

IC606 (+3.3V/AZ1085S)
Vout
Vin
IC605 (+5V_TU/TPS54231)
Vin Ve n Vo Io
3-5. GP2R I2C MAP

DDC_SCL/SDA_1~3
1 (R208,209) 2 (R233,234) 10K 3 (R256,257) DDCR_CK/GPIO72 DDCR_DA/GPIO71
+5V_HD MI
(N22)<I2C-SCL> (M22)<I2C-SDA>
2.2K (R480,R482) EEPROM EEPROM 0xA0 0xA0 Ch2 Ch2 HDCP HDCP EEPROM EEPROM 0xA8 0xA8 Ch2 Ch2
<EEPROM-SCL> +3.3 <EEPROM-SDA> V
HDMI1,2,3 HDMI1,2,3 0xA0 0xA0 Ch10,12,11 Ch10,12,11 TGPIO2/I2C_CLK TGPIO3/I2C_SDA
(R3) <TU_SCL> (T3) <TU_SDA>
4.7K (R319,R326)
TUNER TUNER TDTJ-S001D TDTJ-S001D 0x10/C2 0x10/C2 Ch6 Ch6
<SCL1> +3.3V_T <SDA1>
SATURN7R SATURN7R TGPIO0/UPGAIN TGPIO1/DNGAIN
+3.3V_S T
SUB_SCL SUB_SDA
I2S_IN_WS/GPIO174 (F15) I2S_IN_BCK/GPIO175 (F14)
(U1) (U2)
4.7K (R635,R633)
G_EYE G_EYE 0x20 0x20 Ch7 Ch7 I2S_IN_SD/GPIO176 SPDIF_IN/GPIO177
AMP AMP STA338BWG13TR STA338BWG13TR 0x38 0x38 Ch5 Ch5
2K (R360,R359)
<AMP_SCL> <AMP_SDA>
+3.3 V
TOUCH TOUCH 0x52 0x52 Ch7 Ch7
+3.3 (F13)<P_SCL> <MODULE_SCL/3DF_SCL> 4.7K (R780,R781) <MODULE_SDA/3DF_SDA> (G14)<P_SDA> 3.3K (R1412,R1411) V_A VDD LG8300 MODULE LG8300 MODULE
0x74 0x74 Ch4 Ch4 0x1C 0x1C Ch4 Ch4
DDCA_CK/UART0_RX DDCA_DA/UART0_TX
(B5) <RGB_DDC_SCL> (A5) <RGB_DDC_SDA>
10K (R237,R247)
EEPROM EEPROM RGB RGB 0xA0 0xA0 Ch8 Ch8 ISP ISP
+5.0 <DDC_SCL/UART_RX> <DDC_SDA/UART_TX> V_ST
4. LM1 Power Block optimization.

1. GP2R vs LM1 Power Block.
Amp 17V
17V
Amp
1.8V Tuner LDO (1A) 1.25V _TU LDO (1A) 2.5V LDO (1A)
5V Tuner TPS54231 2A
AP2191 USB 3.3V Multi LDO (3A) 1.25V Tuner LDO 1.8V 3D DDR LDO 3.3V AVDD LDO (3A) 2.5V LDO
3.3V Multi TPS54327(3A)
5.1V
5.1V
3.3V 3D LDO (3A)
AP2191 USB
1V 3D core AOZ1073 3A
FET SW
St 5V 3.3V Standby LDO(AP2121)
1.5V DDR AOZ1073 3A 1.26V Core AOZ1073 3A

3.5V St.
1.24V core 1.5V DDR TPS65253(3A)
3.3V ST AP2121
DC/DC : 4 LDO : 7
DC/DC : 2
GP2R Power Block
LDO : 4
LM1 Power Block
4-1. P_17V
Spec) 850mV 16mVrms 17V to 3.3V 283mVpp
C620 10uF 25V 3216 C621 0.1uF 50V 2012 TPS54327 (3A, $0.14) L605 2.2uH 3.5A 4.9x4.9 C629/50 10uF 16V 6.3V 3216 1608 0.00586 change
Spec) 165mV 8.66mVrms 37.5mVpp

C630 0.1uF 16V 1005
+3.3V L101 120 Ohm 2A 1608 C137 0.1uF 16V 1005
+3.3V_CI
Buffer for CI_ADDR [0:7]
OP-Amp for SC
1 7 V
C667 0.1uF 50V 1608
C668 68uF 35V 8PI/6.3H
Audio AMP
L604 120 Ohm 2A 1608 C627 10uF 6.3V 1608
Spec) 165mV 13.5mVrms 158mVpp
+3.3V_TU
3.3V to 1.8V AP1117E18G (850mW)

C631 10uF 6.3V 1608 C618 0.1uF 16V 1005
C693 10uF 25V 3225
C694 0.01uF 50V 1005
17V to 12V TPS54231D (2A)
Tuner
C614 0.1uF C643 0.1uF C711 10uF 16V 3216 C712 0.1uF 50V 1608 C638 C646 0.1uF 50V 1608 16V
C615 10uF 16V 6.3V 3216 1608 change
LNB
50V 1608
Audio AMP
1005
4-2. P_17V
+3.3V
3.3V to 2.5V TJ3940S-2.5V (714mW)
+2.5V
x3 120 Ohm C612 10uF 6.3V 1608 2A 1608 C605 10uF 6.3V 1608
* Y17

C1417 10uF 10V 6.3V 2012 1608 change x6 0.1uF 16V 1005
L613
LM1
120 Ohm 2A 1608 C682 0.1uF 16V 1005 C671 10uF 10V 6.3V 2012 1608 change
Tuner
DVB_T2
1 7 V
* W18/9
L408/9 120 Ohm 2A 1608 x5 0.1uF 16V 1005

X4 10uF 10V 6.3V 2012 1608 change
x2 0.1uF 16V 1005
C554 10uF 10V 6.3V 2012 1608 change
Nand Flash
+1.25V_TU
3.3V to 1.25V AP1117EG-13 (???mW)
C625 10uF 6.3V 1608
LM1 HDCP
x3 0.1uF 16V 1005
C427 10uF 10V 6.3V 2012 1608 0.00636 change

* L7
C552 0.1uF 16V 1005
NVR
C684 0.1uF 16V 1005 C685 10uF 6.3V 1608
Tuner
NOT_HNIM
4-3. P_5V
L600 120 Ohm 5A 2012 C608 10uF 10V 16V 2012 3216 0.0005 change
Spec) 250mV 7mVrms 70mVpp

C610 0.1uF 16V 1005
+5V
USB OCD
C219 0.1uF 16V 1005
SPDIF
5 V
+5V_CI_ON
L100 120 Ohm 2A 1608 C104 0.1uF 16V 1005 C100 22uF 10V 16V 3216 3225 0.017 change
MOFET Switch
Spec) 250mV 31mVrms 135.4mVpp

C101 0.1uF 16V 1005
PCMCI
4-4. P_5V
+5V
L606 120 Ohm 5A 2012 C653/4 10uF 25V 3225
+1.24V_VDDC
L405
* M14
???mVrms
C683/57 22uF 16V 3225
120 Ohm 2A 1608 x2 0.1uF 16V 1005
Spec) 55mV 9.4mVrms 48.3mVpp C1413 ???mVrms

10uF 10V 6.3V 2012 1608 change x3 10uF 10V 6.3V 2012 1608 change L412 120 Ohm
* R15
LM1
5V to 1.1V TPS65253RH D (adjustable) $0.25
x3 0.1uF 16V 1005
5 V
C651/56 22uF 16V 3225
+1.5V_DDR_IN
* M17

x4 10uF 10V 6.3V 2012 1608 change x4 0.1uF 16V 1005 C468 1uF 10V 1005
C467 1000pF 50V 1005
2A 1608
LM1 MIU0/1
VCC_1.5V_DDR
L500 500 Ohm 3A ??? C544 10uF 10V 6.3V 2012 1608 change C545 0.1uF 16V 1005
* IC501 / G7

x2 1000pF 50V 1005 x2 0.1uF 16V 1005
DDR1/2
4-5. STBY
Spec) 250mV 23mVrms 150mVpp
+3.3V_ST
RS232C
C600 10uF 10V 16V 2012 3216 0.0005 change
C601 0.1uF 16V 1005
5V to 3.3V AP2121N-3.3 (0.3A)
C604 1uF 6.3V 1005
C228 0.1uF 16V 1005
L406 120 Ohm 2A 1608 C469 0.1uF 16V 1005
LM1
S T B Y
C556 0.1uF 16V 1005
Serial Flash
C547 0.1uF 16V 1005
SUB Assy
4-6. GP4 LM1 I2C MAP

+3.3V_TU R3082.2K R309 2.2K
EAX64337201_0
I2C_SCKM1/GPIO75 I2C_SDAM1/GPIO76
IC400
AE6 AD6
TU_SCL TU_SDA
TU300 TDSS-G201D
+3.3V
GPIO49 GPIO50
AB5 AB3
AMP_SCL AMP_SDA
R624 2K
R623 2K
IC300 STA368BWG
+3.3V_AVDD
I2S_IN_WS/GPIO149 SPDIF_IN/GPIO152
D9 D7
P_SCL P_SDA
R468 3.3K
R466 3.3K
SCL_3.3V_MOD P500 SDA_3.3V_MOD LVDS
+3.3V_ST
I2S_IN_SD/GPIO151 I2S_IN_BCK/GPIO150
D8 C8
SUB_SCL SUB_SDA
R539 4.7K
R538 4.7K
P501 KEY/IR PIN8

+3.3V_AVDD
I2C_SCKM2/DDCR_CK/GPIO72 I2C_SDAM2/DDCR_DA/GPIO71
P23 P24
I2C_SCL I2C_SDA
R469 2.2K
R468 2.2K
IC503 EEPROM IC502 HDCP (OTP)

5. GP4 LM1 SOC Power Sequence Procedure

Hot Point
288ms / [Spec] before all pwr input raise SOC_RESET +3.3V_AVDD Multi_PWR 0ms +1.10V_VDDC +1.5V_DDR_IN
SOC_RESET
Threshold
+3.3V_AVDD
+1.10V_VDDC
+1.5V_DDR_IN
SOC_RESET timing and Power sequence are ok.
5. GP4 LM1 SOC Power Sequence Procedure

Solution
Value of Capacitor and resister. Cap 22uF.

0CK226DC67A 22uF 6.3V $0.0117
Resister 100.
+3.3V_AVDD
1
SOC_RESET
Threshold
6. Memory margin test. (DDR)

STEP1. Setting like below. (Red box) STEP2. Call direct MIU Auto BIST function from Menu.
6. Memory margin test. (DDR)

STEP3. Setting like below and push Start DQS. (Red box) STEP4. below picture is test result. Red box is timing margin.
Normal operating board has timing margin 7~9. If timing margin under 7 ,its some problem DDR or Main MIU.
7. Pen touch overview. (Installation_Pentouch Program.)
7. Pen touch overview. (Installation_Pentouch Program.)
7-1. Pen touch overview. (Check the installation status.)

1
Currently installed programs Check the LG Pentouch Multi-touch Driver or Pentouch TV
Check USB Dongle Driver in Device Manager -LG Pentouch Multi-touch Driver(MultiTouch) -LG Pentouch Multi-touch Driver(BUS) -LG Pentouch Multi-touch Driver(Dongle) the Dongle Driver should be displayed when connected USB Dongle
7-2. Pen touch overview. (Pairing between Touch Pen and Dongle)
7-3. Pen touch overview. (Pairing between Touch Pen and Dongle)
7-4. Pen touch overview. (Using the Pentouch Function)

Image shown may differ from your monitor. You need the following items to use the Pentouch functions: 1 Enter the Pentouch mode on your monitor. - Press TOUCH button on the remote control or MENU to access the main menus. Then choose Pentouch function. 2 Select the correct computer input connection to enter the Pentouch mode.
3 Use the touch pen or the mouse to start the Pentouch program. Pressing the /Home button on the touch pen works in the same way as right-clicking the mouse.
Viewing the Screen Settings

I mage shown may differ from your monitor. If you press the OK button on the remote control, the screen shown below appears to indicate that the screen settings have been updated successfully.
The text "Pentouch" should be displayed to indicate that the Pentouch mode is activated. If not, restart the Pentouch mode. "1365x768 " should be displayed to indicate that the resolution has been set successfully. If not, set the monitor resolution again.(See p.38)
7-5. Pen touch overview. (PDP Pen Touch Concept)
Principle 1. The Pen using PDP Cells light energy Step 1. The pen detect the PDP Cells light Step 2. The pen convert detected light to voltage Step 3. The pen calculate X,Y position Step 4. The pen transfer the X,Y data through RF
Principle 2. The position data processed Pentouch TV Application looks like PC mouse. Step 1. USB Dongle receive the position data. Step 2. USB Dongle Driver parsing the positon Step 3. Pentouch TV application drawing and click function. Step 4. The result was displayed PDP TV through HDMI or RGB cable.
Pen
The photo sensor in the pen detect the light
RF Wireless communication (2.4GHz)
USB Dongle
It can use Multi-Touch function by support 2 pens.
Plasma Display
Pentouch TV Application - It was developed by LG. - It can be using internet for web surfing , Flash Game etc.
The HDMI or RGB signal is PCs output that configuration set by clone mode.

Training LG 50pa4500-Dm 50pa4510-Dj CH - Pb23a

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Internal Use Only

North/Latin America Europe/Africa Asia/Oceania http://aic.lgservice.com http://eic.lgservice.com http://biz.lgservice.com

PLASMA TV SERVICE MANUAL

MODEL : 50PA4500 MODEL : 50PA4510

P/NO : MFL67483007 (1205-REV00)

LGE Internal Use Only

Leakage Current Hot Check (See below Figure)

Leakage Current Hot Check circuit

Before returning the receiver to the customer,

Leakage Current Cold Check(Antenna Cold Check)

To Instrument's exposed METALLIC PARTS

Good Earth Ground such as WATER PIPE, CONDUIT etc.

LGE Internal Use Only

2. Requirement for Test

4. Model General Specification

1) VHF : 02~13 2) UHF : 14~69 3) DTV : 14~69 (UHF) 4) CATV : 02~125

Input Voltage Market Screen Size

Aspect Ratio Tuning System Module

Operating Environment Storage Environment

1) Temp : 0 deg ~ 40 deg 2) Humidity : ~ 80 % 1) Temp : -20 deg ~ 60 deg 2) Humidity : ~ 85 %

LGE Internal Use Only

4. PCB Assembly Adjustment

3.1. PCB Assembly adjustment

3.2. Set Assembly Adjustment

LGE Internal Use Only

->  PB23A : USE INTERNAL ADC(LM1) : using internal pattern.

5.1.  Auto Adjust Component 480i/1080p RGB 1080p

* caution : Set Volume 0 after adjustment

5.2. Use Internal ADC(S7R)

LGE Internal Use Only

 It only needs to PCM EDID D/L for North America Product.

LGE Internal Use Only

Using HDMI input

LGE Internal Use Only

LGE Internal Use Only

6. GND and ESD Testing

6.1. Prepare GND and ESD Testing.

Check the connection between set and power cord

6.2. Operate GND and ESD auto-test.

6.3. Check Items.

- Brightness spec. Brightness uniformity -20

6.4. POWER PCB Assy Voltage adjustment

5.3. Test of RS-232C control.

5.4. Selection of Country option.

(fig.1) PCB Assy Voltage adjustment

6.4.3. Adjustment method

7. Default Service option.

Select download file (epk file)

7.2. White balance. Value.

7.3. Temperature Threshold

8. USB DOWNLOAD(*.epk file download)

LGE Internal Use Only

LGE Internal Use Only

E L103 120-ohm EU L103-*1 CB1608UA121T DUP_DVB

PDP GP4 S7LR3 EAX64696601

E Q104 MMBT3904(NXP) EU R143 180 EU

C116 10uF 16V EU

DTV/MNT_VOUT E DUP_DVB 2SC3052 Q106-*1 C E B DUP_DVB 2SC3052 Q105-*1 C

E EU MMBT3904(NXP) Q106 EU C 12K R160

EU 1K R158 B SC_RE1 E EU 1K R157 SC_RE2

EU MMBT3904(NXP) B Q105 C EU 12K R159

E DUP_DVB 2SC3052 Q107-*1 C

-> PB23A : USE INTERNAL ADC(LM1) : using internal pattern.

5.1. Auto Adjust Component 480i/1080p RGB 1080p

It only needs to PCM EDID D/L for North America Product.

DTV/MNT_VOUT E DUP_DVB 2SC3052 Q106-1 C E B DUP_DVB 2SC3052 Q105-1 C