G H PATEL COLLEGE OF ENGINEERING & TECHNOLOGY, V.V.Nagar.

Department of Electronics & Communication Engineering

SEMESTER:- 2(even) AC YEAR:- 2008 – 2009

SUB CODE:- EC254 SUB TITLE:- DIGITAL CIRCUITS &
SYSTEMS
DIVISION:- 5(MC)

Assignment 3
(MSI Components like 4-bit Adder, Decoder, and Multiplexer)

Q-1 Construct 16-bit Parallel Adder with four MSI Chips, each containing a 4-bit Parallel Adder
(IC7483). Use a Block Diagram with 9 inputs and 5 outputs, for each 4-bit Adder. Show
how carries connected between MSI Chips.

Q-2 Construct BCD to Excess-3 and Excess-3 to BCD Code Converter using 4-bit Binary Adder.

Q-3 Design a Decimal Arithmetic Unit with two selection variables, V1 and V0, and two BCD
digits, A and B. The unit should have four arithmetic operations, which depend on the
values of the selection variables as shown below:
V1 V0 Output Function
0 0 A + 9’s complement of B
0 1 A+B
1 0 A + 10’s complement of B
1 1 A + 1 (Add 1 to A) Use MSI Functional Chips in the Design.

Q-4 It is necessary to design a decimal Adder for two digits represented in the Excess-3 Code
so that the correction after adding the two digits with a 4-bit Binary Adder is as follows:
(a) The output carry is equal to the carry out of the Binary adder.
(b) If output carry = 1, add 0011.
(c) If output carry = 0, add 1101.
Construct the Adder with two 4-bit binary adders and an inverter.

Q-5 Design an 8-bit Magnitude Comparator using 4-bit Magnitude comparator ICs. (IC7485).
Explain the comparison algorithm.

Q-6 Design the following using Block Diagram.

(i) Design 5 x 32 Decoder using IC 74138 (3 x 8 Decoders).
(ii) Construct 16 x 1 Multiplexer using 4 x 1 multiplexers (IC 74151).

Q-7 Design a Logic Circuit that generates square of the 3-bit number using
(i) Decoder (ii) Multiplexer (iii) ROM

Q-8 Design a 4-input priority encoder with input D0 having the highest priority and D3 has
lowest priority.

Q-9 An 8 x 1 multiplexer has inputs A, B, and C connected to the selection inputs S2, S1, and
S0, respectively. The data inputs, I0 through I7, are as follows: I1 = I2 = I5 = 0; I3 = I7
= 1; I4 = I0 = D; and I6 = D’. Determine the Boolean Function that the multiplexer
implements.
Q-10 Assume that the exclusive-OR gate has a propagation delay of 20 ns and that of the AND
or OR gates have a propagation delay of 10 ns. What is the total propagation delay time
in the 4-bit adder circuit? (For Circuit with look ahead carry)