Prepared by
N.SHANMUGA SUNDARAM
Assistant Professor
Department of ECE
Mahendra Engg College
Namakkal Dt. - 637503.
Mahendra Engineering College EC1401 – VLSI Design
Unit I
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36. What are the various etching processes used in SOI process?
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38. What are the basic processing steps involved in BiCMOS process?
Additional masks defining P base region
• N Collector area
• Buried Sub collector (SCCD)
• Processing steps in CMOS process
39. What is meant by interconnect? What are the types are of interconnect?
Interconnect means connection between various components in an IC.
Types of Inter connect:
1. Metal Inter connect
2. PolySilicon Inter connect
3. Local Inter connect.
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All p-MOS transistors are placed above demarcation line and n-MOS below the
demarcation line
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Unit – II
When Vgs = 0;
the device will be cut-off.
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Even if Vgs = 0;
the device will be conducting.
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In Inversion mode, the gate is applied with voltage larger than its threshold
voltage (Vgs>Vth).
As the gate voltage is increased, the electrons in the substrate are attracted towards
the region below the gate, pushing the holes to other side of the substrate. Thus, a
layer of electrons is formed below the gate, which is called as Inversion layer.
These electrons constitute the channel for conduction between source and drain.
10. What are the different regions that can be defined in n-MOS depending upon
the voltages applied?
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In submicron technology, the field is high, so, electrons are imparted with enough
energy to become 'hot'. These hot electrons impact the drain, and remove the holes
from that place and then swept towards the negatively charged substrate and
appear as a substrate current. This is known as 'Impact Ionization'.
13. Draw the DC transfer characteristics curve to show its various regions.
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VL = VDD = full value of power supply. This is known as full rail output.
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1
f = -----------
tr + tf
where, tr - Rise time
tf - fall time
f - maximum signal frequency
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These are: i) Static dissipation due to leakage current or other current drawn
continuously from the power supply.
ii) Dynamic dissipation due to
• Switching transient current
• Charging and discharging of load capacitances.
23. What is the formula for power dissipation for CMOS Inverter?
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Unit – III:
3. What is Verilog?
Verilog is a general purpose hardware descriptor language. It is similar in syntax
to the C programming language. It can be used to model a digital system at many
levels of abstraction ranging from the algorithmic level to the switch level.
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Identifiers consists of upper and lower case letters, digits 0 through 9, the
underscore character(_) and the dollar sign($). It must be a single group of
characters.
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27. Initialize port A as input, port b as output, and port c as inout port.
module name (a, b, c)
input a ;
output b;
inout c;
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Unit – IV:
5. What is a FPGA?
A field programmable gate array (FPGA) is a programmable logic device that
supports implementation of relatively large logic circuits. FPGAs can be used to
implement a logic circuit with more than 20,000 gates whereas a CPLD can
implement circuits of upto about 20,000 equivalent gates.
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8. What is an antifuse?
An antifuse is normally high resistance (>100MW). On application of appropriate
programming voltages, the antifuse is changed permanently to a low-resistance
structure (200-500W).
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Unit – V:
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*************** X ***************
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1. Derive the CMOS inverter DC characteristics and obtain the relationship for
output voltage at different region in the transfer characteristics.
Explanation (2)
Diagram (2)
CMOS inverter (2)
DC characteristics (5)
Transfer characteristics (5)
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10. Explain about the various non ideal conditions in MOS device model.
Explanation (2)
Diagram (2)
Operation (4)
13. Explain with neat diagrams the Multiplexer and latches using transmission Gate.
Explanation (2)
Diagram (2)
Multiplexer (4)
latches(4)
15. Explain the concept of MOSFET as switches and also bring the various logic
gates using the switching concept.
Explanation (2)
Diagram (2)
Gate Concepts (4)
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16. Explain the concept involved in structural gate level modeling and also give the
description for Half adder and Full adder.
Explanation (2)
Diagram (2)
Gate Concepts (6)
Half adder (3)
Full adder (3)
b) Explain ATPG.
Definition (2)
Truth tables (2)
Five valued logic (2)
Testability measures (2)
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