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  • 4 Bit LUT

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    Techy Guy
    20 tayangan4 halaman
    The document describes a 4-bit lookup table (LUT) module at different levels of abstraction: 1) The behavioral level describes the LUT functionality using a case statement to assign the output based on the select lines. 2) The data flow level implements the LUT using logic gates by assigning each output bit as the AND of an input bit and the inverted/non-inverted select lines. 3) The gate level further decomposes the design into basic logic gates like AND, OR and inverters. 4) A test bench is provided to simulate and verify the LUT design by applying different input patterns and monitoring the output.

    Deskripsi Asli:

    Verilog Lab Pgm 5

    Judul Asli

    lut(3)

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    The document describes a 4-bit lookup table (LUT) module at different levels of abstraction: 1) The behavioral level describes the LUT functionality using a case statement to assign the output based on the select lines. 2) The data flow level implements the LUT using logic gates by assigning each output bit as the AND of an input bit and the inverted/non-inverted select lines. 3) The gate level further decomposes the design into basic logic gates like AND, OR and inverters. 4) A test bench is provided to simulate and verify the LUT design by applying different input patterns and monitoring the output.

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    20 tayangan4 halaman

    4 Bit LUT

    Diunggah oleh

    Techy Guy
    The document describes a 4-bit lookup table (LUT) module at different levels of abstraction: 1) The behavioral level describes the LUT functionality using a case statement to assign the output based on the select lines. 2) The data flow level implements the LUT using logic gates by assigning each output bit as the AND of an input bit and the inverted/non-inverted select lines. 3) The gate level further decomposes the design into basic logic gates like AND, OR and inverters. 4) A test bench is provided to simulate and verify the LUT design by applying different input patterns and monitoring the output.

    Hak Cipta:

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    dari 4

    FIGURE

    4 bit LUT

    BEHAVIORAL LEVEL
    module lut_4_in(out,i,s);
    input [15:0]i;
    input [3:0]s;
    output out;
    reg out;
    always@(i or s)
    case(s)
    4'b0000 : out =i[0];
    4'b0001 : out =i[1];
    4'b0010 : out =i[2];
    4'b0011 : out =i[3];
    4'b0100 : out =i[4];
    4'b0101 : out =i[5];
    4'b0110 : out =i[6];
    4'b0111 : out =i[7];
    4'b1000 : out =i[8];

    4'b1001 : out
    4'b1010 : out
    4'b1011 : out
    4'b1100 : out
    4'b1101 : out
    4'b1110 : out
    4'b1111 : out
    endcase
    endmodule

    =i[9];
    =i[10];
    =i[11];
    =i[12];
    =i[13];
    =i[14];
    =i[15];

    DATA FLOW
    module lut_4_in(out,i,s);
    input [15:0]i;
    input [3:0]s;
    output out;
    wire [15:0]y;
    assign y[0]=(i[0]&((~s[0])&(~s[1])&(~s[2])&(~s[3])));
    assign y[1]=(i[1]&((s[0])&(~s[1])&(~s[2])&(~s[3])));
    assign y[2]=(i[2]&((~s[0])&(s[1])&(~s[2])&(~s[3])));
    assign y[3]=(i[3]&((s[0])&(s[1])&(~s[2])&(~s[3])));
    assign y[4]=(i[4]&((~s[0])&(~s[1])&(s[2])&(~s[3])));
    assign y[5]=(i[5]&((s[0])&(~s[1])&(s[2])&(~s[3])));
    assign y[6]=(i[6]&((~s[0])&(s[1])&(s[2])&(~s[3])));
    assign y[7]=(i[7]&((s[0])&(s[1])&(s[2])&(~s[3])));
    assign y[8]=(i[8]&((~s[0])&(~s[1])&(~s[2])&(s[3])));
    assign y[9]=(i[9]&((s[0])&(~s[1])&(~s[2])&(s[3])));
    assign y[10]=(i[10]&((~s[0])&(s[1])&(~s[2])&(s[3])));
    assign y[11]=(i[11]&((s[0])&(s[1])&(~s[2])&(s[3])));
    assign y[12]=(i[12]&((~s[0])&(~s[1])&(s[2])&(s[3])));
    assign y[13]=(i[13]&((s[0])&(~s[1])&(s[2])&(s[3])));
    assign y[14]=(i[14]&((~s[0])&(s[1])&(s[2])&(s[3])));
    assign y[15]=(i[15]&((s[0])&(s[1])&(s[2])&(s[3])));
    assign out=y[0]|y[1]|y[2]|y[3]|y[4]|y[5]|y[6]|y[7]|y[8]|y[9]|y[10]|y[11]|y[12]|
    y[13]|y[14]|y[15];
    endmodule

    GATE LEVEL
    module lut_4_in(out,i,s);
    input [15:0]i;
    input [3:0]s;
    output out;
    wire [15:0]y;
    wire x0,x1,x2,x3;
    not(x0,s[0]);
    not(x1,s[1]);
    not(x2,s[2]);
    not(x3,s[3]);
    and(y[0],i[0],x0,x1,x2,x3);
    and(y[1],i[1],s[0],x1,x2,x3);

    and(y[2],i[2],x0,s[1],x2,x3);
    and(y[3],i[3],s[0],s[1],x2,x3);
    and(y[4],i[4],x0,x1,s[2],x3);
    and(y[5],i[5],s[0],x1,s[2],x3);
    and(y[6],i[6],x0,s[1],s[2],x3);
    and(y[7],i[7],s[0],s[1],s[2],x3);
    and(y[8],i[8],x0,x1,x2,s[3]);
    and(y[9],i[9],s[0],x1,x2,s[3]);
    and(y[10],i[10],x0,s[1],x2,s[3]);
    and(y[11],i[11],s[0],s[1],x2,s[3]);
    and(y[12],i[12],x0,x1,s[2],s[3]);
    and(y[13],i[13],s[0],x1,s[2],s[3]);
    and(y[14],i[14],x0,s[1],s[2],s[3]);
    and(y[15],i[15],s[0],s[1],s[2],s[3]);
    or(out,y[0],y[1],y[2],y[3],y[4],y[5],y[6],y[7],y[8],y[9],y[10],y[11],y[12],y[13],
    y[14],y[15]);
    endmodule

    TEST BENCH

    module stimulus;
    reg [15:0]i;
    reg [3:0]s;
    wire out;
    lut_4_in l1(out,i,s);
    initial begin
    i[0]=1;i[1]=1;i[2]=1;i[3]=1;i[4]=0;i[5]=0;i[6]=0;i[7]=1;i[8]=1;i[9]=1;i[10]=0;
    i[11]=0;i[12]=0;i[13]=1;i[14]=1;i[15]=0;s[0]=0;s[1]=0;s[2]=0;s[3]=0;
    #5 i[0]=1;i[1]=1;i[2]=1;i[3]=1;i[4]=0;i[5]=0;i[6]=0;i[7]=1;i[8]=1;i[9]=1;
    i[10]=0;i[11]=0;i[12]=0;i[13]=1;i[14]=1;i[15]=0;s[0]=0;s[1]=0;s[2]=1;s[3]=0;
    #5 $finish;end
    initial begin $monitor($time,"out=%b",out);end
    endmodule

    4 bit LUT

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