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# Arithmetic Building Blocks

Multiplier design
Array multipliers

ECE 261

James Morizio

Input-Output

MEMORY

CONTROL

DATAPATH

ECE 261

James Morizio

## Building Blocks for Digital Architectures

Arithmetic unit - Bit-sliced datapath (adder , multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus
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Bit-Sliced Design
Signals Data Control
Control

Metal 2 (control)

Multiplier

Data-in

Register

Shifter

## Tile identical processing elements

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Data-out

S = A B Cout = AgB
Cout S A B

B C

## S = A B C Cout Cout = MAJ ( A, B, C ) S

A 0 0 1 1

B 0 1 0 1

Cout 0 0 0 1

S 0 1 1 0

A 0 0 0 0 1 1 1 1
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B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Cout 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1
5

ECE 261

A B Cout Full Cin adder Sum

ECE 261

James Morizio

A Cin B Cout Full adde r S um
Sum = A B C = ABCi + ABCi + ABCi + ABCi Co = AB + BCi + ACi

ECE 261

James Morizio

## Sum and Carry as a functions of P, G

Define 3 new variable which ONLY depend on A, B Gen erate (G) = AB Prop agate (P) = A +B

ECE 261

James Morizio

A0 Ci, 0 B0 Co,0 FA (= C i,1 ) S0 S1 S2 S3 A1 B1 Co ,1 FA A2 B2 Co,2 A3 B3 Co,3

FA

FA

## Wo rs t ca s e d e la y lin ea r with th e n u m b e r o f b its td = O(N)

td = (N-1)tcarry + tsum
Goa l: Ma ke the fas te s t pos s ible carry pa th circuit
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## Complimentary Static CMOS Full Adder

VDD VDD Ci A B Ci A Ci A B A Ci B VDD A Co B Ci A B X Ci S B VDD B A A B

Note: 1) S = ABCi + Co(A + B + Ci) 2) Placement of Ci 3) Two inverter stages for each Co

O(N) delay
28 Transistors
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Inversion Property
Inverting all inputs results in inverted outputs
A B A B

Ci

FA

Co

Ci

FA

Co

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## Minimize Critical Path by Reducing Inverting Stages

Even Cell Odd Cell

A0 B0
Ci ,0 FA Co,0

A1 B1
FA Co,1

A2 B2
FA Co,2

A3 B3
Co,3 FA

S0

S1

S2

S3

Exploit Inversion Property Need two different types of cells, FA: no inverter in carry path
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## A better structure: the Mirror Adder

VDD VDD A "0"-Propagate Ci "1"-Propagate A B A Generate B A B Ci A B B B Kill A Co Ci S Ci A B VDD Ci A B

24 transistors
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Symmetrical NMOS and PMOS chains
identical rising and falling transitions if the NMOS and PMOS devices are properly sized. Maximum of two series transistors in the carry-generation circuitry.

## Critical issue: minimization of the capacitance at Co.

Reduction of the diffusion capacitances important. The capacitance at Co composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .

Transistors connected to Ci placed closest to output. Only the transistors in carry stage have to be optimized for speed. All transistors in the sum stage can be minimal size.

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James Morizio

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VDD VDD A1 B1 B1 A1 Ci 2 A1 VDD Ci 1 B1 Ci1 A1 B1 VD D VDD A0 A0 Ci0 Carry Path B0 B0 Ci1 A0 B0 Ci0 B0 A0 Ci0 S0 VDD S1

VDD

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James Morizio

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## Manchester Carry Chain

VDD P0 Ci,0 P1 P2 P3 P4 Co,4

G0

G1

G2

G3

G4

Only nMOS transmission gates used. Why? Delay of long series of pass gates: add buffers
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P0 Ci,0 G1
Co,0

P0

G1
Co,1

P2

G2
Co,2

P3

G3 Co,3

FA

FA

FA

FA

P0 G1 Ci,0
Co,0

P0

G1
Co,1

P2

G2
Co,2

P3

G3

BP=P oP1 P2 P3

FA

FA

FA

FA
Co,3

## Idea: If (P 0 and P 1 and P 2 and P3 = 1) then Co3 = C 0 , else kill or generate.

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Manchester-Carry Implementation

P0 Ci,0 G0

P1 G1

P2 G2

P3 G3

BP Co,3

BP

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Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
S e tu p S e tu p S e tu p S e tu p

C arry

## C arry Pro pagati on

C arry Propagati on

C arry Propagati on

C i,0

Propagati on

Sum

S um

Sum

Sum

Design N-bit adder using N/M equal length stages e.g. N = 16, M = 4 What is the critical path? tp = tsetup + Mtcarry + (N/M-1)tbypass + Mtcarry + tsum , i.e. O(N)
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## Carry Ripple versus Carry Bypass

tp

4..8

N
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ECE 261

Generate carry out for both 0 and 1 incoming carries
Setup
P,G

"0"

"1"

Co,k-1

Multiplexer
Carry Vector

Co,k+3

Sum Generation

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James Morizio

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## Carry Select Adder: Critical Path

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15 Setup Setup Setup Setup

"0"

"0" Carry

"0"

"0" Carry

"0"

"0" Carry

"0"

"0" Carry

"1" Carry

## Multiplexer Co,15 Sum Generation S12-15

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Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15 Setup Setup Setup Setup

(1)
"0" "0" Carry "0" "0" Carry "0" "0" Carry "0" "0" Carry

(1)
"1" Carry "1" "1" "1" Carry "1" "1" Carry "1" "1" Carry

(5)
Ci,0

(5)

Multiplexer

(6)
Co,3

(5)
Multiplexer

(5) (7)
Co,7 Multiplexer

(8)
Co,11

(5)
Multiplexer Co,15 Sum Generation S12-15

## Are equal-sized blocks best?

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## Linear Carry Select

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15 Setup Setup Setup Setup

"0"

"0" Carry

"0"

"0" Carry

"0"

"0" Carry

"0"

"0" Carry

"1" Carry

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## Square Root Carry Select

Bit 0-1
Setup

Bit 2-4
Setup

Bit 5-8
Setup

Bit 9-13
Setup

(1)
"0" "0" Carry "0" "0" Carry "0" "0" Carry "0" "0" Carry

(1)
"1" Carry "1" "1" "1" Carry "1" "1" Carry "1" "1" Carry

(3)
Ci,0

(3)

Multiplexer

(4)
Co,3

(4)
Multiplexer

(5) (5)
Co,7 Multiplexer

(6)
Co,11

(6)
Multiplexer Co,15 Sum Generation

Sum Generation

Sum Generation

Sum Generation

i.e., O(N)
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50.0

40.0

30.0 tp
linear select

20.0

10.0

0.0

0.0

20.0 N

40.0

60.0

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A0 ,B 0 A1 ,B 1
...

AN-1 ,BN-1

Ci,0

P0

Ci,1

P1

Ci,N-1
...

PN-1

S0

S1

SN-1

## Delay independent of the number of bits

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High fanin for large N Implement as CLA slices, or use 2nd level lookahead generator
4 4 4 4 4 4 4 4

## 16-bit CLA based on 4-bit slices and ripple carry

4 4

4 4 4

4 4 4

4 4 4 4

Faster implementation

CLA generator
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