module xor2ip(c, a, b);

input a;
input b;
output reg c;
always@(a or b)
begin
if(a != b)
c = 0;
else
c = 1;
end
endmodule
///////////////////////////////////////
module fulladder(sum, cout, ip1, ip2, cin);
input ip1,ip2,cin;
output sum, cout;
// for sum
xor2ip xor1 (s1, ip1, ip2);
xor2ip xor2 (sum, s1, cin);
// for carry
assign cout = (ip1 & ip2) | (ip2 & cin) | (ip1 & cin);
endmodule
////////////////////////////////////////////////////////////////////////////////
//////
module fulladder4bit(sum, cout, ip1, ip2, cin);
input [3:0] ip1,ip2;
input cin;
output [3:0] sum;
output cout;
wire [2:0] tc;
fulladder fa1(sum[0],tc[0],ip1[0],ip2[0],cin);
fulladder fa2(sum[1],tc[1],ip1[1],ip2[1],tc[0]);
fulladder fa3(sum[2],tc[2],ip1[2],ip2[2],tc[1]);
fulladder fa4(sum[3],cout,ip1[3],ip2[3],tc[2]);
endmodule
////////////////////////////////////////////////////////////////////////////////
/////

module distram(dataout, addr, datain, csn, rwn);

output reg [3:0] dataout;
input [3:0] addr;
input [3:0] datain;
input csn;
input rwn;
reg [3:0] data [15:0];
always@(rwn,datain,csn,addr)
begin

if(csn == 1)
begin
data[0] = 0;
data[1] = 1;
data[2] = 2;
data[3] = 3;
data[4] = 4;
data[5] = 5;
data[6] = 6;
data[7] = 7;
data[8] = 8;
data[9] = 9;
data[10] = 10;
data[11] = 11;
data[12] = 12;
data[13] = 13;
data[14] = 14;
data[15] = 15;
end
if(csn==0 && rwn==1)
begin
dataout = data[addr];
end
else if(csn==0 && rwn==0)
begin
data[addr] = datain;
//dataout = 4'bzzzz;
end
else
begin
dataout = 4'bzzzz;
end
end
endmodule
////////////////////////////////////////////////////////////////////////////////
///////////////
module registeralu(rf, rcout, a, b, cin, sel, rst, clk);
output reg [3:0] rf;
output reg rcout;
input [3:0] a,b;
input [2:0] sel;
input cin,rst,clk;
wire [3:0] f;
wire cout;
alu4bit alu1(f, cout, a, b, cin, sel);
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
rf=4'b0000;
rcout=0;
end

else
begin
rf=f;
rcout=coumodule registeralu(rf, rcout, a, b, cin, sel, r
st, clk);
output reg [3:0] rf;
output reg rcout;
input [3:0] a,b;
input [2:0] sel;
input cin,rst,clk;
wire [3:0] f;
wire cout;
alu4bit alu1(f, cout, a, b, cin, sel);
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
rf=4'b0000;
rcout=0;
end
else
begin
rf=f;
rcout=cout;
end
end
endmodulet;
end
end
endmodule
///////////////////////////////////////////////////////////////////////////
module instdecoder(address,dataout,aluin1,aluin2,selalu,chipsel,rwn,state,clk,rs
t,oper1,oper2,opcode,datain,aluout);
output reg[3:0] address,dataout,aluin1,aluin2;
output reg [2:0]selalu;
output reg chipsel,rwn;
output reg [1:0] state;
input
input
input
input

clk,rst;
[3:0]oper1,oper2;
[2:0]opcode;
[3:0]datain,aluout;

reg [1:0]
parameter
parameter
parameter
parameter

prestate,nxtstate;
init= 2'b00;//init
fetch =2'b10;//fetch
execute =2'b11;//execute
load =2'b01;//load

always@(posedge clk or negedge rst)

begin
if(rst==0)
prestate <= init;
else

prestate <= nxtstate;

end
always@(prestate or rst)
begin
case(prestate)
0 : begin
if(rst == 0)
begin
nxtstate <= init;
state<=init;
end
else
begin
nxtstate <= fetch;
state<=init;
chipsel=1;
end
end
2 : begin
if(rst == 1)
nxtstate <= init;
else
begin
nxtstate <= execute;
state <= fetch;
chipsel<=0;
rwn<=1;
address <= oper1;
end
end
3 : begin
if(rst == 0 )
begin
nxtstate <= init;
end
else
begin
nxtstate <= load;
aluin1<=datain;
aluin2<=oper2;
selalu<=opcode;
state<=execute;
end
end
1 : begin
if(rst == 1 )
begin

nxtstate <= init;

end
else
begin
nxtstate <= fetch;
state <= load;
chipsel<=0;
rwn<=0;
address <= oper1;
dataout<=aluout;
end
end
endcase
end
endmodule
////////////////////////////////////////////////////////////////////////////////
////////
module alu4bit(f, cout, a, b, cin, sel);
output [3:0] f;
output cout;
input [3:0] a,b;
input cin;
input [2:0] sel;
wire [3:0] temps,tempx;
wire tempc;
wire [3:0] tempb,templog;
fulladder4bit fa1 (temps,tempc,a,tempb,cin);
xor2ip
xor2ip
xor2ip
xor2ip

xor1
xor2
xor3
xor4

(
(
(
(

tempx[0],a[0],b[0]);
tempx[1],a[1],b[1]);
tempx[2],a[2],b[2]);
tempx[3],a[3],b[3]);

assign tempb=(sel[1]==0)?((sel[0]==0)?0:b):((sel[0]==0)?(~b):15);
assign templog=(sel[1]==0)?((sel[0]==0)?(~(a|b)):(tempx)):((sel[0]==0)?
(a&b):(~a));
assign f=(sel[2]==0)?temps:templog;
assign cout=(sel[2]==0)?tempc:~sel[2];
endmodule
////////////////////////////////////////////////////////////////////////////////
/////////
module distram(dataout, addr, datain, csn, rwn);
output reg [3:0] dataout;
input [3:0] addr;
input [3:0] datain;
input csn;
input rwn;
reg [3:0] data [15:0];
always@(rwn,datain,csn,addr)
begin

if(csn == 1)
begin
data[0] = 0;
data[1] = 1;
data[2] = 2;
data[3] = 3;
data[4] = 4;
data[5] = 5;
data[6] = 6;
data[7] = 7;
data[8] = 8;
data[9] = 9;
data[10] = 10;
data[11] = 11;
data[12] = 12;
data[13] = 13;
data[14] = 14;
data[15] = 15;
end
if(csn==0 && rwn==1)
begin
dataout = data[addr];
end
else if(csn==0 && rwn==0)
begin
data[addr] = datain;
//dataout = 4'bzzzz;
end
else
begin
dataout = 4'bzzzz;
end
end
endmodule