Prof.G.

Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

DEPARTMENT OF AERONAUTICAL ENGINEERING AE 2401 AVIONICS QUESTION BANK (Regulation 2004/2008) SUPPLIMENTARY COPY -1 AS ON 04.10.2012 UNIT I - PART A 1. What is the importance of FMS? (Nov/Dec 2011 Arrear) Ans: Refer Part A Ques 7 Unit I in QB 2. Name the actuators that are used in spacecraft attitude control system. (Nov/Dec 2011 Arrear) Ans: The following are the actuators that are used in spacecraft attitude control system: 1 Thrusters 2 Spin stabilization 3 Momentum wheels 4 Control moment gyros 5 Solar sails 6 Gravity-gradient stabilization 7 Magnetic torquers actuator 8 Pure passive attitude control 3. What is the importance of vehicle management system? (Nov/Dec 2011 Arrear) Ans: Refer Part A Ques 7 Unit I in QB (VMS = FMS) 4. What is meant by avionics and the need for it in civil and military aircrafts? (May/June 2012) Ans:-All electronic and electromechanical systems and subsystems (hardware and software) installed in an aircraft that are dependent on electronics for its operation. Avionics Systems are essential to enable the flight crew to carry out the aircraft mission safely and to meet the mission requirements with minimum flight crew. Avionics systems are needed in aircraft To enable the flight crew to carry out the aircraft mission safely and efficiently Mission is carrying passengers to their destination (Civil Airliner) Intercepting a hostile aircraft, attacking a ground target, reconnaissance or maritime patrol (Military Aircraft) 5. Avionics system equipment is very different in many ways from ground based equipment in carrying out similar functions. Justify the statement. (May/June 2012) Ans: Refer Part A Ques 13 Unit 1 in QB Or Equipments in avionics system are different from ground based equipment in many ways: 1. The importance of achieving minimum weight. 2. The adverse operating environment particularly in military aircraft in terms of operating temperature range, acceleration, shock, vibration, humidity range and electromagnetic interference. 3. The importance of very high reliability, safety and integrity. 4. Space constraints particularly in military aircraft requiring an emphasis on miniaturisation and high packaging densities. 6. Give the need for standard in design of avionics systems (Nov/Dec 2011 ) Ans: Refer Part A Ques 6 Unit I in QB 7. What are the major drivers for avionics in civil and military aircraft? (Nov/Dec 2011 ) Ans: Refer Part A Ques 3 Unit I in QB

AE 2401 AVIONICS

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Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE UNIT I - PART-B

1. Discuss the design and development of civil avionics system using top down approach. (16) (Nov/Dec 2011 Arrear) Ans: Refer Part B Ques 5 Unit I in QB

2. Discuss the role of avionics in spacecrafts systems. (16) (Nov/Dec 2011 Arrear) Ans: Refer Part B Ques 2 Unit I in QB

3. (i) Explain the various layers of avionics systems used in a typical airplane with a neat sketch (8) (Nov/Dec 2011) Ans: Refer Part B Ques 2 Unit I in QB

(ii) List out the important Illities used as a yardstick in the design of avionics systems (8) (Nov/Dec 2011) Ans: Refer Part B Ques 1 Unit I in QB

4. (i) What are the essential requirements of an avionics integration facility? (8) (Nov/Dec 2011) Ans: Essential Requirements-Setting for Avionics Systems Proper requirements are the sine qua non for building an acceptable avionics system. No avionics systems can perform as expected by the customer unless the customer requirements, along with requirements from other stakeholders and relevant regulations and standards, are completely documented and understood by the avionics manufacturer. Safety, mission, cost, and certification drive the requirements. For all aircraft, safety of flight in all possible flight regimes is the prime requirement. All aircraft without the possibility of ejection in case of an emergency typically have a probability of catastrophic failure on the order per flight hour. If the crew has the potential to eject in case of an emergency the probability of failure is somewhat less demanding, but still significant. Second only to safety, the mission of the aircraft is the principal driver of requirements. Mission requirements may be in terms of aircraft performance, ground turnaround times, or maintenance practices. Virtually every mission requirement translates into an avionics requirement in some form. Life cycle cost is of great importance in civil aircraft and is of increasing performance in military aircraft, more specifically the emerging Joint Strike Fighter. For a typical commercial transport aircraft the acquisition cost is approximately 20 to 25% of the total life cycle cost. In military aircraft, the acquisition cost is probably a smaller fraction of the life cycle cost. It is interesting to note that for the life cycle cost for civil avionics the acquisition cost rises to 60% of the total. Avionics life cycle cost, for example, will drive, the need for builtin testing, fault tolerance, and the ratio of mean time between unscheduled removals (MTBUR) and mean time between failure (MTBF.) Finally, certification is a major factor in avionics design. As the complexity and criticality of avionics increases so does the need for extensive certification activities. Certification issues begin with the initial definition of requirements and last until the equipment is removed from the aircraft or the aircraft is retired. It is important to note that the requirements definition, especially after the preliminary requirements are set, is very much an iterative process between the customer and the vendor, often under the purview of a Configuration Control Board. This configuration control process, which is sometimes viewed as an intrusion on the real work, AE 2401 AVIONICS 2 BE (Aero)

Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

is necessary to ensure that everyone is cognizant of proposed changes to requirements and can comment on them.

Aircraft functional requirements are at the top of the requirements hierarchy. The aircraft mission is broken into phases including pre flight checkout, taxi out, take-off, cruise, descent, landing, rollout, taxi in, and post flight. Additional specialized mission phases such as weather diversions, cargo drop, electronic warfare, etc. also drive the aircraft performance requirements. (ii) Explain how an avionics system is integrated on such a facility with suitable examples. (8) (Nov/Dec 2011) Ans: Refer Part B Ques 6 Unit I in QB

5. (i) What are the major drivers for avionics systems? (4) (May/June 2012) Ans: Refer Part B Ques 4 Unit I in QB

(ii) Explain with a neat diagram, the main avionics subsystems according to their role and their functions. (12) (May/June 2012) Ans: Refer Part B Ques 2 Unit I in QB

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JEPPIAAR ENGINEERING COLLEGE UNIT II - PART-A

1. List any four basic rules that are used in the Boolean algebra expression. (Nov/Dec 2011 ) Ans: Basic rules of Boolean algebra:

2. What is meant by a programmable peripheral device? (Nov/Dec 2011 ) Ans: Programmable Peripheral Device is an integrated circuit, which can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O. Eg.8255A, is a general purpose I/O device that can be used with almost any microprocessor which is flexible, versatile, and economical (when multiple I/O ports are required). 3. What are the various addressing modes used in 8085? (Nov/Dec 2011 Arrear) Ans: There are five types of addressing modes used in Microprocessor 8085 that are: 1. Immediate addressing. 2. Register addressing. 3. Direct addressing. 4. Indirect addressing. 5. Implicit Addressing 4. Differentiate between semiconductor and magnetic memories? (May/June 2012) Ans: Refer Part A Ques 19 Unit II in QB 5. What is the purpose of accumulator in microprocessor? (May/June 2012) Ans: Refer Part A Ques 34 Unit II in QB 6. Give the applications of 8251 programmable communication interface chip Ans. 1. 8251 can be used to transmit receive serial data Data transmission to a CRT terminal using the 8251 in status check mode. 2. A programmable chip designed for synchronous/asynchronous serial data communication. 7. What is DMA data transfer? Explain in brief. Ans. DMA implies direct memory access. Either in programmed I/O or interrupt I/O transfer, the data between the I/O devices and external memory is via the accumulator. For voluminous data transfer, there are the time commuting and even through the I/O devices speed matches with speed of UR So there is direct transfer of data directly between the I/O device and external memory without going through accumulator. This is called DMA. AE 2401 AVIONICS 4 BE (Aero)

Prof.G.Prabhakaran 8. Write short note on semiconductor memory. Ans.

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Semiconductor memory: Semiconductor memory is used to store data. The main advantages of semiconductor memories are 1. Small in size 2. Low cost 3. Better reliability 4. High speed.

Volatile Memory: If the information stored in a memory is lost when the electrical power is switched OFF, then the memory is called as volatile memory. These are called RAM (Random Access Memories). Non-volatile Memory: If the information once stored in memory does not change unless altered deliberately are called as non-volatile memory. These are ROM, PROM, EPROM etc. 9. Differentiate between parallel data transfer and serial data transfer. Ans.

10. Distinguish between synchronous and asynchronous data transfer Ans.

AE 2401 AVIONICS

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JEPPIAAR ENGINEERING COLLEGE UNIT II - PART-B

11. (i) Explain any one memory interfacing technique with neat diagram. (8) (Nov/Dec 2011 Arrear) Ans: IC 8251 - programmable communication interface chip: Features of 8251: 1. It supports both synchronous and asynchronous modes of operation. 2. The synchronous baud rate DC to 64 K baud. 3. The asynchronous baud rate DC to 19.2 K baud. 4. The synchronous mode supports 5-8 bits characters. 5. In asynchronous mode it supports 5-8 bits characters. 6. It contains full duplex system. Function of 8251 Chip: IC 8251 (USART) USART is Universal Synchronous/Asynchronous Receiver and Transmitter 8251 supports both synchronous as well as asynchronous data transfer It contains full duplex double buffered system It provides error detection logic, detects parity over run, framing errors It uses separate TxC and RxC clock inputs for transmitter and receiver So transmitter and receiver can be operated in different baud rates. IC 8251 Block diagram: The 8251 is a 28 pin DIP package all inputs and outputs are TTL compatible. The block diagram of 8251 contains following blocks: 1 Data bus buffer 2 Read/write control logic 3 Transmitter section 4 Receiver section 5 Modem control

1. Data Bus Buffer: It is a 3 state bi-directional, buffer used to interface internal data bus of 8251 to the system data bus The direction of data transfer through data bus buffer is decided by and This buffer transfers control word, status word data for transmitter and data from receiver, depending on signal given by R/W control logic 2. Read/Write Control Logic: This block accepts different control signals such as RD, WR C/D CS, CLK and Reset from control bus and generates control signals for device operation. AE 2401 AVIONICS 6 BE (Aero)

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3. Transmitter Section: It is accepts parallel data from the data bus buffer. The contents of the transmitter buffer are automatically transferred to output register if the output register is empty. The data is shifted out serially on the TxD pin for asynchronous mode start bit and stop bits are added to data byte for synchronous mode synchronous characters are transferred before the data bytes.

4. Receiver Section: This section consists of receive buffer and receive control blocks. The expanded block diagram of receiver section show 3 blocks (a) Receiver buffer register (b) Serial input register (c) Receiver control logic.

5. Modem Control: For sending data over long distances the telephone lines are used. The telephone lines are analog in nature so MODEM are used to convert digital data to analog data. To control MODEM, 8051 provides a block called as MODEM control.

(ii) Explain memory mapping process with example. (8) (Nov/Dec 2011 Arrear) Ans: Memory Mapped I/O: (i) Each I/O device will have 16-bit address. (ii) The I/O devices are treated as memory locations. There will be no separation like memory and I/O. (iii) The control signals used will be same as memory i.e. MEMR and MEMW. (iv) The number of I/O device will be 64 KB shared by I/O and memory. (v) For data transfer, microprocessor will send address on A0 to Al 5 lines and generates control signals or MEMR and MEMW. (vi) In MEMR it accepts data from I/O device while in MEMW it transfers data to I/O device. AE 2401 AVIONICS 7 BE (Aero)

Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

Input/Output Interfacing in Memory Mapped I/O: (i)The simple input device is a buffer and output device is latch. To interface these devices to 8085, the control lines 1G, 2G of buffer and G input of h cont 8085. (ii) The address is of 16 bits A0 to A15 and control signal MEMR and MEMW are used to control the buffer latch. (iii) The combination of address lines A0 and A15 can be done by using NAND gates and then it is combined with MEMR and MEMW signal. (iv) The interfacing diagram will be as shown in fig. For buffer when A0 to A15 all are ls the output of NAND gate will be low (0). It is combined with MEMR using NAND gate with inverted inputs and they are connected to 1 G and 2G. So, the address of buffer with be FFFF H.

(v) For latch when A0 to A14 all are ls and the line A15 MEMW = 0 the output of NAND gate will be low, after that it is combined with MEMW using AND gate with inverted inputs and connected to G. So, the address of latch will be 7FFE H. (vi) Instead of gates a 3: 8 decoder logic can be used to select the appropriate device. 12. (i) Explain the process how the microprocessor communicate with the Memory and I/O devices. (8) (Nov/Dec 2011 Arrear) Ans: Refer Part B Ques 1 Unit II in QB Supplementary Copy 1 (ii) Explain the classification of RAM with neat diagram. (8) (Nov/Dec 2011 Arrear) Ans:

AE 2401 AVIONICS

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Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

AE 2401 AVIONICS

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Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

AE 2401 AVIONICS

10

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Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

AE 2401 AVIONICS

11

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Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

13. (i) Discuss in detail about the different types of memories with suitable examples. (10) (Nov/Dec 2011) Ans: Ans: Refer Part B Ques 1 Unit II in QB Refer Part A Ques 9 Unit II in QB (ii) List out a few a few advantages of digital systems over its analog counterpart (6) 14. (i) Mention the different categories of instruction in 8085 microprocessor and give two examples for each category. (12) (Nov/Dec 2011) Ans: An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. These instructions can be classified into the following five functional categories: Data transfer (copy) operations, Arithmetic operations, Logical operations, Branching operations, and Machine-control operations. Data transfer (copy) operations: This group of instructions copy data from a location called a source to another location called a destination, without modifying the contents of the source. In technical manuals, the term data transfer is used for this copying function. However, the term transfer is misleading; it creates the impression that the contents of the source are destroyed when, in fact, the contents are retained without any modification. The various types of data transfer (copy) are listed below together with examples of each type: Examples 1. Between Registers ----- Copy the contents of the register B into register D. 2. Specific data byte to a register or a memory location --Load register B with the data byte 32H. 3. Between a memory location and a register -- From a memory location 2000H to register B. 4. Between an I/O device and the accumulator -- From an input keyboard to the accumulator. MVI r,data r <-- data Example: MVI A,30H coded as 3EH 30H as two contiguous bytes. This is an example of immediate addressing. AE 2401 AVIONICS 12 BE (Aero)

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LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate addressing. LDA addr A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH 34H 21H. This is also an example of direct addressing. MOV Rd,Rs MVI R,8 BIT IN 8-BIT LXI Rp, 16-BIT STAX Rp Arithmetic operations: These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement. Addition - Any 8-bit number, or the contents of a register or the contents of a memory location can be added to the contents of the accumulator and the sum is stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the contents of register B cannot be added directly to the contents of the register C). The instruction DAD is an exception; it adds 16-bit data directly in register pairs. Example: ADD, ADI Subtraction - Any 8-bit number, or the contents of a register, or the contents of a memory location can be subtracted from the contents of the accumulator and the results stored in the accumulator. The subtraction is performed in 2's compliment, and the results if negative, are expressed in 2's complement. No two other registers can be subtracted directly. Example: SUB, SBB Increment/Decrement - The 8-bit contents of a register or a memory location can be incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such as BC) can be incremented or decrement by 1. These increment and decrement operations differ from addition and subtraction in an important way; i.e., they can be performed in any one of the registers or in a memory location. Example: DCR, INR. ADD R ADI 8-BIT SUB R SUI 8-BIT INX Rp DCX Rp SUB M INR M DCR M ADD M Logical operations: These instructions perform various logical operations with the contents of the accumulator. AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of a memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents of the accumulator. The results are stored in the accumulator. Example: XRA C, ORA B, ANA E Rotate- Each bit in the accumulator can be shifted either left or right to the next position. Example: RAL, RAR Compare- Any 8-bit number, or the contents of a register, or a memory location can be compared for equality, greater than, or less than, with the contents of the accumulator. Example: CMP C, AE 2401 AVIONICS 13 BE (Aero)

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Complement - The contents of the accumulator can be complemented. All 0s are replaced by 1s and all 1s are replaced by 0s. ANA R/M ANI 8-BIT ORI 8-BIT XAI 8-BIT CMA RLC RAL RRC Branching operations: This group of instructions alters the sequence of program execution either conditionally or unconditionally. Jump - Conditional jumps are an important aspect of the decision-making process in the programming. These instructions test for a certain conditions (e.g., Zero or Carry flag) and alter the program sequence when the condition is met. In addition, the instruction set includes an instruction called unconditional jump. Call, Return, and Restart - These instructions change the sequence of a program either by calling a subroutine or returning from a subroutine. The conditional Call and Return instructions also can test condition flags. JMP 16-BIT ADDRESS JZ JNZ JC JNC CALL RET Machine-control operations: These instructions control machine functions such as Halt, Interrupt, or do nothing. HLT: Halt NOP: No Operation (ii) Differentiate between maskable and non-maskable interrupts. (4) (Nov/Dec 2011) Ans: Refer Part A Ques 38 Unit II in QB At many occasions, the programmer may like to prevent the occurrence of a few of several interrupts while P is performing certain tasks. This is done by masking off those interrupts which are not required to occur when certain task is being performed. There are two main classes of interrupts explained below: 1. Maskable interrupts. 2. Non-maskable interrupts. 1. Maskable interrupts: The commonly used interrupts by number are called maskable interrupts The processor can ask o temporarily ignore such interrupts These interrupts are temporarily 1gnred such that processor can finish the task under execution. The processor inhibits (block) these types of interrupts by use of special interrupt mask bit. This mask bit is part of the condition code register or a special interrupt request input, it is ignored else processor services the interrupts when processor is free, processor will serve these types of interrupts. 14 BE (Aero)

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JEPPIAAR ENGINEERING COLLEGE

Eg:- RST 7.5, RST 6.5 & RST 5.5. Maskable interrupts can be turned off by programmable settings. 2. Non-Maskable Interrupts (NMI): Some interrupts cannot be masked out or ignored by the processor. These are referred to as non-maskable interrupts. These are associated with high priority tasks that cannot be ignored. Example system bus faults. The TRAP is a non-maskable interrupt. It need not be enabled. It cannot be disabled. It is not accessible to user. It is used for emergency situation such as power failure and energy shut off. A non - maskable interrupt can be caused by two things 1. When an I/O channel check signal is received from an adapter card located in one of the board's expansion slot. 2. When there is the occurrence of a parity check in the system's DRAM Non-maskable interrupts are always active and cannot be turned off The computer has a non-maskable interrupts (NMI) that can be used for serious conditions that demand the processors attentions immediately. The NMI cannot be ignored by the system unless it is shut off specifically. In general most processors support the nonmaskable interrupt (NMI). This interrupt has absolute priority. When it occurs the processor will finish the current memory cycle and then branch to a special routine written to handle the interrupt request. When a NMI signal is received the processor immediately stops whenever it as doing and attends to it. That can lead to problem if these type of interrupts are used improperly. The NMI signal is used only for critical problem situation like Hardware errors. 15. (i) Implement the expression with logic gates (1) AB + BCD + EFGH (2) (A+B) (C+D+E) with logic gates Ans: (8) (May/June 2012)

1.

2. AE 2401 AVIONICS 15 BE (Aero)

Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

(ii) Draw the logic diagram for a master slave J-K flip flop and explain its operation (8) (May/June 2012) Ans:

AE 2401 AVIONICS

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Prof.G.Prabhakaran

JEPPIAAR ENGINEERING COLLEGE

16. (i) With a neat sketch explain 8085 microprocessor architecture in detail. (8) (May/June 2012) Ans: Refer Part B Ques 1 Unit II in QB (ii) Explain the registers of microprocessor and mention different categories of instructions in 8085 microprocessor. (8) (May/June 2012) Ans: Microprocessor 8085 consists of following registers: (a) Temporary data register (b) Instruction registers (c) 16-bit stack pointer (d) Flag register (e) Temporary registers W and Z (f) 8-bit accumulator (g) Six general purpose registers (B, C, D, E, H and L) (h) 16-bit program counter. Six general purpose registers (B, C, D, E, H and L): The 8085 microprocessor contains 6 general purpose registers of 8 bits each, named as B, C, D, E, H and L. These registers are programmable by user. They are used to hold data, results of arithmetic and logical operations and address of data memory. The valid register pairs available are BC, DE and HL. The user cannot form a register pair of his/her choice. Temporary Data Register: This register is also called as operand register. It provides operands to the ALU. It is a 8-bit register and not available to user. Temporary Registers (W and Z): These registers are used by control section to hold the data during an arithmetic or logical operation. It is hold 8 bit data. These register are not available to user. They are internally used by the microprocessor. AE 2401 AVIONICS 17 BE (Aero)

Prof.G.Prabhakaran e.g.:

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(a) XCHG (exchange) (b) XTHL (exchange top of stack with registers H and L). Accumulator: It is 8-bit general purpose register of 8085. It has some special functions due to this it is also known as special register. Following are special functions of accumulator: (a) It has to private one of operand for any ALU operations. (b) It is used for accumulation. (c) Whenever a data is read from input device it comes in accumulator and similarly output device gets data from the accumulator. Status or Flag Register: Flag is a flip-flop. It indicates some condition produced by execution of an instruction. (a) The flag register 8085 consists of five flags. It is connected to the ALU. (b) When any operation is performed by ALU result is transferred on internal data bus and status of result will be stored in flip-flops. Instruction Register: 1. The register is not accessible to user. 2. Instruction register holds the opcode of instruction that is decoded and executed. 3. This opcode is sent for instruction decoder to select one of 256 alternatives. Program Counter: 1. Used for holding the address of program memory. 2. In reset condition, the program counter is set to 000H, means that the address of first instruction to be fetched and executed. 3. The size of program counter depends upon the number of address bits. 4. In case of JUMP and call instructions, the address followed by JUMP and call instructions is placed in program counter. If the condition is satisfied then 8085 fetches the next instruction from the new address specified by JUMP or call instructions. 5. During instruction fetch operation, the contents of program counter on the address bus and it fetches first byte of instruction from memory location. Stack Pointer: 1. It is portion of memory where information can be stored or taken back. This memory area is known as stack area. 2. It is 16-bit register used for defining the stack starting address. 3. Used to keep track of data store don stack. 4. It is loaded with an initial value by means of transfer type instruction. Arithmetic Logic Unit (ALU): This section processes all data i.e. it perform arithmetic and logic operations. 1. It performs addition, subtraction and logical, operations like AND, OR, EX-OR. 2. ALU is always controlled by timing and control circuits. 3. It looks after the branching decisions. 4. It provides status of result to the flag register. An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. These instructions can be classified into the following five functional categories: Data transfer (copy) operations, Arithmetic operations, Logical operations, Branching operations, and Machine-control operations. AE 2401 AVIONICS 18 BE (Aero)

Prof.G.Prabhakaran

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17. Differentiate I/O Mapped I/O and Memory Mapped I/O Ans:

18. Differentiate I/O Mapped I/O and Memory Mapped I/O Ans:

19. Define following terms (a) Simplex Ans. (b) Duplex (c) Half duplex (d) Full duplex

(a) Simplex: It is one way transmission on the other hand the connection in such a way that transfer data only in one direction (b) Duplex: It is two way transmission It transfer data in both direction (c) Half duplex: It is also two way transmission But it is a connection between two terminals such that, data may travel in both the directions as well as transmission activated in one direction at a time (d) Full duplex: It is a connection between two terminals such that data may travel in both the directions simultaneously. So, it will contain one way transmission or two way transmission at a time AE 2401 AVIONICS 19 BE (Aero)

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JEPPIAAR ENGINEERING COLLEGE UNIT III - PART-A

1. Differentiate the protocol systems that are used in ARINC629. (Nov/Dec 2011 Arrear) Ans: Sl. MIL STD 1553B ARINC 429 ARINC 629 No. Command /Response Protocol: CSMA/CA Carrier sense 01 Williamsberg Protocol Protocol multiple access/Collision avoidance 2. What is the function of bus controller in MIL STD 1553B data bus? (May/June 2012) Ans: Refer Part A Ques 14 Unit III in QB 3. Differentiate MIL and ARINC standards in terms of bus speed. (May/June 2012) Ans: Sl. No. MIL STD 1553B ARINC 429 ARINC 629 Speed Critical data 100 Kb/s 01 Speed 1 Mb/s Speed 2 Mb/s Non Critical data 12-14.5 Kb/s 4. How is the federated architecture different from centralized architecture? (Nov/Dec 2011 ) Ans: Refer Part A Ques 6 Unit III in QB 5. What are the different types of protocols and topology used in avionics data buses? (Nov/Dec 2011 ) Ans: Sl.No MIL STD 1553B ARINC 429 ARINC 629 Protocol: CSMA/CA Carrier Williamsberg 1 Command /Response Protocol sense multiple Protocol access/Collision avoidance Called as Digital Time Division Called as Digital Called as DATAC- Digital 2 Command / Response Data Compendium Autonomous Terminal Access Multiplex Data bus Control 6. Differentiate simplex, half duplex and full duplex transmission. (Nov/Dec 2011 Arrear) Ans: In simplex transmission, data flow only in one direction -- from the sending device to the receiving device. Eg: 1. Simplex transmission is used only when the sending device does not require a response from the receiving device. 2. Security systems and fire alarms that contain a sensor use simplex transmission. In half-duplex transmission, data can flow in either direction -- from the sending device to the receiving device, and back -- but only in one direction at a time. Eg: Many fax machines, credit card verification systems, and automatic teller machines use half-duplex transmission. In full-duplex transmission, data can flow in both directions at the same time. Eg: A regular telephone line supports full-duplex transmission so that both parties can talk at the same time. AE 2401 AVIONICS 20 BE (Aero)

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JEPPIAAR ENGINEERING COLLEGE UNIT III - PART-B

1. Discuss the protocols of ARINC 429 data bus in detail. (16) (Nov/Dec 2011 Arrear) Ans: Protocols of ARINC 429 ARINC 429 is a very simple, point-to-point protocol. There can be only one transmitter on a wire pair. The transmitter is always transmitting either 32-bit data words or the NULL state. There is at least one receiver on a wire pair; there may be up to 20. In most cases, an ARINC message consists of a single data word. The label field of the word defines the type of data that is contained in the rest of the word. Bit Timing and Slew Rate The slew rate refers to the rise and fall time of the ARINC waveform. Specifically, it refers to the amount of time it takes the ARINC signal to rise from the 10% to the 90% voltage amplitude points on the leading and trailing edges of the pulse.

File Data Transfer Techniques This File Data Transfer Techniques specification describes a system in which an LRU may generate binary extended length messages on demand. Data is sent in the form of Link Data Units (LDU) organized in 8-bit octets. System Address Labels (SAL) are used to identify the recipient. Two data bus speeds are supported. Data Transfer The same principles of the physical layer implementation apply to file data transfer. Any avionics system element having information to transmit does so from a designated output port over a single twisted and shielded pair of wires to all other system elements having need of that information. Unlike the simple broadcast protocol that can deliver data to multiple recipients in a single transmission, the file transfer technique can be used only for point-to-point message delivery. Broadcast Data The broadcast transmission technique described above can be supported concurrently with file data transfer. Transmission Order The most significant octet of the file and least significant bit (LSB) of each octet should be transmitted first. The label is transmitted ahead of the data in each case. It may be noted that the Label field is encoded AE 2401 AVIONICS 21 BE (Aero)

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JEPPIAAR ENGINEERING COLLEGE

in reverse order, i.e., the least significant bit of the word is the most significant bit of the label. This reversed label characteristic is a legacy from past systems in which the octal coding of the label field was, apparently, of no significance. Data Bit Encoding Logic A HI state after the beginning of the bit interval returning to a NULL state before the end of the same bit interval signifies a logic one. A LO state after the beginning of the bit interval returning to a NULL state before the end of the same bit interval signifies a logic zero. Bit-Oriented Protocol Determination An LRU will require logic to determine which protocol (character- or bit-oriented) and which version to use when prior knowledge is not available. Bit-Oriented Communications Protocol This subsection describes Version 1 of the bit-oriented (Williamsburg) protocol and message exchange procedures for file data transfer between units desiring to exchange bitoriented data assembled in data files. The bit-oriented protocol is designed to accommodate data transfer between sending and receiving units in a form compatible with the Open Systems Interconnect (OSI) model developed by the International Standards Organization (ISO). This document directs itself to an implementation of the Link layer, however, an overview of the first four layers (Physical, Link, Network, and Transport) is provided. Communications will permit the intermixing of bit-oriented file transfer data words (which contain System Address Labels [SALs]) with conventional data words (which contain label codes). If the sink should receive a conventional data word during the process of accepting a bit-oriented file transfer message, the sink should accept the conventional data word and resume processing of the incoming file transfer message. The data file and associated protocol control information are encoded into 32-bit words and transmitted over the physical interface. At the Link layer, data are transferred using a transparent bit-oriented data file transfer protocol designed to permit the units involved to send and receive information in multiple word frames. It is structured to allow the transmission of any binary data organized into a data file composed of octets. Bit Rate and Word Timing Data transfer may operate at either high speed or low speed. The source introduces a gap between the end of each ARINC 429 word transmitted and the beginning of the next. The gap should be 4 bit times (minimum). The sink should be capable of receiving the LDU with the minimum word gap of 4 bit times between words. The source should not exceed a maximum average of 64 bit times between data words of an LDU. The maximum average word gap is intended to compel the source to transmit successive data words of an LDU without excessive delay. This provision prevents a source that is transmitting a short message from using the full available LDU transfer time. The primary value of this provision is realized when assessing a maximum LDU transfer time for short fixed-length LDUs, such as for Automatic Dependence Surveillance (ADS). Word Type The Word Type field occupies bit 3129 in all bit-oriented LDU words. The Word Type field is used to identify the function of each ARINC 429 data word used by the bit-oriented communication protocol. Protocol Words The protocol words are identified with a Word Type field of 100 and are used to control the file transfer process. Protocol Identifier The protocol identifier field occupies bits 2825 of the protocol word and identifies the type of protocol word being transmitted. Protocol words with an invalid protocol identifier field are ignored. AE 2401 AVIONICS 22 BE (Aero)

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Destination Code Some protocol words contain a Destination Code. The Destination Code field (bits 24 17) indicates the final destination of the LDU. If the LDU is intended for the use of the system receiving the message, the destination code may be set to null (hex 00). However, if the LDU is a message intended to be passed on to another on-board system, the Destination Code will indicate the system to which the message is to be passed. The Destination Codes are assigned according to the applications involved. The codes are used in the Destination Code field to indicate the address of the final destination of the LDU. Word Count Some protocol words contain a Word Count field. The Word Count field (bits 169) reflects the number of ARINC 429 words to be transmitted in the subsequent LDU. The maximum word count value is 255 ARINC 429 words and the minimum word count value is 3 ARINC 429 words. A LDU with the minimum word count value of 3 ARINC 429 words would contain a SOT word, one data word, and an EOT word. A LDU with the maximum word count value of 255 ARINC 429 words would contain a SOT word, 253 data words, and an EOT word. 2. (i) Compare the third generation and fourth generation architectures. (6) (Nov/Dec 2011 Arrear) Ans: Third generation -Pave Piller Architecture: Pave Pillar is a USAF program to define the requirements and avionics architecture for fighter aircraft of the 1990s The Program Emphasizes Increased Information Fusion Higher levels and complexity of software Standardization for maintenance simplification Lower costs Backward and growth capability while making use of emerging technology VHSIC, Voice Recognition /synthesis and Artificial Intelligence Provides capability for rapid flow of data in, through and from the system as well as between and within the system Higher levels of avionics integration and resource sharing of sensor and computational capabilities Pilot plays the role of a WEAPON SYSTEM MANAGER as opposed to subsystem operator/information integrator Able to sustain operations with minimal support, fly successful mission day and night in any type of weather Face a numerically and technologically advanced enemy aircraft and defensive systems Component reliability gains Use of redundancy and resource sharing Application of fault tolerance Reduction of maintenance test and repair time Increasing crew station automation Enhancing stealth operation Wide use of common modules (HW & SW)) Ability to perform in-aircraft test and maintenance of avionics Use of VHSIC technology and Capability to operate over extended periods of time at austere, deployed locations and be maintainable without the Avionics Intermediate Shop

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Fourth generation Pave Pace Architecture: Modularity concepts cuts down the cost of the avionics related to VMS, Mission Processing, PVI and SMS The sensor costs accounts for 70% of the avionics cost USAF initiated a study project to cut down the cost of sensors used in the fighter aircraft In 1990, Wright Laboratory McDonnell Aircraft, Boeing aircraft company and Lockheed launched the Pave Pace Program Come with the Concept of Integrated Sensor System(IS2) Pave Pace takes Pave Pillar as a base line standard The integration concept extends to the skin of the aircraft Integration of the RF & EO sensors Originally designed for Joint Strike Fighter (JSF) (ii) Explain BC-RT and RT-RT communication in MIL STD 1553B data bus (10) (Nov/Dec 2011 Arrear) Ans: Bus Controller to Remote Terminal The bus controller to remote terminal (BC-RT) message is referred to as the receive command since the remote terminal is going to receive data. The bus controller outputs a command word to the terminal defining the sub-address of the data and the number of data words it is sending. Immediately (without any gap in the transmission), the number of data words specified in the command word are sent. The remote terminal upon validating the command word and all of the data words will issue its status word within the response time requirements (maximum of 12 sec). The remote terminal must be capable of processing the next command that the bus controller issues. Therefore the remote terminal has approximately 56 sec (status word response time 12 sec, plus status word transmit time 20 sec, plus inter-message gap minimum 4 sec, plus command word transmit time 20 sec, to either pass the data to the subsystem or buffer the data. Remote Terminal to Remote Terminal The remote terminal to remote terminal (RT-RT) command is provided to allow a terminal (the data source) to transfer data directly to another terminal (the data sink) without going through the bus controller. The bus controller may, however, collect and use the data. The bus controller first issues a command word to the receiving terminal immediately followed by a command word to the transmitting terminal. The receiving terminal is expecting data, but instead of data after the command word it sees a command sync (the second command word). The receiving terminal ignores this word and waits for a word with data sync. The transmitting terminal ignored the first command word (it did not contain its terminal address). The second word was addressed to it, so it will process the command as an RT-BC command as described above by transmitting its status word and the required data words. The receiving terminal, having ignored the second command word, again sees a command (status) sync on the next word and waits further. The next word (the first data word sent) now has data sync and the receiving remote terminal starts collecting data. After receipt of all of the data words (and validating), the terminal transmits its status word. RT-RT Validation There are several things that the receiving remote terminal of an RT-RT message should do. First, Notice 2 requires that the terminal time out in 54 to 60 sec after receipt of the command word. This is required since if the transmitting remote terminal did not validate its command word (and no transmission occurred) then the receiving terminal will not collect data from some AE 2401 AVIONICS 24 BE (Aero)

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new message. This could occur if the next message is either a transmit or receive message, where the terminal ignores all words with a command/status sync and would start collecting data words beginning with the first data sync. If the same number of data words were being transferred in the follow-on message and the terminal did not test the command/status word contents, then the potential exists for the terminal to collect erroneous data. The other function that the receiving terminal should do, but is not required by the standard, is to capture the second command word and the first transmitted data word. The terminal could compare the terminal address fields of both words to insure that the terminal doing the transmitting was the one commanded to transmit. This would allow the terminal to provide a level of protection for its data and subsystem. Mode Command Formats Three mode command formats are provided for. This allows for mode commands with no data words and for the mode commands with one data word (either transmitted or received). The status/data sequencing is as described for the BC-RT or RT-BC messages except that the data word count is either one or zero. Mode codes and their use are described later. Broadcast Information Transfer Formats The broadcast information transfer formats, as shown in Figure 1.8, are identical to the non-broadcast formats described above with the following two exceptions. First, the bus controller issues commands to terminal address 31 (11111) which is reserved for this function. And secondly, the remote terminals receiving the messages (those which implement the broadcast option) suppress the transmission of their status word. The broadcast option can be used with the message formats in which the remote terminal receives data. Obviously, multiple terminals cannot transmit data at the same time, so the RTBC transfer format and the transmit mode code with data format cannot be used. The broadcast RT-RT allows the bus controller to instruct all remote terminals to receive and then instructs one terminal to transmit, thereby allowing a single subsystem to transfer its data directly to multiple users. Notice 2 allows the bus controller to only use broadcast commands with mode codes Remote terminals are allowed to implement this option for all broadcast message formats. Command and Message Validation The remote terminal must validate the command word and all data words received as part of the message. The criteria for a valid command word are that the: word begins with a valid command sync, valid terminal address (matches the assigned address of the terminal or the broadcast address if implemented), all bits are in a valid Manchester code, there are 16 information field bits, and there is a valid parity bit (odd). The criteria for a data word are the same except a valid data sync is required and the terminal address field is not tested. If a command word fails to meet the criteria, the command is ignored. After the command has been validated, and a data word fails to meet the criteria, then the terminal shall set the Message Error bit in the status word and suppress the transmission of the status word. Any single error within a message shall invalidate the entire message and the data shall not be used. Illegal Commands The standard allows remote terminals the option of monitoring for Illegal Commands. An Illegal Command is one that meets the valid criteria for a command word, but is a command (message) that is not implemented by the terminal. An example is if a terminal only outputs 04 data words to sub-address 01 and a command word was received by the terminal that requested it to transmit 06 data words from Sub-address 03, then this command, while still a valid command, could be considered by the terminal as illegal. The standard only states that the bus controller shall not issue illegal or invalid commands. The standard provides the terminal designer with two options. First, the terminal can respond to all commands as usual (this is referred to as responding in form). The data received is typically placed in a series of memory locations which are not accessible by the subsystem or applications programs. AE 2401 AVIONICS 25 BE (Aero)

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This is typically referred to as the bit bucket. All invalid commands are placed into the same bit bucket. For invalid transmit commands, the data transmitted is read from the bit bucket. Remember, the bus controller is not supposed to send these invalid commands. The second option is for the terminal to monitor for Illegal Commands. For most terminal designs, this is as simple as a look-up table with the T/R bit, subaddress, and word count fields supplying the address and the output being a single bit that indicates if the command is valid or not. If terminal implements Illegal Command detection and an illegal command is received, the terminal sets the Message Error bit in the status word and responds with the status word. Terminal Response Time The standard states that a remote terminal, upon validation of a transmit command word or a receive message (command word and all data words) shall transmit its status word to the bus controller. The response time is the amount of time the terminal has to transmit its status word. To allow for accurate measurements, the time frame is measured from the mid-crossing of the parity bit of the command word to the mid-crossing of the sync field of the status word. The minimum time is 4.0 _sec, the maximum time is 12.0 sec. However, the actual amount of dead time on the bus is 2 to 10 sec since half of the parity and sync waveforms are being transmitted during the measured time frame. The standard also specifies that the bus controller must wait a minimum of 14.0 sec for a status word response before determining that a terminal has failed to respond. In applications where long data buses are used or where other special conditions exist, it may be necessary to extend this time to 20.0 sec or greater. Inter-message Gap The bus controller must provide for a minimum of 4.0 sec between messages. Again, this time frame is measured from the mid-crossing of the parity bit of the last data word or the status word and the mid-crossing of the sync field of the next command word. The actual amount of dead time on the bus is 2 sec since half of the parity and sync waveforms are being transmitted during the measured time frame. The amount of time required by the bus controller to issue the next command is a function of the controller type (e.g., word, message, or frame). The gap typically associated with word controllers is between 40 and 100 sec. Message controllers typically can issue commands with a gap of 10 to 30 sec. But frame controllers are capable of issuing commands at the 4 sec rate and often must require a time delay to slow them down. Superseding Commands A remote terminal must always be capable of receiving a new command. This may occur while operating on a command on bus A and after the minimum intermessage gap, a new command appears, or if operating on bus A and a new command appears on bus B. This is referred to as a Superseding Command. A second valid command (the new command) shall cause the terminal to stop operating on the first command and start on the second. For dual redundant applications, this requirement implies that all terminals must, as a minimum, have two receivers, two decoders, and two sets of command word validation logic. 3. Discuss the evolution of avionics architecture and explain them in detail. (16) (Nov/Dec 2011) Ans: 4. Refer Part B Ques 4 Unit III in QB

(i) Explain word formats, data transfer format and coding format of MIL STD 1553B (8) (Nov/Dec 2011) Ans: Refer Part B Ques 1 and 6 Unit III in QB 26 BE (Aero)

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JEPPIAAR ENGINEERING COLLEGE

(ii) What are the main aspects of ARINC 429 differs from MIL STD 1553B and give a specification overview. (8) (Nov/Dec 2011) Ans:

**** use required data only

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5. (i) Discuss the different types of architectures used in modern integrated avionics of aircrafts. (8) (May/June 2012) Ans: Refer Part B Ques 4 Unit III in QB

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(ii) Explain in brief about the Pave Pillar conceptual architectures and partitioning of pave pillar system software. (8) (May/June 2012) Ans: TGA PAVE PILLAR The reason for using pave pillar : Pave Pillar is a USAF program to define the requirements and avionics architecture for fighter aircraft of the 1990s The Program Emphasizes Increased Information Fusion Higher levels and complexity of software Standardization for maintenance simplification Lower costs Backward and growth capability while making use of emerging technology VHSIC, Voice Recognition /synthesis and Artificial Intelligence Provides capability for rapid flow of data in, through and from the system as well as between and within the system Higher levels of avionics integration and resource sharing of sensor and computational capabilities Pilot plays the role of a WEAPON SYSTEM MANAGER as opposed to subsystem operator/information integrator Able to sustain operations with minimal support, fly successful mission day and night in any type of weather Face a numerically and technologically advanced enemy aircraft and defensive systems

ABOUT PAVE PILLR ARCHITECTURE: Component reliability gains Use of redundancy and resource sharing Application of fault tolerance Reduction of maintenance test and repair time Increasing crew station automation Enhancing stealth operation Wide use of common modules (HW & SW)) Ability to perform in-aircraft test and maintenance of avionics Use of VHSIC technology and Capability to operate over extended periods of time at austere, deployed locations and be maintainable without the Avionics Intermediate Shop AE 2401 AVIONICS 29 BE (Aero)

Prof.G.Prabhakaran 6.

JEPPIAAR ENGINEERING COLLEGE

(i) Explain MIL STD_1553 B data bus in detail bringing out clearly the bus architecture, protocol, word and message formats and coupling methods (12) (May/June 2012) Ans: Refer Part B Ques 1 Unit III in QB (ii) What are the similarities between ARINC 629 and MIL-STD-1553B? (4) (May/June 2012) Ans:

Similarites between ARINC 629 and MIL STD 1553B Bus architecture Encoding Transmission mode & coupling Media Mil-Std-1553 time division multiplex Bipolar, Manchester II voltage, direct or transformer shielded twisted wire pair ARINC 629 time division multiplex bipolar, doublets Manchester current coupling shielded twisted wire pair

NB: In-case if the ques is asked as comparison follow the answer given below:

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JEPPIAAR ENGINEERING COLLEGE UNIT IV - PART-A

1. List out the various types of display technologies used in cockpit display. (May/June 2012) Ans: Head Up Display (HUD) Helmet Mounted Display (HMD) Forward Looking InfraRed (FLIR) video picture through HUD Head position sensor Night Vision Goggles (NVG) - HMD HMDs & Virtual cockpit Colored Head Down Display (HDD) Multi-Function Display (MFD) with Multi Function Keys (MFK) 2. What is meant by glass cockpit? (May/June 2012) Ans: Refer Part A Ques 6 Unit IV in QB 3. What is meant by total FOV in HUD (Nov/Dec 2011 Arrear) Ans: A very important parameter with any HUD is the field of view (FOV), which should be as large as possible within the severe space constraints imposed by the cockpit geometry. A large horizontal FOV is particularly important to enable the pilot to look into turns when the HUD forms part of a night vision system and the only visibility the pilot has of the outside world is the FLIR image displayed on the HUD. 4. What are the advantages and versatility of CRTs that suit them to use as display devices in modern aircraft? (Nov/Dec 2011 ) Ans: Reasons for using CRTs as display devices in that suit them to use as display devices in modern aircrafts are: 1) Versatile Display Device: It overshadows the functional limitations of traditional Electromechanical Indicators. 2) Excellent Reliability 3) Active Display: It emits light rather than reflecting ambient light, provisions must be made to dim the CRT during night flying. 5. What are the advantages of HMD over HUD? (Nov/Dec 2011 ) Ans: Refer Part A Ques 23 Unit IV in QB 6. What do you mean by isolated word recognition in speech recognition method? (Nov/Dec 2011 Arrear) Ans: Isolated word recognition: The ability of the SR system to recognize a specific word in a stream of words. Isolated word recognition can be used as a trigger to place the SR system into an active standby mode, ready to accept input. SR system - Speech Recognition system

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JEPPIAAR ENGINEERING COLLEGE UNIT IV - PART-B

1. Discuss the following : (1) CRT (Nov/Dec 2011 Arrear) Ans:

(2) LCD

(8+8)

Refer Part B Unit IV in QB

2. Discuss the following: (i) Plasma panels (ii) MFK (iii) Functional elements of HUD (4+4+8) (Nov/Dec 2011 Arrear) Ans: Refer Part B Unit IV in QB

3. (i) What are roles of HUD in modern civil transport aircraft? (4) (Nov/Dec 2011) Ans: Refer Part B Unit IV in QB

(ii) Explain in detail how HMD works and improves the operational efficiency of a pilot? (12) (Nov/Dec 2011) Ans: 4. Refer Part B Unit IV in QB

(i) Explain DVI concept in cockpit and discuss the pros and cons of that system. (8) (Nov/Dec 2011) Ans: Refer Part B Unit IV in QB

(ii) Discuss in detail about HOTAS. (8) (Nov/Dec 2011) Ans: Refer Part B Unit IV in QB

5. (i) Compare and contrast the display technologies CRT, LED, LCD, EL and plasma panel. (8) (May/June 2012) Ans: Refer Part B Unit IV in QB

(ii) What are the various types of CRTs used in civil and military aircraft and explain them in detail? (8) (May/June 2012) Ans: Refer Part B Unit IV in QB

6.

(i) List the main types of display devices used in cockpit displays with the advantages of each of them. (8) (May/June 2012) Ans: Refer Part B Unit IV in QB (8) (May/June 2012)

(ii) Explain in brief about DVI and HOTAS. Ans:

Refer Part B Unit IV in QB

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JEPPIAAR ENGINEERING COLLEGE UNIT V PART -A

1. What are the inertial sensors used in the aircraft and list out the need for them? (May/June 2012) Ans: Gyroscopes (hereafter abbreviated to gyros) and accelerometers are known as inertial sensors. Need for inertial sensors: To exploit the property of inertia, namely the resistance to a change in momentum To sense angular motion in the case of the gyro To sense changes in linear motion in the case of the accelerometer To the control and guidance of an aircraft. As a essential elements to the spatial reference system or attitude/heading reference system (AHRS) and the inertial navigation system (INS). To determine the performance and accuracy of these systems and account for a major part of the system cost. 2. Why is the certificability very important for the civil avionics? (May/June 2012) Ans: Refer Part A Ques 11 Unit I in QB 3. How reliability and maintainability related to each other? (Nov/Dec 2011 ) Ans: Refer Part A Ques 39 Unit I in QB 4. What is meant by FBW control system and list out the advantages of FBW over conventional flight control system? (Nov/Dec 2011 ) Ans: FBW: A fly-by-wire system actually replaces manual control of the aircraft with an electronic interface. Advantages of FBW over conventional flight control system: Care free maneuvering characteristics Continuous automatic stabilization of the aircraft by computer control of the control surfaces Auto pilot integration Good consistent handling which is sensibly constant over a wide flight envelope and range of load conditions Enables a lighter, higher performance aircraft designed with relaxed stability 5. Differentiate between SIGINT and ELINT? (Nov/Dec 2011 Arrear) Ans: In ESM, where intelligence gathering is directed towards data on electromagnetic radiations it is known as signals intelligence (SIGINT), which may be divided into communications intelligence (COMINT) and electronic intelligence (ELINT). ELINT in particular has an input into EW in that it provides most of the background knowledge necessary for the effective design and operation of ESM, ECM, and EPM systems. 6. What is the principle of GPS? (May/June 2012) Ans: The basic principle of GPS is the same as for multi-DME. i.e. in three dimensions, if the distances of the vehicle from three known points is known then the position of the vehicle can be determined. AE 2401 AVIONICS 33 BE (Aero)

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GPS Principle In the GPS system the known points are the satellites (or space segment) and the ranges are determined by measuring the time of travel of an electromagnetic wave from the satellite to the receiver. Note that the navigation equipment is not required to transmit as is the case with DME. Thus the number of users is unlimited 7. What is GPS? (Nov/Dec 2011 Arrear) Ans: - The Global Positioning System (GPS) is a U.S. space-based global navigation satellite system. It provides reliable positioning, navigation, and timing services to worldwide users on a continuous basis in all weather, day and night, anywhere on or near the Earth. GPS is made up of three parts: between 24 and 32 satellites orbiting the Earth, four control and monitoring stations on Earth, and the GPS receivers owned by users. GPS satellites broadcast signals from space that are used by GPS receivers to provide three-dimensional location (latitude, longitude, and altitude) plus the time.

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JEPPIAAR ENGINEERING COLLEGE UNIT V - PART-B

1. Discuss the elements of electronic warfare with neat blocks (16) (Nov/Dec 2011 Arrear) Ans: 2. Discuss the following : Refer Part B Unit IV in QB (iii) Strap down INS (4+4+8)

(i) Common mode failure (ii) Fly by light (Nov/Dec 2011 Arrear)

Ans: Refer Part B Unit IV in QB 3. (i) Discuss about the various types of navigation used in an aircraft in detail. (8) (Nov/Dec 2011) Ans: Refer Part B Unit IV in QB (ii)What is FBW and explain its salient features with block diagram in comparison with the conventional flight control system? (8) (Nov/Dec 2011) 4. Ans: Refer Part B Unit IV in QB (i) Explain the principle of electronic warfare. (8) (Nov/Dec 2011) Ans: Refer Part B Unit IV in QB (ii) Describe the methods involved in certification (8) (Nov/Dec 2011) Ans: Refer Part B Unit IV in QB 6. (i) Explain the principle of electronic warfare. (8) (May/June 2012) Ans: Refer Part B Unit IV in QB (ii) Describe the methods involved in certification (8) (May/June 2012) Ans: Refer Part B Unit IV in QB 5. (i) Explain the concept of inertial navigation system and the inertial sensors in detail. (8) (May/June 2012) Ans: Refer Part B Unit IV in QB (ii) Explain briefly the operation of a GPS. (8) (May/June 2012) Ans: Refer Part B Unit IV in QB 6. (i) Describe a FBW flight control system and its characteristics and redundancy concepts in detail. (8) (May/June 2012) Ans: Refer Part B Unit IV in QB (ii) Explain in detail about Radar Electronic warfare and its salient features and its usage. (8) (May/June 2012) Ans: Refer Part B Unit IV in QB

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