VHDL

component OR2

library ieee;
use ieee.std_logic_1164.ALL;

port ( I0 : in
I1 : in

use ieee.numeric_std.ALL;

std_logic;
std_logic;

O : out std_logic);

library UNISIM;
use UNISIM.Vcomponents.ALL;

end component;
attribute BOX_TYPE of OR2 :
component is "BLACK_BOX";

entity afagfag is
port ( A : in

std_logic;

B : in

std_logic;

C : in

std_logic;

Y : out std_logic);
end afagfag;

begin
AkaliB : AND2
port map (I0=>B,
I1=>A,
O=>HasilAkaliB);

architecture BEHAVIORAL of afagfag is

attribute BOX_TYPE : string ;
signal HasilAkaliB

: std_logic;

signal HasilAtambahC : std_logic;

AtambahC : OR2
port map (I0=>C,
I1=>A,
O=>HasilAtambahC);

signal HasilCtambahB : std_logic;

signal HasilKurungAwal : std_logic;
component AND2
port ( I0 : in
I1 : in

std_logic;
std_logic;

CtambahB : OR2
port map (I0=>C,
I1=>B,
O=>HasilCtambahB);

O : out std_logic);
end component;
attribute BOX_TYPE of AND2 :
component is "BLACK_BOX";

HasilKaliAkhir : AND2
port map (I0=>HasilAtambahC,

I1=>HasilKurungAwal,
O=>Y);

Verilog
KurungAwal : OR2

`timescale 1ns / 1ps

port map (I0=>HasilCtambahB,

I1=>HasilAkaliB,
O=>HasilKurungAwal);

module sfagfg(A,
B,
C,

end BEHAVIORAL;

Y);

input A;
input B;
input C;
output Y;

wire HasilAkaliB;
wire HasilAtambahC;
wire HasilCtambahB;
wire HasilKurungAwal;

AND2 AkaliB (.I0(B),

.I1(A),
.O(HasilAkaliB));
OR2 AtambahC (.I0(C),
.I1(A),
.O(HasilAtambahC));
OR2 CtambahB (.I0(C),

.I1(B),
.O(HasilCtambahB));
AND2 HasilKaliAkhir
(.I0(HasilAtambahC),
.I1(HasilKurungAwal),
.O(Y));
OR2 KurungAwal (.I0(HasilCtambahB),
.I1(HasilAkaliB),
.O(HasilKurungAwal));
endmodule