Anda di halaman 1dari 1

EE3DSD - Digital Systems Design

Top down design of complex digital systems Requirements analysis, partitioning designs into dataflow and control systems, system design elaboration and modular design, design refinement, module and system simulation and verification, system implementation, test and verification. Timing problems, asynchronous I/O, state races, clock skews. Design Case Study including the dataflow model and FSM controller. Techniques for handling complexity; state machine reduction using symbolic manipulation, modular designs, re-entrant structures, linked state machines. Design of asynchronous circuits; asynchronous ASM's. Design for test: controllability and observability, serial test I/O. Scan path techniques, scan & structured design. Boundary scan, test access ports and controllers, JTAG.,Built in self test. Test sequence generation & fault detection. Computer Aided Design Electronic CAD (ECAD) design cycle: specification capture, behavioural simulation, circuit synthesis, gate level simulation, netlist abstraction, selection of target (e.g. specific FPGA /CPLD) and binding to target architecture, layout and routing, design rule compliance, back annotation and simulation, FPGA /CPLD implementation, circuit test and verification, closing the loop between simulation and test

Anda mungkin juga menyukai