VinRZ ISA Quick Reference Manual

FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

DATA PROCESSING

ADDITION DP.ADD.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 + # IMM

# IMM

DP.ADD.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 + RSRC2

<RSRC2>

DP.ADD.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 + (RSRC2 <SHIFT> # SHIFT_IMM)

<RSRC2> <SHIFT> # SHIFT_IMM

DP.ADD.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 + (RSRC2 <SHIFT> RSHIFT)

<RSRC2> <SHIFT> <RSHIFT>

ADDITION WITH DP.ADC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 + # IMM + CARRY

CARRY
# IMM

DP.ADC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 + RSRC2 + CARRY

<RSRC2>

DP.ADC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 + (RSRC2 <SHIFT> # SHIFT_IMM) +

<RSRC2> <SHIFT> # SHIFT_IMM CARRY

DP.ADC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 + (RSRC2 <SHIFT> RSHIFT) + CARRY

<RSRC2> <SHIFT> <RSHIFT>

SUBTRACTION DP.SUB.{cond}.{F} <RDEST>, <RSRC1>, # N, Z, C, V RDEST = RSRC1 - # IMM

IMM

DP.SUB.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 - RSRC2

<RSRC2>

DP.SUB.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 - (RSRC2 <SHIFT> # SHIFT_IMM)

<RSRC2> <SHIFT> # SHIFT_IMM

DP.SUB.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 - (RSRC2 <SHIFT> RSHIFT)

<RSRC2> <SHIFT> <RSHIFT>

SUBTRACTION DP.SBC.{cond}.{F} <RDEST>, <RSRC1>, # N, Z, C, V RDEST = RSRC1 - # IMM - (~CARRY)

WITH BORROW
IMM

DP.SBC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 - RSRC2 - (~CARRY)

<RSRC2>

DP.SBC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 - (RSRC2 <SHIFT> # SHIFT_IMM) -

<RSRC2> <SHIFT> # SHIFT_IMM (~CARRY)

DP.SBC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC1 - (RSRC2 <SHIFT> RSHIFT) -

<RSRC2> <SHIFT> <RSHIFT> (~CARRY)
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

REVERSE DP.RSUB.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = # IMM - RSRC1

SUBTRACTION
# IMM

DP.RSUB.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC2 - RSRC1

<RSRC2>

DP.RSUB.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = (RSRC2 <SHIFT> # SHIFT_IMM) - RSRC1

<RSRC2> <SHIFT> # SHIFT_IMM

DP.RSUB.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = (RSRC2 <SHIFT> RSHIFT) - RSRC1

<RSRC2> <SHIFT> <RSHIFT>

REVERSE DP.RSBC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = # IMM - RSRC1 - (~CARRY)

SUBTRACTION
WITH BORROW # IMM

DP.RSBC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = RSRC2 - RSRC1 - (~CARRY)

<RSRC2>

DP.RSBC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = (RSRC2 <SHIFT> # SHIFT_IMM) - RSRC1 -

<RSRC2> <SHIFT> # SHIFT_IMM (~CARRY)

DP.RSBC.{cond}.{F} <RDEST>, <RSRC1>, N, Z, C, V RDEST = (RSRC2 <SHIFT> RSHIFT) - RSRC1 -

<RSRC2> <SHIFT> <RSHIFT> (~CARRY)

AND IMM N,Z,C RDEST = RSRC1 & # IMM

DP.AND.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 & RSRC2

<RSRC2>

DP.AND.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 & (RSRC2 <SHIFT> # SHIFT_IMM)
<RSRC2> <SHIFT> # SHIFT_IMM

DP.AND.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 & (RSRC2 <SHIFT> RSHIFT)
<RSRC2> <SHIFT> <RSHIFT>

EXCLUSIVE-OR DP.EOR.{cond}.{F} <RDEST>, <RSRC1>, # N,Z,C RDEST = RSRC1 ^ # IMM

IMM

DP.EOR.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 ^ RSRC2

<RSRC2>

DP.EOR.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 ^ (RSRC2 <SHIFT> # SHIFT_IMM)

<RSRC2> <SHIFT> # SHIFT_IMM

DP.EOR.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 ^ (RSRC2 <SHIFT> RSHIFT)

<RSRC2> <SHIFT> <RSHIFT>
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

INCLUSIVE-OR DP.ORR.{cond}.{F} <RDEST>, <RSRC1>, # N,Z,C RDEST = RSRC1 | # IMM

IMM

DP.ORR.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 | RSRC2

<RSRC2>

DP.ORR.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 | (RSRC2 <SHIFT> # SHIFT_IMM)

<RSRC2> <SHIFT> # SHIFT_IMM

DP.ORR.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 | (RSRC2 <SHIFT> RSHIFT)

<RSRC2> <SHIFT> <RSHIFT>

CLEAR BIT DP.CLRB.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 & ~(# IMM)
# IMM

DP.CLRB.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 & ~(RSRC2)

<RSRC2>

DP.CLRB.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 & ~(RSRC2 <SHIFT> # SHIFT_IMM)
<RSRC2> <SHIFT> # SHIFT_IMM

DP.CLRB.{cond}.{F} <RDEST>, <RSRC1>, N,Z,C RDEST = RSRC1 & ~(RSRC2 <SHIFT> RSHIFT)
<RSRC2> <SHIFT> <RSHIFT>

MOVE DP.Mov.{cond}.{F} <RDEST>, # IMM N,Z,C RDEST = # IMM

DP.Mov.{cond}.{F} <RDEST>, <RSRC2> N,Z,C RDEST = RSRC2

DP.Mov.{cond}.{F} <RDEST>, <RSRC2> N,Z,C RDEST = (RSRC2 <SHIFT> # SHIFT_IMM)

<SHIFT> # SHIFT_IMM

DP.Mov.{cond}.{F} <RDEST>, <RSRC2> N,Z,C RDEST = (RSRC2 <SHIFT> RSHIFT)

<SHIFT> <RSHIFT>

NEGATION DP.NOT.{cond}.{F} <RDEST>, # IMM N,Z,C RDEST = ~(# IMM)

DP.NOT.{cond}.{F} <RDEST>, <RSRC2> N,Z,C RDEST = ~RSRC2

DP.NOT.{cond}.{F} <RDEST>, <RSRC2> N,Z,C RDEST = ~(RSRC2 <SHIFT> # SHIFT_IMM)

<SHIFT> # SHIFT_IMM

DP.NOT.{cond}.{F} <RDEST>, <RSRC2> N,Z,C RDEST = ~(RSRC2 <SHIFT> RSHIFT)

<SHIFT> <RSHIFT>

COMPARE DP.CPN.{cond}.{F} <RSRC1>, # IMM N, Z, C, V Tmp = RSRC1 + # IMM

NEGATED
DP.CPN.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C, V Tmp = RSRC1 + RSRC2

DP.CPN.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C, V Tmp = RSRC1 + (RSRC2 <SHIFT> # SHIFT_IMM)

<SHIFT> # SHIFT_IMM

DP.CPN.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C, V Tmp = RSRC1 + (RSRC2 <SHIFT> RSHIFT)

<SHIFT> <RSHIFT>
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

COMPARE DP.CP.{cond}.{F} <RSRC1>, # IMM N, Z, C, V Tmp = RSRC1 - # IMM

DP.CP.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C, V Tmp = RSRC1 - RSRC2

DP.CP.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C, V Tmp = RSRC1 - (RSRC2 <SHIFT> # SHIFT_IMM)

<SHIFT> # SHIFT_IMM

DP.CP.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C, V Tmp = RSRC1 - (RSRC2 <SHIFT> RSHIFT)

<SHIFT> <RSHIFT>

TEST DP.TST.{cond}.{F} <RSRC1>, # IMM N, Z, C Tmp = RSRC1 & # IMM

DP.TST.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C Tmp = RSRC1 & RSRC2

DP.TST.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C Tmp = RSRC1 & (RSRC2 <SHIFT> # SHIFT_IMM)

<SHIFT> # SHIFT_IMM

DP.TST.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C Tmp = RSRC1 & (RSRC2 <SHIFT> RSHIFT)

<SHIFT> <RSHIFT>

TEST DP.TEQ.{cond}.{F} <RSRC1>, # IMM N, Z, C Tmp = RSRC1 ^ # IMM

EQUIVALENCE
DP.TEQ.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C Tmp = RSRC1 ^ RSRC2

DP.TEQ.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C Tmp = RSRC1 ^ (RSRC2 <SHIFT> # SHIFT_IMM)

<SHIFT> # SHIFT_IMM

DP.TEQ.{cond}.{F} <RSRC1>, <RSRC2> N, Z, C Tmp = RSRC1 ^ (RSRC2 <SHIFT> RSHIFT)

<SHIFT> <RSHIFT>

MISCELLANEOUS DATA PROCESSING

MULTIPLY DP.MUL .{cond} <ROP_1>, <ROP_A>, ----- ROP_1 = (ROP_A * ROP_B) [31:0]
<ROP_B>

MULTIPLY DP.MA.{cond} <ROP_1>, <ROP_2>, ----- ROP_1 = (ROP_A * ROP_B) [31:0] + ROP_2
ACCUMULATE
<ROP_A>, <ROP_B>

UNSIGNED DP.DMULU.{cond} <ROP_1>, <ROP_2>, ----- {ROP_1, ROP_2} = (ROP_A * ROP_B)

MULTIPLY LONG
<ROP_A>, <ROP_B>

UNSIGNED MULTI- DP.DMAU.{cond} <ROP_1>, <ROP_2>, ----- {ROP_1, ROP_2} = (ROP_A * ROP_B) +
PLY ACCUMU-
LATE LONG <ROP_A>, <ROP_B> {ROP_1,ROP_2}

SIGNED MULTI- DP.DMULS.{cond} <ROP_1>, <ROP_2>, ----- {ROP_1, ROP_2} = (ROP_A * ROP_B)
PLY LONG
<ROP_A>, <ROP_B>

SIGNED MULTI- DP.DMAS.{cond} <ROP_1>, <ROP_2>, ----- {ROP_1, ROP_2} = (ROP_A * ROP_B) +
PLY ACCUMU-
LATE LONG <ROP_A>, <ROP_B> {ROP_1,ROP_2}

DSP DATA PROCESSING

SATURATED SP.SAT.ADD.{cond} <ROP_1>, <ROP_A>, Q ROP_1 = ROP_A + ROP_B

ADDITION
<ROP_B>
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

SATURATED DOU- SP.SAT.DADD.{cond} <ROP_1>, Q ROP_1 = (2 * ROP_A) + ROP_B

BLING & ADDI-
TION <ROP_A>, <ROP_B>

SATURATED SUB- SP.SAT.SUB.{cond} <ROP_1>, <ROP_A>, Q ROP_1 = ROP_A - ROP_B

TRACTION
<ROP_B>

SATURATED DOU- SP.SAT.DSUB.{cond} <ROP_1>, Q ROP_1 = (2 * ROP_A) - ROP_B

BLING & SUB-
TRACTION <ROP_A>, <ROP_B>

SIGNED MULTI- SP.MULS.HH.{cond} <ROP_1>, <ROP_A>, ----- ROP_1 = ROP_A(16-bit) * ROP_B(16-bit)

PLY (16X16)
<ROP_B>

SIGNED MULTI- SP.MAS.HH.{cond} <ROP_1>, <ROP_2>, Q ROP_1 = (ROP_A(16-bit) * ROP_B(16-bit)) + ROP_2

PLY ACCUMU-
LATE (16X16) <ROP_A>, <ROP_B>

SIGNED MULTI- SP.MULS.WH.{cond} <ROP_1>, <ROP_A>, ----- ROP_1 = (ROP_A * ROP_B(16-bit)) [47:16]
PLY (32X16)
<ROP_B>

SIGNED MULTI- SP.MAS.WH.{cond} <ROP_1>, <ROP_2>, Q ROP_1 = ((ROP_A * ROP_B(16-bit)) + ROP_2)

PLY ACCUMU-
LATE(32X16) <ROP_A>, <ROP_B> [47:16]

SIGNED MULTI- SP.MAS.HH.{cond} <ROP_1>, <ROP_2>, ----- {ROP_1, ROP_2} = (ROP_A(16-bit) * ROP_B(16-
PLY ACCUMU-
LATE LONG (16X16) <ROP_A>, <ROP_B> bit)) + {ROP_1,ROP_2}

COUNT LEADING SP.CLZ .{conf} <ROP_1>, <ROP_2> ----- ROP_1 = No of Leading 0’s in ROP_2 content
ZEROS

COUNT LEADING SP.CLO.{conf} <ROP_1>, <ROP_2> ----- ROP_1 = No of Leading 1’s in ROP_2 content
ONES

BYTE REVERSE SP.BYRE.{cond} <ROP_1>, <ROP_2> ----- ROP_1 = {ROP_2 [7:0], ROP_2 [16:8], ROP_2
[23:16], ROP_2 [31:24]}

BIT REVERSE SP.BIRE.{cond} <ROP_1>, <ROP_2> ----- ROP_1 = ROP_2 [0:31]

STATUS REGISTER ACCESS INSTRUCTION

CURRENT STATUS SR.CSR.{cond} <RDEST> ----- RDEST = CSR

REGISTER READ
INSTRUCTION

SAVED STATUS SR.SSR.{cond} <RDEST> ----- RDEST = SSR

REGISTER READ
INSTRUCTION
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

CURRENT STATUS sw.CSR.{cond} <field_mask>, #IMM ----- if (field_mask == ALL)

REGISTER WRITE
INSTRUCTION
CSR = #IMM else
if (field_mask == CF)
CSR = {CSR[31:16, #IMM [16:0]}
else if (field_mask == FF)
CSR = {#IMM[31:16, CSR[16:0]}

sw.CSR.{cond} <field_mask>, <ROP_B> ----- if (field_mask == ALL)

CSR = ROP_B else
if (field_mask == CF)
CSR = {CSR[31:16], ROP_B [16:0]}
else if (field_mask == FF)
CSR = {ROP_B[31:16, CSR[16:0]}

sw.CSR.{cond} <field_mask>, <ROP_B> ----- if (field_mask == ALL)

<SHIFT> # SHIFT_IMM CSR = (ROP_B <SHIFT> # SHIFT_IMM)
else if (field_mask == CF)
CSR = {CSR[31:16],
(ROP_B <SHIFT> # SHIFT_IMM) [16:0]} else if
(field_mask == FF)
CSR = {(ROP_B <SHIFT> # SHIFT_IMM)[31:16],
CSR[16:0]}

LOAD AND STORE INSTRUCTION

LOAD WORD (POST M{p}.LD.W.{cond} <RDEST>, [<ROP_A>], ----- RDEST = MEM[ROP_A],

INDEX)
+/- #IMM ROP_A = ROP_A + / - #IMM

M{p}.LD.W.{cond} <RDEST>, [<ROP_A>], ----- RDEST = MEM[ROP_A],

+/- <ROP_B> ROP_A = ROP_A + / - ROP_B

M{p}.LD.W.{cond} <RDEST>, [<ROP_A>], ----- RDEST = MEM[ROP_A],

+/- <ROP_B> <SHIFT> # SHIFT_IMM ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD WORD M{p}.LD.W.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - #IMM]

(IMMEDIATE/REG-
ISTER OFFSET) +/- #IMM]

M{p}.LD.W.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - ROP_B]

+/- <ROP_B>]

M{p}.LD.W.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM] SHIFT_IMM)]

LOAD WORD (PRE M{p}.LD.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A] = ROP_C,

INDEX)
+/- #IMM]* ROP_A = ROP_A + / - #IMM

M{p}.LD.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A] = ROP_C,

+/- <ROP_B>]* ROP_A = ROP_A + / - ROP_B

M{p}.LD.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A] = ROP_C,

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

STORE WORD M{p}.ST.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A + / - #IMM] = ROP_C

(IMMEDIATE/REG-
ISTER OFFSET) +/- #IMM]

M{p}.ST.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A + / - ROP_B] = ROP_C

+/- <ROP_B>]

M{p}.ST.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM] SHIFT_IMM)] = ROP_C

STORE WORD (PRE M{p}.ST.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A + / - #IMM] = ROP_C,
INDEX)
+/- #IMM]* ROP_A = ROP_A + / - #IMM

M{p}.ST.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A + / - ROP_B] = ROP_C,

+/- <ROP_B>]* ROP_A = ROP_A + / - ROP_B

M{p}.ST.W.{cond} <RDEST>, [<ROP_A>, ----- MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* SHIFT_IMM)] = ROP_C,
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD DOUBLE M{p}.LD.D.{cond} <RDEST>, [<ROP_A>], ----- RDEST = MEM[ROP_A],

WORD (POST
INDEX) +/- #IMM R(DEST+1) = MEM[ROP_A + 4],
ROP_A = ROP_A + / - #IMM

M{p}.LD.D.{cond} <RDEST>, [<ROP_A>], ----- RDEST = MEM[ROP_A],

+/- <ROP_B> R(DEST+1) = MEM[ROP_A + 4],
ROP_A = ROP_A + / - ROP_B

M{p}.LD.D.{cond} <RDEST>, [<ROP_A>], ----- RDEST = MEM[ROP_A],

+/- <ROP_B> <SHIFT> # SHIFT_IMM R(DEST+1) = MEM[ROP_A + 4],
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD DOUBLE M{p}.LD.D.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - #IMM],

WORD (IMMEDI-
ATE/REGISTER +/- #IMM] R(DEST+1) = MEM[ROP_A + / - #IMM + 4]
OFFSET)
M{p}.LD.D.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - ROP_B],
+/- <ROP_B>] R(DEST+1) = MEM[ROP_A + / - ROP_B + 4]

M{p}.LD.D.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM] SHIFT_IMM)],
R(DEST+1) = MEM[ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM) + 4]
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

LOAD DOUBLE M{p}.LD.D.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - #IMM],

WORD (PRE INDEX)
+/- #IMM]* R(DEST+1) = MEM[ROP_A + / - #IMM + 4],
ROP_A = ROP_A + / - #IMM

M{p}.LD.D.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - ROP_B],

+/- <ROP_B>]* R(DEST+1) = MEM[ROP_A + / - ROP_B + 4],
ROP_A = ROP_A + / - ROP_B

M{p}.LD.D.{cond} <RDEST>, [<ROP_A>, ----- RDEST = MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* SHIFT_IMM)],
R(DEST+1) = MEM[ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM) + 4]
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD DOUBLE M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C,

STORE (POST
INDEX) +/- #IMM MEM[ROP_A + 4] = R(OP_C+1),
ROP_A = ROP_A + / - #IMM

M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C,

+/- <ROP_B> MEM[ROP_A + 4] = R(OP_C+1),
ROP_A = ROP_A + / - ROP_B

M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C,

+/- <ROP_B> <SHIFT> # SHIFT_IMM MEM[ROP_A + 4] = R(OP_C+1),
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD DOUBLE M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - #IMM] = ROP_C,

STORE (IMMEDI-
ATE/REGISTER +/- #IMM] MEM[ROP_A + / - #IMM + 4] = R(OP_C+1)
OFFSET)
M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - ROP_B] = ROP_C,
+/- <ROP_B>] MEM[ROP_A + / - ROP_B + 4] = R(OP_C +1)

M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM] SHIFT_IMM)] = ROP_C,
MEM[ROP_A + / - (ROP_B <SHIFT> # SHIFT_IMM)
+ 4] = R(OP_C+1)
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

LOAD DOUBLE M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - #IMM] = ROP_C,

STORE (PRE
INDEX) +/- #IMM]* MEM[ROP_A + / - #IMM + 4] = R(OP_C+1),
ROP_A = ROP_A + / - #IMM

M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - ROP_B] = ROP_C,

+/- <ROP_B>]* MEM[ROP_A + / - ROP_B + 4] = R(OP_C +1),
ROP_A = ROP_A + / - ROP_B

M{p}.ST.D.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* SHIFT_IMM)] = ROP_C,
MEM[ROP_A + / - (ROP_B <SHIFT> # SHIFT_IMM)
+ 4] = R(OP_C+1),
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD BYTE (POST M{p}.LD.B.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Zero Extended (MEM[ROP_A]),
INDEX)
+/- #IMM ROP_A = ROP_A + / - #IMM

M{p}.LD.B.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Zero Extended (MEM[ROP_A]),

+/- <ROP_B> ROP_A = ROP_A + / - ROP_B

M{p}.LD.B.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Zero Extended (MEM[ROP_A]),

+/- <ROP_B> <SHIFT> # SHIFT_IMM ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD BYTE M{p}.LD.B.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -
(IMMEDIATE/REG-
ISTER OFFSET) +/- #IMM] #IMM])

M{p}.LD.B.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -

+/- <ROP_B>] ROP_B])

M{p}.LD.B.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -

+/- <ROP_B> <SHIFT> # SHIFT_IMM] (ROP_B <SHIFT> # SHIFT_IMM)])

LOAD BYTE (PRE M{p}.LD.B.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -
INDEX)
+/- #IMM]* #IMM]), ROP_A = ROP_A + / - #IMM

M{p}.LD.B.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -

+/- <ROP_B>]* ROP_B]), ROP_A = ROP_A + / - ROP_B

M{p}.LD.B.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* (ROP_B <SHIFT> # SHIFT_IMM)]),
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD SIGNED M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Sign Extended (MEM[ROP_A]),
BYTE (POST
INDEX) +/- #IMM ROP_A = ROP_A + / - #IMM

M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Sign Extended (MEM[ROP_A]),

+/- <ROP_B> ROP_A = ROP_A + / - ROP_B

M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Sign Extended (MEM[ROP_A]),

+/- <ROP_B> <SHIFT> # SHIFT_IMM ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

LOAD SIGNED M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -
BYTE (IMMEDI-
ATE/REGISTER +/- #IMM] #IMM])
OFFSET)
M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -
+/- <ROP_B>] ROP_B])

M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -

+/- <ROP_B> <SHIFT> # SHIFT_IMM] (ROP_B <SHIFT> # SHIFT_IMM)])

LOAD SIGNED M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -
BYTE (PRE INDEX)
+/- #IMM]* #IMM]), ROP_A = ROP_A + / - #IMM

M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -

+/- <ROP_B>]* ROP_B]), ROP_A = ROP_A + / - ROP_B

M{p}.LD.SB.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* (ROP_B <SHIFT> # SHIFT_IMM)]),
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

STORE BYTE (POST M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C[7:0],

INDEX)
+/- #IMM ROP_A = ROP_A + / - #IMM

M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C[7:0],

+/- <ROP_B> ROP_A = ROP_A + / - ROP_B

M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C[7:0],

+/- <ROP_B> <SHIFT> # SHIFT_IMM ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

STORE BYTE M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - #IMM] = ROP_C [7:0]
(IMMEDIATE/REG-
ISTER OFFSET) +/- #IMM]

M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - ROP_B] = ROP_C [7:0]

+/- <ROP_B>]

M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM] SHIFT_IMM)] = ROP_C [7:0]

STORE BYTE (PRE M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - #IMM] = ROP_C [7:0],
INDEX)
+/- #IMM]* ROP_A = ROP_A + / - #IMM

M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - ROP_B] = ROP_C [7:0],

+/- <ROP_B>]* ROP_A = ROP_A + / - ROP_B

M{p}.ST.B.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* SHIFT_IMM)] = ROP_C [7:0],
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

LOAD HALFWORD M{p}.LD.H.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Zero Extended (MEM[ROP_A]),
(POST INDEX)
+/- #IMM ROP_A = ROP_A + / - #IMM

M{p}.LD.H.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Zero Extended (MEM[ROP_A]),

+/- <ROP_B> ROP_A = ROP_A + / - ROP_B

M{p}.LD.H.{cond} <RDEST>, [<ROP_A>], ----- RDEST = Zero Extended (MEM[ROP_A]),

+/- <ROP_B> <SHIFT> # SHIFT_IMM ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD HALFWORD M{p}.LD.H.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -
(IMMEDIATE/REG-
ISTER OFFSET) +/- #IMM] #IMM])

M{p}.LD.H.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -

+/- <ROP_B>] ROP_B])

M{p}.LD.H.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -

+/- <ROP_B> <SHIFT> # SHIFT_IMM] (ROP_B <SHIFT> # SHIFT_IMM)])

LOAD HALFWORD M{p}.LD.H.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -
(PRE INDEX)
+/- #IMM]* #IMM]), ROP_A = ROP_A + / - #IMM

M{p}.LD.H.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -

+/- <ROP_B>]* ROP_B]), ROP_A = ROP_A + / - ROP_B

M{p}.LD.H.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Zero Extended (MEM[ROP_A + / -

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* (ROP_B <SHIFT> # SHIFT_IMM)]),
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

LOAD SIGNED M{p}.LD.SH.{cond} <RDEST>, ----- RDEST = Sign Extended (MEM[ROP_A]),

HALFWORD (POST
INDEX) [<ROP_A>], +/- #IMM ROP_A = ROP_A + / - #IMM

M{p}.LD.SH.{cond} <RDEST>, ----- RDEST = Sign Extended (MEM[ROP_A]),

[<ROP_A>], +/- <ROP_B> ROP_A = ROP_A + / - ROP_B

M{p}.LD.SH.{cond} <RDEST>, ----- RDEST = Sign Extended (MEM[ROP_A]),

[<ROP_A>], +/- <ROP_B> <SHIFT> # ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM SHIFT_IMM)

LOAD SIGNED M{p}.LD.SH.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -
HALFWORD
(IMMEDIATE/REG- +/- #IMM] #IMM])
ISTER OFFSET)
M{p}.LD.SH.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -
+/- <ROP_B>] ROP_B])

M{p}.LD.SH.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -

+/- <ROP_B> <SHIFT> # SHIFT_IMM] (ROP_B <SHIFT> # SHIFT_IMM)])
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

LOAD SIGNED M{p}.LD.SH.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -
HALFWORD (PRE
INDEX) +/- #IMM]* #IMM]), ROP_A = ROP_A + / - #IMM

M{p}.LD.SH.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -

+/- <ROP_B>]* ROP_B]), ROP_A = ROP_A + / - ROP_B

M{p}.LD.SH.{cond} <RDEST>, [<ROP_A>, ----- RDEST = Sign Extended (MEM[ROP_A + / -

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* (ROP_B <SHIFT> # SHIFT_IMM)]),
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

STORE HALFWORD M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C[16:0],

(POST INDEX)
+/- #IMM ROP_A = ROP_A + / - #IMM

M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C[16:0],

+/- <ROP_B> ROP_A = ROP_A + / - ROP_B

M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>], ----- MEM[ROP_A] = ROP_C[16:0],

+/- <ROP_B> <SHIFT> # SHIFT_IMM ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

STORE HALFWORD M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - #IMM] = ROP_C [16:0]
(IMMEDIATE/REG-
ISTER OFFSET) +/- #IMM]

M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - ROP_B] = ROP_C [16:0]

+/- <ROP_B>]

M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM] SHIFT_IMM)] = ROP_C [16:0]

STORE HALFWORD M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - #IMM] = ROP_C [16:0],
(PRE INDEX)
+/- #IMM]* ROP_A = ROP_A + / - #IMM

M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - ROP_B] = ROP_C [16:0],

+/- <ROP_B>]* ROP_A = ROP_A + / - ROP_B

M{p}.ST.H.{cond} <ROP_C>, [<ROP_A>, ----- MEM[ROP_A + / - (ROP_B <SHIFT> #

+/- <ROP_B> <SHIFT> # SHIFT_IMM]* SHIFT_IMM)] = ROP_C [16:0],
ROP_A = ROP_A + / - (ROP_B <SHIFT> #
SHIFT_IMM)

MULIPLE LOAD M.MLD.{ia|ib| Da| Db}.{cond} -----

INSTRUCTION
<ROP_A>{*}, <Register_list>{!}

MULIPLE STORE M.MST.{ia|ib| Da| Db}.{cond} -----

INSTRUCTION
<ROP_A>{*}, <Register_list>{!}
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

SEMAPHORE SM.SWP.B.{cond} <ROP_2>, <ROP_C>, ----- ROP_2 = Zero Extended (MEM[ROP_1]),

INSTRUCTION
<ROP_1> MEM[ROP_1] = ROP_C

SM.SWP.H.{cond} <ROP_2>, <ROP_C>, ----- ROP_2 = Zero Extended (MEM[ROP_1]),

<ROP_1> MEM[ROP_1] = ROP_C

SM.SWP.W.{cond} <ROP_2>, <ROP_C>, ----- ROP_2 = MEM[ROP_1],

<ROP_1> MEM[ROP_1] = ROP_C

MEMORY MOVE M.Mov.{cond} <ROP_A>, <ROP_A2> ----- MEM[ROP_A2] = MEM[ROP_A]

INSTRUCTION

MEMORY READ M.BIS.{cond} <ROP_A>, #<bit_pos> ----- Set the bit specified by <bit_pos> in
MODIFY WRITE
INSTRUCTION
MEM[ROP_A]

M.BIC.{cond} <ROP_A>, #<bit_pos> ----- Clear the bit specified by <bit_pos> in

MEM[ROP_A]

BRANCH INSTRUCTIONS

IMMEDIATE BR.{l}.IMM.{cond} <target_addr> ----- R16 = R16 + Sign Extended 24-bit Immediate
BRANCH INSTRUC-
TION value.

REGISTER BR.{l}.Reg.{cond} <ROP_B> ----- R16 = ROP_B & 0xFFFF_FFFC

BRANCH INSTRUC-
TION

PROCEDURE-RETURN INSTRTUCTION

RESTORE RESTORE,{cond} ----- R16 = R16.

INSTRUCTION
CSR = SSR

EXCEPTION GENERATING INSTRUCTION

SOFTWARE INTER- EX.SYS.{cond} #IMM_24 -----

RUPT

BREAKPOINT EX.BKPT.{cond} #IMM_16 -----

INSTRUCTION

UNDEFINED EX.UND.{cond} -----

INSTRUCTION

AUXILIARY PROCESSOR INSTRUCTION

AP LOAD WORD AP.LD.{cond} <apnum>, <RAP_DEST>, ----- RAP_DEST = MEM[ROP_A],

(POST INDEX)
[<ROP_A>], +/- #IMM ROP_A = ROP_A + / - #IMM

AP.LD.{cond} <apnum>, <RAP_DEST>, ----- RAP_DEST = MEM[ROP_A],

[<ROP_A>], +/- <ROP_B> ROP_A = ROP_A + / - ROP_B

AP LOAD WORD AP.LD.{cond} <apnum>, <RAP_DEST>, ----- RAP_DEST = MEM[ROP_A + / - #IMM]

(IMMEDIATE/REG-
ISTER OFFSET) [<ROP_A>, +/- #IMM]

AP.LD.{cond} <apnum>, <RAP_DEST>, ----- RAP_DEST = MEM[ROP_A + / - ROP_B]

[<ROP_A>, +/- <ROP_B>]
 FLAG
OPERATION ASSEMBLY SYNTAX ACTION
UPDATES

AP LOAD WORD AP.LD.{cond} <apnum>, <RAP_DEST>, ----- RAP_DEST = MEM[ROP_A + / - #IMM],

(PRE INDEX)
[<ROP_A>, +/- #IMM] ROP_A = ROP_A + / - #IMM

AP.LD.{cond} <apnum>, <RAP_DEST>, ----- RAP_DEST = MEM[ROP_A + / - ROP_B],

[<ROP_A>, +/- <ROP_B>]* ROP_A = ROP_A + / - ROP_B

AP STORE WORD AP.ST.{cond} <apnum>, <RAP_SRC>, ----- MEM[ROP_A] = RAP_SRC,

(POST INDEX)
[<ROP_A>], +/- #IMM ROP_A = ROP_A + / - #IMM

AP.ST.{cond} <apnum>, <RAP_SRC>, ----- MEM[ROP_A] = RAP_SRC,

[<ROP_A>], +/- <ROP_B> ROP_A = ROP_A + / - ROP_B

AP STORE WORD AP.ST.{cond} <apnum>, <RAP_SRC>, ----- MEM[ROP_A + / - #IMM] = RAP_SRC

(IMMEDIATE/REG-
ISTER OFFSET) [<ROP_A>, +/- #IMM]

AP.ST.{cond} <apnum>, <RAP_SRC>, ----- MEM[ROP_A + / - ROP_B] = RAP_SRC

[<ROP_A>, +/- <ROP_B>]

AP STORE WORD AP.ST.{cond} <apnum>, <RAP_SRC>, ----- MEM[ROP_A + / - #IMM] = RAP_SRC,

(PRE INDEX)
[<ROP_A>, +/- #IMM] ROP_A = ROP_A + / - #IMM

AP.ST.{cond} <apnum>, <RAP_SRC>, ----- MEM[ROP_A + / - ROP_B] = RAP_SRC,

[<ROP_A>, +/- <ROP_B>]* ROP_A = ROP_A + / - ROP_B

AP DATA PROCESS- AP.DP.{cond} <apnum>, <opcode>, -----

ING INSTRUCTION
<RAP_DEST>, <RAP_SRC1>, <RAP_SRC2>

AP DATA MOVE AP.RAR.{cond} <apnum>, <opcode1>, ----- RDEST = RAP_SRC

INSTRUCTION
<RDEST>, <RAP_SRC>, <opcode2>

AP.WAR.{cond} <apnum>, <opcode1>, ----- RAP_DEST = RSRC

<RSRC>, <RAP_DEST>, <opcode2>

AP.RAR.D.{cond} <apnum>, <opcode>, ----- RDEST1 = RAP_SRC,

<RDEST1>, <RDEST2>, <RAP_SRC> RDEST2 = RAP_SRC+1

AP.WAR.D.{cond} <apnum>, <opcode>, ----- RAP_DEST = RSRC1,

<RSRC1>, <RSRC2>, <RAP_DEST> RAP_DEST+1 = RSRC2