Scheme Dell Inspiron n5110 m5110 Dq15 Wistron Queen 15 Intel Discrete Uma Sandy Bridge

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Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
QUEEN 15
A00
Cover Page
A3
1 108
Tuesday, J anuary04, 2011
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Cover Page
A3
1 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Cover Page
A3
1 108
<Core Design>
Intel PCH
2011-01-04
REV : A00
Discrete/UMA Schematics Document
Sandy Bridge
DY :None Installed
UMA:UMA ONLY installed
DN15: ONLY FOR DN15 installed.
DQ15:ONLY FOR DQ15 installed.
PSL: KBC795 PSL circuit for 10mW solution installed.
10mW: External circuit for 10mW solution installed.
MUXLESS:MUXLESS solution installed.
OPTIMUS:OPTIMUS solution installed.
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Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Block Diagram
2 108 Tuesday, J anuary04, 2011
<Core Design>
A3
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Block Diagram
<Core Design>
A3
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Block Diagram
<Core Design>
A3
INPUTS
VGA
DCBATOUT
OUTPUTS
26
RT8208B
VGA_CORE
0D75V_S0
3D3V_AUX_S5
ISL95831HRTZ
INPUTS
VCC_CORE
OUTPUTS
SYSTEM DC/DC
TPS51216RUKR
DDR_VREF_S3
OUTPUTS
CPU DC/DC
DCBATOUT
1D5V_S3
INPUTS
TPS51123RGER
DCBATOUT 5V_S5
OUTPUTS
3D3V_S5
TPS51218
OUTPUTS
SYSTEM DC/DC
INPUTS
DCBATOUT
INPUTS
SYSTEM DC/DC
DCBATOUT
1D5V_S0
OUTPUTS
OUTPUTS
SYSTEM DC/DC
INPUTS
BQ24745
INPUTS
TI CHARGER
DCBATOUT +PBATT
5V_AUX_S5
+DC_IN_S5
INPUTS
SYSTEM DC/DC
5V_S0
OUTPUTS
26
5V_S5
TPS51311
3D3V_S5
3D3V_S0 3D3V_S5
1D8V_S0
DCBATOUT
PCB LAYER
L1:Top
L2:VCC
L3:Signal
VCC_GFXCORE
1D5V_S3
ISL95831HRTZ
SYSTEM DC/DC
Switches
INPUTS OUTPUTS
1D05V_VTT
15V_S5
42~43
45
41
46
44
92
47
93
Project code : 91.4IE01.001
PCB P/N : 10260-1
Revision : A00
P2800
IDT
92HD87
DMIx4
10/100/
1000 NIC
Realtek
RJ45
CONN
I
/
O

B
o
a
r
d
C
o
n
n
e
c
t
o
r
S
P
I
Flash ROM
4MB
51
HDMI
HDMI
88,89,90,91
83.84,85,86,87
RTL8111E/8105E
KBC
Thermal Int.
KB
L
P
C

B
u
s
DDRIII
1066/1333
Intel CPU
DDRIII 1066/1333 Channel A
Slot 0
14
15
4,5,6,7,8,9,10,11,12,13
Slot 1
Block Diagram
(Discrete/UMA co-lay)
Bluetooth
63
CRT Board
PCIE x 4
Left Side:
USB x 1
CAMERA
54
Mini-Card
USB 2.0 x 3
802.11a/b/g
LVDS(Sigal Channel)
CRT
LCD
RGB CRT
Intel
SATA x 2
14 USB 2.0/1.1 ports
High Definition Audio
SATA ports (6)
ACPI 1.1
LPC I/F
USB2.0 x 5
Azalia
CODEC
29
2CH SPEAKER
Internal Digital MIC
NPCE795P
ETHERNET (10/100/1000Mb)
NUVOTON
28
PCIE ports (8)
DDR3
800MHz
55
1GB
Fan Control
4
VRAM
27
49
69 25
17,18,19,20,21,22,23,24,25,26
PCIe x 16
Touch
PAD
69
FDIx4x2
(UMA only) Discreet/UMA Co-lay
(Discrete only)
1.N12P-GE-A1-GP(64Mx16b*8)
WKS P/N:72.51G63.H0U HYNIX
WKS P/N:72.41164.I0U SAMSUNG
##OnMainBoard
D/A
USB 2.0 x 1
PCIE x 1
PCIE x 1
USB2.0 x 1
LPC debug port
82
82
60
71
40
G9731
INPUTS OUTPUTS
1D5V_S3 1V_VGA_S0
Robson-XT&
Seymour-XT&
Whistler-LP&
N12P-GE
Sandy Bridge
DDRIII
1066/1333
DDRIII 1066/1333 Channel B
PCH
Cougar Point
AZALIA
64
Finger Print
L4:Signal
L5:GND
L6:Bottom
APL5916
INPUTS
0D85V_S0
OUTPUTS
SYSTEM LDO
1D05V_VTT
48
VOSTRO
USB 2.0 x 1BPCIE X 1
56
ODD
56
HDD
Realtek
RTS5138
CardReader
32
SD/MMC+/MS/
MS Pro/xD
Express Card
(On daughter board)
VOSTRO
75
P2793
NEC USB3.0
UPD720200FA
USB3.0 X2
CONN
PCIE x 1
ESATA/USB/Powershare
Combo
SATAx1 / USB2.0x1
SIM
Mini-Card
WWAN
PCIE x 1,USB x 1
MIC IN
HP1
57
A/D
58
74
DCIN
15~25W
ATI : Co-layout HDMI coming from UMA(default) &
dGPU by reserving Resistor(0ohm) for optional selection.
NVidia : Co-layout HDMI coming from dGPU(Default) &
UMA by reserving Resistor(0ohm) for optional selection.
A
A
B
B
C
C
D
D
E
E
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3 3
2 2
1 1
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Table of Content
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Table of Content
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Table of Content
A3
<Variant Name>
PCIE Routing
LANE2
LANE3
Card Reader
Onboard LAN LANE4
Mini Card1(WLAN)
SATA Table
Pair
SATA
Device
0
5
4
3
2
1
HDD1
ODD
N/A
HDD2
N/A
ESATA
LANE1
Mini Card2(WWAN)
LANE5
LANE6
LANE7
LANE8 Express Card
Intel GBE LAN
CFG[6:5]
CFG[7]
Processor Strapping
CFG[2]
Disabled - No Physical Display Port attached to
Embedded DisplayPort.
CFG[4]
Pin Name Strap Description Configuration (Default value for each bit is
1 unless specified otherwise)
1:
Huron River Schematic Checklist Rev.0_7
0:
PCI-Express Static
Lane Reversal
Normal Operation.
Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
Default
Value
PCI-Express
Port Bifurcation
Straps
11 : x16 - Device 1 functions 1 and 2 disabled
10 : x8, x8 - Device 1 function 1 enabled ;
function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
enabled
PEG DEFER TRAINING
1
0
1
1:
0:
Enabled - An external Display Port device is
connectd to the EMBEDDED display Port
11
1:
0:
PEG Train immediately following xxRESETB de assertion
PEG Wait for BIOS for training
SPKR
Name Schematics Notes
HAD_DOCK_EN#
/GPIO[33]
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC
Huron River Schematic Checklist Rev.0_7
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
GNT3#/GPIO55
GNT2#/GPIO53
GNT1#/GPIO51
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
PCH Strapping
SPI_MOSI
Internal weak Pull-down.
Connect to Vcc3_3 with 8.2-k[
- 10-k[ weak pull-up resistor.
NV_ALE
Enable Danbury:
Disable Danbury:
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
GPIO15
GPIO8
Reboot option at power-up
Default Mode:
No Reboot Mode with TCO Disabled:
Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
Left floating, no pull-down required.
Connect to +NVRAM_VCCQ with 8.2-kohm
weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]
Leave floating (internal pull-down)
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features.
High (1) - Security measure defined in the Flash Descriptor will be enabled.
Platform design should provide appropriate pull-up or pull-down depending on
the desired settings. If a jumper option is used to tie this signal to GND as
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for
strapping functions.
GPIO27
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
Voltage Rails
VOLTAGE DESCRIPTION
ACTIVE IN
POWER PLANE
CPU Core Rail
Graphics Core Rail
AC Brick Mode only
Legacy WOL
Powered by Li Coin Cell in G3
and +V3ALW in Sx
3D3V_AUX_KBC
3.3V
DSW, Sx ON for supporting Deep Sleep states
S0
S3
All S states
WOL_EN
G3, Sx
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
0D85V_S0
0D75V_S0
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0
5V
3.3V
1.8V
1.5V
1.05V
0.95 - 0.85V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V
1V
5V
1.5V
0.75V
5V_USBX_S3
1D5V_S3
DDR_VREF_S3
BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5
6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V
3.3V 3D3V_LAN_S5
3.3V
3D3V_AUX_S5
GNT[3:0]# functionality is not available on Mobile.
Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.
Enable Danbury:
Disable Danbury:
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher
suite with confidentiality
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
SML1_CLK/SML1_DATA
PCH_SMBDATA/PCH_SMBCLK
Device
I C / SMBus Addresses 2
EC SMBus 1
Battery
CHARGER
EC SMBus 2
PCH
eDP
PCH SMBus
SO-DIMMA (SPD)
SO-DIMMB (SPD)
Digital Pot
G-Sensor
MINI
BAT_SCL/BAT_SDA
SMBus ADDRESSES
HURON RIVER ORB
Address Hex Bus Ref Des
USB3.0
Dock
USB Table
13
USB Ext. port 3
12
X
Mini Card1 (WLAN)
Fingerprint
X
Express Card
USB Ext. port 2
10
0
11
USB Ext. port 1 (HS)
Pair
4
5
2
3
1
Device
6
7
8
9
BLUETOOTH
Touch Panel / 3G SIM
CARD READER
USB Ext. port 4 / E-SATA /USB CHARGER
CAMERA
Mini Card2 (WWAN)
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEG_TXP[0..15]
PEG_TXN[0..15]
PEG_C_TXN3
PEG_C_TXN15
PEG_C_TXN10
PEG_C_TXN5
PEG_C_TXN0
PEG_C_TXN12
PEG_C_TXN7
PEG_C_TXN2
PEG_C_TXN14
PEG_C_TXN9
PEG_C_TXN4
PEG_C_TXN11
PEG_C_TXN6
PEG_C_TXN1
PEG_C_TXN13
PEG_C_TXN8
PEG_IRCOMP_R
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXP5
PEG_RXN0
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXN[0..15]
PEG_RXP0
PEG_RXP15
PEG_RXN15
PEG_RXN14
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXN13
PEG_RXN12
PEG_RXP11
PEG_RXN11
PEG_RXP10
PEG_RXN10
PEG_RXP9
PEG_RXN9
PEG_RXP8
PEG_RXN8
PEG_RXP7
PEG_RXP[0..15]
PEG_RXP6
PEG_RXN7
PEG_RXN6
PEG_C_TXP3
PEG_C_TXP15
PEG_C_TXP10
PEG_C_TXP5
PEG_C_TXP0
PEG_C_TXP12
PEG_C_TXP7
PEG_C_TXP2
PEG_C_TXP14
PEG_C_TXP9
PEG_C_TXP4
PEG_C_TXP11
PEG_C_TXP6
PEG_C_TXP1
PEG_C_TXP13
PEG_C_TXP8
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
DP_COMP
eDP_HPD
FDI_TXP4
FDI_TXP5
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
FDI_TXP6
FDI_TXP7
FDI_TXN0
FDI_TXN1
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
FDI_TXN2
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
1D05V_VTT
1D05V_VTT PEG_TXP[0..15] 83
PEG_TXN[0..15] 83
PEG_RXP[0..15] 83
PEG_RXN[0..15] 83
DMI_RXN[3:0] 19
DMI_RXP[3:0] 19
DMI_TXN[3:0] 19
DMI_TXP[3:0] 19
FDI_TXN[7:0] 19
FDI_TXP[7:0] 19
FDI_FSYNC0 19
FDI_FSYNC1 19
FDI_INT 19
FDI_LSYNC0 19
FDI_LSYNC1 19
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (PCIE/DMI/FDI)
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (PCIE/DMI/FDI)
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (PCIE/DMI/FDI)
A3
<Variant Name>
SSID = CPU
Stuff to disable internal graphics
function for power saving.
NOTE:
Select aFast FET similar to 2N7002E whoserise/
fall timeis less than 6 ns. If HPD on eDP interfaceis
disabled, connect it to CPU VCCIO viaa10-k[ pull-Up
resistor on themotherboard.
NOTE.
If PEG is not implemented, the RX&TX pairs can be left as No Connect
NOTE.
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
PEG Static Lane Reversal
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
Note:
Intel DMI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
Note:
Lane reversal does not apply to
FDI sideband signals.
Note:
Intel FDI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
EDP_ICOMPO keep W/S=12/15 mils and routing
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
0719 Modify:
un-stuff R403 base on Intel James feedback list.
A00 0103 add 3rd foxcon CPU1 at XBuild batch run
1 2 C404 SCD22U10V2KX-1GP
MUXLESS
C404 SCD22U10V2KX-1GP
MUXLESS
MUXLESS
MUXLESS
1 2 R403
10KR2J -3-GP
DY
R403
10KR2J -3-GP
DY
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
1 2 R401 24D9R2F-L-GP R401 24D9R2F-L-GP
MUXLESS
MUXLESS
MUXLESS
MUXLESS
DMI_RX#0
B27
DMI_RX#1
B25
DMI_RX#2
A25
DMI_RX#3
B24
DMI_RX0
B28
DMI_RX1
B26
DMI_RX2
A24
DMI_RX3
B23
DMI_TX#0
G21
DMI_TX#1
E22
DMI_TX#2
F21
DMI_TX#3
D21
DMI_TX0
G22
DMI_TX1
D22
DMI_TX3
C21
DMI_TX2
F20
FDI0_TX#0
A21
FDI0_TX#1
H19
FDI0_TX#2
E19
FDI0_TX#3
F18
FDI1_TX#0
B21
FDI1_TX#1
C20
FDI1_TX#2
D18
FDI1_TX#3
E17
FDI0_TX0
A22
FDI0_TX1
G19
FDI0_TX2
E20
FDI0_TX3
G18
FDI1_TX0
B20
FDI1_TX1
C19
FDI1_TX2
D19
FDI1_TX3
F17
FDI0_FSYNC
J 18
FDI1_FSYNC
J 17
FDI_INT
H20
FDI0_LSYNC
J 19
FDI1_LSYNC
H17
PEG_ICOMPI
J 22
PEG_ICOMPO
J 21
PEG_RCOMPO
H22
PEG_RX#0
K33
PEG_RX#1
M35
PEG_RX#2
L34
PEG_RX#3
J 35
PEG_RX#4
J 32
PEG_RX#5
H34
PEG_RX#6
H31
PEG_RX#7
G33
PEG_RX#8
G30
PEG_RX#9
F35
PEG_RX#10
E34
PEG_RX#11
E32
PEG_RX#12
D33
PEG_RX#13
D31
PEG_RX#14
B33
PEG_RX#15
C32
PEG_RX0
J 33
PEG_RX1
L35
PEG_RX2
K34
PEG_RX3
H35
PEG_RX4
H32
PEG_RX5
G34
PEG_RX6
G31
PEG_RX7
F33
PEG_RX8
F30
PEG_RX9
E35
PEG_RX10
E33
PEG_RX11
F32
PEG_RX12
D34
PEG_RX13
E31
PEG_RX14
C33
PEG_RX15
B32
PEG_TX#0
M29
PEG_TX#1
M32
PEG_TX#2
M31
PEG_TX#3
L32
PEG_TX#4
L29
PEG_TX#5
K31
PEG_TX#6
K28
PEG_TX#7
J 30
PEG_TX#8
J 28
PEG_TX#9
H29
PEG_TX#10
G27
PEG_TX#11
E29
PEG_TX#12
F27
PEG_TX#13
D28
PEG_TX#14
F26
PEG_TX#15
E25
PEG_TX0
M28
PEG_TX1
M33
PEG_TX2
M30
PEG_TX3
L31
PEG_TX4
L28
PEG_TX5
K30
PEG_TX6
K27
PEG_TX7
J 29
PEG_TX8
J 27
PEG_TX9
H28
PEG_TX10
G28
PEG_TX11
E28
PEG_TX12
F28
PEG_TX13
D27
PEG_TX14
E26
PEG_TX15
D25
EDP_AUX
C15
EDP_AUX#
D15
EDP_TX0
C17
EDP_TX1
F16
EDP_TX2
C16
EDP_TX3
G15
EDP_TX#0
C18
EDP_TX#1
E16
EDP_TX#2
D16
EDP_TX#3
F15
EDP_COMPIO
A18
EDP_HPD
B16
EDP_ICOMPO
A17
P
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1 OF 9
SANDY
CPU1A
SANDY
62.10055.421
SKT-BGA989C470395-1H180
2nd = 62.10040.771
3rd = 62.10055.321
P
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SANDY
CPU1A
SANDY
62.10055.421
SKT-BGA989C470395-1H180
2nd = 62.10040.771
3rd = 62.10055.321
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
1 2 R402 24D9R2F-L-GP R402 24D9R2F-L-GP
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
MUXLESS
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SKTOCC#_R
H_CATERR#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_TRST#
XDP_TCLK
XDP_PRDY#
XDP_PREQ#
H_PROCHOT#_R
BUF_CPU_RST#
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM0
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7
VDDPWRGOOD
XDP_DBRESET#
CLK_DP_P_R
CLK_DP_N_R
H_PROCHOT#
H_CPUPWRGD_R
XDP_TMS
XDP_TCLK
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#
BUF_CPU_RST# BUFO_CPU_RST#
XDP_TDO
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_DBRESET#
1D05V_VTT
3D3V_S0
1D05V_VTT
1D05V_VTT
1D05V_VTT
3D3V_S0
H_PM_SYNC 19
PM_DRAM_PWRGD 19,37
H_PECI 22,27
H_CPUPWRGD 22,36
H_THERMTRIP# 22,36
H_PROCHOT# 27,40,42
CLK_EXP_P 20
CLK_EXP_N 20 H_SNB_IVB# 18
PLT_RST# 18,27,71,75,82,83
VDDPWRGOOD 37
SM_DRAMRST# 37
XDP_DBRESET# 19
PLT_RST# 18,27,71,75,82,83
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (THERMAL/CLOCK/PM )
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Variant Name>
SSID = CPU
Disabling Guidelines:
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
through 1K +/- 5% resistorpower (~15 mW) may be
wasted.
SM_RCOMP keep routing length less than 500 mils.
0617 Modify:
J osephchangeRN501 to R512,R514 1K 0402 Resistor.
0617 Modify:
J osephRemovedU501 Buffer reset to CPU circuit.
0623 Modify:
Reserved C501 220pF 0402 on BUF_CPU_RST#.
20100622 V1.2
CRB : 47pf
CEKLT:43pf
Connect EC to PROCHOT# through inverting OD buffer.
0625 Modify:
Add C502 47p 0402 on H_PROCHOT#.
0630 Modify:
Removed XDP1101 connector
related circuit by layout limitation.
0707 Modify:
Change R516 10K from 1K
0719 Modify:
Add buffer for PLT_RST# based on Intel review.
Buffered reset to CPU
0721 Modify:
SWAP RN501 pin1,2,3
base on swap report.
A00 1229 EMI
A00 1229 EMI
A00 1230 EMI
1
2
E
C
5
0
4
S
C
1
K
P
5
0
V
2
K
X
-
1
G
P
E
C
5
0
4
S
C
1
K
P
5
0
V
2
K
X
-
1
G
P
1 2 R504
0R0402-PAD
R504
0R0402-PAD
1 2
R501
62R2J -GP
R501
62R2J -GP
1 2 R502
4K99R2F-L-GP
R502
4K99R2F-L-GP
1 2 R510
1K5R2F-2-GP
R510
1K5R2F-2-GP
1
TP503 TPAD14-GP TP503 TPAD14-GP
1
2
C501
SC220P50V2KX-3GP
DY
C501
SC220P50V2KX-3GP
DY
1
2
3
4 5
6
7
8
RN501
SRN51J -1-GP
RN501
SRN51J -1-GP
1 2 R516
10KR2J -3-GP
R516
10KR2J -3-GP
1
2
C502
SC47P50V2J N-3GP
C502
SC47P50V2J N-3GP
1
2
E
C
5
0
6
M
S
0
4
A
0
3
T
2
V
2
-
G
P
-
U
DY
E
C
5
0
6
M
S
0
4
A
0
3
T
2
V
2
-
G
P
-
U
DY
1
1
1
1
2
R515
0R2J -2-GP
DY
R515
0R2J -2-GP
DY
1
1 2 R506 140R2F-GP R506 140R2F-GP
1 2
EC505
MS04A03T2V2-GP-U
DY
EC505
MS04A03T2V2-GP-U
DY
1 2
R517 43R2J -GP
DY
R517 43R2J -GP
DY
1
1 2 R503
10KR2J -3-GP
R503
10KR2J -3-GP
1 2 R505
0R2J -2-GP
DY
R505
0R2J -2-GP
DY
1
1
2
C503
SCD1U10V2KX-5GP
DY
C503
SCD1U10V2KX-5GP
DY
1
1
2
R509
750R2F-GP
R509
750R2F-GP
1 2 R511 51R2J -2-GP R511 51R2J -2-GP
1
1
SM_RCOMP1
A5
SM_RCOMP2
A4
SM_DRAMRST#
R8
SM_RCOMP0
AK1
BCLK#
A27
BCLK
A28
DPLL_REF_SSCLK#
A15
DPLL_REF_SSCLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY#
AP29
PREQ#
AP27
TCK
AR26
TMS
AR27
TRST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#0
AT28
BPM#1
AR29
BPM#2
AR30
BPM#3
AT30
BPM#4
AP32
BPM#5
AR31
BPM#6
AT31
BPM#7
AR32
PM_SYNC
AM34
SKTOCC#
AN34
SNB_IVB#
C26
UNCOREPWRGOOD
AP33
C
L
O
C
K
S
M
I
S
C
T
H
E
R
M
A
L
P
W
R

M
A
N
A
G
E
M
E
N
T
D
D
R
3

M
I
S
C
J
T
A
G

&

B
P
M
2 OF 9
SANDY
CPU1B
SANDY
62.10055.421
SKT-BGA989C470395-1H180
2nd = 62.10040.771
3rd = 62.10055.321
C
L
O
C
K
S
M
I
S
C
T
H
E
R
M
A
L
P
W
R

M
A
N
A
G
E
M
E
N
T
D
D
R
3

M
I
S
C
J
T
A
G

&

B
P
M
2 OF 9
SANDY
CPU1B
SANDY
62.10055.421
SKT-BGA989C470395-1H180
2nd = 62.10040.771
3rd = 62.10055.321
1 2 R514
1KR2J -1-GP
R514
1KR2J -1-GP
1
1 2 R507 25D5R2F-GP R507 25D5R2F-GP
1
1
2
E
C
5
0
2
S
C
1
K
P
5
0
V
2
K
X
-
1
G
P
E
C
5
0
2
S
C
1
K
P
5
0
V
2
K
X
-
1
G
P
1
2
R518
75R2J -1-GP
DY
R518
75R2J -1-GP
DY
1 2
R513
56R2J -4-GP
R513
56R2J -4-GP 1 2 R508 200R2F-L-GP R508 200R2F-L-GP
IN B
1
IN A
2
GND
3
OUT Y
4
VCC
5
U501
74VHC1G09DFT2G-GP
73.01G09.AAH
DY
U501
74VHC1G09DFT2G-GP
73.01G09.AAH
DY
1 2 R512
1KR2J -1-GP
R512
1KR2J -1-GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_A_DQ44
M_A_DQ36
M_A_DQ47
M_A_DQ40
M_A_DQ39
M_A_DQ37
M_A_DQ35
M_A_DQ34
M_A_DQ59
M_A_DQ54
M_A_DQ53
M_A_DQ63
M_A_DQ60
M_A_DQ61
M_A_DQ58
M_A_DQ51
M_A_DQ48
M_A_DQ57
M_A_DQ55
M_A_DQ49
M_A_DQ50
M_A_DQ62
M_A_DQ52
M_A_DQ56
M_A_DQ[63:0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ7
M_A_DQ5
M_A_DQ4
M_A_DQ6
M_A_DQ12
M_A_DQ10
M_A_DQ13
M_A_DQ9
M_A_DQ8
M_A_DQ11
M_A_DQ15
M_A_DQ14
M_A_DQ27
M_A_DQ25
M_A_DQ20
M_A_DQ19
M_A_DQ30
M_A_DQ18
M_A_DQ16
M_A_DQ28
M_A_DQ17
M_A_DQ26
M_A_DQ31
M_A_DQ29
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ21
M_A_DQ46
M_A_DQ42
M_A_DQ38
M_A_DQ32
M_A_DQ45
M_A_DQ33
M_A_DQ43
M_A_DQ41
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ15
M_B_DQ13
M_B_DQ12
M_B_DQ14
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ23
M_B_DQ21
M_B_DQ20
M_B_DQ22
M_B_DQ28
M_B_DQ26
M_B_DQ29
M_B_DQ25
M_B_DQ31
M_B_DQ24
M_B_DQ27
M_B_DQ30
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ39
M_B_DQ37
M_B_DQ36
M_B_DQ38
M_B_DQ44
M_B_DQ42
M_B_DQ45
M_B_DQ41
M_B_DQ47
M_B_DQ40
M_B_DQ43
M_B_DQ46
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ55
M_B_DQ53
M_B_DQ52
M_B_DQ54
M_B_DQ60
M_B_DQ58
M_B_DQ61
M_B_DQ57
M_B_DQ63
M_B_DQ56
M_B_DQ59
M_B_DQ62
M_B_DQ[63:0]
M_A_DQS4
M_A_DQS3
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS2
M_A_DQS1
M_A_DQS0
M_A_A7
M_A_A12
M_A_A14
M_A_A13
M_A_A9
M_A_A15
M_A_A10
M_A_A0
M_A_A6
M_A_A8
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A11
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS#3
M_A_DQS#2
M_A_DQS#1
M_A_DQS#0
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#3
M_B_DQS#2
M_B_DQS#1
M_B_DQS#0
M_B_DQS#7
M_B_DQS#6
M_B_DQS#5
M_B_DQS#4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
M_A_DQ[63:0] 15 M_B_DQ[63:0] 14
M_A_BS0 15
M_A_BS1 15
M_A_BS2 15
M_A_CAS# 15
M_A_RAS# 15
M_A_WE# 15
M_B_BS0 14
M_B_BS1 14
M_B_BS2 14
M_B_CAS# 14
M_B_RAS# 14
M_B_WE# 14
M_A_DQS#[7:0] 15
M_A_A[15:0] 15
M_A_DQS[7:0] 15
M_A_DIM0_CKE0 15
M_A_DIM0_CKE1 15
M_A_DIM0_CS#0 15
M_A_DIM0_CS#1 15
M_A_DIM0_ODT0 15
M_A_DIM0_ODT1 15
M_A_DIM0_CLK_DDR0 15
M_A_DIM0_CLK_DDR#0 15
M_A_DIM0_CLK_DDR1 15
M_B_A[15:0] 14
M_B_DQS[7:0] 14
M_B_DQS#[7:0] 14
M_B_DIM0_CKE0 14
M_B_DIM0_CKE1 14
M_B_DIM0_CS#0 14
M_B_DIM0_CS#1 14
M_B_DIM0_ODT0 14
M_B_DIM0_ODT1 14
M_B_DIM0_CLK_DDR0 14
M_B_DIM0_CLK_DDR#0 14
M_B_DIM0_CLK_DDR1 14
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (DDR)
A3
6 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (DDR)
A3
6 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (DDR)
A3
6 108
<Variant Name>
SSID = CPU
A00 0103 add 3rd foxcon CPU1 at XBuild batch run A00 0103 add 3rd foxcon CPU1 at XBuild batch run
SB_BS0
AA9
SB_BS1
AA7
SB_BS2
R6
SB_CAS#
AA10
SB_RAS#
AB8
SB_WE#
AB9
SB_CLK0
AE2
SB_CLK1
AE1
SB_CLK#0
AD2
SB_CLK#1
AD1
SB_CKE0
R9
SB_CKE1
R10
SB_ODT0
AE4
SB_ODT1
AD4
SB_DQS4
AN6
SB_DQS#4
AN5
SB_DQS5
AP8
SB_DQS#5
AP9
SB_DQS6
AK11
SB_DQS#6
AK12
SB_DQS7
AP14
SB_DQS#7
AP15
SB_DQS0
C7
SB_DQS#0
D7
SB_DQS1
G3
SB_DQS#1
F3
SB_DQS2
J 6
SB_DQS#2
K6
SB_DQS3
M3
SB_DQS#3
N3
SB_MA0
AA8
SB_MA1
T7
SB_MA2
R7
SB_MA3
T6
SB_MA4
T2
SB_MA5
T4
SB_MA6
T3
SB_MA7
R2
SB_MA8
T5
SB_MA9
R3
SB_MA10
AB7
SB_MA11
R1
SB_MA12
T1
SB_MA13
AB10
SB_MA14
R5
SB_MA15
R4
SB_DQ0
C9
SB_DQ1
A7
SB_DQ2
D10
SB_DQ3
C8
SB_DQ4
A9
SB_DQ5
A8
SB_DQ6
D9
SB_DQ7
D8
SB_DQ8
G4
SB_DQ9
F4
SB_DQ10
F1
SB_DQ11
G1
SB_DQ12
G5
SB_DQ13
F5
SB_DQ14
F2
SB_DQ15
G2
SB_DQ16
J 7
SB_DQ17
J 8
SB_DQ18
K10
SB_DQ19
K9
SB_DQ20
J 9
SB_DQ21
J 10
SB_DQ22
K8
SB_DQ23
K7
SB_DQ24
M5
SB_DQ25
N4
SB_DQ26
N2
SB_DQ27
N1
SB_DQ28
M4
SB_DQ29
N5
SB_DQ30
M2
SB_DQ31
M1
SB_DQ32
AM5
SB_DQ33
AM6
SB_DQ34
AR3
SB_DQ35
AP3
SB_DQ36
AN3
SB_DQ37
AN2
SB_DQ38
AN1
SB_DQ39
AP2
SB_DQ40
AP5
SB_DQ41
AN9
SB_DQ42
AT5
SB_DQ43
AT6
SB_DQ44
AP6
SB_DQ45
AN8
SB_DQ46
AR6
SB_DQ47
AR5
SB_DQ48
AR9
SB_DQ49
AJ 11
SB_DQ50
AT8
SB_DQ51
AT9
SB_DQ52
AH11
SB_DQ53
AR8
SB_DQ54
AJ 12
SB_DQ55
AH12
SB_DQ56
AT11
SB_DQ57
AN14
SB_DQ58
AR14
SB_DQ59
AT14
SB_DQ60
AT12
SB_DQ61
AN15
SB_DQ62
AR15
SB_DQ63
AT15
SB_CLK2
AB2
SB_CLK#2
AA2
SB_CKE2
T9
SB_CLK3
AA1
SB_CLK#3
AB1
SB_CKE3
T10
SB_CS#0
AD3
SB_CS#1
AE3
SB_CS#2
AD6
SB_CS#3
AE6
SB_ODT2
AD5
SB_ODT3
AE5
D
D
R

S
Y
S
T
E
M

M
E
M
O
R
Y

B
4 OF 9
SANDY
CPU1D
SANDY
2nd = 62.10040.771
62.10055.421
3rd = 62.10055.321
D
D
R

S
Y
S
T
E
M

M
E
M
O
R
Y

B
4 OF 9
SANDY
CPU1D
SANDY
2nd = 62.10040.771
62.10055.421
3rd = 62.10055.321
SA_BS0
AE10
SA_BS1
AF10
SA_BS2
V6
SA_CAS#
AE8
SA_RAS#
AD9
SA_WE#
AF9
SA_CLK0
AB6
SA_CLK1
AA5
SA_CLK#0
AA6
SA_CLK#1
AB5
SA_CKE0
V9
SA_CKE1
V10
SA_CS#0
AK3
SA_CS#1
AL3
SA_ODT0
AH3
SA_ODT1
AG3
SA_DQS0
D4
SA_DQS#0
C4
SA_DQS1
F6
SA_DQS#1
G6
SA_DQS2
K3
SA_DQS#2
J 3
SA_DQS3
N6
SA_DQS#3
M6
SA_DQS4
AL5
SA_DQS#4
AL6
SA_DQS5
AM9
SA_DQS#5
AM8
SA_DQS6
AR11
SA_DQS#6
AR12
SA_DQS7
AM14
SA_DQS#7
AM15
SA_MA0
AD10
SA_MA1
W1
SA_MA2
W2
SA_MA3
W7
SA_MA4
V3
SA_MA5
V2
SA_MA6
W3
SA_MA7
W6
SA_MA8
V1
SA_MA9
W5
SA_MA10
AD8
SA_MA11
V4
SA_MA12
W4
SA_MA13
AF8
SA_MA14
V5
SA_MA15
V7
SA_DQ0
C5
SA_DQ1
D5
SA_DQ2
D3
SA_DQ3
D2
SA_DQ4
D6
SA_DQ5
C6
SA_DQ6
C2
SA_DQ7
C3
SA_DQ8
F10
SA_DQ9
F8
SA_DQ10
G10
SA_DQ11
G9
SA_DQ12
F9
SA_DQ13
F7
SA_DQ14
G8
SA_DQ15
G7
SA_DQ16
K4
SA_DQ17
K5
SA_DQ18
K1
SA_DQ19
J 1
SA_DQ20
J 5
SA_DQ21
J 4
SA_DQ22
J 2
SA_DQ23
K2
SA_DQ24
M8
SA_DQ25
N10
SA_DQ26
N8
SA_DQ27
N7
SA_DQ28
M10
SA_DQ29
M9
SA_DQ30
N9
SA_DQ31
M7
SA_DQ32
AG6
SA_DQ33
AG5
SA_DQ34
AK6
SA_DQ35
AK5
SA_DQ36
AH5
SA_DQ37
AH6
SA_DQ38
AJ 5
SA_DQ39
AJ 6
SA_DQ40
AJ 8
SA_DQ41
AK8
SA_DQ42
AJ 9
SA_DQ43
AK9
SA_DQ44
AH8
SA_DQ45
AH9
SA_DQ46
AL9
SA_DQ47
AL8
SA_DQ48
AP11
SA_DQ49
AN11
SA_DQ50
AL12
SA_DQ51
AM12
SA_DQ52
AM11
SA_DQ53
AL11
SA_DQ54
AP12
SA_DQ55
AN12
SA_DQ56
AJ 14
SA_DQ57
AH14
SA_DQ58
AL15
SA_DQ59
AK15
SA_DQ60
AL14
SA_DQ61
AK14
SA_DQ62
AJ 15
SA_DQ63
AH15
SA_CLK2
AB4
SA_CLK#2
AA4
SA_CLK3
AB3
SA_CLK#3
AA3
SA_CKE2
W9
SA_CKE3
W10
SA_CS#2
AG1
SA_CS#3
AH1
SA_ODT2
AG2
SA_ODT3
AH2
D
D
R

S
Y
S
T
E
M

M
E
M
O
R
Y

A
3 OF 9
SANDY
CPU1C
SANDY
2nd = 62.10040.771
62.10055.421
3rd = 62.10055.321
D
D
R

S
Y
S
T
E
M

M
E
M
O
R
Y

A
3 OF 9
SANDY
CPU1C
SANDY
2nd = 62.10040.771
62.10055.421
3rd = 62.10055.321
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG0
CFG4
CFG2
CFG5
CFG6
CFG7
CFG2
CFG6
CFG5
CFG7
M_VREF_DQ_DIMM0_C
CFG4
M_VREF_DQ_DIMM1_C
H_VCCP_SEL
TP713
TP714
M_VREF_DQ_DIMM0
M_VREF_CA_DIMM0
M_VREF_CA_DIMM1
M_VREF_DQ_DIMM1
1D05V_VTT
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (RESERVED)
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (RESERVED)
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (RESERVED)
A3
<Variant Name>
SSID = CPU
PEG Static Lane Reversal
1: Normal Operation; Lane #
definition matches socket pin map definition CFG2
CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled
PCIE Port Bifurcation Straps
1: PEG Train immediately following xxRESETB de assertion
CFG7
PEG DEFER TRAINING
0:Lane Reversed
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
0: PEG Wait for BIOS for training
B4:VREF_DQ CHA
D1:VREF_DQ CHB
M3 - Processor Generated SO-DIMM VREF_DQ
20 mils
0: Enabled; An external Display Port device is
connected to the Embedded Display Port
Display Port Presence Strap
1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0617 Modify:
J osephChangeM_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1,
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1
fromnet to power.
0629 Modify:
Reserved R710 0ohm to GND to
follow EV board schematic.
0630 Modify:
Removed CLK_XDP_ITP_P&N
and reserved TP713,TP714.
0630 Modify:
Reserved TP715 on CFG0.
0702 Modify
0707 Modify:
Removed CFG1,CFG3,CFG8~17 TP.
0719 Modify:
Reserved EC701 0.1uF near
R711(BOTTOM) for EMC NEO suggestion.
1
2
R701
1
K
R
2
J
-
1
-
G
P
DY
R701
1
K
R
2
J
-
1
-
G
P
DY
CFG0
AK28
CFG1
AK29
CFG2
AL26
CFG3
AL27
CFG4
AK26
CFG5
AL29
CFG6
AL30
CFG7
AM31
CFG8
AM32
CFG9
AM30
CFG10
AM28
CFG11
AM26
CFG12
AN28
CFG13
AN31
CFG14
AN26
CFG15
AM27
CFG16
AK31
CFG17
AN29
RSVD#AM33
AM33
RSVD#AJ 27
AJ 27
RSVD#J 16
J 16
RSVD#AT34
AT34
RSVD#H16
H16
RSVD#G16
G16
RSVD#AR35
AR35
RSVD#AT33
AT33
RSVD#AR34
AR34
RSVD#AT2
AT2
RSVD#AT1
AT1
RSVD#AR1
AR1
RSVD#B34
B34
RSVD#A33
A33
RSVD#A34
A34
RSVD#B35
B35
RSVD#C35
C35
RSVD#AJ 32
AJ 32
RSVD#AK32
AK32
RSVD#AE7
AE7
RSVD#AK2
AK2
RSVD#L7
L7
RSVD#AG7
AG7
RSVD#J 15
J 15
RSVD#C30
C30
RSVD#D23
D23
RSVD#A31
A31
RSVD#B30
B30
RSVD#D30
D30
RSVD#B29
B29
RSVD#A30
A30
RSVD#B31
B31
RSVD#C29
C29
RSVD#J 20
J 20
RSVD#T8
T8
RSVD#B4
B4
RSVD#D1
D1
RSVD#F25
F25
RSVD#F24
F24
RSVD#D24
D24
RSVD#G25
G25
RSVD#G24
G24
RSVD#E23
E23
RSVD#W8
W8
RSVD#AT26
AT26
RSVD#B18
B18
RSVD#AP35
AP35
RSVD#F23
F23
RSVD#AJ 26
AJ 26
RSVD#AJ 31
AJ 31
RSVD#AH31
AH31
RSVD#AJ 33
AJ 33
RSVD#AH33
AH33
RSVD#AH27
AH27
RSVD#A19
A19
RSVD#AN35
AN35
RSVD#AM35
AM35
R
E
S
E
R
V
E
D
5 OF 9
SANDY
CPU1E
SANDY
62.10055.421
SKT-BGA989C470395-1H180
2nd = 62.10040.771
3rd = 62.10055.321
R
E
S
E
R
V
E
D
5 OF 9
SANDY
CPU1E
SANDY
62.10055.421
SKT-BGA989C470395-1H180
2nd = 62.10040.771
3rd = 62.10055.321
1
2
R711
1KR2F-3-GP
R711
1KR2F-3-GP
1 2 R708 0R2J -2-GP
DY
R708 0R2J -2-GP
DY
1
2
R705
1KR2J -1-GP
DY
R705
1KR2J -1-GP
DY
1
2
R704
1
K
R
2
J
-
1
-
G
P
DY
R704
1
K
R
2
J
-
1
-
G
P
DY
1
1
2
E
C
7
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
7
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1 2 R706 0R2J -2-GP
DY
R706 0R2J -2-GP
DY
1
2
R702
1KR2J -1-GP
MUXLESS
R702
1KR2J -1-GP
MUXLESS
1 2 R707 0R2J -2-GP
DY
R707 0R2J -2-GP
DY
1
2
R703
3K3R2F-2-GP
DY
R703
3K3R2F-2-GP
DY
1
1
1 2 R709 0R2J -2-GP
DY
R709 0R2J -2-GP
DY
1 2 R710 0R2J -2-GP
DY
R710 0R2J -2-GP
DY
1
2
R712
1KR2F-3-GP
R712
1KR2F-3-GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_CPU_SVIDCLK
H_CPU_SVIDALRT#
H_CPU_SVIDDAT
H_CPU_SVIDDAT
VCC_CORE
1D05V_VTT
VCC_CORE
VCC_CORE
1D05V_VTT
1D05V_VTT
VCCSENSE 42
VSSSENSE 42
VCCIO_SENSE 45
H_CPU_SVIDDAT 42
VR_SVID_ALERT# 42
H_CPU_SVIDCLK 42
VSSIO_SENSE 45
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VCC_CORE)
Custom
8 108 Tuesday, J anuary 04, 2011
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VCC_CORE)
Custom
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VCC_CORE)
Custom
<Core Design>
PROCESSOR CORE POWER
53A
SSID = CPU
No-stuff sites outside the socket may be removed.
No-stuff sites inside the socket cavity need to remain.
VCC Output Decoupling Recommendation:
4 x 470 uF at Bottom Socket Edge
8 x 22 uF at Top Socket Cavity
8 x 22 uF at Top Socket Edge
8 x 22 uF at Bottom Socket Cavity
VCCIO Output Decoupling Recommendation:
2 x 330 uF (3 x 330 uF for 2012 capable designs)
5 x 22 uF & 5 x 0805 no-stuff at Bottom
7 x 22 uF & 2 x 0805 no-stuff at Top
0617Modify:
Joseph RemovedC812,
C813,C814
0705 Modify:
Removed R805,R806, already PH closed PWM side.
20100610 V1.0
For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7
For CRB VIDALERT# need to pull high 75 ohm close to CPU
PROCESSOR VCCIO: 8.5A
0713 Modify:
Removed C818 10uf 0603 cap
base on layout limitation.
0713 Modify:
Removed C810,C806,C807 10uf 0603 cap
base on layout limitation.
0713 Modify:
Removed C802,C811 10uf 0603
cap base on layout limitation.
0721 Modify:
Removed C836.
0721 Modify:
Removed C822,C823,C824
0819 De-cap
0726 Modify:
un-stuff C826.
0726 Modify:
un-stuff C837.
0819 De-cap
0819 De-cap
X02 1115
1115 X02 Modify:
Reserved C802~C804,C806,C807 10uF 0603
for power team fine tune Vcore quality.
1
2
C
8
4
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
4
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
4
4
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
4
4
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
VCC_SENSE
AJ 35
VSS_SENSE
AJ 34
VIDALERT#
AJ 29
VIDSCLK
AJ 30
VIDSOUT
AJ 28
VSSIO_SENSE
A10
VCC
AG35
VCC
AG34
VCC
AG33
VCC
AG32
VCC
AG31
VCC
AG30
VCC
AG29
VCC
AG28
VCC
AG27
VCC
AG26
VCC
AF35
VCC
AF34
VCC
AF33
VCC
AF32
VCC
AF31
VCC
AF30
VCC
AF29
VCC
AF28
VCC
AF27
VCC
AF26
VCC
AD35
VCC
AD34
VCC
AD33
VCC
AD32
VCC
AD31
VCC
AD30
VCC
AD29
VCC
AD28
VCC
AD27
VCC
AD26
VCC
AC35
VCC
AC34
VCC
AC33
VCC
AC32
VCC
AC31
VCC
AC30
VCC
AC29
VCC
AC28
VCC
AC27
VCC
AC26
VCC
AA35
VCC
AA34
VCC
AA33
VCC
AA32
VCC
AA31
VCC
AA30
VCC
AA29
VCC
AA28
VCC
AA27
VCC
AA26
VCC
Y35
VCC
Y34
VCC
Y33
VCC
Y32
VCC
Y31
VCC
Y30
VCC
Y29
VCC
Y28
VCC
Y27
VCC
Y26
VCC
V35
VCC
V34
VCC
V33
VCC
V32
VCC
V31
VCC
V30
VCC
V29
VCC
V28
VCC
V27
VCC
V26
VCC
U35
VCC
U34
VCC
U33
VCC
U32
VCC
U31
VCC
U30
VCC
U29
VCC
U28
VCC
U27
VCC
U26
VCC
R35
VCC
R34
VCC
R33
VCC
R32
VCC
R31
VCC
R30
VCC
R29
VCC
R28
VCC
R27
VCC
R26
VCC
P35
VCC
P34
VCC
P33
VCC
P32
VCC
P31
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCCIO
AH13
VCCIO
J 11
VCCIO
G12
VCCIO
F14
VCCIO
F13
VCCIO
F12
VCCIO
F11
VCCIO
E14
VCCIO
E12
VCCIO
AH10
VCCIO
AG10
VCCIO
AC10
VCCIO
Y10
VCCIO
U10
VCCIO
P10
VCCIO
L10
VCCIO
J 14
VCCIO
J 13
VCCIO
J 12
VCCIO
H14
VCCIO
H12
VCCIO
H11
VCCIO
G14
VCCIO
G13
VCCIO
E11
VCCIO
C12
VCCIO
C11
VCCIO
B14
VCCIO
B12
VCCIO
A14
VCCIO
A13
VCCIO
A12
VCCIO
A11
VCCIO
D14
VCCIO
D13
VCCIO
D12
VCCIO
D11
VCCIO
C14
VCCIO
C13
VCCIO_SENSE
B10
VCCIO
J 23
POWER
C
O
R
E

S
U
P
P
L
Y
P
E
G

A
N
D

D
D
R
S
E
N
S
E

L
I
N
E
S
S
V
I
D
6 OF 9
SANDY
CPU1F
SANDY
2nd = 62.10040.771
62.10055.421
3rd = 62.10055.321
POWER
C
O
R
E

S
U
P
P
L
Y
P
E
G

A
N
D

D
D
R
S
E
N
S
E

L
I
N
E
S
S
V
I
D
6 OF 9
SANDY
CPU1F
SANDY
2nd = 62.10040.771
62.10055.421
3rd = 62.10055.321
1
2
C
8
0
4
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
C
8
0
4
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
1 2 R804 130R2F-1-GP R804 130R2F-1-GP
1
2
C
8
2
0
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C
8
2
0
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C
8
4
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
4
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
0
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
0
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
3
0
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
3
0
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
3
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
3
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
4
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
4
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
0
6
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
C
8
0
6
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
1
2
C
8
1
9
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C
8
1
9
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
R802
100R2F-L1-GP-U
R802
100R2F-L1-GP-U
1
2C
8
3
1
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
C
8
3
1
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
1
2
C
8
2
6
S
C
2
2
U
6
D
3
V
5
M
X
-
L
2
G
P
C
8
2
6
S
C
2
2
U
6
D
3
V
5
M
X
-
L
2
G
P
1
2
C
8
3
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
3
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
3
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
3
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
4
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
4
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
0
7
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
C
8
0
7
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
1
2C
8
2
7
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
C
8
2
7
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
1
2
C
8
1
7
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
C
8
1
7
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
1
2
C
8
4
0
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
4
0
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
0
5
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
C
8
0
5
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
1
2
R801
100R2F-L1-GP-U
R801
100R2F-L1-GP-U
1
2
C
8
3
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
3
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
3
7
S
C
2
2
U
6
D
3
V
5
M
X
-
L
2
G
P
C
8
3
7
S
C
2
2
U
6
D
3
V
5
M
X
-
L
2
G
P
1
2
C
8
0
2
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
C
8
0
2
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
1 2 R803 43R2J -GP R803 43R2J -GP
1
2
C
8
0
1
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
C
8
0
1
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
1
2
C
8
3
8
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
3
8
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
2
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
2
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
0
3
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
C
8
0
3
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
QC
1
2
C
8
3
4
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
3
4
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
2
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
2
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
1
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
1
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
8
0
8
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C
8
0
8
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C
8
2
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
8
2
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCSA_SEL
H_FC_C22
+V_SM_VREF_CNT
VSS_AXG_SENSE
VCC_AXG_SENSE
VCCUSA_SENSE
1D5V_S0
VCC_GFXCORE
1D8V_S0
0D85V_S0
VCC_GFXCORE
1D5V_S3
DCBATOUT
VCC_AXG_SENSE 42
VSS_AXG_SENSE 42
VCCSA_SEL 48
H_FC_C22 48
+V_SM_VREF_CNT 37
VCCUSA_SENSE 48
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VCC_GFXCORE)
A3
9 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VCC_GFXCORE)
A3
9 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VCC_GFXCORE)
A3
9 108
<Core Design>
SSID = CPU
VAXG Output Decoupling Recommendation:
2 x 22 uF at Top Socket Cavity
4 x 22 uF at Top Socket Edge
PROCESSOR VAXG: 33A
VCCPLL Output Decoupling Recommendation:
1 x 330 uF
2 x 1 uF
1 x 10 uF
Disabling Guidelines for External Graphics Designs:
Can connect to GND if motherboard only supports external
graphics and if GFX VR is not stuffed.
Can be left floating (Gfx VR keeps VAXG rail from floating)
if the VR is stuffed
PROCESSOR VCCPLL: 1.2A
PROCESSOR VCCSA: 6A
VDDQ Output Decoupling Recommendation:
1 x 330 uF
6 x 10 uF
PROCESSOR VDDQ: 10A
VCCSA Output Decoupling Recommendation:
1 x 330 uF
Routing Guideline:
Power from DDR_VREF_S3 and +V_SM_VREF_CNT
should have 10 mils trace width.
Refer to the latest Huron River Mainstream PDG
(Doc# 436735) for more details on S3 power
reduction implementation.
+V_SM_VREF_CNT should have 10 mil trace width
Removed DIS_ONLY Disable Resistor.
R904,R905,R901,R903
20100609 V1.0
0617 Modify:
J osephRemovedTC902,
TC903 330uF cap.
0617 Modify:
J osephRemovedTC902,TC903 330uF cap.
0719 Modify:
ReservedEC902 0.1uF near
C917 for EMC NEO suggestion.
0624 Modify:
Removed C918,C919 10uF 0603 for VCC_GFXCORE.
0624 Modify:
Removed R902 10ohm closed CPU side.
0713 Modify:
Add R908 100ohm PH to 0D85V_S0.
0714 Modify:
Removed R908 PH.
0713 Modify:
Removed C907 10uf 0603 cap.
0726 Modify:
stuff C908 10uF.
0714 Modify:
RN901 change to 1K PL from 10K
base on Intel PDDG updated.
0719 Modify:
Add C907,C918,C919,C925 0402 0.1 uF stitching
capacitors between 1D5V_S3 & 1D5V_S0 based on
Intel's review
0721 Modify:
Removed C903
0726 Modify:
un-stuff C906.
0818
De-cap
1122 X02 Modify:
stuff EC901 0.1uF from
EMC Neo suggestion.
1
2
C
9
2
1
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C
9
2
1
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
R907
100R2F-L1-GP-U
R907
100R2F-L1-GP-U
1
2
C
9
0
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
0
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
0
9
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C
9
0
9
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C
9
2
4
S
C
1
U
1
0
V
2
K
X
-
1
G
P
C
9
2
4
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1
2
C
9
1
7
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
1
7
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
0
4
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
0
4
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
1
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
1
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
0
7
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C
9
0
7
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
C
9
1
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
1
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
1
1
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C
9
1
1
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C
9
2
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
2
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
SM_VREF
AL1
VSSAXG_SENSE
AK34
VAXG_SENSE
AK35
VAXG
AT24
VAXG
AT23
VAXG
AT21
VAXG
AT20
VAXG
AT18
VAXG
AT17
VAXG
AR24
VAXG
AR23
VAXG
AR21
VAXG
AR20
VAXG
AR18
VAXG
AR17
VAXG
AP24
VAXG
AP23
VAXG
AP21
VAXG
AP20
VAXG
AP18
VAXG
AP17
VAXG
AN24
VAXG
AN23
VAXG
AN21
VAXG
AN20
VAXG
AN18
VAXG
AN17
VAXG
AM24
VAXG
AM23
VAXG
AM21
VAXG
AM20
VAXG
AM18
VAXG
AM17
VAXG
AL24
VAXG
AL23
VAXG
AL21
VAXG
AL20
VAXG
AL18
VAXG
AL17
VAXG
AK24
VAXG
AK23
VAXG
AK21
VAXG
AK20
VAXG
AK18
VAXG
AK17
VAXG
AJ 24
VAXG
AJ 23
VAXG
AJ 21
VAXG
AJ 20
VAXG
AJ 18
VAXG
AJ 17
VAXG
AH24
VAXG
AH23
VAXG
AH21
VAXG
AH20
VAXG
AH18
VAXG
AH17
VDDQ
U4
VDDQ
U1
VDDQ
P7
VDDQ
P4
VDDQ
P1
VDDQ
AF7
VDDQ
AF4
VDDQ
AF1
VDDQ
AC7
VDDQ
AC4
VDDQ
AC1
VDDQ
Y7
VDDQ
Y4
VDDQ
Y1
VDDQ
U7
VCCPLL
B6
VCCPLL
A6
VCCSA
M27
VCCSA
M26
VCCSA
L26
VCCSA
J 26
VCCSA
J 25
VCCSA
J 24
VCCSA
H26
VCCSA
H25
VCCSA_SENSE
H23
VCCSA_VID1
C24
VCCPLL
A2
FC_C22
C22
POWER
G
R
A
P
H
I
C
S
D
D
R
3

-
1
.
5
V

R
A
I
L
S
S
E
N
S
E
L
I
N
E
S
1
.
8
V

R
A
I
L
S
A

R
A
I
L
V
R
E
F
M
I
S
C
7 OF 9
SANDY
CPU1G
SANDY
2nd = 62.10040.771
62.10055.421
3rd = 62.10055.321
POWER
G
R
A
P
H
I
C
S
D
D
R
3

-
1
.
5
V

R
A
I
L
S
S
E
N
S
E
L
I
N
E
S
1
.
8
V

R
A
I
L
S
A

R
A
I
L
V
R
E
F
M
I
S
C
7 OF 9
SANDY
CPU1G
SANDY
2nd = 62.10040.771
62.10055.421
3rd = 62.10055.321
1
2
C
9
1
9
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C
9
1
9
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
TC901
ST330U2VDM-4-GP
79.33719.20L
2nd = 77.C3371.13L
TC901
ST330U2VDM-4-GP
79.33719.20L
2nd = 77.C3371.13L
1
2
C
9
2
0
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C
9
2
0
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C
9
0
8
S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
C
9
0
8
S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
1
2
E
C
9
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
9
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
C
9
1
0
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C
9
1
0
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C
9
0
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C
9
0
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
1
2
R906
100R2F-L1-GP-U
R906
100R2F-L1-GP-U
1
2
C
9
1
8
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C
9
1
8
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
12
3 4
RN901
SRN1KJ -7-GP
RN901
SRN1KJ -7-GP
1
2
C
9
0
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
0
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
1
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
1
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
1
4
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
1
4
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
E
C
9
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
C
9
1
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
1
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
0
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
9
0
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
9
2
2
S
C
1
U
1
0
V
2
K
X
-
1
G
P
C
9
2
2
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1
2
C
9
2
5
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C
9
2
5
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VSS)
A3
10 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VSS)
A3
10 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CPU (VSS)
A3
10 108
<Variant Name>
SSID = CPU
A00 0103 add 3rd foxcon CPU1 at XBuild batch run A00 0103 add 3rd foxcon CPU1 at XBuild batch run
VSS
T35
VSS
T34
VSS
T33
VSS
T32
VSS
T31
VSS
T30
VSS
T29
VSS
T28
VSS
T27
VSS
T26
VSS
P9
VSS
P8
VSS
P6
VSS
P5
VSS
P3
VSS
P2
VSS
N35
VSS
N34
VSS
N33
VSS
N32
VSS
N31
VSS
N30
VSS
N29
VSS
N28
VSS
N27
VSS
N26
VSS
M34
VSS
L33
VSS
L30
VSS
L27
VSS
L9
VSS
L8
VSS
L6
VSS
L5
VSS
L4
VSS
L3
VSS
L2
VSS
L1
VSS
K35
VSS
K32
VSS
K29
VSS
K26
VSS
J 34
VSS
J 31
VSS
H33
VSS
H30
VSS
H27
VSS
H24
VSS
H21
VSS
H18
VSS
H15
VSS
H13
VSS
H10
VSS
H9
VSS
H8
VSS
H7
VSS
H6
VSS
H5
VSS
H4
VSS
H3
VSS
H2
VSS
H1
VSS
G35
VSS
G32
VSS
G29
VSS
G26
VSS
G23
VSS
G20
VSS
G17
VSS
G11
VSS
F34
VSS
F31
VSS
F29
VSS
F22
VSS
F19
VSS
E30
VSS
E27
VSS
E24
VSS
E21
VSS
E18
VSS
E15
VSS
E13
VSS
E10
VSS
E9
VSS
E8
VSS
E7
VSS
E6
VSS
E5
VSS
E4
VSS
E3
VSS
E2
VSS
E1
VSS
D35
VSS
D32
VSS
D29
VSS
D26
VSS
D20
VSS
D17
VSS
C34
VSS
C31
VSS
C28
VSS
C27
VSS
C25
VSS
C23
VSS
C10
VSS
C1
VSS
B22
VSS
B19
VSS
B17
VSS
B15
VSS
B13
VSS
B11
VSS
B9
VSS
B8
VSS
B7
VSS
B5
VSS
B3
VSS
B2
VSS
A35
VSS
A32
VSS
A29
VSS
A26
VSS
A23
VSS
A20
VSS
A3
VSS
9 OF 9
SANDY
CPU1I
SANDY
62.10055.421
2nd = 62.10040.771
3rd = 62.10055.321
VSS
9 OF 9
SANDY
CPU1I
SANDY
62.10055.421
2nd = 62.10040.771
3rd = 62.10055.321
VSS
AT35
VSS
AT32
VSS
AT29
VSS
AT27
VSS
AT25
VSS
AT22
VSS
AT19
VSS
AT16
VSS
AT13
VSS
AT10
VSS
AT7
VSS
AT4
VSS
AT3
VSS
AR25
VSS
AR22
VSS
AR19
VSS
AR16
VSS
AR13
VSS
AR10
VSS
AR7
VSS
AR4
VSS
AR2
VSS
AP34
VSS
AP31
VSS
AP28
VSS
AP25
VSS
AP22
VSS
AP19
VSS
AP16
VSS
AP13
VSS
AP10
VSS
AP7
VSS
AP4
VSS
AP1
VSS
AN30
VSS
AN27
VSS
AN25
VSS
AN22
VSS
AN19
VSS
AN16
VSS
AN13
VSS
AN10
VSS
AN7
VSS
AN4
VSS
AM29
VSS
AM25
VSS
AM22
VSS
AM19
VSS
AM16
VSS
AM13
VSS
AM10
VSS
AM7
VSS
AM4
VSS
AM3
VSS
AM2
VSS
AM1
VSS
AL34
VSS
AL31
VSS
AL28
VSS
AL25
VSS
AL22
VSS
AL19
VSS
AL16
VSS
AL13
VSS
AL10
VSS
AL7
VSS
AL4
VSS
AL2
VSS
AK33
VSS
AK30
VSS
AK27
VSS
AK25
VSS
AK22
VSS
AK19
VSS
AK16
VSS
AK13
VSS
AK10
VSS
AK7
VSS
AK4
VSS
AJ 25
VSS
AJ 22
VSS
AJ 19
VSS
AJ 16
VSS
AJ 13
VSS
AJ 10
VSS
AJ 7
VSS
AJ 4
VSS
AJ 3
VSS
AJ 2
VSS
AJ 1
VSS
AH35
VSS
AH34
VSS
AH32
VSS
AH30
VSS
AH29
VSS
AH28
VSS
AH26
VSS
AH25
VSS
AH22
VSS
AH19
VSS
AH16
VSS
AH7
VSS
AH4
VSS
AG9
VSS
AG8
VSS
AG4
VSS
AF6
VSS
AF5
VSS
AF3
VSS
AF2
VSS
AE35
VSS
AE34
VSS
AE33
VSS
AE32
VSS
AE31
VSS
AE30
VSS
AE29
VSS
AE28
VSS
AE27
VSS
AE26
VSS
AE9
VSS
AD7
VSS
AC9
VSS
AC8
VSS
AC6
VSS
AC5
VSS
AC3
VSS
AC2
VSS
AB35
VSS
AB34
VSS
AB33
VSS
AB32
VSS
AB31
VSS
AB30
VSS
AB29
VSS
AB28
VSS
AB27
VSS
AB26
VSS
Y9
VSS
Y8
VSS
Y6
VSS
Y5
VSS
Y3
VSS
Y2
VSS
W35
VSS
W34
VSS
W33
VSS
W32
VSS
W31
VSS
W30
VSS
W29
VSS
W28
VSS
W27
VSS
W26
VSS
U9
VSS
U8
VSS
U6
VSS
U5
VSS
U3
VSS
U2
VSS
8 OF 9
SANDY
CPU1H
SANDY
62.10055.421
2nd = 62.10040.771
3rd = 63.10055.321
VSS
8 OF 9
SANDY
CPU1H
SANDY
62.10055.421
2nd = 62.10040.771
3rd = 63.10055.321
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
XDP
A3
11 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
XDP
A3
11 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
XDP
A3
11 108
<Variant Name>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SA1_DIM1
SA0_DIM1
SA1_DIM1
SA0_DIM1
TS#_DIMM0_1
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A7
M_B_A6
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A12
M_B_A15
M_B_A14
M_B_A13
M_B_A0
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQ43
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ15
M_B_DQ0
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ47
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
M_B_DQ1
M_B_DQ53
M_B_DQ52
M_B_DQ24
M_B_DQ55
M_B_DQ54
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQ2
M_B_DQ57
M_B_DQ56
M_B_DQ59
M_B_DQ58
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
M_B_DQ3
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ33
M_B_DQ32
M_B_DQ35
M_B_DQ34
M_B_DQ5
M_B_DQ4
M_B_DQ7
M_B_DQ6
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DQ8
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQS#0
M_B_DQS3
M_B_DQS#5
M_B_DQS4
M_B_DQS#6
M_B_DQS5
M_B_DQS#7
M_B_DQS#1
M_B_DQS6
M_B_DQS0
M_B_DQS#2
M_B_DQS7
M_B_DQS1
M_B_DQS#3
M_B_DQS2
M_B_DQS#4
1D5V_S3
1D5V_S3
3D3V_S0
0D75V_S0
0D75V_S0
DDR_VREF_S3
3D3V_S0
DDR_VREF_S3
M_VREF_DQ_DIMM1
M_VREF_CA_DIMM1
M_VREF_CA_DIMM1
M_VREF_DQ_DIMM1
3D3V_S0
TS#_DIMM0_1 15
PCH_SMBCLK 15,20,79,82
PCH_SMBDATA 15,20,79,82
M_B_A[15:0] 6
M_B_BS0 6
M_B_BS2 6
M_B_BS1 6
M_B_DQ[63:0] 6
M_B_DQS[7:0] 6
M_B_DQS#[7:0] 6
M_B_DIM0_ODT0 6
M_B_DIM0_ODT1 6
DDR3_DRAMRST# 15,37
M_B_WE# 6
M_B_DIM0_CS#0 6
M_B_CAS# 6
M_B_DIM0_CKE0 6
M_B_DIM0_CKE1 6
M_B_DIM0_CS#1 6
M_B_DIM0_CLK_DDR0 6
M_B_DIM0_CLK_DDR1 6
M_B_RAS# 6
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DDR3-SODIMM2
Custom
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DDR3-SODIMM2
Custom
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DDR3-SODIMM2
Custom
<Variant Name>
Place these caps
close to VTT1 and
VTT2.
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
SODIMM A DECOUPLING
Layout Note:
Place these Caps near
SO-DIMMA.
H =5.2mm
SSID = MEMORY
Thermal EVENT
PART NUMBER
5.2mm REVERSED
62.10017.P61
Height TYPE
5.2mm
0617Modify:
fromnettopower.
0617Modify:
fromnettopower.
0617Modify:
fromnettopower.
0617Modify:
J osephdummyTC1401default un-stuff.
0624 Modify:
SWAP DM1 and DM2 location.
REVERSED
0707 Modify:
Change R1404,R1405 to 0ohm 0402 from short pad.
0818
De-cap
0818
De-cap
0825
62.10017.N41(2nd)
62.10017.P41(3rd) 5.2mm REVERSED
62.10024.E21(4th) 5.2mm REVERSED
1110 X02 Modify:
DM2 1st change to 62.10017.P61; 2nd change
to 62.10017.N41 on ST stage from ME updated
connector list.
A00
A00
1
2
C
1
4
1
4
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
1
4
1
4
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
1
4
2
0
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
C
1
4
2
0
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
1
2
C
1
4
1
0
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C
1
4
1
0
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
1
2
R1404
0R0402-PAD-2-GP
R1404
0R0402-PAD-2-GP
1 2 R1403
10KR2J -3-GP
R1403
10KR2J -3-GP
1
2
C
1
4
0
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C
1
4
0
3
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
1
2
C1425
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
C1425
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
1
2
C
1
4
0
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C
1
4
0
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
A0
98
A1
97
A2
96
A3
95
A4
92
A5
91
A6
90
A7
86
A8
89
A9
85
A10/AP
107
A11
84
A12
83
A13
119
A14
80
A15
78
A16/BA2
79
BA0
109
BA1
108
DQ0
5
DQ1
7
DQ2
15
DQ3
17
DQ4
4
DQ5
6
DQ6
16
DQ7
18
DQ8
21
DQ9
23
DQ10
33
DQ11
35
DQ12
22
DQ13
24
DQ14
34
DQ15
36
DQ16
39
DQ17
41
DQ18
51
DQ19
53
DQ20
40
DQ21
42
DQ22
50
DQ23
52
DQ24
57
DQ25
59
DQ26
67
DQ27
69
DQ28
56
DQ29
58
DQ30
68
DQ31
70
DQ32
129
DQ33
131
DQ34
141
DQ35
143
DQ36
130
DQ37
132
DQ38
140
DQ39
142
DQ40
147
DQ41
149
DQ42
157
DQ43
159
DQ44
146
DQ45
148
DQ46
158
DQ47
160
DQ48
163
DQ49
165
DQ50
175
DQ51
177
DQ52
164
DQ53
166
DQ54
174
DQ55
176
DQ56
181
DQ57
183
DQ58
191
DQ59
193
DQ60
180
DQ61
182
DQ62
192
DQ63
194
DQS0#
10
DQS1#
27
DQS2#
45
DQS3#
62
DQS4#
135
DQS5#
152
DQS6#
169
DQS7#
186
DQS0
12
DQS1
29
DQS2
47
DQS3
64
DQS4
137
DQS5
154
DQS6
171
DQS7
188
ODT0
116
ODT1
120
VREF_DQ
1
VSS
2
NP1
NP1
NP2
NP2
RAS#
110
WE#
113
CAS#
115
CS0#
114
CS1#
121
CKE0
73
CKE1
74
CK0
101
CK0#
103
CK1
102
CK1#
104
DM0
11
DM1
28
DM2
46
DM3
63
DM4
136
DM5
153
DM6
170
DM7
187
SDA
200
SCL
202
VDDSPD
199
SA0
197
SA1
201
VREF_CA
126
VDD18
124
NC#1
77
NC#2
122
NC#/TEST
125
VDD3
81
VDD4
82
VDD5
87
VDD6
88
VDD7
93
VDD8
94
VDD9
99
VDD10
100
VDD13
111
VDD14
112
VDD15
117
VDD16
118
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VDD1
75
VSS
65
VSS
66
VSS
71
VSS
72
VDD2
76
VDD11
105
VDD12
106
VDD17
123
VSS
127
VSS
128
VSS
134
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
151
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
173
VSS
172
VSS
179
VSS
178
VSS
185
VSS
184
VSS
189
VSS
190
VSS
195
VSS
196
RESET#
30
EVENT#
198
VSS
205
VSS
206
VTT1
203
VTT2
204
DM2
DDR3-204P-48-GP
62.10017.P61
2nd = 62.10017.N41
4th = 62.10024.E21
3rd = 62.10017.P41
DM2
DDR3-204P-48-GP
62.10017.P61
2nd = 62.10017.N41
4th = 62.10024.E21
3rd = 62.10017.P41
1
2
R1402
10KR2J -3-GP
R1402
10KR2J -3-GP
1
2
C1423
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1423
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
1
4
0
7
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
1
4
0
7
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
1
4
0
4
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
C
1
4
0
4
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
1
2
C
1
4
0
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C
1
4
0
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
1
2
C
1
4
0
5
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
C
1
4
0
5
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
1
2
C1424
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1424
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
1
4
2
2
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
C
1
4
2
2
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
1
2
C
1
4
1
7
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
1
4
1
7
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C1413
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1413
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C1418
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P DY
C1418
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P DY
1
2
C
1
4
0
8
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
C
1
4
0
8
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
1
2
C1411
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1411
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
1
4
1
5
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
1
4
1
5
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
R1405
0R0402-PAD-2-GP
R1405
0R0402-PAD-2-GP
1
2
C1412
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
C1412
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
1
2
C
1
4
2
1
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
1
4
2
1
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C
1
4
1
9
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
1
4
1
9
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
TC1401
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
DY
TC1401
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
DY
1
2
R1401
10KR2J -3-GP
R1401
10KR2J -3-GP
1
2
C1402
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
C1402
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
1
2
C1401
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1401
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
1
4
1
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
1
4
1
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SA0_DIM0
SA1_DIM0
SA0_DIM0
SA1_DIM0
M_A_DQS7
M_A_DQS0
M_A_DQ35
M_A_DQ17
M_A_DQS#5
M_A_DQ52
M_A_DQ47
M_A_DQ44
M_A_DQ24
M_A_DQ2
M_A_DQ0
M_A_A12
M_A_DQ46
M_A_DQ36
M_A_DQ21
M_A_DQ6
M_A_A4
M_A_DQS#2
M_A_DQ33
M_A_DQ12
M_A_DQ10
M_A_DQS6
M_A_DQS#7
M_A_DQ45
M_A_DQ43
M_A_DQ25
M_A_DQ16
M_A_DQS4
M_A_DQS#4
M_A_DQ51
M_A_DQ39
M_A_DQ31
M_A_DQ20
M_A_DQ1
M_A_A11
M_A_A9
M_A_DQ63
M_A_DQ5
M_A_A15
M_A_A3
M_A_DQS#1
M_A_DQ55
M_A_DQ34
M_A_DQ11
M_A_DQ9
M_A_DQS5
M_A_DQS#6
M_A_DQ50
M_A_DQ32
M_A_DQ15
M_A_DQS3
M_A_DQS#3
M_A_DQ23
M_A_DQ19
M_A_A10
M_A_A8
M_A_DQ62
M_A_DQ57
M_A_DQ54
M_A_DQ42
M_A_DQ4
M_A_A14
M_A_A2
M_A_DQ59
M_A_DQ30
M_A_DQ8
M_A_A6
M_A_DQS#0
M_A_DQ61
M_A_DQ49
M_A_DQ41
M_A_DQ22
M_A_DQ14
M_A_DQS2
M_A_DQ40
M_A_DQ18
M_A_A7
M_A_DQS1
M_A_DQ56
M_A_DQ53
M_A_DQ48
M_A_DQ37
M_A_DQ26
M_A_DQ3
M_A_A13
M_A_A1
M_A_DQ58
M_A_DQ28
M_A_DQ27
M_A_DQ7
M_A_A5
M_A_A0
M_A_DQ60
M_A_DQ38
M_A_DQ29
M_A_DQ13
1D5V_S3
3D3V_S0
1D5V_S3
0D75V_S0
DDR_VREF_S3
0D75V_S0
DDR_VREF_S3
M_VREF_DQ_DIMM0
M_VREF_CA_DIMM0
M_VREF_DQ_DIMM0
M_VREF_CA_DIMM0
TS#_DIMM0_1 14
M_A_A[15:0] 6
M_A_BS2 6
M_A_BS0 6
M_A_BS1 6
M_A_DQ[63:0] 6
DDR3_DRAMRST# 14,37
M_A_DIM0_ODT0 6
M_A_DIM0_ODT1 6
M_A_DQS#[7:0] 6
M_A_DQS[7:0] 6
M_A_WE# 6
M_A_DIM0_CS#0 6
M_A_CAS# 6
M_A_DIM0_CKE0 6
M_A_DIM0_CKE1 6
M_A_DIM0_CS#1 6
M_A_DIM0_CLK_DDR0 6
M_A_DIM0_CLK_DDR1 6
M_A_RAS# 6
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DDR3-SODIMM1
Custom
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DDR3-SODIMM1
Custom
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DDR3-SODIMM1
Custom
<Variant Name>
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
Place these caps
close to VTT1 and
VTT2.
SODIMM B DECOUPLING
Layout Note:
Place these Caps near
SO-DIMMB.
H =9.2mm
SSID = MEMORY
PART NUMBER
9.2mm REVERSED
Height TYPE
62.10017.Q41 9.2mm REVERSED
0617Modify:
fromnettopower.
0617Modify:
fromnettopower.
0617Modify:
fromnettopower.
0624 Modify:
SWAP DM1 and DM2 location.
0707 Modify:
Change R1503,R1504 to 0ohm 0402 from short pad.
0818
De-cap
0818
De-cap
9.2mm REVERSED
62.10017.N11(2nd)
62.10017.N61(3rd)
62.10024.D91(4th) 9.2mm REVERSED
1110 X02 Modify:
DM1 1st change to 62.10017.Q41; 2nd change
to 62.10017.N11 on ST stage from ME updated
connector list.
20101220 R1501 R1502 for change to parallel resistor
A00
A00
A00
1 2
34
RN1501
SRN10KJ -5-GP
RN1501
SRN10KJ -5-GP
1
2
R1504
0R0402-PAD-2-GP
R1504
0R0402-PAD-2-GP
1
2
C
1
5
1
1
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
1
5
1
1
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C1524
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
C1524
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
1
2
C
1
5
0
4
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
C
1
5
0
4
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
1
2
C
1
5
1
8
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
C
1
5
1
8
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
A0
98
A1
97
A2
96
A3
95
A4
92
A5
91
A6
90
A7
86
A8
89
A9
85
A10/AP
107
A11
84
A12
83
A13
119
A14
80
A15
78
A16/BA2
79
BA0
109
BA1
108
DQ0
5
DQ1
7
DQ2
15
DQ3
17
DQ4
4
DQ5
6
DQ6
16
DQ7
18
DQ8
21
DQ9
23
DQ10
33
DQ11
35
DQ12
22
DQ13
24
DQ14
34
DQ15
36
DQ16
39
DQ17
41
DQ18
51
DQ19
53
DQ20
40
DQ21
42
DQ22
50
DQ23
52
DQ24
57
DQ25
59
DQ26
67
DQ27
69
DQ28
56
DQ29
58
DQ30
68
DQ31
70
DQ32
129
DQ33
131
DQ34
141
DQ35
143
DQ36
130
DQ37
132
DQ38
140
DQ39
142
DQ40
147
DQ41
149
DQ42
157
DQ43
159
DQ44
146
DQ45
148
DQ46
158
DQ47
160
DQ48
163
DQ49
165
DQ50
175
DQ51
177
DQ52
164
DQ53
166
DQ54
174
DQ55
176
DQ56
181
DQ57
183
DQ58
191
DQ59
193
DQ60
180
DQ61
182
DQ62
192
DQ63
194
DQS0#
10
DQS1#
27
DQS2#
45
DQS3#
62
DQS4#
135
DQS5#
152
DQS6#
169
DQS7#
186
DQS0
12
DQS1
29
DQS2
47
DQS3
64
DQS4
137
DQS5
154
DQS6
171
DQS7
188
ODT0
116
ODT1
120
VREF_DQ
1
VSS
2
NP1
NP1
NP2
NP2
RAS#
110
WE#
113
CAS#
115
CS0#
114
CS1#
121
CKE0
73
CKE1
74
CK0
101
CK0#
103
CK1
102
CK1#
104
DM0
11
DM1
28
DM2
46
DM3
63
DM4
136
DM5
153
DM6
170
DM7
187
SDA
200
SCL
202
VDDSPD
199
SA0
197
SA1
201
VREF_CA
126
VDD18
124
NC#1
77
NC#2
122
NC#/TEST
125
VDD3
81
VDD4
82
VDD5
87
VDD6
88
VDD7
93
VDD8
94
VDD9
99
VDD10
100
VDD13
111
VDD14
112
VDD15
117
VDD16
118
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VDD1
75
VSS
65
VSS
66
VSS
71
VSS
72
VDD2
76
VDD11
105
VDD12
106
VDD17
123
VSS
127
VSS
128
VSS
134
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
151
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
173
VSS
172
VSS
179
VSS
178
VSS
185
VSS
184
VSS
189
VSS
190
VSS
195
VSS
196
RESET#
30
EVENT#
198
VSS
205
VSS
206
VTT1
203
VTT2
204
DM1
DDR3-204P-42-GP
4th = 62.10024.D91
2nd = 62.10017.N11
62.10017.Q41
3rd = 62.10017.N61
DM1
DDR3-204P-42-GP
4th = 62.10024.D91
2nd = 62.10017.N11
62.10017.Q41
3rd = 62.10017.N61
1
2
C
1
5
0
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C
1
5
0
9
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY 1
2
C1517
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1517
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
1
5
1
9
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
1
5
1
9
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C1522
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1522
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C1501
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1501
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
1
5
1
3
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
C
1
5
1
3
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
1
2
C
1
5
0
5
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
C
1
5
0
5
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
1
2
C
1
5
1
4
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
C
1
5
1
4
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
1
2
C1515
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1515
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C1516
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
C1516
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P DY
1
2
C
1
5
0
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
1
5
0
6
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C
1
5
2
1
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
1
5
2
1
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C
1
5
1
0
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C
1
5
1
0
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
1
2
C
1
5
2
0
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
C
1
5
2
0
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
1
2
C
1
5
0
8
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
C
1
5
0
8
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
1
2
C1523
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C1523
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
1
5
0
7
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C
1
5
0
7
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
1
2
R1503
0R0402-PAD-2-GP
R1503
0R0402-PAD-2-GP
1
2
C
1
5
1
2
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C
1
5
1
2
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
C
1
5
0
3
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
C
1
5
0
3
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
DY
1
2
C1502
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P
DY
C1502
S
C
2
D
2
U
1
0
V
3
K
X
-
1
G
P
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LVDS_VBG
LVDS_IBG
DAC_IREF_R
CRT_GREEN
LVDS_VDD_EN
LVDS_VREFH
LVDS_VREFL
L_CTRL_DATA
L_CTRL_DATA
L_CTRL_CLK
LVDS_DDC_CLK_R
LVDS_DDC_DATA_R
L_BKLT_EN
L_CTRL_CLK
CRT_BLUE
CRT_RED
CRT_BLUE
CRT_RED
CRT_GREEN
CRT_BLUE_N48
CRT_RED_T49
CRT_GREEN_P49
3D3V_S0
CRT_HSYNC 82
CRT_VSYNC 82
LVDS_DDC_CLK_R 49
LVDS_DDC_DATA_R 49
LVDSA_DATA0 49
LVDSA_DATA1 49
LVDSA_DATA2 49
LVDSA_DATA0# 49
LVDSA_DATA1# 49
LVDSA_DATA2# 49
LVDSA_CLK# 49
LVDSA_CLK 49
L_BKLT_CTRL 49
LVDS_VDD_EN 49
L_BKLT_EN 27
CRT_DDC_CLK 82
CRT_DDC_DATA 82
CRT_BLUE 82
CRT_GREEN 82
CRT_RED 82
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (LVDS/CRT/DDI)
A3
17 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (LVDS/CRT/DDI)
A3
17 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (LVDS/CRT/DDI)
A3
17 108
<Variant Name>
Place near PCH
Impedance:90 ohm
Close to PCH side
L_DDC_DATA(PAGE17):
This signal is on the LVDS interface.
This signal needs to be left NC if eDP is
used for the local flat panel display
0617 Modify:
J osephRemovedLVDSB relatednet for
singleLVDS channel baseonDell updatedspec.
0712 Modify:
SWAP RN1704
Notes:
1K 0.5% 0402.
0804 Remove HDMI from PCH.
0917 X01 Modify:
Add R1703~R1705 on RGB signal and reserved
EC1701~EC1703 0.1u from EMC Neo suggestion.
0923 SWAP
0923 SWAP
A00
A00
1
2
E
C
1
7
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
1
7
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1 2 3 4
5678
RN1705
SRN150F-1-GP
RN1705
SRN150F-1-GP
L_BKLTCTL
P45
L_BKLTEN
J 47
L_CTRL_CLK
T45
L_CTRL_DATA
P39
L_DDC_CLK
T40
L_DDC_DATA
K47
L_VDD_EN
M45
LVDSA_CLK#
AK39
LVDSA_CLK
AK40
LVDSA_DATA#0
AN48
LVDSA_DATA#1
AM47
LVDSA_DATA#2
AK47
LVDSA_DATA#3
AJ 48
LVDSA_DATA0
AN47
LVDSA_DATA1
AM49
LVDSA_DATA2
AK49
LVDSA_DATA3
AJ 47
LVDSB_CLK#
AF40
LVDSB_CLK
AF39
LVDSB_DATA#0
AH45
LVDSB_DATA#1
AH47
LVDSB_DATA#2
AF49
LVDSB_DATA#3
AF45
LVDSB_DATA0
AH43
DDPB_0N
AV42
DDPB_1N
AV45
LVD_VREFH
AE48
LVD_VREFL
AE47
DDPD_2N
BF42
DDPD_3N
BJ 42
DDPB_2N
AU48
DDPB_3N
AV47
DDPC_0N
AY47
DDPC_1N
AY43
DDPC_2N
BA47
DDPC_3N
BB47
DDPD_0N
BB43
DDPD_1N
BF44
DDPB_0P
AV40
DDPB_1P
AV46
DDPD_2P
BE42
DDPD_3P
BG42
DDPB_2P
AU47
DDPB_3P
AV49
LVDSB_DATA1
AH49
LVDSB_DATA2
AF47
LVDSB_DATA3
AF43
LVD_IBG
AF37
LVD_VBG
AF36
DDPC_1P
AY45
DDPC_0P
AY49
DDPC_2P
BA48
DDPC_3P
BB49
DDPD_0P
BB45
DDPD_1P
BE44
CRT_BLUE
N48
CRT_DDC_CLK
T39
CRT_DDC_DATA
M40
CRT_GREEN
P49
CRT_HSYNC
M47
CRT_IRTN
T42
CRT_RED
T49
CRT_VSYNC
M49
DAC_IREF
T43
SDVO_CTRLCLK
P38
SDVO_CTRLDATA
M39
DDPC_CTRLCLK
P46
DDPC_CTRLDATA
P42
DDPD_CTRLCLK
M43
DDPD_CTRLDATA
M36
DDPB_AUXN
AT49
DDPC_AUXN
AP47
DDPD_AUXN
AT45
DDPB_AUXP
AT47
DDPC_AUXP
AP49
DDPD_AUXP
AT43
DDPB_HPD
AT40
DDPC_HPD
AT38
DDPD_HPD
BH41
SDVO_TVCLKINP
AP45
SDVO_TVCLKINN
AP43
SDVO_STALLP
AM40
SDVO_STALLN
AM42
SDVO_INTP
AP40
SDVO_INTN
AP39
L
V
D
S
D
i
g
i
t
a
l

D
i
s
p
l
a
y

I
n
t
e
r
f
a
c
e
C
R
T
4 OF 10
Cougar
Point
PCH1D
COUGAR-GP-U2-NF
L
V
D
S
D
i
g
i
t
a
l

D
i
s
p
l
a
y

I
n
t
e
r
f
a
c
e
C
R
T
4 OF 10
Cougar
Point
PCH1D
COUGAR-GP-U2-NF
1
2
E
C
1
7
0
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
1
7
0
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2 3
4
RN1702
SRN100KJ -6-GP
RN1702
SRN100KJ -6-GP
1 2
R1703 0R0402-PAD-2-GP R1703 0R0402-PAD-2-GP
1
2
R1702
1KR2D-1-GP
CHIP RES 1K D 1/16W 0402
R1702
1KR2D-1-GP
CHIP RES 1K D 1/16W 0402
1 2
R1704 0R0402-PAD-2-GP R1704 0R0402-PAD-2-GP 1 2
R1705 0R0402-PAD-2-GP R1705 0R0402-PAD-2-GP
1
2 3
4
RN1701
SRN2K2J -1-GP
RN1701
SRN2K2J -1-GP
1
2
R1701
2K37R2F-GP
R1701
2K37R2F-GP
1 TP1701 TPAD14-GP TP1701 TPAD14-GP
1
2 3
4
R
N
0R4P2R-PAD
RN1704
R
N
0R4P2R-PAD
RN1704
1
2
E
C
1
7
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
1
7
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
INT_PIRQB#
USB_OC#2_3
USB_OC#0_1
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
USB_OC#6_7
BBS_BIT1
CLK_PCI_LPC_R
INT_PIRQF#
INT_PIRQH#
INT_PIRQE#
CLK_PCI_FB_R
CLK_PCI_KBC_R
BBS_BIT1
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQA#
DGPU_PWM_SELECT#
PCI_PLTRST#
PCI_GNT3#
PCI_PME#
DGPU_SELECT#
DGPU_PWR_EN#
USB_OC#8_9 USB_OC#6_7
USB_OC#12_13
BBS_BIT0
USB_OC#10_11 USB_OC#0_1
PCI_PLTRST#
NV_ALE
NV_CLE
PCI_GNT3#
USB_RBIAS
USB_OC#4_5
USB_OC#4_5
USB_OC#2_3
INT_PIRQG#
INT_PIRQE#
INT_PIRQC# INT_PIRQA#
NV_RCOMP
NV_ALE
INT_PIRQD#
INT_PIRQF#
INT_PIRQG#
DGPU_PWR_EN#
DGPU_HOLD_RST#
NV_CLE
FFS_INT2_R
3D3V_S5
3D3V_S5
1D8V_S0
3D3V_S0
3D3V_S0
3D3V_S0
1D8V_S0
USB_OC#8_9 61 CLK_PCI_FB 20
CLK_PCI_LPC 71
CLK_PCI_KBC 27
USB_PN12 49
USB_PP12 49
PLT_RST# 5,27,71,75,82,83
USB_PP5 32
USB_PN5 32
USB_PN11 82
USB_PP11 82
USB_PN1 82
USB_PP1 82
USB_PN3 63
USB_PP3 63
USB_PN0 49
USB_PP0 49
USB_PP13 75
USB_PN13 75
USB_PN4 82
USB_PP4 82
HDD_FALL_INT1 79
USB_PN8 57
USB_PP8 57
BBS_BIT0 21
USB_PP2 64
USB_PN2 64
SATA_ODD_DA# 56
DGPU_PWR_EN# 93
USB30_SMI# 82
DGPU_HOLD_RST# 83
KB_LED_BL_DET 69
H_SNB_IVB# 5
FFS_INT2_R 79
USB_OC#0_1 61
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (PCI/USB/NVRAM)
A3
18 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (PCI/USB/NVRAM)
A3
18 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (PCI/USB/NVRAM)
A3
18 108
<Variant Name>
Danbury Technology:
Disabled when Low.
Enable when High.
KBC CLK EMI
Reserved 0 1
1 1
BOOT BIOS Strap
GNT1#/GPIO51 BOOT BIOS Location SATA1GP/GPIO19
0 1 Reserved
SPI(Default)
SSID = PCH
0 0 LPC
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3 Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default
OC[3:0]# for Device 29 (Ports 0-7)
OC[7:4]# for Device 26 (Ports 8-13)
USB Table
13
12
X
Mini Card1 (WLAN)
Fingerprint
X
Express Card
USB Ext. port 2
10
0
11
Pair
4
5
2
3
1
Device
6
7
8
9
BLUETOOTH
CARD READER
USB Ext. port 3
CAMERA
Mini Card2 (WWAN)
External debug port use on Huron river platform
Touch Panel / 3G SIM
USB Ext. port 4 / E-SATA /USB CHARGE
0617 Modify:
J osephRemovePLT_RST AND
gatelogic IC U1801/C1802. 0628 Modify:
Add EC1803 4.7pF 0402 on CLK_PCI_LPC
base on EMC NEO suggestion.
0707 Modify:
Change R1815,R1812,R1813 to 0ohm 0402
from short pad.
0719 Modify:
Reserved TP on CLKOUT_PCI3,4 from vender feedback.
20100625 V1.2
0629 Modify:
Reseved R1816 100K 0402 on PLT_RST#.
0709 Modify:
Add R1817 0ohm and connect to KB_LED_BL_DET.
(5V Tolerance High Active)
0709 Modify:
Removed INT_PIRQH# on RN1801 pin1.
0719 Modify:
DF_TVS (NV_CLE) connect PROC_SELECT# (H_SNB_IVB#)
with R1808 2.2K5% pull up resistor to PCH VCCPNAND rail
and a R1809 1K5% series resistor base on Intel
feedback.
NV_CLE
Set to Vss when LOW
DMI & FDI Termination Voltage
Set to Vcc when HIGH
0908 X01 Modify:
Add R1818 10K PL on FFS_INT2_R(GPIO14)
0908
1120 X02 Modify:
Reserved USB_OC#0_1 connect from PCH GPIO59.
A00
1 2 R1813 0R0402-PAD R1813 0R0402-PAD
1
2
EC1802
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
EC1802
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
1
2
C1801
SC220P50V2KX-3GP
DY
C1801
SC220P50V2KX-3GP
DY
1 2
R1818 10KR2J -3-GP R1818 10KR2J -3-GP
1 2
R1807
0R0402-PAD-2-GP
R1807
0R0402-PAD-2-GP
1 2
R1809
1KR2J -1-GP
R1809
1KR2J -1-GP
1
2
EC1803
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
EC1803
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
1
2 3
4
RN1803
SRN10KJ -5-GP
RN1803
SRN10KJ -5-GP
1
2
R1816
1
0
0
K
R
2
J
-
1
-
G
P
DY
R1816
1
0
0
K
R
2
J
-
1
-
G
P
DY
1
2
3
4
5 6
7
8
9
10
RN1802
SRN8K2J -2-GP-U
RN1802
SRN8K2J -2-GP-U
1
1
2
R1814
8K2R2J -3-GP
R1814
8K2R2J -3-GP
1
2
R1808
2K2R2J -2-GP
R1808
2K2R2J -2-GP
RSVD
AV5
RSVD
AY7
RSVD
AV7
RSVD
AU3
RSVD
BG4
DF_TVS
AY1
RSVD
AT10
RSVD
BC8
RSVD
AU2
RSVD
AT4
RSVD
BB5
RSVD
BB3
RSVD
BB7
RSVD
BE8
RSVD
BD4
RSVD
BF6
RSVD
AT3
RSVD
AT1
RSVD
AY3
RSVD
AT5
RSVD
AV3
RSVD
AV1
RSVD
BB1
RSVD
BA3
RSVD
AT8
RSVD
AV10
RSVD
AY5
RSVD
BA2
RSVD
AT12
RSVD
BF3
PIRQA#
K40
PIRQB#
K38
PIRQC#
H38
PIRQD#
G38
REQ1#/GPIO50
C46
REQ2#/GPIO52
C44
REQ3#/GPIO54
E40
GNT1#/GPIO51
D47
GNT2#/GPIO53
E42
GNT3#/GPIO55
F46
PIRQE#/GPIO2
G42
PIRQF#/GPIO3
G40
PIRQG#/GPIO4
C42
PIRQH#/GPIO5
D44
USBP0N
C24
USBP0P
A24
USBP1N
C25
USBP1P
B25
USBP2N
C26
USBP2P
A26
USBP3N
K28
USBP3P
H28
USBP4N
E28
USBP4P
D28
USBP5N
C28
USBP5P
A28
USBP6N
C29
USBP6P
B29
USBP7N
N28
USBP7P
M28
USBP8N
L30
USBP8P
K30
USBP9N
G30
USBP9P
E30
USBP10N
C30
USBP10P
A30
USBP11N
L32
USBP11P
K32
USBP12N
G32
USBP12P
E32
USBP13N
C32
USBP13P
A32
PME#
K10
CLKOUT_PCI0
H49
CLKOUT_PCI1
H43
CLKOUT_PCI2
J 48
USBRBIAS#
C33
USBRBIAS
B33
OC0#/GPIO59
A14
OC1#/GPIO40
K20
OC2#/GPIO41
B17
OC3#/GPIO42
C16
OC4#/GPIO43
L16
OC5#/GPIO9
A16
OC6#/GPIO10
D14
OC7#/GPIO14
C14
CLKOUT_PCI4
H40
CLKOUT_PCI3
K42
PLTRST#
C6
TP1
BG26
TP2
BJ 26
TP3
BH25
TP6
AH38
TP7
AH37
TP8
AK43
TP9
AK45
TP16
Y13
TP17
K24
TP18
L24
TP19
AB46
TP20
AB45
TP21
B21
TP22
M20
TP23
AY16
TP25
BE28
TP26
BC30
TP27
BE32
TP28
BJ 32
TP29
BC28
TP30
BE30
TP31
BF32
TP32
BG32
TP33
AV26
TP34
BB26
TP35
AU28
TP36
AY30
TP37
AU26
TP38
AY26
TP39
AV28
TP40
AW30
TP4
BJ 16
TP5
BG16
TP15
AM5
TP14
AM4
TP13
AH12
TP12
H3
TP11
N30
TP10
C18
TP24
BG46
R
S
V
D
N
V
R
A
M
P
C
I
U
S
B
5 OF 10
Cougar
Point
PCH1E
COUGAR-GP-U2-NF
R
S
V
D
N
V
R
A
M
P
C
I
U
S
B
5 OF 10
Cougar
Point
PCH1E
COUGAR-GP-U2-NF
1 2R1803
1KR2J -1-GP
DY
R1803
1KR2J -1-GP
DY
1 2 R1804 22R2J -2-GP R1804 22R2J -2-GP
1 2R1802
1KR2J -1-GP
DY
R1802
1KR2J -1-GP
DY
1 2
R1811
22D6R2F-L1-GP
R1811
22D6R2F-L1-GP
1
2
3
4
5 6
7
8
9
10
RN1801
SRN8K2J -2-GP-U
RN1801
SRN8K2J -2-GP-U
1
2
EC1801
S
C
1
0
P
5
0
V
2
J
N
-
4
G
P DY
EC1801
S
C
1
0
P
5
0
V
2
J
N
-
4
G
P DY
1 2 R1805 22R2J -2-GP R1805 22R2J -2-GP
1 2 R1815 0R0402-PAD R1815 0R0402-PAD
1 2 R1806 22R2J -2-GP R1806 22R2J -2-GP
1 2 R1817 0R0402-PAD R1817 0R0402-PAD
1 2 R1801 4K7R2J -2-GP
DY
R1801 4K7R2J -2-GP
DY
1
2
R1810
1KR2J -1-GP
DY
R1810
1KR2J -1-GP
DY
1 2 R1812 0R0402-PAD R1812 0R0402-PAD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BATLOW#
PM_CLKRUN#
H_PM_SYNC
DSWODVREN
PM_SUS_STAT#
SUS_CLK
PM_SLP_A#
PM_SLP_SUS#
PM_SLP_S5#
PM_SLP_LAN#
DSWODVREN
PM_RSMRST#
PCH_DPWROK
PM_RI#
PM_RSMRST#
PM_RSMRST#
PCH_SUSCLK_KBC
RBIAS_CPY
SUSACK# SUS_PWR_ACK
DMI_COMP_R
SYS_RESET#
PWROK
PWROK
SYS_PWROK
MEPWROK
PM_RSMRST#
PM_PWRBTN#
AC_PRESENT
PM_SLP_LAN#
SUS_PWR_ACK
BATLOW#
PM_RI#
PCH_WAKE#
RTC_AUX_S5
3D3V_S0
RTC_AUX_S5
1D05V_VTT
3D3V_S0
3D3V_S5
PM_SLP_S4# 27,46,75
PM_SLP_S3# 27,36,37,47,75
H_PM_SYNC 5
PM_CLKRUN# 27
PCH_WAKE# 27
PCH_SUSCLK_KBC 27
DMI_RXP0 4
DMI_RXP1 4
DMI_RXP2 4
DMI_RXP3 4
PM_PWRBTN# 27
DMI_TXN0 4
DMI_TXN1 4
DMI_TXN2 4
DMI_TXN3 4
DMI_TXP0 4
DMI_TXP1 4
DMI_TXP2 4
DMI_TXP3 4
DMI_RXN0 4
DMI_RXN1 4
DMI_RXN2 4
DMI_RXN3 4
AC_PRESENT 27,86
SUS_PWR_ACK 27
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_INT 4
FDI_TXN0 4
FDI_TXP0 4
FDI_TXN6 4
FDI_TXP4 4
FDI_TXP6 4
FDI_TXN4 4
FDI_TXP2 4
FDI_TXP5 4
FDI_TXN2 4
FDI_TXN5 4
FDI_TXP7 4
FDI_TXN7 4
FDI_FSYNC0 4
FDI_LSYNC1 4
FDI_TXN3 4
FDI_TXN1 4
FDI_TXP3 4
FDI_TXP1 4
FDI_TXN[7:0] 4
FDI_TXP[7:0] 4
DMI_RXP[3:0] 4
DMI_RXN[3:0] 4
DMI_TXP[3:0] 4
DMI_TXN[3:0] 4
RSMRST#_KBC 27
S0_PWR_GOOD 27,36
RUNPWROK 45,46,47,93
XDP_DBRESET# 5
SYS_PWROK 36
PM_DRAM_PWRGD 5,37
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (DM I/FDI/PM)
A3
19 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (DM I/FDI/PM)
A3
19 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (DM I/FDI/PM)
A3
19 108
<Variant Name>
DSWODVREN - On Die DSW VR Enable
HIGH Enabled (DEFAULT)
LOW Disabled
SSID = PCH
DMI_ZCOMP keep W=4 mils and
routing length less than 500
mils.
DMI_IRCOMP keep W=4 mils and
routing length less than 500
mils.
For platforms not supporting Deep S4/S5
1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
2.DPWROK and RSMRST# will rise at the same time (connected on board)
3.SLP_SUS# and SUSACK# are left as no connect
4.SUSWARN# used as SUSPWRDNACK/GPIO30
0621 Modify:
J osephremovedQ1901/R1909/R1916 3V_5V_POK
andPM_RSMRST#relatedcontrol circuit.
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
0625 Modify:
Reserved EC1901 on PCH_SUSCLK_KBC for
EMC NEO suggestion.
0628 Modify:
Change R1904 to 100K 0402 from 10K and default stuff.
20100628 V1.3
0629 Modify:
R1926 connect to SYS_PWROK.
0707 Modify:
stuff R1925 and un-stuff R1905.
0707 Modify:
Change R1903 change to 0ohm 0402 from short pad.
0719 Modify:
Change R1908 to 10K ohm based on Intel review:
8.2K to 10K pull-down is recommended.
PCIE_WAKE#
CRB : 1K
CEKLT: 10K
0907 X01 SWAP RN1901
0920 X01 Modify:
move PCH_WAKE# to RN1901 pin4
Add R1909 PH on AC_PRESENT.
1 2 R1923
0R2J -2-GP
DY
R1923
0R2J -2-GP
DY
1 2 R1922 10KR2J -3-GP
DY
R1922 10KR2J -3-GP
DY
1 2
R1925 0R0402-PAD R1925 0R0402-PAD
1 2 R1918 330KR2J -L1-GP
DY
R1918 330KR2J -L1-GP
DY
1 2 R1920 10KR2J -3-GP
DY
R1920 10KR2J -3-GP
DY
1
TP1905TPAD14-GP TP1905TPAD14-GP
1 2 R1912
0R0402-PAD
R1912
0R0402-PAD
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ 18
DMI3RXP
BJ 20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ 24
DMI_IRCOMP
BG25
FDI_RXN0
BJ 14
FDI_RXN1
AY14
FDI_RXN2
BE14
FDI_RXN3
BH13
FDI_RXN4
BC12
FDI_RXN5
BJ 12
FDI_RXN6
BG10
FDI_RXN7
BG9
FDI_RXP0
BG14
FDI_RXP1
BB14
FDI_RXP2
BF14
FDI_RXP3
BG13
FDI_RXP4
BE12
FDI_RXP5
BG12
FDI_RXP6
BJ 10
FDI_RXP7
BH9
FDI_FSYNC0
AV12
FDI_FSYNC1
BC10
FDI_LSYNC0
AV14
FDI_LSYNC1
BB10
FDI_INT
AW16
PMSYNCH
AP14
SLP_SUS#
G16
SLP_S3#
F4
SLP_S4#
H4
SLP_S5#/GPIO63
D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE#
B9
SUS_STAT#/GPIO61
G8
SUSCLK/GPIO62
N14
ACPRESENT/GPIO31
H20
BATLOW#/GPIO72
E10
PWROK
L22
CLKRUN#/GPIO32
N3
SUSWARN#/SUSPWRDNACK/GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN#/GPIO29
K14
APWROK
L10
DPWROK
E22
DMI2RBIAS
BH21
SLP_A#
G10
DSWVRMEN
A18
SUSACK#
C12
D
M
I
F
D
I
S
y
s
t
e
m

P
o
w
e
r

M
a
n
a
g
e
m
e
n
t
3 OF 10
Cougar
Point
PCH1C
COUGAR-GP-U2-NF
D
M
I
F
D
I
S
y
s
t
e
m

P
o
w
e
r

M
a
n
a
g
e
m
e
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t
3 OF 10
Cougar
Point
PCH1C
COUGAR-GP-U2-NF
1
1 2 R1905
10KR2J -3-GP
DY
R1905
10KR2J -3-GP
DY
1 2 R1908
10KR2J -3-GP
R1908
10KR2J -3-GP
1 2 R1907
0R2J -2-GP
DY
R1907
0R2J -2-GP
DY
1 2
R1903 0R0402-PAD R1903 0R0402-PAD
1 2 R1902 750R2F-GP R1902 750R2F-GP
1 2 R1911 10KR2J -3-GP
DY
R1911 10KR2J -3-GP
DY
1 2 R1913 0R0402-PAD R1913 0R0402-PAD
1 2 R1904
100KR2J -1-GP
R1904
100KR2J -1-GP
1 2
R1909 100KR2J -1-GP R1909 100KR2J -1-GP
1
1
2
EC1901
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
EC1901
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
1 2 R1919 8K2R2J -3-GP R1919 8K2R2J -3-GP
1 2 R1906 0R0402-PAD R1906 0R0402-PAD
1 2 R1926
10KR2J -3-GP
DY
R1926
10KR2J -3-GP
DY
1
1 2
R1924 0R0402-PAD R1924 0R0402-PAD
1 2 R1917 330KR2J -L1-GP R1917 330KR2J -L1-GP
1 2 R1901 49D9R2F-GP R1901 49D9R2F-GP
1 2 R1910 0R0402-PAD R1910 0R0402-PAD
1
2
3
4 5
6
7
8
RN1901
SRN10KJ -6-GP
RN1901
SRN10KJ -6-GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XTAL25_IN
PCIE_CLK_REQ6#
CLK_BUF_EXP_N
CLK_BUF_EXP_P
SMB_CLK
CLK_BUF_CKSSCD_P
PCIE_TXP5_C
PCIE_TXN5_C
XTAL25_OUT
CLK_PCI_FB
EC_SWI#
PCH_GPIO74
PCIE_CLK_RQ2#
CLK_PCH_SRC0_P
CLK_PCH_SRC0_N
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
DRAMRST_CNTRL_PCH
PCIE_CLK_REQ6#
PEG_B_CLKRQ#
CLKOUT_DMI_N
CLKOUT_DMI_P CLK_PCH_SRC1_P
CLK_PCH_SRC1_N
ITPXDP_P
ITPXDP_N
PCIE_CLK_REQ5#
CLK_PCH_SRC3_P
CLK_PCH_SRC3_N
PCIE_TXP8_C
PCIE_TXN8_C
SML1_CLK
PEG_CLKREQ#_R
SML1_DATA
PCH_GPIO74
DRAMRST_CNTRL_PCH
SMB_DATA
XCLK_RCOMP
CLK_BUF_REF14
SML0_CLK
SML0_DATA
CL_CLK
CL_DATA
CL_RST#
SMB_DATA
SML0_CLK
PCIE_TXP4_C
PCIE_TXN4_C
PCIE_TXP2_C
PCIE_TXN2_C
SML1_DATA
SML1_CLK
CLK_BUF_DOT96_P
CLK_BUF_DOT96_N
CLK_BUF_CKSSCD_N
SMB_CLK
PEG_CLKREQ#_R
SML0_DATA
CLK_PCH_SRC7_P
CLK_PCH_SRC7_N
CLK_PCIE_NEW_REQ#
SMB_CLK
CLK_PCH_SRC4_P
CLK_PCH_SRC4_N
SMB_DATA
CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P
CLK_48_USB30
DGPU_PRSNT#
J TAG_TCK
CLK_27M_VGA_R
DGPU_PRSNT#
UMA_DIS#
PEG_B_CLKRQ#
CLK_PCIE_NEW_REQ#
USB3_PEGB_CLKREQ#
PCIE_CLK_REQ5#
CLK_PCIE_WLAN_REQ#
PCIE_CLK_RQ2#
EC_SWI#
CLK_PCH_48M
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P
CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
CLK_BUF_REF14
PCIE_CLK_LAN_REQ#
CLK_PCIE_WWAN_REQ#
CLK_PCIE_NEW#
CLK_PCIE_NEW
PCIE_TXP3_C
PCIE_TXN3_C
XTAL25_OUT
XTAL25_IN
+VCCDIFFCLKN
3D3V_S0
3D3V_S5
3D3V_S03D3V_S0
3D3V_S5 3D3V_S0
3D3V_S5
PCIE_RXN2 82
PCIE_RXP2 82
PCIE_TXN2 82
PCIE_TXP2 82
PCIE_RXN4 82
PCIE_RXP4 82
PCIE_TXN4 82
PCIE_TXP4 82
CLK_PCI_FB 18
CLK_PCIE_VGA# 83
CLK_PCIE_VGA 83
SML1_DATA 27,86
SML1_CLK 27,86
PEG_CLKREQ# 83
SMB_CLK 75
SMB_DATA 75
PCIE_RXN5 82
PCIE_RXP5 82
PCIE_TXN5 82
PCIE_TXP5 82
DRAMRST_CNTRL_PCH 37
CLK_PCIE_USB3# 82
CLK_PCIE_USB3 82
CLK_EXP_N 5
CLK_EXP_P 5
CLK_PCIE_WWAN 82
CLK_PCIE_WWAN_REQ# 82
CLK_PCIE_WWAN# 82
PCIE_RXN8 75
PCIE_RXP8 75
PCIE_TXN8 75
PCIE_TXP8 75
CLK_PCIE_NEW_REQ# 75
CLK_PCIE_NEW# 75
CLK_PCIE_NEW 75
EC_SWI# 27
USB3_PEGB_CLKREQ# 82
J TAG_TCK_VGA 86
UMA_DIS# 22
CLK_PCIE_WLAN# 82
CLK_PCIE_WLAN 82
CLK_PCIE_WLAN_REQ# 82
CLK_PCIE_LAN 82
CLK_PCIE_LAN# 82
PCIE_CLK_LAN_REQ# 82
CLK_PCH_48M 32
CLK_27M_VGA 83
PCIE_RXN3 82
PCIE_RXP3 82
PCIE_TXN3 82
PCIE_TXP3 82
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (PCI-E/SMBUS/CLOCK/CL)
A3
20 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
20 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
20 108
<Variant Name>
SSID = PCH
WWAN CLK
NEW CARD
Dock
For DIS_PX mode or MXM mode.
Intel GBE LAN
U8B3.0 CLK
Card Reader
W-WAN
NEWCARD CLK
LAN
USB3.0
WLAN
CRB : 1K
CEKLT: 10K
For VGA_ 27M
V Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3
V Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and
FLEX2
if more than 2 PCI clocks + PCI loopback are routed.
20100621 V1.2
UMA_DISCRETE#
UMA: 1 1
DIS :0 1
SG(PX) : 0 0
Optimus(Muxless) : 1 0
PCIECLKRQ1# and PCIECLKRQ2#
Support S0 power only
20100614 V1.1
0623 Modify:
Change PCIE_CLK_RQ2#&CLK_PCIE_WLAN_REQ#
pull high power to 3D3V_S0 from 3D3V_S5.(add RN2018)
20100614 V1.1
20100614 V1.1
LAN CLK
WLAN CLK
0623 Modify:
SWAP WLAN CLK and LAN CLK routing each other.
0716 Modify:
Rename PCIE_CLK_LAN_RQ1# to PCIE_CLK_LAN_REQ#.
0705 Modify:
Add R2004 from RN2001.
0625 Modify:
Move R2014 to RN2002.
0630 SWAP RN2012
0630 SWAP RN2010,RN2016
0630 Modify:
Removed LAN_XI for LAN 25MHZ and reserved TP2004.
0707 Modify:
Removed R2002 for USB3.0 48MHZ.
0709 Modify:
Add R2002 22ohm for CLK_27M_VGA.
0717 Modify:
default stuff R2002 22ohm for CLK_27M_VGA.
0630 Modify:
Removed XDP CLOCK and reserved TP2005,TP2006.
PL 10K FOR Integrated CLOCK GEN mode.
0705 Modify:
Separate RN2009 10K to RN2019,
RN2021,R2008 for layout routing.
0712 Modify:
SWAP RN2020
0712 Modify:
SWAP RN2008
0712 Modify:
SWAP RN2001 PIN6,7,8
0712 Modify:
SWAP RN2019
0719 Modify:
R2009 change to 1K from 10K
base on Intel James feedback list.
0908
0913 X01 Modify:
Reserved EC2004,EC2005 on CLK_PCIE_NEW
&CLK_PCIE_NEW# for EMC suggestion.
0915 SWAP
1112 X02 Modify:
Dell required us to disable PCIE port of WWAN slot
,If PCIE port 1 is disabled, it will cause all PCIE port
disabled,so change WWAN to PCIE port 3 from port1
at ST stage.
X02 1115
1118 X02 Modify:
Change X2001 to 82.30020.D41 from 82.30020.851
from Sourcer Dick updated.
X02 1118
A00
A00
A00
A00
A00
A00
A00
1 2 C2002 SCD1U10V2KX-5GP C2002 SCD1U10V2KX-5GP
1
2
3 4
5
6
Q2001
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
Q2001
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
1
2
R2004
10KR2J -3-GP
DY
R2004
10KR2J -3-GP
DY
1
2
R2006
1M1R2J -GP
R2006
1M1R2J -GP
1 2
R2001
22R2J -2-GP
DY
R2001
22R2J -2-GP
DY
1
2
EC2003
SC4D7P50V2CN-1GP
DY
EC2003
SC4D7P50V2CN-1GP
DY
1 2 R2016 22R2J -2-GP R2016 22R2J -2-GP
1 2 R2002
0R2J -2-GP
DY
R2002
0R2J -2-GP
DY
1 2
C2007
SC12P50V2J N-3GP
C2007
SC12P50V2J N-3GP
1
2 3
4
R
N
0R4P2R-PAD
RN2010
R
N
0R4P2R-PAD
RN2010
1
2 3
4
R
N
0R4P2R-PAD
RN2011
R
N
0R4P2R-PAD
RN2011
1
2
R2005
10KR2J -3-GP
R2005
10KR2J -3-GP
1 2R2003
0R2J -2-GP
DY
R2003
0R2J -2-GP
DY
1
2 3
4
R
N
0R4P2R-PAD
RN2016
R
N
0R4P2R-PAD
RN2016
1
2
R2010
1
0
K
R
2
J
-
3
-
G
P DY
R2010
1
0
K
R
2
J
-
3
-
G
P DY
4 1
2 3
X2001
XTAL-25MHZ-155-GP
82.30020.D41
2nd = 82.30020.G71
3rd = 82.30020.G61
X2001
XTAL-25MHZ-155-GP
82.30020.D41
2nd = 82.30020.G71
3rd = 82.30020.G61
1
2 3
4
RN2007
SRN2K2J -1-GP
RN2007
SRN2K2J -1-GP
1
1
2
R2013
1
0
K
R
2
J
-
3
-
G
PUMA
R2013
1
0
K
R
2
J
-
3
-
G
PUMA
1
1
2 3
4 RN2006
SRN10KJ -5-GP
RN2006
SRN10KJ -5-GP
1
2 3
4
RN2018
SRN10KJ -5-GP
RN2018
SRN10KJ -5-GP
1
2
R2012
1
0
K
R
2
J
-
3
-
G
P
R2012
1
0
K
R
2
J
-
3
-
G
P
1
2 3
4
RN2005
SRN2K2J -1-GP
RN2005
SRN2K2J -1-GP
1
2
R2011
1
0
K
R
2
J
-
3
-
G
PMUXLESS
R2011
1
0
K
R
2
J
-
3
-
G
PMUXLESS
1
2 3
4
RN2021 SRN10KJ -5-GP RN2021 SRN10KJ -5-GP
1 2
R2008
10KR2J -3-GP
R2008
10KR2J -3-GP
1
2
EC2004
SC4D7P50V2CN-1GP
DY
EC2004
SC4D7P50V2CN-1GP
DY
1
2 3
4
R
N
0R4P2R-PAD
RN2013
R
N
0R4P2R-PAD
RN2013
1
2 3
4
R
N
0R4P2R-PAD
RN2015
R
N
0R4P2R-PAD
RN2015
1
2
3
4 5
6
7
8
RN2001
SRN10KJ -6-GP
RN2001
SRN10KJ -6-GP
1
1
2 3
4
RN2019
SRN10KJ -5-GP
RN2019
SRN10KJ -5-GP
1
2 3
4
R
N
0R4P2R-PAD
RN2012
R
N
0R4P2R-PAD
RN2012
1
1
2
EC2005
SC4D7P50V2CN-1GP
DY
EC2005
SC4D7P50V2CN-1GP
DY
1 2
R2007
90D9R2F-1-GP
R2007
90D9R2F-1-GP
1
2 3
4
RN2008
SRN10KJ -5-GP
RN2008
SRN10KJ -5-GP
1
2
3
4 5
6
7
8
RN2002
SRN10KJ -6-GP
RN2002
SRN10KJ -6-GP
PERN1
BG34
PERP1
BJ 34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ 36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ 38
PERP6
BG38
PERN7
BG40
PERP7
BJ 40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_GND1_N
BJ 30
CLKIN_GND1_P
BG30
CLKIN_DMI_N
BF18
CLKIN_DMI_P
BE18
CLKIN_DOT_96N
G24
CLKIN_DOT_96P
E24
CLKIN_SATA_N
AK7
CLKIN_SATA_P
AK5
XTAL25_IN
V47
XTAL25_OUT
V49
REFCLK14IN
K45
CLKIN_PCILOOPBACK
H45
CLKOUT_PEG_A_N
AB37
CLKOUT_PEG_A_P
AB38
PEG_A_CLKRQ#/GPIO47
M10
PCIECLKRQ0#/GPIO73
J 2
PCIECLKRQ1#/GPIO18
M1
PCIECLKRQ2#/GPIO20
V10
PCIECLKRQ3#/GPIO25
A8
PCIECLKRQ4#/GPIO26
L12
PCIECLKRQ5#/GPIO44
L14
CLKOUTFLEX0/GPIO64
K43
CLKOUTFLEX1/GPIO65
F47
CLKOUTFLEX2/GPIO66
H47
CLKOUTFLEX3/GPIO67
K49
CLKOUT_DMI_N
AV22
CLKOUT_DMI_P
AU22
PEG_B_CLKRQ#/GPIO56
E6
CLKOUT_PEG_B_P
AB40
CLKOUT_PEG_B_N
AB42
XCLK_RCOMP
Y47
CLKOUT_DP_P
AM13
CLKOUT_DP_N
AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
PCIECLKRQ7#/GPIO46
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_ITPXDP_N
AK14
CLKOUT_ITPXDP_P
AK13
SMBALERT#/GPIO11
E12
SMBCLK
H14
SMBDATA
C9
SML0ALERT#/GPIO60
A12
SML0CLK
C8
SML0DATA
G12
SML1ALERT#/PCHHOT#/GPIO74
C13
SML1CLK/GPIO58
E14
SML1DATA/GPIO75
M16
CL_CLK1
M7
CL_DATA1
T11
CL_RST1#
P10
PCIECLKRQ6#/GPIO45
T13
P
C
I
-
E
*
C
L
O
C
K
S
F
L
E
X

C
L
O
C
K
S
S
M
B
U
S
C
o
n
t
r
o
l
l
e
r
L
i
n
k
2 OF 10
Cougar
Point
PCH1B
COUGAR-GP-U2-NF
P
C
I
-
E
*
C
L
O
C
K
S
F
L
E
X

C
L
O
C
K
S
S
M
B
U
S
C
o
n
t
r
o
l
l
e
r
L
i
n
k
2 OF 10
Cougar
Point
PCH1B
COUGAR-GP-U2-NF
1 2 R2009
1KR2J -1-GP
R2009
1KR2J -1-GP
1
2 3
4
RN2020
SRN10KJ -5-GP
RN2020
SRN10KJ -5-GP
1
2 3
4 RN2003
SRN2K2J -1-GP
RN2003
SRN2K2J -1-GP
1
2 3
4
R
N
0R4P2R-PAD
RN2014
R
N
0R4P2R-PAD
RN2014
1 2
C2008
SC12P50V2J N-3GP
C2008
SC12P50V2J N-3GP
1
2 3
4
RN2004
SRN2K2J -1-GP
RN2004
SRN2K2J -1-GP
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_J TAG_TMS
HDA_BITCLK
HDA_RST#
HDA_SYNC
PCH_J TAG_TDI
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
PCH_J TAG_TDO
RBIAS_SATA3
SATA_COMP
SATA_DET#0
PCH_J TAG_TCK_BUF
RTC_X2
SM_INTRUDER#
RTC_X2
RTC_X1
SRTC_RST#
PCH_INTVRMEN
BBS_BIT0
RTC_X1
RTC_RST#
SATA3_COMP
HDA_SPKR
HDA_SYNC
HDA_RST#
HDA_BITCLK
HDA_SDOUT
HDA_SDOUT
PCH_GPIO33
HDA_SYNC
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_CS0#
LPC_AD[0..3]
SPI_CS0#_R HDA_CODEC_BITCLK HDA_CODEC_SDOUT HDA_CODEC_SYNC
HDA_SYNC_R SATA_DET#0
INT_SERIRQ
HDA_SDOUT
HDA_SYNC HDA_SYNC_R
RTC_AUX_S5
RTC_AUX_S5
1D05V_VTT
1D05V_VTT
3D3V_S0
+3VS_+1.5VS_HDA_IO
+3VS_+1.5VS_HDA_IO
RUN_ENABLE
3D3V_S0
BBS_BIT0 18
HDA_SPKR 29
INT_SERIRQ 27
LPC_AD[0..3] 27,71
HDA_SDIN0 29
SPI_CS0#_R 27,60
SPI_SO_R 27,60
SPI_SI_R 27,60
SPI_CLK_R 27,60
SATA_LED# 68
ME_UNLOCK 27
LPC_FRAME# 27,71
HDA_CODEC_BITCLK 29
HDA_CODEC_RST# 29
HDA_CODEC_SYNC 29
SATA_RXN5 57
SATA_RXP5 57
SATA_TXN5 57
SATA_TXP5 57
SATA_RXN0 56
SATA_RXP0 56
SATA_TXN0 56
SATA_TXP0 56
SATA_RXN4 56
SATA_RXP4 56
SATA_TXN4 56
SATA_TXP4 56
KB_DET# 69
PSW_CLR# 22
FP_DET# 22
S_GPIO 22
HDA_CODEC_SDOUT 29
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (SPI/RTC/LPC/SATA/IHDA)
A3
21 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
21 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
21 108
<Variant Name>
SSID = PCH
INTVRMEN- Integrated SUS
1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs
NO REBOOT STRAP
No Reboot Strap
HDA_SPKR
Low =Default
High =No Reboot
HDA_SDOUT
Low =Default
High =Enable
Flash Descriptor Security Overide
This signal has a weak internal pull down.
On Die PLL VR is supplied by 1.5V when
sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform.
co-operate with R2310
PLL ODVR VOLTAGE
HDA_SYNC
Low =1.8V (Default)
High =1.5V
0625 Modify:
Reserved EC2101 on SPI_CSO#_R for
EMC NEO suggestion.
0625 Modify:
Reserved EC2102,EC2103 on HDA_CODEC_BITCLK&HDA_CODEC_SDOUT for
EMC NEO suggestion.
0629 Modify:
Move All of 0.01uF cap closed to all
connector base on Layout guideline.
20100625 V1.2
ESATA
ODD
HDD1
HDD2
0630 modify:
Change RN2104 PH 20K to
R2115,R2216 20K 0402.
0707 Modify:
Change RN2101 to R2122,R2123 33ohm 0402.
0707 Modify:
Reserved Q2101 for isolate CODE and PCH
base on design guide update 1.01.
0712 Modify:
Add R2124 between HDA_SYNC_R and HDA_SYNC.
HDA_SYNC: This strap is sampled on rising edgeof RSMRST#and is used to
sample1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on theboard. Signal may haveleakagepaths viapowered off devices (Audio
Codec) and hencecontend with theexternal pull-up. A blocking FET is
recommended in such acaseto isolateHDA_SYNC fromtheAudio Codec device
until after theStrap sampling is complete.
0709 Modify:
KB_DET# connect to GPIO23.(inter PH 20K)
Notes:
ME_UNLOCK (HDA_SDO) connect to EC.
Make sure EC drive this pin "low" all the time.
0720 Modify:
un-stuff R2122 33ohm.
0720 Modify:
Add R2117 100K and stuff Q2101,R2124.
0805
0916 X01 Modify:
Add RN2104 instead of R2111 10K.
A00
1 2
R2110 33R2J -2-GP R2110 33R2J -2-GP
1
2
EC2101
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
EC2101
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
1
2
C2104
SC1U6D3V2KX-GP
C2104
SC1U6D3V2KX-GP
1
2
EC2103
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
EC2103
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
1
2 3
4
RN2105 SRN33J -5-GP-U RN2105 SRN33J -5-GP-U
1 2
R2109 33R2J -2-GP R2109 33R2J -2-GP
1
2 3
4
RN2102
SRN33J -5-GP-U
RN2102
SRN33J -5-GP-U
1 2 R2103 1KR2J -1-GP R2103 1KR2J -1-GP
2
1
G2101
GAP-OPEN
G2101
GAP-OPEN
1 2
R2116
20KR2J -L2-GP
R2116
20KR2J -L2-GP
1 2 R2114 750R2F-GP R2114 750R2F-GP
1
2
R2117
100KR2J -1-GP
R2117
100KR2J -1-GP
1 2 R2107 1KR2J -1-GP R2107 1KR2J -1-GP
1
2 3
4
RN2104
SRN10KJ -5-GP
RN2104
SRN10KJ -5-GP
1 2 R2122 33R2J -2-GP
DY
R2122 33R2J -2-GP
DY
1 2 R2102 1KR2J -1-GP
DY
R2102 1KR2J -1-GP
DY
1 2
R2101 10MR2J -L-GP R2101 10MR2J -L-GP
1
2
C2103
SC1U6D3V2KX-GP
C2103
SC1U6D3V2KX-GP
1
2
C2102
SC15P50V2J N-2-GP
C2102
SC15P50V2J N-2-GP
1 2
R2115
20KR2J -L2-GP
R2115
20KR2J -L2-GP
1 4
3 2
X2101
X-32D768KHZ-67-GP
82.30001.A81
2nd = 82.30001.691
3rd = 82.30001.861
X2101
X-32D768KHZ-67-GP
82.30001.A81
2nd = 82.30001.691
3rd = 82.30001.861
1 2 R2112 37D4R2F-GP R2112 37D4R2F-GP
1 2 R2106 1KR2J -1-GP
DY
R2106 1KR2J -1-GP
DY
1
2
C
2
1
0
1
S
C
1
5
P
5
0
V
2
J
N
-
2
-
G
P
C
2
1
0
1
S
C
1
5
P
5
0
V
2
J
N
-
2
-
G
P
1 2
R2108 33R2J -2-GP R2108 33R2J -2-GP
G
S
D
Q2101
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q2101
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1
2
EC2102
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
EC2102
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
1 2
R2104
1M1R2J -GP
R2104
1M1R2J -GP
1
2
3
4 5
6
7
8
RN2103
SRN10KJ -6-GP
RN2103
SRN10KJ -6-GP
1 2 R2113 49D9R2F-GP R2113 49D9R2F-GP
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED#
P3
FWH0/LAD0
C38
FWH1/LAD1
A38
FWH2/LAD2
B37
FWH3/LAD3
C37
LDRQ1#/GPIO23
K36
FWH4/LFRAME#
D36
LDRQ0#
E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_EN#/GPIO33
C36
HDA_DOCK_RST#/GPIO13
N32
SRTCRST#
G22
SATA0RXN
AM3
SATA0RXP
AM1
SATA0TXN
AP7
SATA0TXP
AP5
SATA1RXN
AM10
SATA1RXP
AM8
SATA1TXN
AP11
SATA1TXP
AP10
SATA2RXN
AD7
SATA2RXP
AD5
SATA2TXN
AH5
SATA2TXP
AH4
SATA3RXN
AB8
SATA3RXP
AB10
SATA3TXN
AF3
SATA3TXP
AF1
SATA4RXN
Y7
SATA4RXP
Y5
SATA4TXN
AD3
SATA4TXP
AD1
SATA5RXN
Y3
SATA5RXP
Y1
SATA5TXN
AB3
SATA5TXP
AB1
SATAICOMPI
Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP/GPIO21
V14
SATA1GP/GPIO19
P1
J TAG_TCK
J 3
J TAG_TMS
H7
J TAG_TDI
K5
J TAG_TDO
H1
SERIRQ
V5
SPKR
T10
SATAICOMPO
Y11
SATA3COMPI
AB13
SATA3RCOMPO
AB12
SATA3RBIAS
AH1
R
T
C
I
H
D
A
S
A
T
A
L
P
C
S
P
I
J
T
A
G
S
A
T
A

6
G
1 OF 10
Cougar
Point
PCH1A
COUGAR-GP-U2-NF
R
T
C
I
H
D
A
S
A
T
A
L
P
C
S
P
I
J
T
A
G
S
A
T
A

6
G
1 OF 10
Cougar
Point
PCH1A
COUGAR-GP-U2-NF
1 2
R2105
330KR2F-L-GP
R2105
330KR2F-L-GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_THERMTRIP_R
INIT3_3V#
FDI_OVRVLTG
DMI_OVRVLTG
H_PECI_R
PLL_ODVR_EN
GSENSOR_DET
RTC_DET#
DBC_EN
PCH_GPIO15
EC_SMI#
DGPU_HPD_INTR#
PCH_GPIO27
GSENSOR_DET
PLL_ODVR_EN
DMI_OVRVLTG
FDI_OVRVLTG
ICC_EN#
MFG_MODE
S_GPIO GPIO0
ICC_EN#
EC_SCI#
PCH_GPIO16
DGPU_PWROK
PCH_TEMP_ALERT#
PSW_CLR#
PCH_GPIO48
VRAM_SIZE1
VRAM_SIZE2
TS_VSS
UMA_DIS#
USB2_CRT_ON#
3G_EN
H_RCIN#
RTC_DET#
USB2_CRT_ON#
H_A20GATE
SATA_ODD_PRSNT#
PCH_TEMP_ALERT#
MFG_MODE
PCH_NCTF_2
PCH_NCTF_4
PCH_NCTF_3
PCH_NCTF_1
PCH_GPIO15
PCH_GPIO48
DBC_EN
EC_SMI#
DGPU_HPD_INTR#
EC_SCI#
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S5
3D3V_S0
H_A20GATE 27
H_CPUPWRGD 5,36
H_THERMTRIP# 5,36
H_RCIN# 27
H_PECI 5,27
EC_SMI# 27
SATA_ODD_PRSNT# 56
EC_SCI# 27
DGPU_PWROK 83,92,93
SATA_ODD_PWRGT 56
FP_DET# 21
UMA_DIS# 20
3G_EN 82
PSW_CLR# 21
S_GPIO 21
RTC_DET# 60
USB2_CRT_ON# 61
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (GPIO/CPU)
A3
22 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (GPIO/CPU)
A3
22 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (GPIO/CPU)
A3
22 108
<Variant Name>
SSID = PCH
GSENSOR_ST GSENSOR_ADI

R2205 DY 10K
R2206 100K DY
ICC_EN#
GPIO36
(DMI_OVRVLTG)
DMI TERMINATION VOLTAGE OVERRIDE
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
PLL ON DIE VR ENABLE
NOTE:This signal has a weak internal pull-up
20K
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT
DISABLED -- LOW (R2212 STUFFED)
LOW (R2211)- ENABLED
Integrated Clock Chip Enable
HIGH (R2211 DY)- DISABLED [DEFAULT]
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
GPIO37
(FDI_OVRVLTG)
FDI TERMINATION VOLTAGE OVERRIDE
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
Note:
For PCH debug with XDP, need to NO STUFF R2218
GPIO8 has a weak[20K] internal pull up.
TS Signal Disable Guideline:
TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
should not float on the motherboard. They should
be tied to GND directly.
[VRAM_SIZE1:VRAM_SIZE2]
LL=512M / HL=1G / LH=2G
0625 Modify:
Change PL 100K 0402 from PH on GFX_CRB_DET.
20100625 V1.2
20100625 V1.2
GPIO27 has a weak[20K] internal pull up.
To enable on-die PLL Voltage regurator,
should not place external pull down.
0629 Modify:
Stuff R2202 200K 0402 1%(ANNIE updated)
0629 Modify:
Add R2221 10K 0402 on PCH_GPIO24(ANNIE updated)
0709 Modify:
Rename PCH_GPIO24 to 3G_EN on R2221.
0701 Modify:
Separate PCH_TEMP_ALERT# from RN2201
to R2222 10K base on layout limitation.
0701 Modify:
Separate MFG_MODE from RN2202
to R2223 10K base on layout limitation.
0705 Modify:
Removed R2214~R2217 10K 0402 on VRAM_SIZE1&2.
0707 Modify:
Change R2219 change to 0ohm 0402 from short pad.
0709 Modify:
Rename PCH_GPIO22 to DBC_EN.
Rename PCH_GPIO24 to 3G_EN.
0712 Modify:
SWAP RN2203
0714 Modify:
Add TP2206~TP2209 on PCH NCTF pin.
0719 Modify:
ChangeR2202 to 100K from200K.
0720 Modify:
Removed DBC_EN on GPIO22.
0908 X01 Modify:
change FFS_INT2_R from PCH GPIO48 to GPIO14
Keep PCH_GPIO5 PH R2201,PCH_GPIO48 PH R2220
0916 X01 Modify:
Move EC_SCI#,DBC_EN to RN2201.
Move S_GPIO to RN2103.
Move PSW_CLR# to RN2104.
0923 SWAP 1118 X02 Modify:
Rename GFX_CRB_DET to GSENSOR_DET
on GPIO39.
1120 X02 Modify:
Rename PCH_GPIO12 to RTC_DET#
on GPIO12.
1120 X02 Modify:
Rename PCH_GPIO12 to RTC_DET#
on GPIO12.
1118 X02 Modify:
Rename USB3_PWR_ON to PCH_GPIO57.
1120 X02 Modify:
Reserved USB2_CRT_ON# to control
U6102 USB power switch from PCH GPIO57.
1
2 3
4
RN2204
SRN10KJ -5-GP
RN2204
SRN10KJ -5-GP
1
2
1
G2201
G
A
P
-
O
P
E
N
G2201
G
A
P
-
O
P
E
N
1 2 R2201
1KR2J -1-GP
R2201
1KR2J -1-GP
1
2
R2210
10KR2J -3-GP
R2210
10KR2J -3-GP
1
1
1
2
R2206
100KR2J -1-GP
DY
R2206
100KR2J -1-GP
DY
1 2 R2211
1KR2J -1-GP
R2211
1KR2J -1-GP
1 2
R2213 0R0402-PAD R2213 0R0402-PAD
1
2
R2205
10KR2J -3-GP
DY
R2205
10KR2J -3-GP
DY
1 2
R2222 10KR2J -3-GP R2222 10KR2J -3-GP
1
2
3
4 5
6
7
8
RN2201
SRN10KJ -6-GP
RN2201
SRN10KJ -6-GP
1
1 2 R2212
1KR2J -1-GP
DY
R2212
1KR2J -1-GP
DY
1 2
R2202
100KR2J -1-GP
R2202
100KR2J -1-GP
1
2 3
4
RN2203
SRN10KJ -5-GP
RN2203
SRN10KJ -5-GP
1 2
R2221
10KR2J -3-GP
R2221
10KR2J -3-GP
1 2
R2223 10KR2J -3-GP R2223 10KR2J -3-GP
1 2 R2218
100R2J -2-GP
R2218
100R2J -2-GP
1 2 R2204 390R2J -1-GP R2204 390R2J -1-GP
1 2 R2203
0R2J -2-GP
DY
R2203
0R2J -2-GP
DY
1
2
R2207
10KR2J -3-GP
DY
R2207
10KR2J -3-GP
DY
1 2
R2219 0R0402-PAD R2219 0R0402-PAD
1 2
R2220 10KR2J -3-GP R2220 10KR2J -3-GP
1
2
R2208
10KR2J -3-GP
R2208
10KR2J -3-GP
1
2
R2209
10KR2J -3-GP
DY
R2209
10KR2J -3-GP
DY
GPIO27
E16
GPIO28
P8
GPIO24/MEM_LED
E8
GPIO57
D6
LAN_PHY_PWR_CTRL/GPIO12
C4
NCTF_VSS#A4
A4
NCTF_VSS#A44
A44
NCTF_VSS#A45
A45
NCTF_VSS#A46
A46
NCTF_VSS#A5
A5
NCTF_VSS#A6
A6
NCTF_VSS#B3
B3
NCTF_VSS#B47
B47
NCTF_VSS#BD1
BD1
NCTF_VSS#BD49
BD49
NCTF_VSS#BE1
BE1
NCTF_VSS#BE49
BE49
TACH2/GPIO6
H36
TACH0/GPIO17
D40
TACH3/GPIO7
E38
SATA3GP/GPIO37
M5
SATA5GP/GPIO49
V3
SCLOCK/GPIO22
T5
SLOAD/GPIO38
N2
SDATAOUT0/GPIO39
M3
SDATAOUT1/GPIO48
V13
PROCPWRGD
AY11
RCIN#
P5
PECI
AU16
THRMTRIP#
AY10
GPIO8
C10
BMBUSY#/GPIO0
T7
GPIO15
G2
TACH1/GPIO1
A42
SATA2GP/GPIO36
V8
INIT3_3V#
T14
STP_PCI#/GPIO34
K1
GPIO35
K4
SATA4GP/GPIO16
U2
NCTF_VSS#F49
F49
A20GATE
P4
TACH4/GPIO68
C40
TACH6/GPIO70
C41
TACH7/GPIO71
A40
TACH5/GPIO69
B41
NCTF_VSS#BH3
BH3
NCTF_VSS#BH47
BH47
NCTF_VSS#BJ 4
BJ 4
NCTF_VSS#BJ 44
BJ 44
NCTF_VSS#BJ 45
BJ 45
NCTF_VSS#BJ 46
BJ 46
NCTF_VSS#BJ 5
BJ 5
NCTF_VSS#BJ 6
BJ 6
NCTF_VSS#C2
C2
NCTF_VSS#C48
C48
NCTF_VSS#D1
D1
NCTF_VSS#D49
D49
NCTF_VSS#E1
E1
NCTF_VSS#E49
E49
NCTF_VSS#F1
F1
TS_VSS4
AK10
TS_VSS3
AH10
TS_VSS2
AK11
TS_VSS1
AH8
NC_1
P37
NCTF_VSS#BF1
BF1
NCTF_VSS#BF49
BF49
NCTF_VSS#BG2
BG2
NCTF_VSS#BG48
BG48
C
P
U
/
M
I
S
C
N
C
T
F
G
P
I
O
6 OF 10
N
C
T
F

T
E
S
T

P
I
N
:
A
4
,
A
4
4
,
A
4
5
,
A
4
6
,
A
5
,
A
6
,
B
3
,
B
4
7
,
B
D
1
,
B
D
4
9
,
B
E
1
,
B
E
4
9
,
B
F
1
,
B
F
4
9
B
G
2
,
B
G
4
8
,
B
H
3
,
B
H
4
7
,
B
J
4
,
B
J
4
4
,
B
J
4
5
,
B
J
4
6
,
B
J
5
,
B
J
6
,
C
2
,
C
4
8
D
1
,
D
4
9
,
E
1
,
E
4
9
,
F
1
,
F
4
9
Cougar
Point
PCH1F
COUGAR-GP-U2-NF
C
P
U
/
M
I
S
C
N
C
T
F
G
P
I
O
6 OF 10
N
C
T
F

T
E
S
T

P
I
N
:
A
4
,
A
4
4
,
A
4
5
,
A
4
6
,
A
5
,
A
6
,
B
3
,
B
4
7
,
B
D
1
,
B
D
4
9
,
B
E
1
,
B
E
4
9
,
B
F
1
,
B
F
4
9
B
G
2
,
B
G
4
8
,
B
H
3
,
B
H
4
7
,
B
J
4
,
B
J
4
4
,
B
J
4
5
,
B
J
4
6
,
B
J
5
,
B
J
6
,
C
2
,
C
4
8
D
1
,
D
4
9
,
E
1
,
E
4
9
,
F
1
,
F
4
9
Cougar
Point
PCH1F
COUGAR-GP-U2-NF
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.8VS_VCCTX_LVDS
+1.05VS_VCC_DMI_CCI
+1.05VS_VCC_DMI
+VCCA_DAC_1_2
+1.05VS_VCC_DMI
+3VS_VCCA_LVDS
VCCAPLLEXP
VCCFDIPLL
VCCVRM
1D05V_VTT
1D05V_VTT
1D05V_VTT
1D05V_VTT
3D3V_S0
1D05V_VTT
3D3V_S0
1D05V_VTT
1D8V_S0
3D3V_S5
3D3V_S0
3D3V_S0
1D8V_S0
1D5V_S0
3D3V_DAC_S0
1D5V_S0
3D3V_S0 5V_S5 3D3V_DAC_S0
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (POWER1)
A3
23 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (POWER1)
A3
23 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (POWER1)
A3
23 108
<Variant Name>
SSID = PCH
6A
2.925A(Total current of VCCIO)
0.266A (Totally VCC3_3 current)
0.159A(Totally current of VCCVRM)
0.042A (Totally current of VCCDMI)
(10uF x1)
(1uFx3)
(10uFx1_0603)
(1uF x4)
(0.1uF x1)
1.3A(Total current of VCCCORE)
(10uF x1_0603)
(0.1uF/0.01uF x1)
(22uF x1)
(0.01uF x2)
0.06A
(0.1uFx1)
(1uFx1)
0.001A
(1uF x1)
(1uFx1)
(10uFx1)
0.02A
0.19A
(0.1uFx1)
VCCVRM(Internal PLL and VRMs):
A.1.5V for Mobile
B.1.8 V for Desktop
Refer to NPCE795 shared SPI flash architecture
0.001A
0.266A
0.16A
0.042A
0.02A
0818
De-cap
0917 X01 Modify:
Change R2304 to 0R0603
short pad from 0ohm.
1111 X02 Modify:
Change VCCADAC power source to
3D3V_DAC_S0 from 3D3V_S0.
A00 1228
A00
1119 X02 Modify:
Reserved R2308 on VCCVRM power rail.
1122 X02 Modify:
Removed U2302 LDO for VCCVRM.
1117 X02 Modify:
Add G9091 LDO circuit for CRT DAC power
to avoid monitor noise issue.
1122 X02 Modify:
base on layout condition change 3D3V_DAC_S0
circuit.
Current Limit=360mA
20100621 V1.2
3.3V CRT LDO
A00
A00
A00 1229 add 3rd Richtek(74.09198.G7F) on U2301 at XBuild batch run config
1
2
C
2
3
0
9
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
3
0
9
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C
2
3
0
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
2
3
0
5
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C2313
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
C2313
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
1
2
C2323
SC1U6D3V2KX-GP
C2323
SC1U6D3V2KX-GP
1
2
C
2
3
0
2
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
3
0
2
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C
2
3
0
4
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
3
0
4
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C2310
SCD1U10V2KX-5GP
C2310
SCD1U10V2KX-5GP
1
2
C
2
3
1
6
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
C
2
3
1
6
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
1
2
C2320
SC1U6D3V2KX-GP
C2320
SC1U6D3V2KX-GP
VIN
1
GND
2
EN
3
NC#4
4
VOUT
5
U2301
G9091-330T11U-GP
2nd = 74.09198.G7F
74.09091.J3F
3rd = 74.07716.A7F
U2301
G9091-330T11U-GP
2nd = 74.09198.G7F
74.09091.J3F
3rd = 74.07716.A7F
1
2
C
2
3
0
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C
2
3
0
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
VCCCORE
AA23
VCCCORE
AC23
VCCCORE
AD21
VCCCORE
AD23
VCCCORE
AF21
VCCCORE
AF23
VCCCORE
AG21
VCCCORE
AG23
VCCCORE
AG24
VCCCORE
AG26
VCCCORE
AG27
VCCCORE
AG29
VCCCORE
AJ 23
VCCCORE
AJ 26
VCCCORE
AJ 27
VccDFTERM
AJ 17
VccDFTERM
AJ 16
VCCIO
AN21
VCCIO
AN26
VCCIO
AN27
VCCIO
AP21
VCCIO
AP26
VCCIO
AT24
VCCIO
AN16
VCCIO
AN17
VCCIO
AP23
VCCIO
AP24
VCCADAC
U48
VCCTX_LVDS
AM37
VCCTX_LVDS
AM38
VCCALVDS
AK36
VCCVRM
AT16
VCCVRM
AP16
VCCAPLLEXP
BJ 22
VCCAFDIPLL
BG6
VCCIO
AN19
VCCTX_LVDS
AP37
VCCTX_LVDS
AP36
VSSADAC
U47
VSSALVDS
AK37
VCCIO
AP17
VCC3_3
V33
VCC3_3
V34
VCC3_3
BH29
VccDFTERM
AG17
VccDFTERM
AG16
VCCDMI
AT20
VCCIO
AN33
VCCIO
AN34
VCCCORE
AJ 29
VCCCORE
AJ 31
VCCSPI
V1
VCCCLKDMI
AB36
VCCDMI
AU20
POWER
V
C
C

C
O
R
E
D
M
I
V
C
C
I
O
C
R
T
L
V
D
S
F
D
I
N
A
N
D

/

S
P
I
H
V
C
M
O
S
7 OF 10
Cougar
Point
PCH1G
COUGAR-GP-U2-NF
POWER
V
C
C

C
O
R
E
D
M
I
V
C
C
I
O
C
R
T
L
V
D
S
F
D
I
N
A
N
D

/

S
P
I
H
V
C
M
O
S
7 OF 10
Cougar
Point
PCH1G
COUGAR-GP-U2-NF
1 2
R2307
0R0402-PAD-2-GP
R2307
0R0402-PAD-2-GP
1
2
C2312
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C2312
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C2315
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C2315
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C2319
SCD1U10V2KX-5GP
C2319
SCD1U10V2KX-5GP
1
2
C2322
SCD1U10V2KX-5GP
C2322
SCD1U10V2KX-5GP
1
2
C2321
SC1U6D3V2KX-GP
C2321
SC1U6D3V2KX-GP
1 2
R2306
0R0402-PAD-2-GP
R2306
0R0402-PAD-2-GP
1 2
R2308
0R0402-PAD-2-GP
R2308
0R0402-PAD-2-GP
1
2
C
2
3
0
7
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
3
0
7
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C2318
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C2318
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1 2
R2301
0R0402-PAD-2-GP
R2301
0R0402-PAD-2-GP
1 2
L2301
HCB1608KF-181-GP
2nd = 68.00206.041
3rd = 68.00335.081
68.00214.051
DY
L2301
HCB1608KF-181-GP
2nd = 68.00206.041
3rd = 68.00335.081
68.00214.051
DY
1
2
C
2
3
0
8
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
3
0
8
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C
2
3
0
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
3
0
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1 2 R2305
0R0805-PAD
R2305
0R0805-PAD
1
2
C
2
3
0
3
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
3
0
3
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C
2
3
1
7
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
C
2
3
1
7
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
1
2
C2314
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C2314
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C2311
S
C
1
U
1
0
V
2
K
X
-
1
G
P
C2311
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1 2 R2304
0R0603-PAD
R2304
0R0603-PAD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V1.05S_SSCVCC
+VCCSUS1
+V1.05S_VCCAPLL_SATA3
+V3.3S_VCC_CLKF33
+V1.05S_SSCVCC
+V3.3S_VCC_CLKF33
+1.05VS_VCCA_A_DPL
+VCCRTCEXT
DCPSUSBYP
VCCACLK
+VCCSST
+VCCDIFFCLK
+1.05VS_VCCA_B_DPL
+5VA_PCH_VCC5REFSUS
+VCCAPLL_CPY_PCH
+5VS_PCH_VCC5REF
+VCCPDSW
+VCCDIFFCLK
+VCCA_USBSUS
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+1.05VS_VCCA_A_DPL
DCPSUS
3D3V_S5
3D3V_S5
3D3V_S0
3D3V_S5
1D05V_VTT
1D05V_VTT
3D3V_S0
1D05V_VTT
3D3V_S0
1D05V_VTT
1D05V_VTT
1D05V_VTT
1D05V_VTT
RTC_AUX_S5
1D05V_VTT
3D3V_S0
1D5V_S0
1D05V_VTT
1D05V_VTT
+VCCDIFFCLKN
3D3V_S5
1D05V_VTT
3D3V_S5
1D05V_VTT
5V_S0
5V_S5
1D5V_S0
+3VS_+1.5VS_HDA_IO
3D3V_S5
+3VS_+1.5VS_HDA_IO
3D3V_S5
1D05V_VTT
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (POWER2)
A3
24 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (POWER2)
A3
24 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (POWER2)
A3
24 108
<Variant Name>
SSID = PCH
(1uFx1)
(10uFx1)
(0.1uFx1)
(1uFx3)
(22uFx2_0603)
(10uFx1)
0.002A
1.01A (Total current of VCCASW)
0.16A (Totally current of VCCVRM
(0.1uFx1)
0.055A
(0.1uFx1)
0.095A
0.001A
6uA
(0.1uFx2)
(1uFx1)
(1uFx1)
(0.1uFx2)
(1uFx1)
(1uFx1)
(4.7uFx1_0603)
(1uFx1)
(10uFx1)
(0.1uFx1)
(1uFx1)
(0.1uFx2)
(1uFx1)
0.01A
(1uFx1)
0.001A
0.001A
0.097A (Totally current of VCCSUS3_3)
(1uFx1)
(0.1uFx1)
(0.1uFx1)
(0.1uFx1)
(0.1uFx1)
(1uFx1)
0617 Modify:
J osephRename1D5V_S0_1D8V_S0 to 1D5V_S0 for VCCVRM.
0714 Modify:
Reserved C2443,C2444 on +1.05VS_VCCA_A_DPL,
+1.05VS_VCCA_B_DPL same as DG15.
0.08A
0.08A
(220uFx1)
(220uFx1)
(1uFx1)
(1uFx1)
0714 Modify:
Removed C2419 1uF base on
Annie updated schematic.
0818
De-cap
0818
De-cap
0818
De-cap
A00
A00
2
1
D2402
CH751H-40PT-GP
83.R0304.A8F 2nd =83.R2004.B8F
D2402
CH751H-40PT-GP
83.R0304.A8F 2nd =83.R2004.B8F
1
2
C2423
SCD1U10V2KX-5GP
C2423
SCD1U10V2KX-5GP
1 2
L2401
IND-10UH-218-GP
2nd = 68.1001E.10N
68.10050.10Y
L2401
IND-10UH-218-GP
2nd = 68.1001E.10N
68.10050.10Y
1
2
C2427
SC1U10V2KX-1GP
C2427
SC1U10V2KX-1GP
1
2
C2434
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C2434
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
DCPSUSBYP
V12
VCCASW
AA19
VCCASW
AA21
VCCASW
AA24
VCCASW
AA27
VCCASW
AA29
VCCSUSHDA
P32
VCCSUS3_3
P24
VCCIO
T26
VCCIO
AD17
VCCASW
AA31
VCCASW
AC26
VCCASW
AC27
VCCASW
AC29
VCCASW
AC31
VCCASW
AD29
V5REF
P34
VCC3_3
T34
VCCRTC
A22
VCCSUS3_3
V24
VCCSUS3_3
V23
VCCSUS3_3
T24
VCCSUS3_3
T23
VCCIO
AC16
VCCADPLLB
BF47
VCCDIFFCLKN
AF33
V5REF_SUS
M26
VCCIO
AC17
DCPSUS
T17
VCCSSC
AG33
VCCADPLLA
BD47
VCCVRM
Y49
VCCACLK
AD49
DCPRTC
N16
VCCASW
AA26
VCCDIFFCLKN
AF34
VCCIO
AF17
DCPSST
V16
VCCIO
AF13
VCCASW
T21
VCCASW
V21
VCCASW
T19
VCC3_3
AA16
VCC3_3
W16
VCCSUS3_3
N20
VCCSUS3_3
N22
VCCSUS3_3
P20
VCCSUS3_3
P22
VCCIO
N26
VCCIO
P26
VCCIO
P28
VCCIO
T27
V_PROC_IO
BJ 8
VCCIO
T29
VCCDIFFCLKN
AG34
VCCASW
AD31
VCCASW
W21
VCCASW
W23
VCCASW
W24
VCCASW
W26
VCCASW
W29
VCCASW
W31
VCCASW
W33
VCCIO
AF14
VCCVRM
AF11
VCCIO
AH13
VCCIO
AH14
VCC3_3
AJ 2
VCCAPLLSATA
AK1
DCPSUS
AL24
VCCIO
AL29
DCPSUS
AN23
VCCSUS3_3
AN24
VCCAPLLDMI2
BH23
DCPSUS
V19
VCCDSW3_3
T16
VCC3_3
T38
POWER
S
A
T
A
U
S
B
C
l
o
c
k

a
n
d

M
i
s
c
e
l
l
a
n
e
o
u
s
H
D
A
C
P
U
R
T
C
P
C
I
/
G
P
I
O
/
L
P
C
M
I
S
C
10 OF 10
Cougar
Point
PCH1J
COUGAR-GP-U2-NF
POWER
S
A
T
A
U
S
B
C
l
o
c
k

a
n
d

M
i
s
c
e
l
l
a
n
e
o
u
s
H
D
A
C
P
U
R
T
C
P
C
I
/
G
P
I
O
/
L
P
C
M
I
S
C
10 OF 10
Cougar
Point
PCH1J
COUGAR-GP-U2-NF
1
2
C2411
SCD1U10V2KX-5GP
C2411
SCD1U10V2KX-5GP
1 2
L2403
IND-10UH-218-GP
2nd = 68.1001E.10N
68.10050.10Y
L2403
IND-10UH-218-GP
2nd = 68.1001E.10N
68.10050.10Y
1
2
C2426
SCD1U10V2KX-5GP
C2426
SCD1U10V2KX-5GP
1
2
C
2
4
1
8
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
4
1
8
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C2429
SCD1U10V2KX-5GP
C2429
SCD1U10V2KX-5GP
1
2
C
2
4
0
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
4
0
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1 2
L2402
IND-10UH-218-GP
2nd = 68.1001E.10N
68.10050.10Y
L2402
IND-10UH-218-GP
2nd = 68.1001E.10N
68.10050.10Y
1 2
R2411
0R3J -0-U-GP
DY
R2411
0R3J -0-U-GP
DY
1
2
C
2
4
0
7
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
4
0
7
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1 2 R2403
0R0603-PAD
R2403
0R0603-PAD
1
2
C2430
SCD1U10V2KX-5GP
C2430
SCD1U10V2KX-5GP
1
2
C
2
4
0
8
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
4
0
8
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C2433
SCD1U10V2KX-5GP
C2433
SCD1U10V2KX-5GP
1
2
C
2
4
2
2
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
4
2
2
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C2443
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C2443
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C2425
SCD1U10V2KX-5GP
C2425
SCD1U10V2KX-5GP
2
1
D2401
CH751H-40PT-GP
83.R0304.A8F 2nd =83.R2004.B8F
D2401
CH751H-40PT-GP
83.R0304.A8F 2nd =83.R2004.B8F
1 2
C2415
SCD1U10V2KX-5GP
C2415
SCD1U10V2KX-5GP
1
2
C2404
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C2404
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C2403
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C2403
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
1
2
C2412
SC1U6D3V2KX-GP
C2412
SC1U6D3V2KX-GP
1
2
C2444
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C2444
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C2402
SC1U10V2KX-1GP
C2402
SC1U10V2KX-1GP
1
2
C2413
SC1U6D3V2KX-GP
C2413
SC1U6D3V2KX-GP
1
2
C2435
SCD1U10V2KX-5GP
C2435
SCD1U10V2KX-5GP
1
2
C
2
4
2
1
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
4
2
1
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1 2 R2409
0R0603-PAD
R2409
0R0603-PAD
1 2
R2408
10R2J -2-GP
R2408
10R2J -2-GP
1
2
C2428
SC1U6D3V2KX-GP
C2428
SC1U6D3V2KX-GP
1
2
C2431
SCD1U10V2KX-5GP
C2431
SCD1U10V2KX-5GP
1
2
C2409
SC1U6D3V2KX-GP
C2409
SC1U6D3V2KX-GP
1
2
C2424
SCD1U10V2KX-5GP
C2424
SCD1U10V2KX-5GP
1 2
R2405
0R0402-PAD-2-GP
R2405
0R0402-PAD-2-GP
1 2
R2407
10R2J -2-GP
R2407
10R2J -2-GP
1 2 R2406
0R0603-PAD
R2406
0R0603-PAD
1
2
C2410
SC1U6D3V2KX-GP
C2410
SC1U6D3V2KX-GP
1
2
C2417
SC4D7U6D3V3KX-GP
C2417
SC4D7U6D3V3KX-GP
1
2
C2432
SC1U6D3V2KX-GP
C2432
SC1U6D3V2KX-GP
1
2
C2437
SC1U10V2KX-1GP
DY
C2437
SC1U10V2KX-1GP
DY
1 2
R2404
0R0402-PAD-2-GP
R2404
0R0402-PAD-2-GP
1
2
C2414
SC1U6D3V2KX-GP
C2414
SC1U6D3V2KX-GP
1
2
C2401
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
C2401
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (VSS)
A3
25 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (VSS)
A3
25 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
PCH (VSS)
A3
25 108
<Variant Name>
SSID = PCH
VSS
AY4
VSS
AY42
VSS
AY46
VSS
AY8
VSS
B11
VSS
B15
VSS
B19
VSS
B23
VSS
B27
VSS
B31
VSS
B35
VSS
B39
VSS
B7
VSS
BB12
VSS
BB16
VSS
BB20
VSS
BB22
VSS
BB24
VSS
BB28
VSS
BB30
VSS
BB38
VSS
BB4
VSS
BB46
VSS
BC14
VSS
BC18
VSS
BC2
VSS
BC22
VSS
BC26
VSS
BC32
VSS
BC34
VSS
BC36
VSS
BC40
VSS
BC42
VSS
BC48
VSS
BD46
VSS
BD5
VSS
BE22
VSS
BE26
VSS
BE40
VSS
BF10
VSS
BF12
VSS
BF16
VSS
BF20
VSS
BF22
VSS
BF24
VSS
BF26
VSS
BF28
VSS
BD3
VSS
BF30
VSS
BF38
VSS
BF40
VSS
BF8
VSS
BG17
VSS
BG21
VSS
BG33
VSS
BG44
VSS
BG8
VSS
BH11
VSS
BH15
VSS
BH17
VSS
BH19
VSS
BH27
VSS
BH31
VSS
BH33
VSS
BH35
VSS
BH39
VSS
BH43
VSS
BH7
VSS
D3
VSS
D12
VSS
D16
VSS
D18
VSS
D22
VSS
D24
VSS
D26
VSS
D30
VSS
D32
VSS
K7
VSS
L18
VSS
L2
VSS
L20
VSS
L26
VSS
L28
VSS
L36
VSS
L48
VSS
M12
VSS
P16
VSS
M18
VSS
M22
VSS
M24
VSS
M30
VSS
M32
VSS
M34
VSS
M38
VSS
M4
VSS
M42
VSS
M46
VSS
M8
VSS
N18
VSS
P30
VSS
P11
VSS
P18
VSS
T33
VSS
P40
VSS
P43
VSS
P47
VSS
P7
VSS
R2
VSS
R48
VSS
T12
VSS
T31
VSS
T37
VSS
T4
VSS
W34
VSS
T46
VSS
T47
VSS
T8
VSS
V11
VSS
V17
VSS
V26
VSS
V27
VSS
V29
VSS
V31
VSS
V36
VSS
V39
VSS
V43
VSS
V7
VSS
W17
VSS
W19
VSS
D34
VSS
D38
VSS
D42
VSS
D8
VSS
E18
VSS
E26
VSS
G18
VSS
G20
VSS
G26
VSS
G28
VSS
G36
VSS
G48
VSS
H12
VSS
H18
VSS
W2
VSS
W27
VSS
W48
VSS
Y12
VSS
Y38
VSS
Y4
VSS
Y42
VSS
Y46
VSS
Y8
VSS
BG29
VSS
N24
VSS
AJ 3
VSS
N47
VSS
H22
VSS
H24
VSS
H26
VSS
H30
VSS
H32
VSS
H34
VSS
F3
VSS
K39
VSS
K46
VSS
H46
VSS
K18
VSS
K26
VSS
AD47
VSS
B43
VSS
BE10
VSS
BG41
VSS
G14
VSS
H16
VSS
T36
VSS
BG22
VSS
BG24
VSS
C22
VSS
AP13
VSS
F45
VSS
H10
VSS
M14
VSS
AP3
VSS
AP1
VSS
BE16
VSS
BC16
VSS
BG28
VSS
BJ 28
9 OF 10
Cougar
Point
PCH1I
COUGAR-GP-U2-NF
9 OF 10
Cougar
Point
PCH1I
COUGAR-GP-U2-NF
VSS
AA17
VSS
AA2
VSS
AA3
VSS
AA34
VSS
AB11
VSS
AB14
VSS
AB39
VSS
AB4
VSS
AB43
VSS
AB5
VSS
AB7
VSS
AC19
VSS
AC2
VSS
AC21
VSS
AC24
VSS
AC33
VSS
AC34
VSS
AC48
VSS
AD10
VSS
AD11
VSS
AD12
VSS
AD13
VSS
AD19
VSS
AD24
VSS
AD26
VSS
AD27
VSS
AD33
VSS
AD34
VSS
AD36
VSS
AD37
VSS
AD39
VSS
AD4
VSS
AD40
VSS
AD42
VSS
AD43
VSS
AD45
VSS
AD46
VSS
AF10
VSS
AF12
VSS
AD16
VSS
AF16
VSS
AF19
VSS
AF24
VSS
AF26
VSS
AF27
VSS
AF29
VSS
AF31
VSS
AF38
VSS
AF4
VSS
AF42
VSS
AF46
VSS
AF7
VSS
AF8
VSS
AG19
VSS
AG2
VSS
AG31
VSS
AG48
VSS
AH11
VSS
AH3
VSS
AH36
VSS
AH39
VSS
AH40
VSS
AH42
VSS
AH46
VSS
AH7
VSS
AJ 19
VSS
AJ 33
VSS
AJ 34
VSS
AK12
VSS
AK3
VSS
AK38
VSS
AK4
VSS
AK42
VSS
AK46
VSS
AK8
VSS
AL16
VSS
AL17
VSS
AL19
VSS
AL2
VSS
AL21
VSS
AL23
VSS
AL26
VSS
AL27
VSS
AL31
VSS
AL48
VSS
AM11
VSS
AM14
VSS
AM36
VSS
AM39
VSS
AM45
VSS
AM46
VSS
AM7
VSS
AN2
VSS
AN29
VSS
AN3
VSS
AN31
VSS
AP12
VSS
AP19
VSS
AP28
VSS
AP30
VSS
AP32
VSS
AP38
VSS
AP42
VSS
AP46
VSS
AP8
VSS
AR2
VSS
AR48
VSS
AT11
VSS
AT13
VSS
AT18
VSS
AT22
VSS
AT26
VSS
AT28
VSS
AT30
VSS
AT32
VSS
AT42
VSS
AT46
VSS
AT7
VSS
AU24
VSS
AU30
VSS
AV16
VSS
AV20
VSS
AV24
VSS
AV30
VSS
AV38
VSS
AV4
VSS
AV43
VSS
AV8
VSS
AW14
VSS
AW18
VSS
AW2
VSS
AW22
VSS
AW26
VSS
AW28
VSS
AW32
VSS
AW34
VSS
AW36
VSS
AW40
VSS
AW48
VSS
AV11
VSS
AY12
VSS
AY22
VSS
AY28
VSS
AD8
VSS
AE3
VSS
AD14
VSS
AP4
VSS
H5
VSS
AF5
VSS
AD38
VSS
AA33
VSS
AJ 21
VSS
AJ 24
VSS
AE2
VSS
AT34
VSS
AT39
VSS
AM43
VSS
AL34
VSS
AL33
8 OF 10
Cougar
Point
PCH1H
COUGAR-GP-U2-NF
8 OF 10
Cougar
Point
PCH1H
COUGAR-GP-U2-NF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Reserved
A3
26 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Reserved
A3
26 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Reserved
A3
26 108
<Variant Name>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PSL_IN1
PROCHOT_EC
ECSMI#_KBC
EC_GPIO97
ECRST#
USB3_PWR_ON
EC_SPI_DO_C
EC_SPI_CLK_C
ECSWI#_KBC
ECSCI#_KBC
PECI
KCOL0
ECRST#
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KROW0
KROW1
KCOL1
KROW2
KCOL2
KROW3
KCOL3
KCOL4
KROW4
KROW5
KCOL5
KCOL6
KROW6
KROW7
KCOL7
KCOL8
KBC_VCORF
PANEL_BLEN
ECSCI#_KBC
ECSWI#_KBC
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
MEDIA_BTN1#
VBAT
H_PROCHOT#_EC
PROCHOT_EC
3D3V_AUX_KBC_VCC
EC_GPIO72
EC_SPI_DI_C
PSL_OUT
ECSMI#_KBC
PSL_IN2
PLT_RST#_EC
PCB_VER_AD
MODEL_ID_DET
USB_DET#
EC_SPI_CS#_C
MEDIA_BTN2#
E
C
_
A
G
N
D
EC_SPI_DI_C
EC_ENABLE#_1
PANEL_BLEN
EC_VTT
KBC_ON#
EC_GPIO72
AC_IN#_KBC
KBC_ON#_R
AC_OK
KBC_ON#_R KBC_ON#
EC_ENABLE#_1
PSL_IN1
EC_GPIO72
FAN_TACH1
E51_RxD
BAT_SCL
BAT_SDA
BLUETOOTH_EN
AC_IN#_KBC
BAT_IN#
S5_ENABLE
ECRST#
EC_ENABLE#_1
PSL_IN1
ECSWI#_KBC
ECSCI#_KBC
ECSMI#_KBC
PCB_VER_AD MODEL_ID_DET
CPU_THRM
USB3_PWR_ON
SYS_THRM
KBC_ON#_R
INSTANT_ON#
MEDIA_BTN1#
MEDIA_BTN3#
MEDIA_BTN1#
PCIE_WAKE#
USB_DET#
USB_DET#
KBC_ON#_R
USBDET_CON#
KBC_ON#_R
DATA_RECOVERY#
MEDIA_BTN2#
PSL_OUT
AD_IA_HW2
KBC_ON#_R
EC_GPIO72
KBC_ON#
PSL_IN2
AC_IN#_KBC
KBC_ON#_GATE
S5_ENABLE
MEDIA_BTN2#
MODEL_ID_DET
3D3V_S0
3D3V_AUX_KBC
EC_AGND
1D05V_VTT
3D3V_AUX_S5
EC_AGND
3D3V_AUX_KBC RTC_AUX_S5
3D3V_AUX_KBC
3D3V_AUX_KBC
3D3V_S0
3D3V_AUX_KBC
EC_AGND
3D3V_AUX_KBC
EC_AGND
EC_AGND
EC_AGND 3D3V_AUX_KBC
3D3V_AUX_S5
3D3V_AUX_S5
3D3V_AUX_KBC
3D3V_AUX_KBC
EC_AGND
SPI_CLK_R 21,60
SPI_SI_R 21,60
BAT_IN# 39
SPI_SO_R 21,60
AD_IA 40
PM_SLP_S3# 19,36,37,47,75
KBC_BEEP 29
SPI_CS0#_R 21,60
TPCLK 69
TPDATA 69
USB_PWR_EN# 61
EC_SCI# 22
EC_SWI# 20
PM_SLP_S4# 19,46,75
AMP_MUTE# 29
RSMRST#_KBC 19
BLON_OUT 49
SUS_PWR_ACK 19
PCH_SUSCLK_KBC 19
PLT_RST# 5,18,71,75,82,83
PURE_HW_SHUTDOWN# 28,36,86
PWRLED# 68
ME_UNLOCK 21
H_PECI 5,22
KCOL[0..16] 69
KROW[0..7] 69
H_A20GATE 22
LID_CLOSE# 70
BAT_SDA 39,40
BAT_SCL 39,40
WIFI_RF_EN 82
PM_CLKRUN# 19
LPC_FRAME# 21,71
INT_SERIRQ 21
LPC_AD[0..3] 21,71
S5_ENABLE 36
E51_RxD 82
E51_TxD 82
AC_PRESENT 19,86
BLUETOOTH_EN 63,82
CLK_PCI_KBC 18
SML1_DATA 20,86
SML1_CLK 20,86
HDMI_IN# 51
PM_PWRBTN# 19
H_RCIN# 22
H_PROCHOT# 5,40,42
CHG_AMBER_LED# 68
USB3_PWR_ON 82
EC_SMI# 22
FAN1_DAC 28
FAN_TACH1 28
CPU_THRM 28
SYS_THRM 28
S0_PWR_GOOD 19,36
L_BKLT_EN 17
KB_BL_CTRL 69
PSID_EC 82
USBCHARGER_CB0 57
PM_LAN_ENABLE 82
LCD_TST 49
BATT_WHITE_LED# 68
CAP_LED 69
RCID 82
LCD_TST_EN 49
TP_LOCK_LED# 68
AC_OK 40
FAN_TACH1 28
MEDIA_LED1# 82
MEDIA_LED3# 82
IMVP_PWRGD 36,42
PCIE_WAKE# 75,82
MEDIA_BTN3# 82
PCH_WAKE# 19
EC_SCI# 22
EC_SWI# 20
EC_SMI# 22
MEDIA_LED2# 82
AD_IA_HW 40
USBDET_CON# 57
INSTANT_ON# 82
DATA_RECOVERY# 82
AD_IA_HW2 40
KBC_PWRBTN# 68
AC_IN# 40
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
KBC Nuvoton NPCE795
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
KBC Nuvoton NPCE795
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
KBC Nuvoton NPCE795
A2
<Core Design>
<------PCH / eDP
<------ BATTERY / CHARGER
SSID = KBC
NOTE:
Connect GND and AGND planes via either
0R resistor or one point layout connection.
Need very close to EC
EC_GPIO47 High Active
NOTE:
Locate resistors R2736,R2719 and R2722 close
to the NPCE795P.
<------ TP
ROSA Multi GPIO setting
0604 Modify:
Add Pull down 100k ohm at F_SDI for Power consumption concern.
0604 Modify:
RN2704 pull-Low 10K Resistor to DY
on BLUETOOTH_EN.
20100609 V1.0
0621 Modify:
Removed R2723
PSL SOLUTION
PSL_IN1
PSL_OUT
10mW SOLUTION
VBACKUP
0623 Modify:
Change RN2704 to R2708 10K 0402
Resistor on BLUETOOTH_EN.
0604 Modify:
RN2704 pull-Low 10K Resistor to DY
on BLUETOOTH_EN.
0623 Modify:
Change RN2702 to R2712 10K 0402
Resistor on FAN_TACH1.
EC GPIO standard PH/PL
0628 Modify:
Move R2771 to closed 3D3V_AUX_KBC power
rail base on layout placement.
0628 Modify:
Stuff R2712 and Removed R2805.
0629 Modify:
Rename PWRLED#&PWR_BTN_LED#&CHARGE_LED#.
0715 Modify:
Removed PWR_BTN_LED# on KBC GPIO45.
0720 Modify:
Change MEDIA_LED2# to KBC GPIO45.
Add AD_IA_HW on KBC GPIO66.
0629 Modify:
Rename TP_LOCK_LED#&BATT_WHITE_LED#
0630 Modify:
Removed LID_CLOSE#
PH 10K on RN2705.
0630 Modify:
Removed R2762 100K 0402.
0702 Modify:
Rename EC_GPIO6 to PSL_IN2
0702 Modify:
Rename EC_GPIO71 to PSL_OUT
0702 Modify:
0702 Modify:
Rename EC_GPIO71 to PSL_OUT
0702 Modify:
Rename CHARGE_LED# to CHG_AMBER_LED#
Rename DC_BATFULL# to BATT_WHITE_LED#.
0702 Modify:
0707 Modify:
KBC_GPIO14 change to PCIE_WAKE#.
0706 Modify:
KBC GPIO7 change to DISCRETE#
KBC GPIO97 change to IMVP_PWRGD.
0707 Modify:
Rename DISCRETE# to MODEL_ID_DET.
Rename EC_GPIO36 for MEDIA_BTN3#.
0707 Modify:
Rename DISCRETE# to MODEL_ID_DET.
Change R2739 to 100K 0402 from 10K.
Reserved
47.0K
1.65V Reserved
64.9K
76.8
100.0K
PCB VERSION A/D(PIN98) PULL-LOWRESISTOR PULL-HIGH RESISTOR VOLTAGE
100.0K X00
X01
3.0V
2.75V
X02
100.0K
2.48V
A00
100.0K
100.0K
100.0K
100.0K
100.0K
10.0K
2.24V
Reserved
20.0K
2.0V
33.0K
1.87V
0707 Modify:
Rename PCH_TEMP_ALERT# for HDMI_IN#
0708 Modify:
Rename EG_EN to MEDIA_BTN2# on GPIO96.
0709 Modify:
KB_DET# rename to MEDIA_BTN1# on KBC GPIO26.
0709 Modify:
Removed R2772 10K PH on EC_GPIO27.
0714 Modify:
Un-stuff D2705 and Add R2760 between EC_SMI# and
ECSMI#_KBC already confirm with NUVOTON and SW.
0709 Modify:
EC_GPIO27 change to PCH_WAKE# to PCH.
0712 Modify:
default stuff R2756, un-stuff R2734.
0714 Modify:
Add USB_DET# on KBC GPIO57/KBSOUT17.
143.0K 100.0K 1.358V Reserved
174.0K Reserved 100.0K 1.204V
Reserved 100.0K 215.0K 1.048V
MODEL_ID_DET(GPIO07)
143.0K 100.0K 1.358V
174.0K 100.0K
47.0K
1.65V
64.9K
76.8K
100.0K
PULL-LOWRESISTOR PULL-HIGH RESISTOR VOLTAGE
100.0K DQ15_UMA 3.0V
2.75V 100.0K
2.48V 100.0K
100.0K
100.0K
100.0K
100.0K
10.0K
2.24V
20.0K
2.0V
33.0K
1.87V
1.204V
DQ15_Ventura 100.0K 215.0K 1.048V
DQ15_ATI
DQ15_NVIDIA
DN15_UMA
DN15_ATI
DQ13_UMA
DQ13_ATI
DN13_UMA
DN13_ATI
0714 Modify:
Change C2709,C2710 to EC_AGND from GND.
20100712 V1.5
0714 Modify:
Un-stuff D2701,D2704 and Add R2758,R2759
ohm confirm with NUVOTON and SW.
0719 Modify:
Reserved 0.1uF on all of ADC input pins base on
NUVOTON feedback list.(C2717~C2721)
0719 Modify:
Reserved 0.1uF on all of ADC input pins base on
NUVOTON feedback list.(C2717~C2721)
Notes:
The total SPI interface signal between EC and PCH
cant not exceed 6500mil. The mismatch between
SPI signal must be within 500mil
NOTES:
The NPCE795P GPIO/PWM outputs that are connected
to LEDs have high drive buffers (20mA) and can be
connected directly to the LEDs.
C2712 Need very close to EC
NOTES:
Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.
0720 Modify:
Stuff C2714 0.1uF on AD_IA.
0722 Modify:
Add R2757 0ohm only for DQ15 stuff,
change D2706 only for DN15 stuff.
0712 Modify:
Add D2706 connect to MEDIA
BUTTON Instant_on#.
0713 Modify:
Add R2772,D2707 for USBCHARGER
DETECT Function.
0709 Modify:
Add R2774,R2775 PH 100K to 3D3V_AUX_KBC
for MEDIA_BTN2#,MEDIA_BTN3#.
Add R2776 100K to 3D3V_AUX_KBC for PCIE_WAKE#
from DEVICE to KBC.
KB_DET# rename to MEDIA_BTN1# on KBC GPIO26.
MEDIA BUTTON CONTROL
0723 Modify:
Add R2764,D2708 Base on Dell Peter request, both
13/15 Media BTN 2(Recovery Button) need
support bootable capability.
0728
0902 X01 Modify:
Add C2722 0.1uF between Q2703 G&S pin for
fixed leakage voltage to 3D3V_AUX_KBC under
DC mode.
0916 X01 Modify:
Add Q2706 2N7002 to avoid leakage loop from
3D3V_S5 to 3D3V_AUX_KBC issue when 10mW
latched fail timing.
215K=64.21535.6DL
A00 1222
A00 R2739 R2774 for change to parallel resistor
A00
A00
A00
A00
A00
A00
Ventura need to change to 215K(64.21535.6DL)
A00 1228
A00 1228
A00 1228
A00 1228
1
2
C2701
S
C
2
D
2
U
1
0
V
3
K
X
-1
G
P
C2701
S
C
2
D
2
U
1
0
V
3
K
X
-1
G
P
1
2
R2726
100KR2F-L1-GP
R2726
100KR2F-L1-GP
1 2
C2711
SC220P50V2KX-3GP
DY
C2711
SC220P50V2KX-3GP
DY
1 2
R2770 100KR2J -1-GP R2770 100KR2J -1-GP
1 2 33R2J -2-GP R2736 33R2J -2-GP R2736
1
2
C
2
7
0
4
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
C
2
7
0
4
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
1 2
R2734
0R2J -2-GP
DY
R2734
0R2J -2-GP
DY
1 2
R2757
0R2J -2-GP
DQ15
R2757
0R2J -2-GP
DQ15
C
B
E
Q2701
MMBT3906-4-GP
2nd = 84.03906.F11
84.T3906.A11
Q2701
MMBT3906-4-GP
2nd = 84.03906.F11
84.T3906.A11
1 2
C2722
SCD1U10V2KX-5GP
C2722
SCD1U10V2KX-5GP
1 2
DY
DY
1
2
3
D2701
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
DY
D2701
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
DY
1
2
R2773
100KR2J -1-GP
R2773
100KR2J -1-GP
1
2
3
D2708
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
D2708
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
1 2
R2733 0R0402-PAD R2733 0R0402-PAD
1
2
R2732
1
0
0
K
R
2
J
-1
-G
P
R2732
1
0
0
K
R
2
J
-1
-G
P
1
2
3
D2706
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
DN15
D2706
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
DN15
1
2
R2724
47KR2F-GP
R2724
47KR2F-GP
1 2
R2712 10KR2J -3-GP R2712 10KR2J -3-GP
1
2
R2769
100KR2J -1-GP
PSL
R2769
100KR2J -1-GP
PSL
1 2 R2721 43R2J -GP R2721 43R2J -GP
1 2
R2760
0R0402-PAD-2-GP
R2760
0R0402-PAD-2-GP
1 2 R2762
0R0402-PAD-2-GP
R2762
0R0402-PAD-2-GP
1
2
C
2
7
0
5
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
C
2
7
0
5
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
1 2
R2711 0R0402-PAD R2711 0R0402-PAD
1 2 R2722 33R2J -2-GP R2722 33R2J -2-GP
1 2 R2737 0R0402-PAD-2-GP R2737 0R0402-PAD-2-GP
1
2
C2713
SCD1U10V2KX-5GP
DY
C2713
SCD1U10V2KX-5GP
DY
1
2
C
2
7
0
6
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
C
2
7
0
6
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
1 2
R2708 10KR2J -3-GP
DY
R2708 10KR2J -3-GP
DY
1
2 3
4
RN2701
SRN4K7J -8-GP
RN2701
SRN4K7J -8-GP
1
2
R2710
33KR2F-GP
64.33025.6DL
R2710
33KR2F-GP
64.33025.6DL
1
2
3
D2703
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
10mW
D2703
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
10mW
1
2
R2705
10KR2J -3-GP
R2705
10KR2J -3-GP
VREF
104
GPIO90/AD0
97
GPIO91/AD1
98
GPIO92/AD2
99
GPIO93/AD3
100
GPIO94/DA0
101
GPIO95/DA1
105
GPIO96/DA2
106
GPIO2
79
GPIO3/AD6
95
GPIO4/AD5
96
GPIO5/AD4
108
PSL_IN2#_GPIO6
93
GPIO7/AD7
94
GPIO16
114
GPIO24
6
GPIO30
109
GPIO34/CIRRXL
14
GPIO41
80
GPIO42/TCK
17
GPIO43/TMS
20
GPIO44/TDI
21
GPIO46/CIRRXM/TRST#
23
GPIO51
26
PSL_IN1_GPIO70
73
PSL_OUT_GPIO71
74
VBKUP
75
GPIO75
82
GPO76/SHBM
83
GPIO77
84
GPIO81
91
GPO82/IOX_LDSH/TEST#
110
GPIO84/IOX_SCLK/XORTR#
112
GPIO97
107
GPIO36
15
VCORF
44
G
N
D
1
8
G
N
D
4
5
G
N
D
7
8
G
N
D
8
9
G
N
D
1
1
6
G
N
D
5
A
G
N
D
1
0
3
GPIO11/CLKRUN#
8
LAD3
1
LAD2
128
LAD1
127
LAD0
126
LFRAME#
3
LCLK
2
LRESET#
7
SERIRQ
125
GPIO85/GA20
121
KBRST#/GPIO86
122
ECSCI#/GPIO54
29
GPIO65/SMI#
9
GPIO10/LPCPD#
124
GPIO67/PWUREQ#
123
GPIO37/PSCLK1
72
GPIO26/PSCLK2
10
GPIO35/PSDAT1
71
GPIO27/PSDAT2
11
GPIO50/PSCLK3/TDO
25
GPIO52/PSDAT3/RDY#
27
GPIO17/SCL1
70
GPIO73/SCL2
67
GPIO23/SCL3
119
GPIO22/SDA1
69
GPIO74/SDA2
68
GPIO31/SDA3
120
GPIO47/SCL4
24
GPIO53/SDA4
28
F_SDI/F_SDIO1
86
F_SDIO/F_SDIO0
87
F_SCK
92
F_CS0#
90
V
C
C
1
9
V
C
C
4
6
V
C
C
7
6
V
C
C
8
8
V
C
C
1
1
5
A
V
C
C
1
0
2
V
D
D
4
1 OF 2 U2701A
NPCE795PA0DX-GP-U
1 OF 2 U2701A
NPCE795PA0DX-GP-U
G
S
D
Q2706
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q2706
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1 2 R2767
0R2J -2-GP
DY
R2767
0R2J -2-GP
DY
1
2
3
D2707
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
D2707
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
1 2
DY
DY
1 2
R2766
0R0402-PAD-2-GP
10mW
R2766
0R0402-PAD-2-GP
10mW
1
2
R2771
2D2R3-1-U-GP
R2771
2D2R3-1-U-GP
1 2 R2759
0R0402-PAD-2-GP
R2759
0R0402-PAD-2-GP
1
2
C2712
SC1U10V3ZY-6GP
C2712
SC1U10V3ZY-6GP
1
2
C2716
S
C
D
1
U
1
6
V
2
K
X
-3
G
P
C2716
S
C
D
1
U
1
6
V
2
K
X
-3
G
P
1 2
DY
DY
1
2
C
2
7
0
9
S
C
2
D
2
U
1
0
V
3
K
X
-1
G
P
C
2
7
0
9
S
C
2
D
2
U
1
0
V
3
K
X
-1
G
P
1 2 33R2J -2-GP R2719 33R2J -2-GP R2719
1
2 3
4
RN2703
SRN100KJ -6-GP
RN2703
SRN100KJ -6-GP
1
2
C2702
SCD1U10V2KX-5GP
C2702
SCD1U10V2KX-5GP
1 2
R2761 0R0402-PAD R2761 0R0402-PAD
1 2
R2735
0R0402-PAD-2-GP
R2735
0R0402-PAD-2-GP
1
2
C2715
S
C
1
U
6
D
3
V
2
K
X
-G
P
DY
C2715
S
C
1
U
6
D
3
V
2
K
X
-G
P
DY
G
S
D
Q2702
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q2702
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1
2 3
4
RN2706
SRN10KJ -5-GP
RN2706
SRN10KJ -5-GP
1
2
C2703
SC2D2U10V3KX-1GP DY
C2703
SC2D2U10V3KX-1GP DY
1 2
R2776 100KR2J -1-GP R2776 100KR2J -1-GP
G
S
D
Q2705
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
PSL
Q2705
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
PSL
G
S
D
Q2704
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
10mW
Q2704
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
10mW
1 2 R2702
0R0603-PAD
R2702
0R0603-PAD
1
2
C2717
SCD1U10V2KX-5GP
C2717
SCD1U10V2KX-5GP
1 2 R2768
0R2J -2-GP
PSL
R2768
0R2J -2-GP
PSL
1 2
R2720 0R0402-PAD R2720 0R0402-PAD
1
2
3
D2702
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
D2702
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
1
2 3
4
RN2707
SRN100KJ -6-GP
RN2707
SRN100KJ -6-GP
1
2
C2718
SCD1U10V2KX-5GP
C2718
SCD1U10V2KX-5GP
1 2
R2772 100KR2J -1-GP R2772 100KR2J -1-GP
1
2
3
D2705
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
DY
D2705
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
DY
1
2
3
4 5
6
7
8
RN2705
SRN10KJ -6-GP
RN2705
SRN10KJ -6-GP
1 2 R2756
0R0402-PAD-2-GP
10mW
R2756
0R0402-PAD-2-GP
10mW
1 2
R2763
0R0402-PAD-2-GP
10mW
R2763
0R0402-PAD-2-GP
10mW
1
2
C
2
7
1
0
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
C
2
7
1
0
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
1
2
C
2
7
0
8
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
C
2
7
0
8
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
GPIO56/TA1
31
GPIO20/TA2
117
GPIO14/TB1
63
GPIO01/TB2
64
GPIO15/A_PWM
32
GPIO21/B_PWM
118
GPIO13/C_PWM
62
GPIO32/D_PWM
65
GPIO66/G_PWM
81
GPIO33/H_PWM
66
GPIO45/E_PWM
22
GPIO40/F_PWM
16
VCC_POR#
85
GPIO83/SOUT_CR/TRIST#
111
GPIO87/CIRRXM/SIN_CR
113
GPIO00/EXTCLK
77
GPIO55/CLKOUT/IOX_DIN_DIO
30
PECI
13
VTT
12
KBSOUT0/J ENK#
53
KBSOUT1/TCK
52
KBSOUT2/TMS
51
KBSOUT3/TDI
50
KBSOUT4/J EN0#
49
KBSOUT5/TDO
48
KBSOUT6/RDY#
47
KBSOUT7
43
KBSOUT8
42
KBSOUT9/SDP_VIS#
41
KBSOUT10/P80_CLK
40
KBSOUT11/P80_DAT
39
KBSOUT12/GPIO64
38
KBSOUT13/GPIO63
37
KBSOUT14/GPIO62
36
KBSOUT15/GPIO61/XOR_OUT
35
GPIO60/KBSOUT16
34
GPIO57/KBSOUT17
33
KBSIN0
54
KBSIN1
55
KBSIN2
56
KBSIN3
57
KBSIN4
58
KBSIN5
59
KBSIN6
60
KBSIN7
61
2 OF 2 U2701B
NPCE795PA0DX-GP-U
2 OF 2 U2701B
NPCE795PA0DX-GP-U
1 2
R2758
0R0402-PAD-2-GP
R2758
0R0402-PAD-2-GP
1 2
R2704
330KR2J -L1-GP
R2704
330KR2J -L1-GP
1 2
R2775 100KR2J -1-GP R2775 100KR2J -1-GP
1
2
C
2
7
0
7
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
C
2
7
0
7
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
S
D
G
G
D
Q2703
DMP2130L-7-GP
2ND = 84.03413.A31
84.02130.031
G
D
Q2703
DMP2130L-7-GP
2ND = 84.03413.A31
84.02130.031
1 2
R2709 10KR2J -3-GP
DY
R2709 10KR2J -3-GP
DY
1
2
3
D2704
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
DY
D2704
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
THERM_SYS_SHDN#
THERM_SYS_SHDN#_OTZ
P2800_DXN
ADJ
P2800_DXP
FAN_VCC
FAN_VCC
FAN_TACH1_C
FON#
FAN_VCC
FAN_VCC
ADJ
FAN_VCC
FAN_TACH1_C
U2805_5 U2805_1
U2805_4
THERM_SYS_SHDN#_OTZ
THERM_SYS_SHDN#
3D3V_S0
3D3V_S0
3D3V_DAC_S0
5V_S0
5V_S0 3D3V_DAC_S0
3D3V_DAC_S0
3D3V_DAC_S0
CPU_THRM 27
SYS_THRM 27
FAN_TACH1 27
FAN1_DAC 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Thermal P2800/Fan Controllor P2793
A3
28 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
28 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
28 108
<Core Design>
SSID = Thermal
Layout notice :
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing.
1.H/W T8 Shutdown
2.System Sensor, Put on palm rest
Thermal sensor P2800
For linear FAN
*Layout* 15 mil
Fan controller P2793
0614 Modify:
Change FAN1 connector part number to
20.D0210.103 base on ME EMN and DXF.
0712 Modify:
Change FAN1 part number to 20.F1639.004
from 20.D0210.103 base on latest EMN and DXF.
0628 Modify:
Stuff R2712 and Removed R2805.
0705 Modify:
R2802 change to 0ohm 0402 from
short pad and default un-stuff.
0709 Modify:
Removed R2811 and connect
3D3V_S0 to Q2802.G directly.
EMI/ESD
0724 Modify:
Removed C2808 0.1uF.
0831
87.1 Degree
*Layout* 10 mil
20101019 X01:
Reserve U2804 for PURE_HW_SHUTDOWN# test.
20101020 X01:
Reserve R2810 to 3D3V_S0 and R2811 to GND for HYST.
1111 X02 Modify:
Reserved G709T1UF for T8 solution
sync with DN13.
X02 1111
1117 X02 Modify:
Add R2805 0hm between THERM_SYS_SHDN#_OTZ
and THERM_SYS_SHDN#.
1117 X02 Modify:
Rename U2801&U2804 pin 8 to
THERM_SYS_SHDN#_OTZ from THERM_SYS_SHDN#.
X02 1118
1111 X02 Modify:
ADJ&ADJ_VGA power source change to 3D3V_DAC_S0
from 3D3V_S0 to solve T8 shut down issue.
1111 X02 Modify:
ADJ&ADJ_VGA power source change to 3D3V_DAC_S0
from 3D3V_S0 to solve T8 shut down issue.
1110 X02 Modify:
Add 2nd 20.F1841.003 on FAN1 from
ME updated connector list.
1119 X02 Modify:
Change U2801,U2804,U2805 VCC power to
3D3V_DAC_S0 from 3D3V_S0.
A00 1224
A00 1224
Hysterisis:
10C for HYST= VCC
2C for HYST=GND
A00 1227
1227 A00 Modify:
If stuff P2800EA1 then must stuff R2803,R2804,C2805 but if stuff P28003B0 should be unstuff.
A00 1228
A00 1228 un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805
A00 1228 Cancel VGA Thermal sensor P2800 circuit
2
1
D2802
CH551H-30PT-GP
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
83.R5003.C8F
D2802
CH551H-30PT-GP
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
83.R5003.C8F
1
2
R2808
NTC-100K-8-GP
DY
R2808
NTC-100K-8-GP
DY
1 2
R2802 0R2J -2-GP
DY
R2802 0R2J -2-GP
DY
1
2
C2810
S
C
2
2
0
0
P
5
0
V
2
K
X
-
2
G
P
DY
C2810
S
C
2
2
0
0
P
5
0
V
2
K
X
-
2
G
P
DY
1
2
C2806
SC470P50V3J N-2GP
C2806
SC470P50V3J N-2GP
1
2
R2804
226KR2F-GP
P2800A1
R2804
226KR2F-GP
P2800A1
1
2
C2802
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C2802
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C2809
S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
C2809
S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
1 2
R2807 0R0402-PAD R2807 0R0402-PAD
G
S
D
Q2802
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q2802
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
FON#
1
VIN
2
VO
3
VSET
4
GND
8
GND
7
GND
6
GND
5
U2802
G991P11U-GP
2nd = 74.02793.A31
3rd = 74.05606.A71
74.00991.031
U2802
G991P11U-GP
2nd = 74.02793.A31
3rd = 74.05606.A71
74.00991.031
VCC
5
DXP
6
DXN
7
OTZ
8
GND
2
ADJ
1
TDL
3
TDR
4
U2801
P2800EA1-GP
74.02800.A71
U2801
P2800EA1-GP
74.02800.A71
1
2
3
4
5
FAN1
ACES-CON3-11-GP
20.F0772.003
2nd = 20.F1841.003
FAN1
ACES-CON3-11-GP
20.F0772.003
2nd = 20.F1841.003
1
2
C2807
SC2200P50V2KX-2GP
C2807
SC2200P50V2KX-2GP
1
2
R2803
107KR2F-GP
P2800A1
R2803
107KR2F-GP
P2800A1
1
2
C2817
SCD1U10V2KX-5GP
DY
C2817
SCD1U10V2KX-5GP
DY
1 2
R2806
24K3R2F-1-GP
DY
R2806
24K3R2F-1-GP
DY
1 AFTP2801 AFTP2801
1
2
R2809
100KR2J -1-GP
R2809
100KR2J -1-GP
1
2
EC2801
S
C
D
1
U
1
6
V
2
K
X
-
3
G
P
DY
EC2801
S
C
D
1
U
1
6
V
2
K
X
-
3
G
P
DY
1 2
R2810
0R2J -2-GP
DY
R2810
0R2J -2-GP
DY
1
2
C2805
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
P2800A1
C2805
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
P2800A1
1
2
C2811
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P DY
C2811
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P DY
1
2
C2804
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C2804
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
SET
1
GND
2
OUT#
3
HYST
4
VCC
5
U2805
G709T1UF-GP
74.00709.A7F
DY
U2805
G709T1UF-GP
74.00709.A7F
DY
3
1
2
Q2801
PMBS3904-1-GP
84.03904.L06
2ND = 84.03904.P11
Q2801
PMBS3904-1-GP
84.03904.L06
2ND = 84.03904.P11
1 2
R2811
0R2J -2-GP
DY
R2811
0R2J -2-GP
DY
1
2
C2803
S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
C2803
S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
1 2
R2805
0R2J -2-GP
R2805
0R2J -2-GP
1 AFTP2802 AFTP2802
1 2
R2812 0R2J -2-GP
DY
R2812 0R2J -2-GP
DY
1 2
R2801
150R2F-1-GP
DY
R2801
150R2F-1-GP
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDA_CODEC_SDIN0
AUD_DVDDCORE
HDA_CODEC_BITCLK
HDA_CODEC_BITCLK
AUD_HP1_J ACK_R
PUMP_CAPN
AUD_SENSE_A
PUMP_CAPP
AMP_MUTE#
KBC_BEEP_R
SB_SPKR_R
AUD_V_B
AUD_SENSE_B
AUD_VREG
AUD_SPK_L+
AUD_SPK_L-
AUD_EXT_MIC_R
AUD_HP1_J ACK_L
AUD_EXT_MIC_L
AUD_VREFOUT_B
P
C
H
_
A
Z
_
C
O
D
E
C
_
S
D
O
U
T
1
HDA_CODEC_SDOUT
AUD_VREFFLT
AMP_MUTE#
HDA_CODEC_SYNC
HDA_CODEC_RST#
HDA_CODEC_SDOUT
AUD_CAP2
AUD_PC_BEEP
A
U
D
_
S
E
N
S
E
_
A
A
U
D
_
S
E
N
S
E
_
B
A
U
D
_
P
C
_
B
E
E
P
A
U
D
_
C
A
P
2
A
U
D
_
V
R
E
F
F
L
T
A
U
D
_
V
R
E
F
O
U
T
_
B
AUD_VREFOUT_B
AUD_V_B
A
U
D
_
V
R
E
G
AUD_PC_BEEP
AUD_SPK_R-
AUD_SPK_R+
AUD_VREFOUT_B
AUD_DMIC_CLK
AUD_DMIC_IN0
AUD_DMIC_IN0_R
AUD_DMIC_CLK_R
AUD_DMIC_CLK_R
AUD_DMIC_IN0_R 3D3V_S0
+AVDD
+AVDD
5V_S0
3D3V_S0
5V_S0 +PVDD
+AVDD
+AVDD
+AVDD
+PVDD
HDA_CODEC_SYNC 21
HDA_CODEC_RST# 21
HDA_SDIN0 21
HDA_CODEC_BITCLK 21
HDA_CODEC_SDOUT 21
AUD_HP1_J D# 82
EXT_MIC_J D# 82
AUD_SPK_L+ 58
AUD_SPK_L- 58
AMP_MUTE# 27
HDA_SPKR 21
KBC_BEEP 27
AUD_HP1_J ACK_L2 82
AUD_HP1_J ACK_R2 82
MIC_IN_L 82
MIC_IN_R 82
AUD_SPK_R- 58
AUD_SPK_R+ 58
MIC_IN_L 82
MIC_IN_R 82
AUD_DMIC_CLK 49
AUD_DMIC_IN0 49
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Audio Codec 92HD87B1
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Core Design>
Close to codec
Close to Pin14
From SB
From EC
SSID = AUDIO
Close to Pin13
Azalia /F EM
Close to codec
AUD_PC_BEEP
Trace width>15 mils
Close to codec
2010/06/30 Changeto 92HD87 (71.92H87.A03)
Put C2921 and C2922 close to codec
CLOSE TO CODEC
0707 Modify:
Change R2911,R2914,R2917 change
to 0ohm 0603 from short pad.
0726 Modify:
Removed all of AUD_AGND and R2911,R2914,R2917.
0707 Modify:
updated U2901 part number from data base.
MC N
0719 Modify:
Move RN2901 to closed AUDIO CODEC from speaker connector.
For EMI
1122 X02 Modify:
change R2920,R2921 to 22ohm from 0ohm and
stuff EC2901,EC2902 22p from EMC Neo updated.
A00
1 2 R2906 60D4R2F-GP R2906 60D4R2F-GP
1
2
C
2
9
0
2
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
9
0
2
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C
2
9
1
0
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
C
2
9
1
0
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
1
2
C
2
9
0
9
S
C
1
U
1
0
V
2
K
X
-
1
G
P
C
2
9
0
9
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1
2
G2901
DUMMY-C2
G2901
DUMMY-C2
1 2
R2910 470KR2J -2-GP R2910 470KR2J -2-GP
1 2 R2904
0R0603-PAD
R2904
0R0603-PAD
1
2
C
2
9
0
8
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
9
0
8
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
R2918
20KR2F-L-GP
R2918
20KR2F-L-GP
1
2
R2916
2K49R2F-GP
R2916
2K49R2F-GP
1
2
C2923
SC1U10V2KX-1GP
C2923
SC1U10V2KX-1GP
1
2
C2914
SC2D2U10V3KX-1GP
C2914
SC2D2U10V3KX-1GP
1
2
C
2
9
0
5
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
9
0
5
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C2901
SC10U6D3V5MX-3GP
C2901
SC10U6D3V5MX-3GP
1 2 C2922 SC1U10V3KX-3GP C2922 SC1U10V3KX-3GP
1 2
34
RN2901
SRN4K7J -8-GP
RN2901
SRN4K7J -8-GP
1
2
C
2
9
0
3
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
9
0
3
S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
C
2
9
1
8
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
C
2
9
1
8
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
1
2
EC2901
SC22P50V2J N-4GP
EC2901
SC22P50V2J N-4GP
1
2
C
2
9
0
4
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C
2
9
0
4
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1 2
R2913
20KR2F-L-GP
R2913
20KR2F-L-GP
1 2 R2903
0R0603-PAD
R2903
0R0603-PAD
1 2
R2919
39K2R2F-L-GP
R2919
39K2R2F-L-GP
1
2
R2912
47R2J -2-GP
DY
R2912
47R2J -2-GP
DY
1
2
R2915
2K49R2F-GP
R2915
2K49R2F-GP
1
2
C2907
SC4D7P50V2CN-1GP
DY
C2907
SC4D7P50V2CN-1GP
DY
1
2
C2919
SC1000P50V3J N-GP-U
C2919
SC1000P50V3J N-GP-U
1
2
C2920
SCD1U10V2KX-5GP
DY
C2920
SCD1U10V2KX-5GP
DY
DVDD_LV
1
DMIC_CLK/GPIO_1
2
DMIC_0/GPIO_2
3
SDATA_OUT
4
BITCLK
5
SDATA_IN
6
DVDD
7
SYNC
8
RESET#
9
PCBEEP
10
S
E
N
S
E
_
A
1
1
S
E
N
S
E
_
B
1
2
P
O
R
T
F
_
L
1
3
P
O
R
T
F
_
R
1
4
P
O
R
T
C
_
L
1
5
P
O
R
T
C
_
R
1
6
V
R
E
F
F
I
L
T
1
7
C
A
P
2
1
8
V
R
E
F
O
U
T
_
A
1
9
V
R
E
F
O
U
T
_
C
2
0
AVDD1
21
PORTA_L
22
PORTA_R
23
AVSS2
24
PORTB_L
25
PORTB_R
26
AVSS2
27
V-
28
CAP-
29
CAP+
30
V
R
E
G
/
+
2
_
5
V
3
1
A
V
D
D
2
3
2
P
V
D
D
3
3
P
O
R
T
D
_
+
L
3
4
P
O
R
T
D
_
-
L
3
5
P
V
S
S
3
6
P
O
R
T
D
_
-
R
3
7
P
O
R
T
D
_
+
R
3
8
P
V
D
D
3
9
E
A
P
D
4
0
T
H
E
R
M
A
L
_
P
A
D
4
1
U2901
92HD87B1A5NDGXTBX8-GP
71.92H87.A03
U2901
92HD87B1A5NDGXTBX8-GP
71.92H87.A03
1 2 R2905 60D4R2F-GP R2905 60D4R2F-GP 1 2
33R2J -2-GP
R2901
33R2J -2-GP
R2901
1
2
C
2
9
1
7
S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
C
2
9
1
7
S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P 1
2 3
4
RN2902
SRN22J -7-GP
RN2902
SRN22J -7-GP
1 2
R2909
120KR2J -L-GP
R2909
120KR2J -L-GP
1
2
R2908
10KR2J -3-GP
R2908
10KR2J -3-GP
1
2
C
2
9
0
6
S
C
1
U
1
0
V
2
K
X
-
1
G
P
C
2
9
0
6
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1 2 R2902
0R0603-PAD
R2902
0R0603-PAD
1
2
EC2902
SC22P50V2J N-4GP
EC2902
SC22P50V2J N-4GP
1
2
C
2
9
1
5
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
C
2
9
1
5
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
1 2 C2921 SC1U10V3KX-3GP C2921 SC1U10V3KX-3GP
1
2
C
2
9
1
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
C
2
9
1
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB_PN5_R
RREF
USB_PP5_R
V18
XD_CD#
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
XD_D7
USB_PP5_R
USB_PN5_R
3D3V_CARD_S0
3D3V_S0
3D3V_CARD_S0
CLK_PCH_48M 20
XD_CD# 74
SP1 74
SP2 74
SP3 74
SP4 74
SP5 74
SP6 74
SP7 74
SP8 74
SP9 74
SP10 74
SP11 74
SP12 74
SP13 74
SP14 74
XD_D7 74
USB_PN5 18
USB_PP5 18
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Card Reader-RTS5138
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Card Reader-RTS5138
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Card Reader-RTS5138
A3
<Core Design>
SSID = SDIO
Close to chip
3D3V_CARD_S0
PCH GPIO67(48M) confirm with SW
The maximum range of the PMOS output current
1. xD-Picture Card: 250mA
2. SD/MMC Card: 250mA
3. MS/MSPRO/Duo-HG: 250mA
MAX 0.4A
The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout
with differential characteristic impedance (Zdiff) is 90[
10%
48MHz clock input trace of characteristic impedance (Zo) must be 50
15%.
POWER TRACE
1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum).
2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum).
3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum).
Keep the trace routing lengths as short as possible.
4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).
5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.
6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.
7.It is recommended that use of ferrites bead on power trace.
8.Via size: Pad>=32 mils, Finished hole>=16 mils.
0917 X01 Modify:
stuff TR3201 and un-stuff R3211,R3210
at X01 stage from EMC Neo suggestion.
A00 1229
1 2
R3210
0R0402-PAD-2-GP
R3210
0R0402-PAD-2-GP
1 2 R3201
6K2R2F-GP
R3201
6K2R2F-GP
1
2
C3206
SCD1U10V2KX-4GP
C3206
SCD1U10V2KX-4GP
1 2
R3211
0R0402-PAD-2-GP
R3211
0R0402-PAD-2-GP
1
2
C3207
SC4D7U6D3V3KX-GP
C3207
SC4D7U6D3V3KX-GP
C
L
K
_
I
N
2
4
RREF
1
DM
2
DP
3
3V3_IN
4
CARD_3V3
5
V18
6
X
D
_
C
D
#
7
S
P
1
8
S
P
2
9
S
P
3
1
0
S
P
4
1
1
S
P
5
1
2
SP6
13
SP7
14
SP8
15
SP9
16
GPIO0
17
SP10
18
S
P
1
1
1
9
S
P
1
2
2
0
S
P
1
3
2
1
S
P
1
4
2
2
X
D
_
D
7
2
3
GND
25
U3201
RTS5138-GR-GP
71.05138.003
U3201
RTS5138-GR-GP
71.05138.003
1 2
C3201
SC100P50V2J N-3GP
DY
C3201
SC100P50V2J N-3GP
DY
1
2
C3204
SC4D7U6D3V3KX-GP
DY
C3204
SC4D7U6D3V3KX-GP
DY
1
2
C3202
SC1U10V2KX-1GP
C3202
SC1U10V2KX-1GP
1
2
C3203
SCD1U10V2KX-4GP
C3203
SCD1U10V2KX-4GP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PS_S3CNTRL
5V_RUN_ENABLE
3.3V_RUN_ENABLE
1.5V_RUN_ENABLE
H_PWRGD_R
SYS_PWROK
PS_S3CNTRL
15V_S5
5V_S5 5V_S0
3D3V_S5 3D3V_S0
3D3V_AUX_S5
1D5V_S3 1D5V_S0
RUN_ENABLE
1D05V_VTT
3D3V_S0
S0_PWR_GOOD 19,27
SYS_PWROK 19
PS_S3CNTRL 37
S5_ENABLE 27
H_THERMTRIP# 5,22
H_CPUPWRGD 5,22
3V_5V_EN 41
PM_SLP_S3# 19,27,37,47,75
IMVP_PWRGD 27,42
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Power Plane Enable
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Power Plane Enable
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Power Plane Enable
A3
<Core Design>
Power Sequence
+3.3V_RUN Comsumption
Peak current 8.14A
+5V_RUN Comsumption
Peak current 7.73A
5V_S0
3D3V_S0
ROSA Run Power
SSID = Reset.Suspend
G
G D
D
S
S
AO4468 MAX 9A
Rds(on) = 18.5mOhm
AO4468 MAX 11.6A
Rds(on) = 18.5mOhm
1.5V_RUN for VGA Comsumption
Peak current 7.39A
+1.5V_RUN_CPU Comsumption
Peak current 3A
+1.5V_RUN for Mini-Card Comsumption
Peak current 1A
Total= 11.39A
1D5V_S0
MAX Current ? mA
Design Current ? mA
TPCA8062-H-GP MAX 28A
Rds(on) = 4.1~5.4m OHM
0615 Modify:
RemovedR3626,R3628 0ohm0805 Resistor,
they areunnecessary for this power rail.
RemovedR3627,R3629 0ohm0805 Resistor for 1D5V_DDR_S0.
0621 Modify:
Change R3603 to 1K from 2K 0402.
0628 Modify:
Utilize D3602 Diode instead of U3603 AND GATE
for SYS_PWROK sequnece control.
0628 Modify:
Removed R3609,R3610,R3613,C3613 and Stuff R3614.
0713 Modify:
Change U3606 part number to 84.08062.037
from 84.04468.037.
0827 Add 2nd and 3rd.
0719 Modify:
Reserved EC3601 0.1uF near
C3604 for EMC NEO suggestion.
0723 Modify:
Default stuff R3622 PH Resistor to fix Annie
demo board abnormal issue from Annie team
updated.
A00
A00 1228 stuff Q3603
1
2
C3610
SCD01U50V2KX-1GP
C3610
SCD01U50V2KX-1GP
1
2
C3612
SCD01U50V2KX-1GP
DY
C3612
SCD01U50V2KX-1GP
DY
1 2 R3601
1KR2J -1-GP
DY
R3601
1KR2J -1-GP
DY
123
4 5 6
Q3602
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
Q3602
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
1 2 R3630
10KR2J -3-GP
R3630
10KR2J -3-GP
1 2 R3614
0R0402-PAD-2-GP
R3614
0R0402-PAD-2-GP
C
B
E
Q3601
CHT2222APT-GP
DY
Q3601
CHT2222APT-GP
DY
1 2 R3607
10KR2J -3-GP
R3607
10KR2J -3-GP
1 2 R3605
10KR2J -3-GP
R3605
10KR2J -3-GP
1
2
C3604
SC10U6D3V5KX-1GP
C3604
SC10U6D3V5KX-1GP
1
2
C3603
SC10U10V5ZY-1GP
C3603
SC10U10V5ZY-1GP
G
S
D
Q3603
2N7002K-2-GP
2nd = 84.2N702.031
84.2N702.J31
Q3603
2N7002K-2-GP
2nd = 84.2N702.031
84.2N702.J31
1
2
E
C
3
6
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
3
6
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
3
4 5
6
7
8 S
S
S
G D
D
D
D
U3601
AO4468-GP
84.04468.037
2nd = 84.08882.037
S
S
S
G D
D
D
D
U3601
AO4468-GP
84.04468.037
2nd = 84.08882.037
1
2
3
D3602
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
D3602
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
1
2
C3602
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P DY
C3602
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P DY
1
2
3
D3601
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
D3601
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
1 2
R3622
56R2J -4-GP
R3622
56R2J -4-GP
1
2
C3605
SCD01U50V2KX-1GP
C3605
SCD01U50V2KX-1GP
1
2
C3608
SCD01U50V2KX-1GP
C3608
SCD01U50V2KX-1GP
1
2
C3609
SC10U6D3V5KX-1GP
C3609
SC10U6D3V5KX-1GP
1
2
3
4 5
6
7
8 S
S
S
G D
D
D
D
U3602
AO4468-GP
84.04468.037
2nd = 84.08882.037
S
S
S
G D
D
D
D
U3602
AO4468-GP
84.04468.037
2nd = 84.08882.037
1
2
R
3
6
0
2
2
0
0
K
R
2
J
-
L
1
-
G
P
DY
R
3
6
0
2
2
0
0
K
R
2
J
-
L
1
-
G
P
DY
1 2
R3603 1KR2J -1-GP R3603 1KR2J -1-GP
1 2 R3606
100KR2J -1-GP
R3606
100KR2J -1-GP
1
2
R3604
100KR2J -1-GP
R3604
100KR2J -1-GP
1
2
3
4 5
6
7
8 S
S
S
G D
D
D
D
U3606
TPCA8062-H-GP
84.08062.037
2nd = 84.00460.037
3rd = 84.00312.037
S
S
S
G D
D
D
D
U3606
TPCA8062-H-GP
84.08062.037
2nd = 84.00460.037
3rd = 84.00312.037
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PS_S3CNTRL
Q
3
7
0
2
_
D
Q
3
7
0
1
_
D
SM_DRAMRST#_D
DRAMRST_CNTRL_PCH
+V_SM_VREF
0D75V_EN
VDDPWRGOOD_R
VDDPWRGOOD_R
0D75V_EN
1D5V_S0 0D75V_S0
1D5V_S3
1D5V_S0
3D3V_S0
3D3V_S0
M_VREF_DQ_DIMM0
RUN_ENABLE PS_S3CNTRL 36
0D75V_EN 46 PM_SLP_S3# 19,27,36,47,75
DDR3_DRAMRST# 14,15
DRAMRST_CNTRL_PCH 20
SM_DRAMRST# 5
+V_SM_VREF_CNT 9
PM_DRAM_PWRGD 5,19
VDDPWRGOOD 5
PM_DRAM_PWRGD 5,19
1.05VTT_PWRGD 45,48 PS_S3CNTRL 36
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
ADAPTER
A3
37 108
DN15ATI
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
ADAPTER
A3
37 108
DN15ATI
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
ADAPTER
A3
37 108
DN15ATI
2
5 S3 Power Reduction X01 20091111
S3 Power Reduction Circuit
SM_DRAMRST#
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK
SM_DRAMPWROK must have a maximum of 15ns rise or fall time
over VDDQ * 0.55 200mV and the edge must be monotonic
CEKLT V1.0: PCH to 1K,CUP to 200R
Close to CPU
Close to DIMM
0629 Modify 0629 Modify
0706 Modify:
Removed Q3707,R3717 and connect
RUN_ENABLE to Q3708.G directly
same as EV board.
0709 Modify:
Change U3701 pin1,5 to 3D3V_S0 from 3D3V_S5.
0709 Modify:
U3701 change to OD type 73.01G09.AAH.
0723 Modify:
Change U3701 to push pull type 73.01G08.L04.
R3720 change to 910ohm 0402.
R3719 change to 750ohm 0402.
default un-stuff R3702.
PUSH PULL
0730
0920
0827
0908 X01 Modify:
Stuff Q3704,R3710; un-stuff R3716.
U3701 pin2 change to 1.05VTT_PWRGD from
RUNPWROK.
X02 1111
1110 X02 Modify:
Change U3701 1st to 73.7SZ08.EAH;2nd to
73.01G08.L04;3rd to 73.7SZ08.DAH from
Sourcer Eason updated.
A00
1
2
R3710
0R0402-PAD-2-GP
R3710
0R0402-PAD-2-GP
1
2
R3703
22R2J -2-GP
R3703
22R2J -2-GP
1
2
R3713
200R2F-L-GP
R3713
200R2F-L-GP
1 2
R3719
910R2F-GP
R3719
910R2F-GP
G
S
D
Q3708
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q3708
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1
2
R3705
100KR2J -1-GP
R3705
100KR2J -1-GP
1
2
R3706
1KR2J -1-GP
R3706
1KR2J -1-GP
GS
D
Q3702
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
Q3702
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
1 2
R3707
0R2J -2-GP
DY
R3707
0R2J -2-GP
DY
1 2 R3718
1KR2J -1-GP
R3718
1KR2J -1-GP
GS
D
Q3701
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q3701
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1
2
R3702
200R2F-L-GP
DY
R3702
200R2F-L-GP
DY
1 2
R3717
0R2J -2-GP
DY
R3717
0R2J -2-GP
DY
G
S
D
Q3703
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q3703
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1
2
C3702
SC100P50V2J N-3GP
C3702
SC100P50V2J N-3GP
1
2
C3705
SCD1U10V2KX-5GP
DY
C3705
SCD1U10V2KX-5GP
DY
1
2
R3704
220R2J -L2-GP
DY
R3704
220R2J -L2-GP
DY
1 2
R3708 0R0402-PAD R3708 0R0402-PAD
1
2
3
4
5
U3701
TC7SZ08FU-2-GP
73.7SZ08.EAH
3rd = 73.7SZ08.DAH
2nd = 73.01G08.L04
U3701
TC7SZ08FU-2-GP
73.7SZ08.EAH
3rd = 73.7SZ08.DAH
2nd = 73.01G08.L04
1 2 R3709
0R2J -2-GP
DY
R3709
0R2J -2-GP
DY
1
2
R3720
750R2F-GP
R3720
750R2F-GP
1 2
R3716 22R2J -2-GP
DY
R3716 22R2J -2-GP
DY
1 2
C3703
SCD047U16V2KX-1-GP
C3703
SCD047U16V2KX-1-GP
G
S
D
Q3704
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q3704
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DCIN
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DCIN
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
DCIN
A3
<Core Design>
SSID = PWR.Support
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PBAT_SMBDAT1
PBAT_SMBCLK1
PBAT_PRES1#
BAT_ALERT
BT+
PBAT_PRES1#
PBAT_SMBCLK1
PBAT_SMBDAT1
B
A
T
_
S
C
L
B
A
T
_
S
D
A
B
A
T
_
I
N
#
BT+
3D3V_AUX_KBC
DCBATOUT
BATT_SENSE 40
BAT_SDA 27,40
BAT_SCL 27,40
BAT_IN# 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
BATT CONN
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
BATT CONN
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
BATT CONN
A3
<Core Design>
For actual location, need to be swap all pin
Batt Connecter
Close to Batt Connector
0701 Modify:
Removed D3904 ESD Diode on BAT_IN#.
0714 Modify:
Merge R3902~R3904 to PRN3901 33ohm.
0930 X01 Modify:
Change D3901~D3903 main source to 83.00099.T11
for 83.BAV99.D11 shortage issue.
1122 X02 Modify:
EMC Neo suggestion.
A00 1224
1 AFTP3902 AFTP3902
12
3
D3902
BAV99-5-GP-U
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
D3902
BAV99-5-GP-U
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
1
2
3
4 5
6
7
8
PN3901
SRN33J -7-GP
PN3901
SRN33J -7-GP
12
3
D3901
BAV99-5-GP-U
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
D3901
BAV99-5-GP-U
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
1
2
C3902
SCD1U50V3KX-GP
C3902
SCD1U50V3KX-GP
1
2
3
4
5
6
7
8
9
10
11
BATT1
ALP-CON9-2-GP-U
20.81316.009
2nd = 20.81440.009
3rd = 20.81328.009
BATT1
ALP-CON9-2-GP-U
20.81316.009
2nd = 20.81440.009
3rd = 20.81328.009
1 AFTP3901 AFTP3901
K
A
P
D
3
9
0
2
1
S
M
A
1
8
A
T
3
G
-
G
P
DY
P
D
3
9
0
2
1
S
M
A
1
8
A
T
3
G
-
G
P
DY
12
3
D3903
BAV99-5-GP-U
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
D3903
BAV99-5-GP-U
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
1 AFTP3904 AFTP3904
1
2
C3901
SC2200P50V2KX-2GP
C3901
SC2200P50V2KX-2GP
1 2
G3901
GAP-CLOSE-PWR-3-GP
G3901
GAP-CLOSE-PWR-3-GP
1
2
EC3902
S
C
1
0
P
5
0
V
2
J
N
-
4
G
P
DY
EC3902
S
C
1
0
P
5
0
V
2
J
N
-
4
G
P
DY
1 AFTP3903 AFTP3903
1 AFTP3905 AFTP3905
1
2
EC3901
S
C
1
0
P
5
0
V
2
J
N
-
4
G
P
DY
EC3901
S
C
1
0
P
5
0
V
2
J
N
-
4
G
P
DY
1
2
E
C
3
9
0
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
3
9
0
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A
D
+
_
G
_
1
PWR_CHG_FBO
PWR_CHG_DCIN
PWR_CHG_EAO
PWR_CHG_SDA
PWR_DCBATOUT_CHG
PWR_CHG_ACOK
PWR_CHG_LX1
AC_OK
PWR_CHG_SCL
D
C
_
I
N
_
D
PWR_CHG_CSON
PWR_CHG_CSOP_1
PWR_CHG_ACOK
PWR_CHG_ICOUT
PWR_CHG_REF
PWR_CHG_VICM
PWR_CHG_PHASE
AD+_G_2
P
W
R
_
C
H
G
_
F
B
O
1
P
R
4
5
3
3
_
0
2
PWR_CHG_VFB
I
C
R
E
F
PWR_CHG_VDDP
PWR_CHG_LGATE
PWR_CHG_BST1
PWR_CHG_UGATE
PWR_CHG_CE
PWR_CHG_CSSN
PWR_CHG_CSOP
PWR_CHG_CSSP
P
R
4
5
2
4
_
0
3
PR4526_01
PWR_CHG_EAI
PWR_CHG_ACIN
PG4009_1
PWR_CHG_BOOT
AC_OK
DC_IN_D PWR_CHG_ACOK
AC_OK
PQ4003_G
PQ4003_D
ICREF
PQ4004_D
PQ4004_G
BT+
CHG_AGND
CHG_AGND
CHG_AGND
BT+_R
CHG_AGND
CHG_AGND
CHG_AGND
3D3V_AUX_KBC
CHG_AGND
AD+_TO_SYS
PWR_DCBATOUT_CHG
DCBATOUT
AD+
CHG_AGND
CHG_AGND
BT+
CHG_AGND
AD+
CHG_AGND
AD+
CHG_AGND
PWR_CHG_REF
BT+
AD+ BT+
CHG_AGND
PWR_CHG_REF
CHG_AGND
CHG_AGND
AC_IN# 27
AD_IA 27
BAT_SDA 27,39
BAT_SCL 27,39
BATT_SENSE 39
AC_OK 27
AD_IA_HW 27
H_PROCHOT# 5,27,42
AD_IA_HW2 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CHARGER BQ24745
A3
40 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CHARGER BQ24745
A3
40 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CHARGER BQ24745
A3
40 108
<Core Design>
SSID = Charger
AC_IN# to KBC
PU4004
Id=12A
Qg=3.8nC
Rdson=24~30mohm
Charger Current=1.4~3.6A
84.00412.037
Id=12A
Qg=3.8nC
Rdson=24~30mohm
This Resistor
must be 1%
tolerance.
Id=-12A
Qg=-25nC
Rdson=10~38mohm
68.5R610.10X
Id=5.5A
DCR=39~42mohm
Size=6.6X7.3X3
0603 Modify:
Add PC4034 to 78.10622.52L.
0603 Modify:
change PL4001 to 68.5R610.10X.
Id=-12A
Qg=-25nC
Rdson=10~38mohm
0625 Modify:
Reserved EC4003,EC4004 on DC_IN_D&PWR_CHG_ACOK for
EMC NEO suggestion.
0719 Modify:
Reserved EC4005 0.1uF near PR4004 for EMC NEO suggestion.
Reserved EC4008 0.1uF near PC4017 for EMC NEO suggestion.
0629 Modify
0701 Modify:
Change PQ4002 to single 2N7002.
0702 Modify:
Change PR4014 from 48.7K to 49.9K
0402 base on power team suggest.
0707 Modify:
Change PR4012 change to 0ohm 0402 from short pad.
0707 Modify:
Change PR4023 change to 0ohm 0402 from short pad.
EMI/ESD
0719 Modify:
Reserved EC4006 0.1uF near PR4002
for EMC NEO suggestion. 0719 Modify:
Reserved EC4007 0.1uF near PG4006
for EMC NEO suggestion.
0720 Modify:
Add AD_IA_HW related circuit
from TOM suggestion.
0720 Modify:
Change PR4001 to 20K from 0ohm
base on power team Brian updated.
0721 Modify:
Change PU4005 to 84.00412.037
from power team Brian updated.
0723 Modify:
Removed PR4038 PH.
0818
0827
0916 X01 Modify:
Reserved PQ4004,PR4036,PR4037 for
AD_IA_HW2 function.
0917 X01 Modify:
Change PR4027 to 0R0402
0917 X01 Modify:
Change PR4008,PR4010 to 0R0402
A001222
A001222
A001222
A001222
A001222
A001222
A001222
A001222
A001222
1
2
P
C
4
0
3
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
P
C
4
0
3
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
PC4013
SC3300P50V3KX-1GP
DY
PC4013
SC3300P50V3KX-1GP
DY
1
2
PR4024
0R0402-PAD
PR4024
0R0402-PAD
1 2
PR4019
D01R2512F-4-GP
PR4019
D01R2512F-4-GP
1 2
PC4005
SCD1U50V3KX-GP
PC4005
SCD1U50V3KX-GP
1
2
PC4029 S
C
1
U
6
D
3
V
2
K
X
-
G
P
PC4029 S
C
1
U
6
D
3
V
2
K
X
-
G
P
1
2
P
C
4
0
0
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
P
C
4
0
0
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1 2 PR4011
10KR2F-2-GP
PR4011
10KR2F-2-GP
1
2
P
C
4
0
0
8
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
0
0
8
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1
2
PC4001
SCD1U10V2KX-5GP
PC4001
SCD1U10V2KX-5GP
1
2
PC4027
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
DY
PC4027
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
DY
1 2 PR4018
0R0603-PAD
PR4018
0R0603-PAD
1 2
PC4003
SCD47U50V5KX-1GP
PC4003
SCD47U50V5KX-1GP
1
2
P
R
4
0
0
9
3
1
6
K
R
3
F
-
2
-
G
P
P
R
4
0
0
9
3
1
6
K
R
3
F
-
2
-
G
P
CE
7
VDDSMB
11
DCIN
22
PGND
19
SCL
10
SDA
9
ACIN
2
NC#14
14
VICM
8
ACOK
13
GND
12
FBO
6
EAI
5
EAO
4
CSSP
28
CSSN
27
VREF
3
BOOT
25
VDDP
21
UGATE
24
PHASE
23
LGATE
20
I
C
R
E
F
1
CSON
17
NC#16
16
VFB
15
ICOUT
26
CSOP
18
G
N
D
2
9
PU4001
BQ24745RHDR-GP
PU4001
BQ24745RHDR-GP
1
2P
R
4
0
3
0
1
K
8
R
6
J
-
G
P
DY
P
R
4
0
3
0
1
K
8
R
6
J
-
G
P
DY
K A
PD4001
SD103AWS-1-GP
83.1R504.A8F
2nd = 83.1R504.B8F
PD4001
SD103AWS-1-GP
83.1R504.A8F
2nd = 83.1R504.B8F
1
2
P
R
4
0
1
3
3
3
R
3
J
-
2
-
G
P
DY P
R
4
0
1
3
3
3
R
3
J
-
2
-
G
P
DY
1
2
E
C
4
0
0
1
S
C
2
2
0
0
P
5
0
V
2
K
X
-
2
G
P
DY E
C
4
0
0
1
S
C
2
2
0
0
P
5
0
V
2
K
X
-
2
G
P
DY
1 2
PR4026
7K5R2F-1-GP
PR4026
7K5R2F-1-GP
1
2
PC4026
S
C
D
1
U
5
0
V
3
K
X
-
G
PDY
PC4026
S
C
D
1
U
5
0
V
3
K
X
-
G
PDY
1
2
E
C
4
0
0
5
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
0
0
5
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
P
G
4
0
0
4
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
P
G
4
0
0
4
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
P
C
4
0
1
7
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
0
1
7
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P 1 2
PG4008 GAP-CLOSE-PWR-3-GP PG4008 GAP-CLOSE-PWR-3-GP
1
2
3
4 5
6
7
8 S
S
S
G D
D
D
D
PU4003
AO4407A-GP
84.04407.F37
2nd = 84.04835.H37
S
S
S
G D
D
D
D
PU4003
AO4407A-GP
84.04407.F37
2nd = 84.04835.H37
1
2
P
G
4
0
0
6
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
P
G
4
0
0
6
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
P
C
4
0
2
0
S
C
D
1
U
5
0
V
3
K
X
-
G
P
P
C
4
0
2
0
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
EC4004
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
EC4004
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
1 2
PG4007 GAP-CLOSE-PWR-3-GP PG4007 GAP-CLOSE-PWR-3-GP
1 2 PR4029
0R0402-PAD
PR4029
0R0402-PAD
1 2
PC4012
SCD1U50V3KX-GP
PC4012
SCD1U50V3KX-GP
1
2
3
4 5
6
7
8 S
S
S
G D
D
D
D
PU4002
AO4407A-GP
2nd = 84.04835.H37
84.04407.F37
S
S
S
G D
D
D
D
PU4002
AO4407A-GP
2nd = 84.04835.H37
84.04407.F37
1
2
P
R
4
0
2
1
4
K
7
R
2
J
-
2
-
G
P
P
R
4
0
2
1
4
K
7
R
2
J
-
2
-
G
P
1
2
PR4032
0R0402-PAD-2-GP
PR4032
0R0402-PAD-2-GP
1
2
P
C
4
0
2
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
P
C
4
0
2
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
PR4035
300KR2F-L-GP
PR4035
300KR2F-L-GP
GS
D
PQ4003
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
PQ4003
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1 2 PR4017
0R0603-PAD
PR4017
0R0603-PAD
1
2
P
R
4
0
0
5
1
0
K
R
2
F
-
2
-
G
P
P
R
4
0
0
5
1
0
K
R
2
F
-
2
-
G
P
1
2
PR4008
0R0402-PAD
PR4008
0R0402-PAD
1 2
PR4001
20KR2J -L2-GP
PR4001
20KR2J -L2-GP
1
2
P
G
4
0
0
5
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
P
G
4
0
0
5
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
E
C
4
0
0
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
0
0
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
P
C
4
0
2
4
S
C
2
2
0
P
5
0
V
2
J
N
-
3
G
P
P
C
4
0
2
4
S
C
2
2
0
P
5
0
V
2
J
N
-
3
G
P
1
2
E
C
4
0
0
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
0
0
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1 2 3 4
5678
S S S G
DDDD
P
U
4
0
0
4
S
I
S
4
1
2
D
N
-
T
1
-
G
E
3
-
G
P
84.00412.037
2nd = 84.08061.A37
S S S G
DDDD
P
U
4
0
0
4
S
I
S
4
1
2
D
N
-
T
1
-
G
E
3
-
G
P
84.00412.037
2nd = 84.08061.A37
1 2
PC4011
SCD1U50V3KX-GP
PC4011
SCD1U50V3KX-GP
1 2 PR4034
0R0402-PAD-2-GP
PR4034
0R0402-PAD-2-GP
1
2
3 4
5
6
PQ4001
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
PQ4001
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
1
2
P
C
4
0
1
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
P
C
4
0
1
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1 2
PR4033
20R5F-1GP
PR4033
20R5F-1GP
1 2
PC4002
SCD1U50V3KX-GP
PC4002
SCD1U50V3KX-GP
1 2 3 4
5678
S S S G
DDDD
P
U
4
0
0
5
S
I
S
4
1
2
D
N
-
T
1
-
G
E
3
-
G
P
84.00412.037
2nd = 84.08061.A37 S S S G
DDDD
P
U
4
0
0
5
S
I
S
4
1
2
D
N
-
T
1
-
G
E
3
-
G
P
84.00412.037
2nd = 84.08061.A37
1
2
P
C
4
0
0
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY P
C
4
0
0
6
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
1
2
P
R
4
0
1
4
4
9
K
9
R
2
F
-
L
-
G
P
P
R
4
0
1
4
4
9
K
9
R
2
F
-
L
-
G
P
1
2
P
R
4
0
0
3
1
0
0
K
R
2
J
-
1
-
G
P
P
R
4
0
0
3
1
0
0
K
R
2
J
-
1
-
G
P
1 2
PC4025
SC56P50V2J N-2GP
PC4025
SC56P50V2J N-2GP
1 2 PR4028
0R0402-PAD
PR4028
0R0402-PAD
1 2
PC4014
SC220P50V2J N-3GP
DY
PC4014
SC220P50V2J N-3GP
DY
1
2P
C
4
0
1
0
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
P
C
4
0
1
0
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
1
2
P
R
4
0
2
5
8
K
4
5
R
2
F
-
2
-
G
P
DY
P
R
4
0
2
5
8
K
4
5
R
2
F
-
2
-
G
P
DY
1 2
PR4007
0R2J -2-GP
DY
PR4007
0R2J -2-GP
DY
1 2
PR4022
200KR2F-L-GP
PR4022
200KR2F-L-GP
1
2
P
G
4
0
1
0
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
P
G
4
0
1
0
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
PR4036
76K8R2F-GP
PR4036
76K8R2F-GP
1 2
PC4021
SC150P50V2J N-3GP
PC4021
SC150P50V2J N-3GP
G
S
D
Q4001
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q4001
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1
2
PC4032
S
C
D
1
U
2
5
V
2
K
X
-
G
P
DY
PC4032
S
C
D
1
U
2
5
V
2
K
X
-
G
P
DY
1
2
PR4031
150KR2F-L-GP
PR4031
150KR2F-L-GP
1
2
P
C
4
0
0
4
S
C
D
1
U
5
0
V
3
K
X
-
G
P
P
C
4
0
0
4
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1 2 PR4023
0R0402-PAD
PR4023
0R0402-PAD
1
2
P
C
4
0
1
5
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
0
1
5
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1
2
PR4047
174KR2F-GP
PR4047
174KR2F-GP
1 2
PR4002
D01R2512F-4-GP
PR4002
D01R2512F-4-GP
1 2 PR4020
0R0402-PAD
PR4020
0R0402-PAD
1
2
P
C
4
0
1
6
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
0
1
6
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1
2
P
C
4
0
3
4
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
0
3
4
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1
2
P
G
4
0
0
9
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
P
G
4
0
0
9
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1 2
PL4001
IND-5D6UH-48-GP-U1
68.5R610.10X
2nd = 68.5R610.10U
PL4001
IND-5D6UH-48-GP-U1
68.5R610.10X
2nd = 68.5R610.10U
1
2
P
C
4
0
3
0
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY P
C
4
0
3
0
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1 2 PR4027
0R0402-PAD
PR4027
0R0402-PAD
1
2
PC4033
SCD1U10V2KX-5GP
DY
PC4033
SCD1U10V2KX-5GP
DY
1 2 PR4012
0R0402-PAD
PR4012
0R0402-PAD
1 2 PR4037
0R0402-PAD-2-GP
PR4037
0R0402-PAD-2-GP
1 2
PC4022
SC2200P50V2KX-2GP
PC4022
SC2200P50V2KX-2GP
1
2
P
C
4
0
0
7
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
0
0
7
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1
2
E
C
4
0
0
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
0
0
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
P
G
4
0
0
1
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
P
G
4
0
0
1
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
PR4010
0R0402-PAD
PR4010
0R0402-PAD
1
2
EC4003
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
EC4003
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P DY
1
2
EC4002
S
C
D
1
U
2
5
V
2
K
X
-
G
P
EC4002
S
C
D
1
U
2
5
V
2
K
X
-
G
P
1
2
PG4002
GAP-CLOSE-PWR-3-GP
PG4002
GAP-CLOSE-PWR-3-GP
1
2
P
C
4
0
1
8
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
0
1
8
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1
2
PG4003
GAP-CLOSE-PWR-3-GP
PG4003
GAP-CLOSE-PWR-3-GP
GS
D
PQ4004
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
PQ4004
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1
2 PC4028
SCD01U50V2KX-1GP
DY
PC4028
SCD01U50V2KX-1GP
DY
1
2
PR4006
470KR2J -2-GP
PR4006
470KR2J -2-GP
1
2
P
R
4
0
0
4
1
0
K
R
2
J
-
3
-
G
P
P
R
4
0
0
4
1
0
K
R
2
J
-
3
-
G
P
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
PWR_5V3D3V_SKIPSEL
PWR_3D3V_LGATE2_1
PWR_3D3V_FB2
PWR_5V3D3V_TONSEL
P
W
R
_
5
V
3
D
3
V
_
V
R
E
G
3
PWR_3D3V_LGATE2
PWR_5V_FB1
PWR_5V_PHASE1
PWR_3D3V_ENTRIP2
3V_5V_POK
PWR_3D3V_BOOT2
P
W
R
_
5
V
_
S
N
U
B
PWR_5V_UGATE1
PWR_5V_ENTRIP1
PWR_5V_LGATE1
PWR_3D3V_UGATE2
PWR_5V_VOUT1
PWR_3D3V_PHASE2
PWR_5V_BOOT1
PWR_3D3V_VOUT2
PWR_5V_FB1_R
PWR_5V3D3V_EN0
PWR_3D3V_ENTRIP2
PWR_3D3V_FB2_R
PWR_3D3V_BOOT1
PWR_5V3D3V_ENC
P
W
R
_
3
D
3
V
_
S
N
U
B
PWR_5V_VBST1_1
PWR_5V_ENTRIP1
PC4108_1
PD4101_3 PD4103_3
PWR_3D3V_LGATE2
PU4101_5
PU4101_2
PWR_5V3D3V_EN0
5V_PWR 5V_S5
5V_PWR
5V_S5 15V_S5
PWR_5V3D3V_VREF
3D3V_AUX_S5
PWR_5V3D3V_VREF
3D3V_PWR
PWR_5V3D3V_VREF
PWR_3D3V_DCBATOUT
DCBATOUT
3D3V_PWR
3D3V_AUX_S5
3D3V_AUX_S5
3D3V_S5
5V_AUX_S5
3D3V_S5
15V_PWR
PWR_5V_DCBATOUT
PWR_5V_DCBATOUT DCBATOUT
PWR_3D3V_DCBATOUT DCBATOUT
5V_S5
DCBATOUT DCBATOUT
3V_5V_EN 36
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
5V/3D3V(TPS51123RGER)
A2
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
A2
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
A2
<Variant Name>
ROSA team
VREG3 or VREG5
Design Current = 8A
12.6A<OCP< 14.6A
Design Current = 9.2A
14.5A<OCP< 17A
Close to VFB Pin (pin5) Close to VFB Pin (pin2)
375kHz
500kHz
PWM only
CH2 CH1
VREF(2V)
Operating
Mode
OOA Auto Skip Auto Skip
SKIPSEL
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 2.2UH FDVE0630-2R2M=P3 TOKO 21mohm Isat =8.7Arms 68.2R21B.10A
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
H/S: FDSS8884 SO-8/ 23mohm/30mOhm@4.5Vgs/ 84.08884.037
L/S: FDS6690AS SO-8/ 12mohm/15mOhm@4.5Vgs/ 84.06690.E37
GND VREG3 or VREG5
TONSEL
GND
VREF
200kHz
300kHz
400kHz
250kHz
SSID = PWR.Plane.Regulator_5v3p3v
0603 Modify:
Change PR4103 to 187K from 100K.
0604 Modify:
Change PU4103 to 74.8223.A73.
0714 Modify:
Change PU4103 to TPS51123 from RT8223MGQW.
0720 Modify:
Change PR4105 to 2.2ohm from 0ohm from
power team Brian updated.
0629 Modify
0701 Modify:
PC4127 Default un-stuff.
0719Modify:
ReservedEC4101~EC41060.1uF near
PTC4101,PC4119for EMC NEO suggestion.
0719Modify:
ReservedEC4170.1uF for
EMC NEO suggestion.
0721 Modify:
Change PU4104 to 84.04800.D37
from power team Brian updated.
0721 Modify:
Change PR4106 to 0ohm 0603 from
2.2ohm from power team Brian updated.
0721 Modify:
Add PG4127,PG4128 from
0804 0804
0804 Change MOS follow Brian.
0901 PU4104 and PU 4105 horizontally mirror.
0810
0913 X01 Modify:
Add 2nd source 84.08061.A37 on PU4102,
PU4104 base on Brian updated 2nd soruce excel file.
84.07716.037
Id=16A
Qg=7.3nC
Rdson=13.5~16.5mohm
84.00412.037
Id=12A
Qg=3.8nC
Rdson=24~30mohm
Mag. 2.20uH 6.5*6.9*3
DCR=18~20mohm
Idc=8A, Isat=14A
0909 X01 Modify:
Change PL4101,PL4102 to 68.2R210.20B
from 68.2R210.20Q base on Brian updated.
Add 2nd source 68.2R21B.10J on PL4101,
PL4102 base on updated 2nd excel file.
0914 X01 Modify:
Un-stuff PU4101,PD4105,PR4124,
PR4125,PR4101 at X01 stage.
Vz=5.1V
0629 Modify
A00 1224
A00 1224
1 2
PG4108 GAP-CLOSE-PWR PG4108 GAP-CLOSE-PWR
1
2
PC4128
SC18P50V2J N-1-GP
DY PC4128
SC18P50V2J N-1-GP
DY
1 2
3
PD4101
BAT54S-7F-GP
83.00054.Y81
2nd = 83.0R203.081
PD4101
BAT54S-7F-GP
83.00054.Y81
2nd = 83.0R203.081
1
2
P
C
4
1
2
2
S
C
D
2
2
U
1
0
V
2
K
X
-1
G
P
P
C
4
1
2
2
S
C
D
2
2
U
1
0
V
2
K
X
-1
G
P
1
2
PR4114
0R2J -2-GP DY
PR4114
0R2J -2-GP DY
1
2
E
C
4
1
0
3
S
C
D
1
U
5
0
V
3
K
X
-G
P
E
C
4
1
0
3
S
C
D
1
U
5
0
V
3
K
X
-G
P
1 2
1
2
PT4104
S
E
3
3
0
U
6
D
3
V
M
-1
5
-G
P
77.53371.04L
2nd = 77.93371.011
PT4104
S
E
3
3
0
U
6
D
3
V
M
-1
5
-G
P
77.53371.04L
2nd = 77.93371.011
1 2
PC4115
SCD1U25V3KX-GP
PC4115
SCD1U25V3KX-GP
1 2
1
2
PC4116
S
C
1
0
U
2
5
V
6
K
X
-1
G
P
PC4116
S
C
1
0
U
2
5
V
6
K
X
-1
G
P
1
2
3 4
5
6
PU4101
2N7002KDW-GP
84.2N702.A3F
DY
PU4101
2N7002KDW-GP
84.2N702.A3F
DY
1 2
1
2
PR4108
2D2R5F-2-GP
DY
PR4108
2D2R5F-2-GP
DY
1
2
3
PD4102
BAT54-7-F-GP
DY
PD4102
BAT54-7-F-GP
DY
1 2
1 2
1
2
PC4105
SC18P50V2J N-1-GP
DY PC4105
SC18P50V2J N-1-GP
DY
1
2
PR4112
0R2J -2-GP
DY
PR4112
0R2J -2-GP
DY
1 2
PR4109 820KR2F-GP
DY
PR4109 820KR2F-GP
DY
1
2
PC4113 S
C
D
0
1
U
5
0
V
2
K
X
-1
G
P
PC4113 S
C
D
0
1
U
5
0
V
2
K
X
-1
G
P
1
2
P
R
4
1
0
4
1
4
7
K
R
2
F
-G
P
P
R
4
1
0
4
1
4
7
K
R
2
F
-G
P
1
2
PC4112
S
C
1
0
U
2
5
V
6
K
X
-1
G
P
PC4112
S
C
1
0
U
2
5
V
6
K
X
-1
G
P
1 2
PR4117
0R2J -2-GP DY
PR4117
0R2J -2-GP DY
1
2
PC4110
S
C
1
0
U
2
5
V
6
K
X
-1
G
P
PC4110
S
C
1
0
U
2
5
V
6
K
X
-1
G
P
1 2 PR4123
0R2J -2-GP DY
PR4123
0R2J -2-GP DY
1
2
PC4109
SCD1U25V3KX-GP
PC4109
SCD1U25V3KX-GP
1 2
1
2
PR4124
40K2R2F-GP
DY
PR4124
40K2R2F-GP
DY
1
2
PC4107
SC1U25V3KX-1-GP
PC4107
SC1U25V3KX-1-GP
1
2
PC4121
SC330P50V3KX-GP
DY
PC4121
SC330P50V3KX-GP
DY 1
2
PC4123
SC560P50V-GP
DY
PC4123
SC560P50V-GP
DY
1 2
1 2
PL4102
IND-2D2UH-46-GP-U
68.2R210.20B
2nd = 68.2R21B.10J
PL4102
IND-2D2UH-46-GP-U
68.2R210.20B
2nd = 68.2R21B.10J
1 2
1
2
PR4125
750KR2F-GP
DY
PR4125
750KR2F-GP
DY
1
2
PC4106
SC18P50V2J N-1-GP
DY PC4106
SC18P50V2J N-1-GP
DY
1 2
1 2
1
2
EC4107
S
C
D
1
U
5
0
V
3
K
X
-G
P
EC4107
S
C
D
1
U
5
0
V
3
K
X
-G
P
VBST2
9
DRVH2
10
LL2
11
DRVL2
12
VO2
7
VFB2
5
EN0
13
TRIP2
6
VREF
3
TONSEL
4
V
R
E
G
3
8
V
IN
1
6
VBST1
22
DRVH1
21
LL1
20
DRVL1
19
VO1
24
VFB1
2
PGOOD
23
TRIP1
1
GND
15
V
R
E
G
5
1
7
GND
25
ENC
18
SKIPSEL
14
PU4103
TPS51123RGER-GP
74.51123.073
PU4103
TPS51123RGER-GP
74.51123.073
1
2
PC4125
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
PC4125
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
1
2
PC4111
S
C
D
1
U
5
0
V
3
K
X
-G
P
PC4111
S
C
D
1
U
5
0
V
3
K
X
-G
P
1
2
PT4102
S
E
3
3
0
U
6
D
3
V
M
-1
5
-G
P
77.53371.04L
2nd = 77.93371.011
PT4102
S
E
3
3
0
U
6
D
3
V
M
-1
5
-G
P
77.53371.04L
2nd = 77.93371.011
1 2
PG4125
GAP-CLOSE-PWR-3-GP
PG4125
GAP-CLOSE-PWR-3-GP
1 2
PL4101
IND-2D2UH-46-GP-U
68.2R210.20B
2nd = 68.2R21B.10J
PL4101
IND-2D2UH-46-GP-U
68.2R210.20B
2nd = 68.2R21B.10J
1 2
1
2
PR4113
0R0402-PAD
PR4113
0R0402-PAD
1 2 PR4121
0R0402-PAD
PR4121
0R0402-PAD
1 2 PR4106
0R0603-PAD
PR4106
0R0603-PAD
1 2
1
2
PR4116
10KR2F-2-GP
PR4116
10KR2F-2-GP
1 2 PR4120
0R2J -2-GP DY
PR4120
0R2J -2-GP DY
1
2
P
C
4
1
0
3
S
C
D
1
U
2
5
V
3
K
X
-G
P
P
C
4
1
0
3
S
C
D
1
U
2
5
V
3
K
X
-G
P
1 2
1
2
PD4105
MMPZ5231BPT-GP
DY
2nd = 83.PDZ51.AVF
83.5R103.E3F
PD4105
MMPZ5231BPT-GP
DY
2nd = 83.PDZ51.AVF
83.5R103.E3F
1
2
P
C
4
1
0
2
S
C
D
1
U
2
5
V
3
K
X
-G
P
P
C
4
1
0
2
S
C
D
1
U
2
5
V
3
K
X
-G
P
1
2
PR4110
100KR2J -1-GP
PR4110
100KR2J -1-GP
1 2
PR4105
2D2R3-1-U-GP
PR4105
2D2R3-1-U-GP
1 2
PG4101
GAP-CLOSE-PWR-3-GP
PG4101
GAP-CLOSE-PWR-3-GP
1 2
PC4118
SCD1U25V3KX-GP
PC4118
SCD1U25V3KX-GP
1 2
1 2
1
2
PC4108
SCD1U25V3KX-GP
PC4108
SCD1U25V3KX-GP
1 2 3 4
5678
S S S G
DDDD
PU4104
SIS412DN-T1-GE3-GP
84.00412.037
2nd = 84.08061.A37
S S S G
DDDD
PU4104
SIS412DN-T1-GE3-GP
84.00412.037
2nd = 84.08061.A37
1 2
1
2P
C
4
1
1
9
S
C
D
1
U
1
0
V
2
K
X
-4
G
P
P
C
4
1
1
9
S
C
D
1
U
1
0
V
2
K
X
-4
G
P
1
2
PR4119
21K5R2F-GP
PR4119
21K5R2F-GP
1 2
1
2
PC4101 S
C
1
0
U
2
5
V
6
K
X
-1
G
P
DY
PC4101 S
C
1
0
U
2
5
V
6
K
X
-1
G
P
DY
1 2
1
2
E
C
4
1
0
1
S
C
D
1
U
5
0
V
3
K
X
-G
P
DY
E
C
4
1
0
1
S
C
D
1
U
5
0
V
3
K
X
-G
P
DY
1 2
1
2
E
C
4
1
0
2
S
C
D
1
U
5
0
V
3
K
X
-G
P
E
C
4
1
0
2
S
C
D
1
U
5
0
V
3
K
X
-G
P
1 2
1
2
PC4117
S
C
D
1
U
5
0
V
3
K
X
-G
P
PC4117
S
C
D
1
U
5
0
V
3
K
X
-G
P
1 2
3
PD4103
BAT54S-7F-GP
83.00054.Y81
2nd = 83.0R203.081
PD4103
BAT54S-7F-GP
83.00054.Y81
2nd = 83.0R203.081
1
2
PC4126
S
C
1
0
U
6
D
3
V
5
K
X
-1
G
P
PC4126
S
C
1
0
U
6
D
3
V
5
K
X
-1
G
P
1
2
P
R
4
1
0
3
1
8
7
K
R
2
F
-G
P
P
R
4
1
0
3
1
8
7
K
R
2
F
-G
P
1
2
PG4114 G
A
P
-C
L
O
S
E
-P
W
R
-3
-G
P
PG4114 G
A
P
-C
L
O
S
E
-P
W
R
-3
-G
P
1
2
PR4101
100KR2F-L1-GP DY
PR4101
100KR2F-L1-GP DY
1 2 3 4
5678
S S S G
DDDD
PU4105
SI7716ADN-T1-GE3-GP
84.07716.037
2nd = 84.08065.B37
S S S G
DDDD
PU4105
SI7716ADN-T1-GE3-GP
84.07716.037
2nd = 84.08065.B37
1
2
PR4107
2D2R5F-2-GP
DY
PR4107
2D2R5F-2-GP
DY
1
2
PR4111
6K65R2F-GP
PR4111
6K65R2F-GP
1 2
1
2
PC4127
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
DY
PC4127
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
DY
1 2
1 2 PR4102
0R0402-PAD
PR4102
0R0402-PAD
1 2
1
2
P
C
4
1
0
4
S
C
1
K
P
5
0
V
2
K
X
-1
G
P
P
C
4
1
0
4
S
C
1
K
P
5
0
V
2
K
X
-1
G
P
1234
5 6 7 8
SSSG
D D D D
PU4102
SIS412DN-T1-GE3-GP
84.00412.037
2nd = 84.08061.A37
SSSG
D D D D
PU4102
SIS412DN-T1-GE3-GP
84.00412.037
2nd = 84.08061.A37
1
2
PC4120
S
C
D
1
U
1
0
V
2
K
X
-4
G
P
PC4120
S
C
D
1
U
1
0
V
2
K
X
-4
G
P
1
2
PG4113
G
A
P
-C
L
O
S
E
-P
W
R
-3
-G
P
PG4113
G
A
P
-C
L
O
S
E
-P
W
R
-3
-G
P
1234
5 6 7 8
SSSG
D D D D
PU4106
SI7716ADN-T1-GE3-GP
84.07716.037
2nd = 84.08065.B37
SSSG
D D D D
PU4106
SI7716ADN-T1-GE3-GP
84.07716.037
2nd = 84.08065.B37
1
2
PC4114
S
C
1
0
U
2
5
V
6
K
X
-1
G
P
PC4114
S
C
1
0
U
2
5
V
6
K
X
-1
G
P
A
K
PD4104
BZT52C15S-GP
83.15R03.C3F
2nd = 83.15R03.E3F
PD4104
BZT52C15S-GP
83.15R03.C3F
2nd = 83.15R03.E3F
1 2 PR4118
0R0402-PAD
PR4118
0R0402-PAD
1
2
PR4115
33KR2F-GP
PR4115
33KR2F-GP
1
2
PC4124
SC18P50V2J N-1-GP DY
PC4124
SC18P50V2J N-1-GP DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
95831_VIN
VSUM-
I
S
E
N
3
I
S
E
N
2
I
S
E
N
1
IMVP_VR_ON
BOOT2
95831_NTC
UGATE2
PHASE2
H_PROCHOT#_C
NTCG
LGATE2
P
R
4
2
2
0
_
1
ISEN2
ISEN1
ISEN3
95831_COMPG
PC4211_2
PC4221_1
95831_VWG
95831_SCLK
95831_PGOODG
P
R
4
2
2
8
_
1
ISEN3
P
C
4
2
1
0
_
2
PC4213_1
95831_COMP
P
R
4
2
1
8
_
2
PR4242_2
95831_VDD
9
5
8
3
1
_
P
R
O
G
2
95831_PWM3
LGATE1
95831_SDA
95831_PROG1
95831_FB
PHASE1
UGATE1
BOOT1 95831_VW
95831_FBG
9
5
8
3
1
_
I
S
U
M
N
95831_VDDP
VSS_AXG_SENSE
95831_IMONG
95831_IMON
VSSSENSE
PR4216_1
PR4214_1
1D05V_VTT
3D3V_S0
3D3V_S0
1D05V_VTT
PWR_VCCCORE1_DCBATOUT
5V_S5
5V_S0
VCC_GFXCORE
ISEN3 43
ISEN2 43
ISEN1 43
H_CPU_SVIDDAT 8
VR_SVID_ALERT# 8
H_CPU_SVIDCLK 8
IMVP_PWRGD 27,36
H_PROCHOT# 5,27,40
VCCSENSE 8
VSSSENSE 8
VCC_AXG_SENSE 9
VSS_AXG_SENSE 9
ISPG 44
ISNG 44
BOOTG 44
PHASEG 44
UGATEG 44
LGATEG 44
BOOT2 43
UGATE2 43
PHASE2 43
LGATE2 43
LGATE1 43
PHASE1 43
UGATE1 43
BOOT1 43
PWM3 43
VSUM+ 43
VSUM- 43
D85V_PWRGD 48
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
ISL95831_CPU_CORE(1/3)
A3
42 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
42 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
42 108
<Variant Name>
Close to CPU
NTC place near high side MOSFET of Phase1
Place near choke of Phase1
Place near high side MOSFET of Phase1
SSID = CPU.Regulator
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0629 Modify
0707 Modify:
Removed PR4233.
0707 Modify:
Updated IMONG and IMON circuit
from power team Brian.
0707 Modify:
Stuff PR4247 NTC Resistor.
0707 Modify:
Removed PR4240 GND to 95831_AGND.
0707 Modify:
Change all of 9531_AGND to GND for vender suggest.
0719 Modify:
Stuff PR4246 NTC resistor.
0719 Modify:
Reserved EC4201~EC4203 0.1uF near
PR4246(TOP) for EMC NEO suggestion.
0721 Modify:
Removed EC4201~EC4203.
0719 Modify:
Reserved EC4204~EC4207 0.1uF near
C1403(TOP),C1507,C1509,C1406,
TP_LOCK_LED1 for EMC NEO suggestion.
0721 Modify:
Change PR4217 to 1K from 698ohm from
0721 Modify:
Change PR4213 to 3.16K from 2.32K from
0721 Modify:
Change PC4227 to 33uF from 47uF from
Change PC4225 to 0.033uF from 0.068uF from
0901
0921
Change PU4201 VDD power source to 5V_S5 from
5V_S0 to avoid abnormal MVP_PWRGD waveform.
0920 X01 Modify:
Change PR4213 to 3.6K from 3.16K
from Brian updated.
0920 X01 Modify:
Change PR4236 to 3.01K from 3.32K
from Brian updated.
0921 X01 Modify:
Add PR4216,PC4231 from vender suggestion.
0921 X01 Modify:
Add PR4214,PC4230 from vender suggestion.
Only for Dual-core,
Qual-core stuff 1K27R
(64.12715.6DL)
Only for Dual-core,
Qual-core stuff 3K6R(64.36015.6DL)
Only for Dual-core,
Qual-core stuff 18K2R
(64.18225.LDL)
Only for Dual-core,
Qual-core stuff 22KR
(64.22025.6DL)
A00 1227
A00 1227
A00 1227
A00 1230
1
2
P
C
4
2
2
6
S
C
1
U
1
0
V
2
K
X
-
1
G
P
P
C
4
2
2
6
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1 2
PR4212
499R2F-2-GP
PR4212
499R2F-2-GP
1 2
PR4217
845R2F-GP
DC&QC
PR4217
845R2F-GP
DC&QC
1 2
PR4246
NTC-470K-9-GP
69.60013.141
2nd = 69.60037.021
PR4246
NTC-470K-9-GP
69.60013.141
2nd = 69.60037.021
1
2
PC4202
SC1000P50V3J N-GP-U
PC4202
SC1000P50V3J N-GP-U
1
2
PR4243
0R0402-PAD
PR4243
0R0402-PAD
2
1
P
C
4
2
0
1
S
C
D
2
2
U
2
5
V
3
K
X
-
G
P
2
1
P
C
4
2
0
1
S
C
D
2
2
U
2
5
V
3
K
X
-
G
P
1 2
PC4207
DUMMY-C2
PC4207
DUMMY-C2
1 2
PR4210
475KR2F-GP
PR4210
475KR2F-GP
1 2
PG4201
DUMMY-C2
PG4201
DUMMY-C2
1 2
PG4202
DUMMY-C2
PG4202
DUMMY-C2
1 2
PC4231
SC330P50V2KX-3GP
PC4231
SC330P50V2KX-3GP
1 2
PC4221
SC680P50V2KX-2GP
PC4221
SC680P50V2KX-2GP
1 2
PC4222
SC1000P50V3J N-GP-U
PC4222
SC1000P50V3J N-GP-U
1
2
PC4212
SCD068U10V2KX-1GP
PC4212
SCD068U10V2KX-1GP
1 2
PC4230
SC560P50V-GP
PC4230
SC560P50V-GP
1 2
PR4201
75R2F-2-GP
DY
PR4201
75R2F-2-GP
DY
1 2
PR4224
1R2F-GP
PR4224
1R2F-GP
1
2
P
R
4
2
3
4
5
4
D
9
R
2
F
-
L
1
-
G
P
P
R
4
2
3
4
5
4
D
9
R
2
F
-
L
1
-
G
P
1 2
PC4211
SC150P50V2KX-GP
PC4211
SC150P50V2KX-GP
1
2
PR4242
2K61R2F-1-GP
PR4242
2K61R2F-1-GP
1 2
PC4209
SC39P50V2J N-1GP
PC4209
SC39P50V2J N-1GP
1 2 PR4215
0R0402-PAD
PR4215
0R0402-PAD
1 2
PC4214
SCD1U10V2KX-4GP
PC4214
SCD1U10V2KX-4GP
1 2
PR4247
NTC-470K-9-GP
69.60013.141
2nd = 69.60037.021
PR4247
NTC-470K-9-GP
69.60013.141
2nd = 69.60037.021
1 2
PR4209
316KR2F-GP
PR4209
316KR2F-GP
1 2
PR4239
16K5R2F-2-GP
PR4239
16K5R2F-2-GP
1 2
PR4236
3K01R2F-3-GP
PR4236
3K01R2F-3-GP
1
2 P
C
4
2
2
7
S
C
D
3
3
U
6
D
3
V
2
K
X
-
1
-
G
P
P
C
4
2
2
7
S
C
D
3
3
U
6
D
3
V
2
K
X
-
1
-
G
P
1 2
PC4215
SCD22U10V2KX-1GP
PC4215
SCD22U10V2KX-1GP
1 2
PR4226
5K62R2F-GP
PR4226
5K62R2F-GP
1
2
PR4230
1K91R2F-1-GP
PR4230
1K91R2F-1-GP
1 2
PR4219
3K83R2F-GP
PR4219
3K83R2F-GP
1 2
PC4213
SC470P50V-2-GP
PC4213
SC470P50V-2-GP
1
2
P
C
4
2
2
8
S
C
1
U
1
0
V
2
K
X
-
1
G
P
P
C
4
2
2
8
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1 2
PC4210
SC150P50V2KX-GP
PC4210
SC150P50V2KX-GP
1
2
E
C
4
2
0
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
2
0
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1 2
PR4220
27K4R2F-GP
PR4220
27K4R2F-GP
1
2
PR4237
D
U
M
M
Y
-
R
2
PR4237
D
U
M
M
Y
-
R
2
1
2
P
C
4
2
0
3
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
P
C
4
2
0
3
S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
1
2
PC4204
SC47P50V2J N-3GP
PC4204
SC47P50V2J N-3GP
1
2
P
C
4
2
2
5
S
C
D
0
3
3
U
1
6
V
2
K
X
-
G
P
P
C
4
2
2
5
S
C
D
0
3
3
U
1
6
V
2
K
X
-
G
P
1 2
PR4218
DUMMY-R2
PR4218
DUMMY-R2
1
2
P
R
4
2
4
1
1
1
K
R
2
F
-
L
-
G
P
P
R
4
2
4
1
1
1
K
R
2
F
-
L
-
G
P
1
2
PR4245
NTC-10K-27-GP
2nd = 69.60011.201
69.60013.131
PR4245
NTC-10K-27-GP
2nd = 69.60011.201
69.60013.131
1
2
P
R
4
2
3
2
1
3
0
R
2
F
-
1
-
G
P
P
R
4
2
3
2
1
3
0
R
2
F
-
1
-
G
P
1
2
PR4222
0R0402-PAD
PR4222
0R0402-PAD
1 2
PR4216
2KR2F-3-GP
PR4216
2KR2F-3-GP
1
2
PR4202
22KR2F-GP
PR4202
22KR2F-GP
VWG
1
IMONG
2
PGOODG
3
SDA
4
ALERT#
5
SCLK
6
VR_ON
7
PGOOD
8
IMON
9
VR_HOT#
10
NTC
11
VW
12
C
O
M
P
1
3
F
B
1
4
I
S
E
N
3
/
F
B
2
1
5
I
S
E
N
2
1
6
I
S
E
N
1
1
7
V
S
E
N
1
8
R
T
N
1
9
I
S
U
M
N
2
0
I
S
U
M
P
2
1
V
D
D
2
2
V
I
N
2
3
P
R
O
G
1
2
4
C
O
M
P
G
4
8
F
B
G
4
7
V
S
E
N
G
4
6
R
T
N
G
4
5
I
S
P
G
4
4
I
S
N
G
4
3
N
T
C
G
4
2
P
R
O
G
2
4
1
B
O
O
T
G
4
0
U
G
G
3
9
P
H
G
3
8
L
G
G
3
7
BOOT2
36
UG2
35
PH2
34
VSSP2
33
LG2
32
VDDP
31
PWM3
30
LG1
29
VSSP1
28
PH1
27
UG1
26
BOOT1
25
G
N
D
4
9
PU4201
ISL95831HRTZ-T-GP
PU4201
ISL95831HRTZ-T-GP
1
2
P
C
4
2
0
5
S
C
D
0
4
7
U
2
5
V
2
K
X
-
G
P
P
C
4
2
0
5
S
C
D
0
4
7
U
2
5
V
2
K
X
-
G
P
1 2
PR4206
DUMMY-R2
PR4206
DUMMY-R2
1 2
PR4214
2KR2F-3-GP
PR4214
2KR2F-3-GP
1 2
PR4228
27K4R2F-GP
PR4228
27K4R2F-GP
1 2 PR4223
0R2J -2-GP
DY
PR4223
0R2J -2-GP
DY
1
2
PC4218
SCD1U10V2KX-4GP
PC4218
SCD1U10V2KX-4GP
1 2
PR4211
422R2F-2-GP
PR4211
422R2F-2-GP
1
2
PC4206
SC1000P50V3J N-GP-U
PC4206
SC1000P50V3J N-GP-U
1
2
PR4205
8
K
0
6
R
2
F
-
G
P
PR4205
8
K
0
6
R
2
F
-
G
P1 2
PC4216
SCD22U10V2KX-1GP
PC4216
SCD22U10V2KX-1GP
1 2 PR4225
0R0402-PAD
PR4225
0R0402-PAD
1
2
P
C
4
2
2
4
S
C
3
3
0
P
5
0
V
2
K
X
-
3
G
P
P
C
4
2
2
4
S
C
3
3
0
P
5
0
V
2
K
X
-
3
G
P
1
2
P
R
4
2
4
4
7
5
R
2
F
-
2
-
G
P
P
R
4
2
4
4
7
5
R
2
F
-
2
-
G
P
1 2 PR4204
0R0402-PAD
PR4204
0R0402-PAD
1 2
PC4220
SC330P50V2KX-3GP
DY
PC4220
SC330P50V2KX-3GP
DY
1 2 PR4235 1K91R2F-1-GP PR4235 1K91R2F-1-GP
1 2
PC4219
SC330P50V2KX-3GP
DY
PC4219
SC330P50V2KX-3GP
DY
1
2
P
C
4
2
2
9
S
C
1
U
1
0
V
2
K
X
-
1
G
P
P
C
4
2
2
9
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1 2
PR4213
2K37R2F-GP
DC&QC
PR4213
2K37R2F-GP
DC&QC
1 2
PC4217
SCD22U10V2KX-1GP
PC4217
SCD22U10V2KX-1GP
1
2
PR4208
8K06R2F-GP
PR4208
8K06R2F-GP
1 2
PR4229
3K83R2F-GP
PR4229
3K83R2F-GP
1 2 PR4231
0R0402-PAD
PR4231
0R0402-PAD
1 2 PR4203
0R0402-PAD
PR4203
0R0402-PAD
1 2
PC4208
SC39P50V2J N-1GP
PC4208
SC39P50V2J N-1GP
1
2
PR4207
22KR2F-GP DC&QC
PR4207
22KR2F-GP DC&QC
1 2
PG4203
DUMMY-C2
PG4203
DUMMY-C2
1 2
PC4223
SC1000P50V3J N-GP-U
PC4223
SC1000P50V3J N-GP-U
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR_VCCCORE_LG3
P
W
R
_
V
C
C
C
O
R
E
_
V
S
U
M
-
_
3
PWR_VCCCORE_BOOT3_1
PWR_VCCCORE_HG3
P
W
R
_
V
C
C
C
O
R
E
_
B
O
O
T
3
PWR_VCCCORE_PH3
PWR_FCCM
PWR_VCCCORE_BOOT1_1
P
W
R
_
V
C
C
C
O
R
E
_
V
S
U
M
+
_
1
P
W
R
_
V
C
C
C
O
R
E
_
V
S
U
M
-
_
1
P
W
R
_
V
C
C
C
O
R
E
_
V
S
U
M
+
_
2
UGATE2
LGATE2
PWR_VCCCORE_BOOT2_1
PHASE2
P
W
R
_
V
C
C
C
O
R
E
_
V
S
U
M
-
_
2
P
W
R
_
V
C
C
C
O
R
E
_
V
S
U
M
+
_
3
U
4
3
0
6
_
V
I
N
-
INA_A1
U
4
3
0
6
_
V
I
N
+
INA_A0
P
W
R
_
V
C
C
C
O
R
E
_
V
S
U
M
+
_
3
PWR_VCCCORE3_DCBATOUT 5V_S0
VCC_CORE
VCC_CORE
VCC_CORE
PWR_VCCCORE3_DCBATOUT DCBATOUT_IMVP7
DCBATOUT DCBATOUT_IMVP7
DCBATOUT_IMVP7
DCBATOUT_IMVP7
DCBATOUT
3D3V_VGA_S0
PWM3 42
VSUM- 42
ISEN1 42
ISEN2 42
ISEN3 42
VSUM+ 42
UGATE1 42
PHASE1 42
LGATE1 42
BOOT1 42
ISEN2 42
ISEN3 42
ISEN1 42
VSUM+ 42
VSUM- 42
ISEN1 42
ISEN3 42
ISEN2 42
VSUM+ 42
VSUM- 42
BOOT2 42
UGATE2 42
PHASE2 42
LGATE2 42
SMBD_INA219 85,92
SMBC_INA219 85,92
Title
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, HsinTai WuRd., Hsichih,
Taipei Hsien221, Taiwan, R.O.C.
QUEEN 15 A00
ISL95831_CPU_CORE ( 2 of 3 )
Custom
DN15ATI
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Custom
DN15ATI
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Custom
DN15ATI
84.00460.037
SIR460DP
Id=40A,Qg=16.8nC,
Rdson=4.7~6.1mohm
68.R3610.20A
0.36uH, Idc=20A,
Isat=25A
DCR=1.4 +/-7% mohm
80.3371V.A2L
330uF, 2.5V, B2
ESR=9m[, Iripple=3.073A
Vcc_core
Iomax=53A
OCP>97.5A
84.00462.037
SIR462DP
Id=30A, Qg=8.8nC,
Rdson=7.9~10 mohm
FOR NVIDIA VENTURA
0705 Modify
0705 Modify
0705 Modify
0705 Modify
0705 Modify
0705 Modify
0719 Modify:
Reserved PTC4307 47uF.
0721 Modify:
Removed PTC4307.
0719 Modify:
ChangePU4302 part number to 84.00172.037 from
84.07686.037 baseon power teamBrian suggestion.
0726 Modify:
Brian updatedePU4302 changeto 84.00462.037.
0719 Modify:
0726 Modify:
0719 Modify:
0726 Modify:
84.00462.037
SIR462DP
Id=30A, Qg=8.8nC,
Rdson=7.9~10 mohm
84.00462.037
SIR462DP
Id=30A, Qg=8.8nC,
Rdson=7.9~10 mohm
84.00460.037
SIR460DP
Id=40A,Qg=16.8nC,
Rdson=4.7~6.1mohm
84.00460.037
SIR460DP
Id=40A,Qg=16.8nC,
Rdson=4.7~6.1mohm
0702 Modify:
Change U4306 power source to
3D3V_VGA_S0 from 3D3V_S0.
0705 Modify:
R4346 change to PR4320 4m ohm sense
Resistor from 3m ohm.
0708 Modify:
PR4320 change to BIG SIZE footprint for CPU VENTURA.
0705 Modify:
Add PR4321,PR4322,PC4319.
0712 Modify:
Change VENTURA solution part number to
74.00900.079 from 74.00219.079.
Would be instead of INA219 by HPA00900
0705 Modify:
Removed R4347 sense Resistor base on VENTURA SPEC.
0728
0809
0809
0809
A00 1223 no co-lay
A00 1224
A00 1224
A00 1224
A00 1224
1
2
R4346
3K3R2J -3-GP
DY
R4346
3K3R2J -3-GP
DY
1 2
PG4323
GAP-CLOSE-PWR
PG4323
GAP-CLOSE-PWR
1 2
PR4313
3K65R2F-1-GP
PR4313
3K65R2F-1-GP
1 2
PG4311
GAP-CLOSE-PWR
PG4311
GAP-CLOSE-PWR
V
I
N
+
1
V
I
N
-
2
G
N
D
3
V
S
4
S
C
L
5
S
D
A
6
A
0
7
A
1
8
U4306
HPA00900AIDCNR-GP
VENTURA
74.00900.079
U4306
HPA00900AIDCNR-GP
VENTURA
74.00900.079
1
2
PT4303
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4303
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
1 2
PR4309
1R2F-GP
DY
PR4309
1R2F-GP
DY
1 2 3 4
5678
S S S
DDDD
G
PU4304
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
S S S
DDDD
G
PU4304
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
1 2
PG4321
GAP-CLOSE-PWR
PG4321
GAP-CLOSE-PWR
1 2
PR4310
1R2F-GP
DY
PR4310
1R2F-GP
DY
1 2
PR4302
2D2R3-1-U-GP
PR4302
2D2R3-1-U-GP
1 2
PG4308
GAP-CLOSE-PWR
PG4308
GAP-CLOSE-PWR
1 2
PR4308
2D2R3-1-U-GP
PR4308
2D2R3-1-U-GP
1
2
PG4301
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
PG4301
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1 2
PG4313
GAP-CLOSE-PWR
PG4313
GAP-CLOSE-PWR
1 2
PR4311
1R2F-GP
PR4311
1R2F-GP
1
2
PT4309
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4309
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
1 2
PR4319
3K65R2F-1-GP
PR4319
3K65R2F-1-GP
1
2
PC4316
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P QC
PC4316
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P QC
1 2
PR4315
1R2F-GP
DY
PR4315
1R2F-GP
DY
1
2
PT4306
SE47U25VM-11-GP
2nd = 79.47612.60L
79.47612.3FL
PT4306
SE47U25VM-11-GP
2nd = 79.47612.60L
79.47612.3FL
1 2
PG4310
GAP-CLOSE-PWR
PG4310
GAP-CLOSE-PWR
1
2
PG4317
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
PG4317
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
PG4303
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
PG4303
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1 2
PG4316
GAP-CLOSE-PWR
PG4316
GAP-CLOSE-PWR
1
2
PG4302
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
PG4302
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1 2
PG4315
GAP-CLOSE-PWR
PG4315
GAP-CLOSE-PWR
1
2
PG4318
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
PG4318
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1 2
PR4314
2D2R3-1-U-GP
PR4314
2D2R3-1-U-GP
1 2
PR4320
D004R3720F-GP
PR4320
D004R3720F-GP
1 2
PL4302
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
PL4302
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
1
2
PC4302
SCD22U25V3KX-GP
PC4302
SCD22U25V3KX-GP
1 2
PR4318
10KR2F-2-GP
PR4318
10KR2F-2-GP
1
2
C4301
SCD1U10V2KX-5GP
VENTURA
C4301
SCD1U10V2KX-5GP
VENTURA
1
2
PC4317
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4317
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
PG4304
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
PG4304
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
PT4301
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4301
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
1
2
PC4312
SCD22U25V3KX-GP
PC4312
SCD22U25V3KX-GP
1 2
PR4304
1R2F-GP
DY
PR4304
1R2F-GP
DY
1
2
PC4313
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4313
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2
PG4314INS43029
GAP-CLOSE-PWR
PG4314INS43029
GAP-CLOSE-PWR
1 2
PL4301
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
PL4301
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
1
2
PC4305
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4305
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2 3 4
5678
S S S
DDDD
G
PU4306 S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
QC
S S S
DDDD
G
PU4306 S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
QC
1 2
PR4306
10KR2F-2-GP
PR4306
10KR2F-2-GP
1 2
PG4320
GAP-CLOSE-PWR
PG4320
GAP-CLOSE-PWR
1
2
PC4309
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4309
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2 3 4
5678
S S S
DDDD
G
PU4309 S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
QC
S S S
DDDD
G
PU4309 S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
QC
1
2
PC4301 S
C
1
U
1
0
V
2
K
X
-
1
G
P
PC4301 S
C
1
U
1
0
V
2
K
X
-
1
G
P
1 2
PG4322
GAP-CLOSE-PWR
PG4322
GAP-CLOSE-PWR
1
2
R4347
3K3R2J -3-GP
DY
R4347
3K3R2J -3-GP
DY
1 2 3 4
5678
S S S G
DDDD
PU4305
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
S S S G
DDDD
PU4305
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
1 2
PC4319
SCD1U25V2KX-GP
VENTURA
PC4319
SCD1U25V2KX-GP
VENTURA
1 2
PR4307
3K65R2F-1-GP
PR4307
3K65R2F-1-GP
1
2
PT4304
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4304
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
1 2
PR4317
1R2F-GP
PR4317
1R2F-GP
1
2
PC4311
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4311
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2
PG4312
GAP-CLOSE-PWR
PG4312
GAP-CLOSE-PWR
1
2
PC4315
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4315
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
PC4318
SCD22U25V3KX-GP
PC4318
SCD22U25V3KX-GP
1 2
PR4305
1R2F-GP
PR4305
1R2F-GP
1 2 3 4
5678
S S S
DDDD
G
PU4303 S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
QC
S S S
DDDD
G
PU4303 S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
QC
1
2
PC4306
SC4D7U25V5KX-GP
PC4306
SC4D7U25V5KX-GP
1 2
PG4309
GAP-CLOSE-PWR
PG4309
GAP-CLOSE-PWR
1
2
PR4301
0R0402-PAD
PR4301
0R0402-PAD
1
2
PT4308
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4308
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
1 2 3 4
5678
S S S
DDDD
G
PU4307
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
S S S
DDDD
G
PU4307
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
1 2
PG4307
GAP-CLOSE-PWR
PG4307
GAP-CLOSE-PWR
1
2
PC4303
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4303
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2
PR4303
1R2F-GP
DY
PR4303
1R2F-GP
DY
1
2
PR4322
10R2F-L-GP
VENTURA
PR4322
10R2F-L-GP
VENTURA
1
2
PC4304
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4304
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2
PG4305
GAP-CLOSE-PWR
PG4305
GAP-CLOSE-PWR
1 2
PR4316
1R2F-GP
DY
PR4316
1R2F-GP
DY
1
2
R4345
3K3R2J -3-GP
VENTURA
R4345
3K3R2J -3-GP
VENTURA
1 2 3 4
5678
S S S G
DDDD
PU4308
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
S S S G
DDDD
PU4308
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
1 2
PR4312
10KR2F-2-GP
PR4312
10KR2F-2-GP
1
2
PC4314
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4314
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
PC4307
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
QC
PC4307
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
QC
1 2 3 4
5678
S S S
DDDD
G
PU4310
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
S S S
DDDD
G
PU4310
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
1
2
R4344
3K3R2J -3-GP
VENTURA
R4344
3K3R2J -3-GP
VENTURA
1
2
PC4310
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4310
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2
PG4324
GAP-CLOSE-PWR
PG4324
GAP-CLOSE-PWR
1 2 3 4
5678
S S S G
DDDD
PU4302
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
S S S G
DDDD
PU4302
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
1 2
PL4303
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
PL4303
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
1
2
PR4321
10R2F-L-GP
VENTURA
PR4321
10R2F-L-GP
VENTURA
1 2
PG4306
GAP-CLOSE-PWR
PG4306
GAP-CLOSE-PWR
1 2
PG4319
GAP-CLOSE-PWR
PG4319
GAP-CLOSE-PWR
1
2
PC4308
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4308
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
PT4302
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4302
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
B
O
O
T
1
PWM
2
G
N
D
3
LGATE
4
V
C
C
5
FCCM
6
PHASE
7
UGATE
8
G
N
D
9
PU4301
ISL6208CRZ-TGP-U
PU4301
ISL6208CRZ-TGP-U
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR_GFXCORE_BOOT_1
P
W
R
_
G
F
X
C
O
R
E
_
I
S
P
_
R
P
W
R
_
G
F
X
C
O
R
E
_
I
S
N
_
R
PR4405_2
PR4403_2
PC4408_1
VCC_GFXCORE
PWR_GFXCORE_DCBATOUT
PWR_GFXCORE_DCBATOUT
DCBATOUT_IMVP7
VCC_CORE VCC_CORE PWR_VCCCORE1_DCBATOUT PWR_VCCCORE2_DCBATOUT PWR_VCCCORE3_DCBATOUT VCC_GFXCORE PWR_GFXCORE_DCBATOUT
PHASEG 42
UGATEG 42
LGATEG 42
BOOTG 42
ISNG 42
ISPG 42
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
44 108
DN15ATI
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
44 108
DN15ATI
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
44 108
DN15ATI
VCC_GFXCORE
Iomax=33A
OCP>50A
84.03503.037
BSZ035N03MS
Id=18A,Qg=27~35nC,
Rdson=3.4~4.3mohm
68.R3610.20A
0.36uH, Idc=20A, Isat=25A
DCR=1.4 +/-7% mohm
80.3371V.A2L
330uF, 2.5V, B2
0624 Modify:
Removed PU4402
MOSFET.
0629 Modify
0629 Modify
0629 Modify
0705 Modify
EMI/ESD
0715 Modify:
Add EC4401~EC4410 for EMC NEO suggestion.
0719 Modify:
0720 Modify:
84.00172.037 baseon power teamBrian suggestionl.
84.00462.037
SIR462DP-T1-GE3-GP
Id=30A, Qg=8.8nC,
Rdson=7.9 mohm
0721 Modify:
Removed PC4401
0721 Modify:
Change PR4404 to 768ohm from 549ohm from
0809
0920 X01 Modify:
Change PC4410 to 0.01u from 0.022uF
from Brian updated.
A00 1224
1 2 3 4
5678
S S S G
DDDD
PU4401
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
S S S G
DDDD
PU4401
SIR462DP-T1-GE3-GP
84.00462.037
2nd = 84.08064.A37
1
2
E
C
4
4
0
5
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
4
0
5
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
PT4402
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4402
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
1 2
PR4408
10KR2F-2-GP
PR4408
10KR2F-2-GP
1 2
PR4402
549R2F-GP
DY
PR4402
549R2F-GP
DY 1
2
PC4409
SCD1U10V2KX-4GP
PC4409
SCD1U10V2KX-4GP
1 2
PL4401
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
PL4401
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
1
2
PC4407
SCD22U25V3KX-GP
PC4407
SCD22U25V3KX-GP
1 2
1 2
1
2
PC4410
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
PC4410
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
1
2
PC4406
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4406
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
PC4402
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4402
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
E
C
4
4
0
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
4
0
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1 2
1
2
PR4406
1
1
K
R
2
F
-
L
-
G
P
PR4406
1
1
K
R
2
F
-
L
-
G
P
1
2
PC4403
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4403
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
PC4404
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4404
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
E
C
4
4
0
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
4
0
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
PG4402
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
PG4402
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1 2
1
2
E
C
4
4
0
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
4
0
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
PT4403
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4403
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
1
2
PC4405
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4405
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2
1
2
E
C
4
4
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
4
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1 2
1 2
PR4401
1R3J -L1-GP
PR4401
1R3J -L1-GP
1 2
PR4404
768R2F-1-GP
PR4404
768R2F-1-GP
1
2
PG4401
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
PG4401
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
PT4401
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
PT4401
S
T
3
3
0
U
2
V
D
M
-
4
-
G
P
79.33719.20L
2nd = 77.C3371.13L
1 2
1
2
E
C
4
4
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
4
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
E
C
4
4
1
0
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
4
1
0
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
E
C
4
4
0
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
4
0
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
PR4407
7
K
5
R
2
F
-
1
-
G
P
PR4407
7
K
5
R
2
F
-
1
-
G
P
1 2 3 4
5678
S S S
DDDD
G
PU4404
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
S S S
DDDD
G
PU4404
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
1 2
PC4408
SCD068U16V2KX-GP
DY
PC4408
SCD068U16V2KX-GP
DY
1
2
PR4405
NTC-10K-27-GP
2nd = 69.60011.201
69.60013.131
PR4405
NTC-10K-27-GP
2nd = 69.60011.201
69.60013.131
1
2
PC4411
SCD068U16V2KX-GP
PC4411
SCD068U16V2KX-GP
1 2 3 4
5678
S S S
DDDD
G
PU4403
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
S S S
DDDD
G
PU4403
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
1 2
PR4403
1R2F-GP
PR4403
1R2F-GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VTT_SENSE_L
VSS_SENSE_L
PWR_1D05V_VFB
PWR_1D05V_CCM
PWR_1D05V_DRVL
PWR_1D05V_VBST_R
PWR_1D05V_DRVH
PWR_1D05V_VBST
PWR_1D05V_SW PWR_1D05V_VFB
PWR_1D05V_EN
PWR_1D05V_TRIP
P
W
R
_
1
D
0
5
V
_
S
N
U
B
VSS_SENSE_L
VTT_SENSE_L
1D05V_PWR
5V_S5
PWR_1D05V_DCBATOUT
DCBATOUT PWR_1D05V_DCBATOUT
1D05V_VTT 1D05V_PWR
3D3V_S0
VCCIO_SENSE 8
1.05VTT_PWRGD 37,48
VSSIO_SENSE 8
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TPS51218_+1.05V_VTT
A3
45 108
DN15ATI
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TPS51218_+1.05V_VTT
A3
45 108
DN15ATI
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TPS51218_+1.05V_VTT
A3
45 108
DN15ATI
Id=26.5A
Qg=40.6~61nC,
Rdson=2.6~3.2mohm
TPS51218 for 1D05V
Vout=0.704V*(R1+R2)/R2
15.6A<OCP< 18.3A
0617 Modify:
J osephChangePTC4502 to 330uF from390uF
baseonlayout placement status.
0721 Modify:
BrianAddPC4511 1uF.
ChangePTC4502 to 330u 79.33719.L01.
0719 Modify:
84.00172.037
BSZ115N03MSC
Id=20A, Qg=9.8nC,
Rdson=8.9 mohm
0719 Modify:
Reserved EC4502,EC4503 0.1uF near
PG4516(TOP) for EMC NEO suggestion.
0721 Modify:
Brian suggest change PU4503 to 84.00460.037.
Change PR4506 to 9.76K from 10K from
0721 Modify:
Change PR4504 to 2.2ohm from 0ohm from
0727 Modify:
PR4505,PR4508 change to 100ohm from 10ohm.
stuff PR4509,PR4510 0ohm from Brian updated.
0809
0909 X01 Modify:
Change PL4501 to 68.2R210.20C
from IND-D56UH-27-GP base on
Brian updated.
Mag. 2.20uH 10*11.5*4
DCR=6.7~7mohm
Idc=12A, Isat=27A
0901 X01 Modify:
Change PTC4502 to 79.3971V.30L from
79.33719.L01 from power team Brian updated.
0913 X01 Modify:
Add 2nd source 77.93971.02L on PTC4502
base on Brian updated 2nd soruce excel file.
0921
0920 X01 Modify:
Change PR4507 to 20K from 20.5K
from Brian updated.
1122 X02 Modify:
EMC Neo suggestion.
1123 X02 Modify:
Change PR4501 to 75K from 45.3K
for 1.05V OCP set to 20A from Brian.
A00 1224 A00 1224
A00 1224
1
2
E
C
4
5
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
5
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
PC4505
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4505
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2
1
2
PC4509
SC560P50V-GP
DY
PC4509
SC560P50V-GP
DY
1
2
PC4506
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4506
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
PR4506
9K76R2F-1-GP
PR4506
9K76R2F-1-GP
1 2
PC4502
SCD1U25V3KX-GP
PC4502
SCD1U25V3KX-GP
1 2
PR4502
0R0402-PAD-2-GP
PR4502
0R0402-PAD-2-GP
1 2 PR4510
0R0402-PAD
PR4510
0R0402-PAD
1 2
1
2
PR4503
470KR2F-GP
PR4503
470KR2F-GP
1 2
1 2
1
2
PTC4509
S
C
D
1
U
2
5
V
3
K
X
-
G
P
DY
PTC4509
S
C
D
1
U
2
5
V
3
K
X
-
G
P
DY
1 2
1
2
PR4505
100R2F-L1-GP-U
PR4505
100R2F-L1-GP-U
1 2
1 2
PR4501
75KR2F-GP
PR4501
75KR2F-GP
1 2
1
2
PR4514
2D2R5F-2-GP
DY
PR4514
2D2R5F-2-GP
DY
1 2
1 2
1 2
PR4504
2D2R3-1-U-GP
PR4504
2D2R3-1-U-GP
1
2
PC4511
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
DY
PC4511
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
DY
1 2 PR4509
0R0402-PAD
PR4509
0R0402-PAD
1 2 3 4
5678
S S S
DDDD
G
PU4503
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
S S S
DDDD
G
PU4503
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
1
2
E
C
4
5
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
5
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1 2
1 2
PR4516
10KR2J -3-GP
PR4516
10KR2J -3-GP
1
2
PC4507
S
C
D
1
U
2
5
V
3
K
X
-
G
P
PC4507
S
C
D
1
U
2
5
V
3
K
X
-
G
P
1
2
PC4504
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
PC4504
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1 2
1 2
1 2 3 4
5678
S S S G
DDDD
PU4502
SIR172DP-T1-GE3-GP
84.00172.037
2nd = 84.08065.037
S S S G
DDDD
PU4502
SIR172DP-T1-GE3-GP
84.00172.037
2nd = 84.08065.037
1
2
PC4501
S
C
1
K
P
5
0
V
2
K
X
-
1
G
P
DY
PC4501
S
C
1
K
P
5
0
V
2
K
X
-
1
G
P
DY
1
2
P
T
4
5
0
2
S
E
3
9
0
U
2
D
5
V
M
-
7
G
P
79.3971V.30L
2nd = 77.93971.02L
P
T
4
5
0
2
S
E
3
9
0
U
2
D
5
V
M
-
7
G
P
79.3971V.30L
2nd = 77.93971.02L
1
2
PC4508
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
PC4508
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
1
2
PC4510
SC1000P50V3J N-GP-U
DY
PC4510
SC1000P50V3J N-GP-U
DY
DRVL
6
V5IN
7
SW
8
DRVH
9
VBST
10
GND
11
PGOOD
1
TRIP
2
EN
3
VFB
4
CCM
5
PU4501
TPS51218DSCR-GP-U1
PU4501
TPS51218DSCR-GP-U1
1
2
PC4503
S
C
1
U
1
0
V
2
K
X
-
1
G
P
PC4503
S
C
1
U
1
0
V
2
K
X
-
1
G
P
1 2
1 2
1 2
1
2
PR4507
20KR2F-L-GP
PR4507
20KR2F-L-GP
1 2
PL4501
COIL-2D2UH-11-GP
68.2R210.20C
2nd = 68.2R21B.10I
PL4501
COIL-2D2UH-11-GP
68.2R210.20C
2nd = 68.2R21B.10I
1 2
1
2
PR4508
100R2F-L1-GP-U
PR4508
100R2F-L1-GP-U
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TPS51216_DRVL
P
W
R
_
1
D
5
V
_
V
D
D
Q
S
PWR_1D5V_VBST P
R
4
6
0
5
_
2
PWR_1D5V_DRVH
PWR_1D5V_MODE
PWR_1D5V_TRIP
PWR_1D5V_VTTREF
PWR_1D5V_VDDQS
PWR_1D5V_VREF
PWR_1D5V_REFIN
P
R
4
6
0
1
_
1
PWR_1D5V_SW
PWR_1D5V_EN
TPS51216_PHS_SET
PWR_1D5V_EN
PWR_1D5V_VTTREF
1D5V_PWR
+PWR_SRC_1D5V
+PWR_SRC_1D5V
+0D75V_DDR_P 0D75V_S0
DCBATOUT
+0D75V_DDR_P
5V_S5
3D3V_S0
1D5V_PWR 1D5V_S3
1D5V_PWR
DDR_VREF_S3
PM_SLP_S4# 19,27,75
0D75V_EN 37
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TPS51116_+1.5V_SUS
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TPS51116_+1.5V_SUS
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TPS51116_+1.5V_SUS
A3
<Variant Name>
State S3 S5 VDDR VTTREF VTT
S0
S3
S4/S5
Hi Hi
Hi Lo
Lo Lo
On
On
On
On
On
Off Off Off
Off(Hi-Z)
SSID = PWR.Plane.Regulator_1p5v0p75v
PR5003
200k ohm
300kHz
300kHz
400kHz
Tracking Discharge
Non-tracking Discharge
Frequency Discharge Mode
100k ohm
68k ohm
47k ohm 400kHz
MODE
22.71A<OCP< 26.84A
0630 modify
0630 Modify:
Change 1D5V power soluiton to TPS51216 from
TPS51116 follow power team Brian suggest.
0630 Modify:
ADD PC4604 1uF0603 on PWR_1D5V_VTTIN.
0630 Modify:
Change PC4610 to 0.22u 0402
from 0603 from Brian.
0702 Modify:
Add PR4611 0ohm 0603 pad
on PWR_1D5V_VTTREF.
0928
Change PR4606 to 4.02K from
240ohm for fine tune 1.5V output
Voltage.
0719 Modify:
84.00172.037
BSZ115N03MSC
Id=20A, Qg=9.8nC,
Rdson=8.9 mohm
0721 Modify:
Removed PR4615,PR4616 and connect
0D75V_EN to VTTEN directly.
0721 Modify:
Removed PR4615,PR4616 and connect
0D75V_EN to VTTEN directly.
0721 Modify:
un-stuff PC4617 from
0721 Modify:
Change PR4602 to 68K from 6.2K from
84.00460.037
SiR460DP-T1-GE3
Id=40A, Qg=16.8nC,
Rdson=4.7~6.1 mohm
0913 X01 Modify:
Add 2nd source 68.R681A.10Q on PL4601
base on Brian updated 2nd soruce excel file.
68.R6810.20G
Id=22~39A
DCR=2.4~2.7mohm
Size=10X11.5X4
0902 X01 Modify:
Change PTC4602 to 79.3971V.30L from
79.22719.20L sync with DQ15-NV
Add 2nd source 77.93971.02L on PTC4602.
79.3971V.30L
390uF, 2.5V,6.3X5.7
0920 X01 Modify:
Change PR4602 to 110K from 68K
from Brian updated.
A00 1224
A00 1224
1
2
P
R
4
6
0
6
4
K
0
2
R
2
F
-
G
P
P
R
4
6
0
6
4
K
0
2
R
2
F
-
G
P
1 2
PG4622
GAP-CLOSE-PWR
PG4622
GAP-CLOSE-PWR
1 2
PG4612
GAP-CLOSE-PWR
PG4612
GAP-CLOSE-PWR
1
2 P
C
4
6
1
5
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
P
C
4
6
1
5
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
1
2
P
R
4
6
0
2
1
1
0
K
R
2
F
-
G
P
P
R
4
6
0
2
1
1
0
K
R
2
F
-
G
P
1 2 PR4611
0R0603-PAD
PR4611
0R0603-PAD
1
2
PR4612
2D2R5F-2-GP
DY
PR4612
2D2R5F-2-GP
DY
1 2
PR4607
0R0402-PAD-2-GP
PR4607
0R0402-PAD-2-GP
1 2
PG4624
GAP-CLOSE-PWR
PG4624
GAP-CLOSE-PWR
1
2
P
C
4
6
0
1
S
C
1
U
1
0
V
3
K
X
-
3
G
P
P
C
4
6
0
1
S
C
1
U
1
0
V
3
K
X
-
3
G
P
1 2
PG4608
GAP-CLOSE-PWR
PG4608
GAP-CLOSE-PWR
1
2
PC4610
SCD22U6D3V2KX-1GP
PC4610
SCD22U6D3V2KX-1GP
1
2
P
G
4
6
0
7
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
P
G
4
6
0
7
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1
2
P
C
4
6
0
9
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
6
0
9
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1
2
PC4622
SC330P50V2KX-3GP
DY
PC4622
SC330P50V2KX-3GP
DY
1 2
PG4620
GAP-CLOSE-PWR
PG4620
GAP-CLOSE-PWR
1
2
P
C
4
6
0
2
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
P
C
4
6
0
2
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
1 2
PG4601
GAP-CLOSE-PWR
PG4601
GAP-CLOSE-PWR
1 2
PG4617
GAP-CLOSE-PWR
PG4617
GAP-CLOSE-PWR
1
2
P
C
4
6
1
2
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
6
1
2
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1
2
E
C
4
6
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
6
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1 2
PG4613
GAP-CLOSE-PWR
PG4613
GAP-CLOSE-PWR
1 2
PG4610
GAP-CLOSE-PWR
PG4610
GAP-CLOSE-PWR
1
2 P
C
4
6
1
7
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
DY
P
C
4
6
1
7
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
DY
1 2
PG4605
GAP-CLOSE-PWR
PG4605
GAP-CLOSE-PWR
1 2
PR4605
2D2R3J -2-GP
PR4605
2D2R3J -2-GP
1 2
PG4606
GAP-CLOSE-PWR
PG4606
GAP-CLOSE-PWR
1
2
PC4606
SCD1U10V2KX-5GP
DY
PC4606
SCD1U10V2KX-5GP
DY
1
2
P
C
4
6
1
1
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
P
C
4
6
1
1
S
C
1
0
U
2
5
V
6
K
X
-
1
G
P
1 2
PG4614
GAP-CLOSE-PWR
PG4614
GAP-CLOSE-PWR
1 2
PG4623
GAP-CLOSE-PWR
PG4623
GAP-CLOSE-PWR
1 2
PG4602
GAP-CLOSE-PWR
PG4602
GAP-CLOSE-PWR
1
2
P
C
4
6
0
3
S
C
D
1
U
2
5
V
3
K
X
-
G
P
P
C
4
6
0
3
S
C
D
1
U
2
5
V
3
K
X
-
G
P
1
2 P
C
4
6
1
6
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
P
C
4
6
1
6
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
1
2
PT4602
S
E
3
9
0
U
2
D
5
V
M
-
7
G
P
79.3971V.30L
2nd = 77.93971.02L
PT4602
S
E
3
9
0
U
2
D
5
V
M
-
7
G
P
79.3971V.30L
2nd = 77.93971.02L
1 2
PG4609
GAP-CLOSE-PWR
PG4609
GAP-CLOSE-PWR
1 2
PG4625
GAP-CLOSE-PWR
PG4625
GAP-CLOSE-PWR
1 2
PG4621
GAP-CLOSE-PWR
PG4621
GAP-CLOSE-PWR
1 2 3 4
5678
S S S
DDDD
G
PU4603
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
S S S
DDDD
G
PU4603
S
I
R
4
6
0
D
P
-
T
1
-
G
E
3
-
G
P
84.00460.037
2nd = 84.08059.037
1 2
PL4601
IND-D68UH-51-GP-U
68.R6810.20G
2nd = 68.R681A.10Q
PL4601
IND-D68UH-51-GP-U
68.R6810.20G
2nd = 68.R681A.10Q
1 2
PG4619
GAP-CLOSE-PWR
PG4619
GAP-CLOSE-PWR
1
2
PR4603
10KR2F-2-GP
PR4603
10KR2F-2-GP
1
2
P
R
4
6
0
1
4
7
K
R
2
F
-
G
P
P
R
4
6
0
1
4
7
K
R
2
F
-
G
P
VTT
3
VREF
6
VTTS
1
V5IN
12
VTTIN
2
PGND
10
PGOOD
20
VDDQS
9
MODE
19
VTTGND
4
VBST
15
DRVH
14
SW
13
DRVL
11
GND
7
GND
21
EN/PSV
16
VTTEN
17
REFIN
8
TRIP
18
VTTREF
5
PU4601
TPS51216RUKR-GP
74.51216.073
PU4601
TPS51216RUKR-GP
74.51216.073
1 2
PG4604
GAP-CLOSE-PWR
PG4604
GAP-CLOSE-PWR
1 2
PG4603
GAP-CLOSE-PWR
PG4603
GAP-CLOSE-PWR
1 2
PG4618
GAP-CLOSE-PWR
PG4618
GAP-CLOSE-PWR
1 2
PG4616
GAP-CLOSE-PWR
PG4616
GAP-CLOSE-PWR
1 2
PG4615
GAP-CLOSE-PWR
PG4615
GAP-CLOSE-PWR
1
2
PR4604
20KR2J -L2-GP
PR4604
20KR2J -L2-GP
1
2
P
C
4
6
1
4
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
P
C
4
6
1
4
S
C
4
D
7
U
2
5
V
5
K
X
-
G
P
1
2
P
R
4
6
0
8
2
0
0
K
R
2
F
-
L
-
G
P
P
R
4
6
0
8
2
0
0
K
R
2
F
-
L
-
G
P
1 2
PG4611
GAP-CLOSE-PWR
PG4611
GAP-CLOSE-PWR
1
2
P
C
4
6
2
1
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
P
C
4
6
2
1
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
1 2 3 4
5678
S S S G
DDDD
PU4602
SIR172DP-T1-GE3-GP
84.00172.037
2nd = 84.08065.037
S S S G
DDDD
PU4602
SIR172DP-T1-GE3-GP
84.00172.037
2nd = 84.08065.037
1
2
P
C
4
6
1
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
P
C
4
6
1
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
P
C
4
6
2
0
S
C
4
D
7
U
6
D
3
V
5
K
X
-
3
G
P
P
C
4
6
2
0
S
C
4
D
7
U
6
D
3
V
5
K
X
-
3
G
P
1 2
PC4619
SCD1U25V3KX-GP
PC4619
SCD1U25V3KX-GP
1
2
P
C
4
6
0
4
S
C
1
U
1
0
V
3
K
X
-
3
G
P
P
C
4
6
0
4
S
C
1
U
1
0
V
3
K
X
-
3
G
P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
51331_FB_1
51331_COMP
51331_PS
51331_EN
51331_SW
PR4709_1
51331_VBST 51331_VBST_1
PC4712_1
PG4710_1
51331_FB_1 51331_FB
3D3V_S5
1D8V_RUN_PWR 1D8V_S0
3D3V_S5
1D8V_RUN_PWR
3D3V_S0
PM_SLP_S3# 19,27,36,37,75
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TPS51311 for 1D8V_S0
A3
47 108
DN15ATI Whistler
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
47 108
DN15ATI Whistler
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
47 108
DN15ATI Whistler
SSID = PWR.Plane.Regulator_1D8V_S0
TPS51311 PWM for 1D8V_S0
+1.8V_RUN
Design current = 2.7985A
0629 Modify
0629 Modify
0902 X01 Modify:
Change PR4712 to 10K from 0ohm and stuff
PC4717 for fine tune 1D8V_S0 ramp up sequence.
0920 X01 Modify:
stuff PC4714 22uF
from Brian updated.
1
2
PR4711
10KR2F-2-GP
PR4711
10KR2F-2-GP
1
2
PR4701
20KR2F-L-GP
PR4701
20KR2F-L-GP
1 2
PR4709
5K9R2F-GP
PR4709
5K9R2F-GP
1
2
PC4717
SC1U6D3V2KX-GP
PC4717
SC1U6D3V2KX-GP
1
2
PC4711
SCD1U25V3KX-GP
PC4711
SCD1U25V3KX-GP
1 2
PG4706
GAP-CLOSE-PWR
PG4706
GAP-CLOSE-PWR
VBST
4
VIN
13
SW#5
5
MODE
8
PGOOD
3
AGND
11
RES
2
FB
10
COMP
9
VDD
12
EN
1
SW#6
6
SW#7
7
VIN
14
PGND
15
PGND
16
PGND
17
PU4702
TPS51311RGTR-GP
74.51311.073
PU4702
TPS51311RGTR-GP
74.51311.073
1
2
PC4712
SC2200P50V2KX-2GP
PC4712
SC2200P50V2KX-2GP
1
2
P
C
4
7
1
6
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
P
C
4
7
1
6
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
1
2
P
G
4
7
1
0
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
P
G
4
7
1
0
G
A
P
-
C
L
O
S
E
-
P
W
R
-
3
-
G
P
1 2 PR4710
0R0603-PAD
PR4710
0R0603-PAD
1 2
PC4701 SC100P50V2J N-3GP PC4701 SC100P50V2J N-3GP
1
2
PR4713
40D2R2F-GP
PR4713
40D2R2F-GP
1
2
P
C
4
7
1
5
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
P
C
4
7
1
5
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
1 2
PG4707
GAP-CLOSE-PWR
PG4707
GAP-CLOSE-PWR
1 2
PG4702
GAP-CLOSE-PWR
PG4702
GAP-CLOSE-PWR
1 2
PC4710
SC2200P50V2KX-2GP
PC4710
SC2200P50V2KX-2GP
1 2
PR4712
10KR2J -3-GP
PR4712
10KR2J -3-GP
1 2
PG4709
GAP-CLOSE-PWR
PG4709
GAP-CLOSE-PWR
1
2
PC4713
SCD1U25V3KX-GP
PC4713
SCD1U25V3KX-GP
1
2
PC4709
SCD1U25V3KX-GP
PC4709
SCD1U25V3KX-GP
1
2
PR4708
57K6R2F-GP
DY
PR4708
57K6R2F-GP
DY
1 2
PL4701
IND-2D2UH-46-GP-U
68.2R210.20B
2nd = 68.2R21B.10J
PL4701
IND-2D2UH-46-GP-U
68.2R210.20B
2nd = 68.2R21B.10J 1
2
P
C
4
7
1
4
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
P
C
4
7
1
4
S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
1 2
PG4708
GAP-CLOSE-PWR
PG4708
GAP-CLOSE-PWR
1
2
P
C
4
7
1
8
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
P
C
4
7
1
8
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
1 2
PR4714 100KR2J -1-GP
DY
PR4714 100KR2J -1-GP
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR_VCCSA_SLEW
PWR_VCCSA_BST_R
P
W
R
_
V
C
C
S
A
_
S
N
U
B
PWR_VCCSA_BST
PWR_VCCSA_V5DRV
PWR_VCCSA_FB
PWR_VCCSA_VIN
APL5916_EN
PWR_VCCSA_EN
P
W
R
_
V
C
C
S
A
_
C
O
M
P
_
1
P
W
R
_
V
C
C
S
A
_
V
R
E
F
P
Q
4
8
0
1
_
D
P
W
R
_
V
C
C
S
A
_
C
O
M
P
PQ4801_G
PQ4801_5
PWR_VCCSA_SW
PWR_VCCSA_VOUT
PWR_VCCSA_VID1 P
W
R
_
V
C
C
S
A
_
P
G
O
O
D
PWR_VCCSA_VID0
3D3V_S0
VCCSA_PWR
0D85V_S0
1D05V_VTT
5V_S5
5V_S5
5V_S5
0D85V_S0
3D3V_S0
3D3V_S0
0D85V_S0
0D85V_S0
D85V_PWRGD 42
1.05VTT_PWRGD 37,45
1.05VTT_PWRGD 37,45
VCCSA_SEL 9
H_FC_C22 9
D85V_PWRGD 42
VCCSA_SEL 9
VCCUSA_SENSE 9
Title
Date: Sheet of
Wistron Corporation
QUEEN&NIRVANA 15 A00
TPS51461_VCCSA
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
TPS51461_VCCSA
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
TPS51461_VCCSA
A2
<Core Design>
0.725V
0.675V
VCCSA VID0
H
VID1
L
L
H
L 0.8V
0.9V
H
H
L
6.6A<OCP< 7.8A
TPS51461 for VCCSA
Iomax=6A
OCP>9A
VCCSA=0.85V
Vout=0.8*(1+R1/R2)
APL5916 for VCCSA
VCCSA_PWR VCCSA_SEL
H
0.9V
0.8V
L
R2
R1
1112 X02 Modify:
set TPS51461 PWM solution dummy field for
VCCSA_PWM and APL5916 LDO solution dummy
field for VCCSA_LDO. defualt stuff VCCSA_LDO at
ST stage.
20100614 V1.1
for CRB board
1118 X02 Modify:
Change PTC4801 to 100u(77.21071.07L)
from 150u from power team Brian updated.
1122 X02 Modify:
Updated VCCSA_LDO circuit from Power
team Brian updated.
68.R4710.10M
Id=17.5~26A
DCR=4~4.2mohm
Size=6.5X6.9X3
1112 X02 Modify:
CO-LAY APL5916 related circuit for VCCSA LDO
solution.
1 2
PG4810
GAP-CLOSE-PWR
VCCSA_LDO
PG4810
GAP-CLOSE-PWR
VCCSA_LDO
1
2
P
C
4
8
0
3
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
VCCSA_PWM
P
C
4
8
0
3
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
VCCSA_PWM
1
2
PC4819
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
VCCSA_LDO
PC4819
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
VCCSA_LDO
1 2
PR4812
1KR2F-3-GP
DY
PR4812
1KR2F-3-GP
DY
1
2
P
C
4
8
0
5
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
VCCSA_PWM
P
C
4
8
0
5
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
VCCSA_PWM
123
4 5 6
PQ4801
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
DY
PQ4801
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
DY
1 2
PG4811
GAP-CLOSE-PWR
VCCSA_LDO
PG4811
GAP-CLOSE-PWR
VCCSA_LDO
1 2
PR4811
100R2F-L1-GP-U
VCCSA_PWM
PR4811
100R2F-L1-GP-U
VCCSA_PWM
1
2
PC4820
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
VCCSA_LDO
PC4820
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
VCCSA_LDO
1
2
PR4816
80K6R2F-GP
DY
PR4816
80K6R2F-GP
DY
1
2
PC4812
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
VCCSA_PWM
PC4812
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
VCCSA_PWM
1 2
PG4803
GAP-CLOSE-PWR
VCCSA_LDO
PG4803
GAP-CLOSE-PWR
VCCSA_LDO
1
2
E
C
4
8
0
1
S
C
D
1
U
5
0
V
3
K
X
-G
P
DY
E
C
4
8
0
1
S
C
D
1
U
5
0
V
3
K
X
-G
P
DY
1
2
PC4821
SC1U6D3V2KX-GP
DY
PC4821
SC1U6D3V2KX-GP
DY
1
2
PR4818
10KR2F-2-GP
DY
PR4818
10KR2F-2-GP
DY
1
2
PR4809
4K7R2J -2-GP
VCCSA_PWM
PR4809
4K7R2J -2-GP
VCCSA_PWM
1
2
PC4807
S
C
D
1
U
2
5
V
3
K
X
-G
P
VCCSA_PWM
PC4807
S
C
D
1
U
2
5
V
3
K
X
-G
P
VCCSA_PWM
1 2
PG4804
GAP-CLOSE-PWR
VCCSA_LDO
PG4804
GAP-CLOSE-PWR
VCCSA_LDO
1 2
PG4812
GAP-CLOSE-PWR
VCCSA_LDO
PG4812
GAP-CLOSE-PWR
VCCSA_LDO
1
2
PC4802
SCD22U10V2KX-1GP
VCCSA_PWM
PC4802
SCD22U10V2KX-1GP
VCCSA_PWM
1
2
PR4806
1R2F-GP
VCCSA_PWM
PR4806
1R2F-GP
VCCSA_PWM
1
2
PC4822
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
VCCSA_LDO
PC4822
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
VCCSA_LDO
1
2
PC4808
S
C
D
1
U
2
5
V
3
K
X
-G
P
DY
PC4808
S
C
D
1
U
2
5
V
3
K
X
-G
P
DY
1 2 PR4801
0R0402-PAD
VCCSA_PWM
PR4801
0R0402-PAD
VCCSA_PWM
1 2
PG4806
GAP-CLOSE-PWR
VCCSA_LDO
PG4806
GAP-CLOSE-PWR
VCCSA_LDO
1 2
PL4801
IND-D47UH-22-GP
68.R4710.10M
2nd = 68.R4710.10V
VCCSA_PWM
PL4801
IND-D47UH-22-GP
68.R4710.10M
2nd = 68.R4710.10V
VCCSA_PWM
1
2
PC4824
SC1U6D3V2KX-GP
VCCSA_LDO
PC4824
SC1U6D3V2KX-GP
VCCSA_LDO
1
2
PC4817
SC3300P50V3KX-1GP
VCCSA_PWM
PC4817
SC3300P50V3KX-1GP
VCCSA_PWM
1
2
P
C
4
8
0
6
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
VCCSA_PWM
P
C
4
8
0
6
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
VCCSA_PWM
1 2
PG4805
GAP-CLOSE-PWR
VCCSA_LDO
PG4805
GAP-CLOSE-PWR
VCCSA_LDO
1 2
PG4802
GAP-CLOSE-PWR
VCCSA_LDO
PG4802
GAP-CLOSE-PWR
VCCSA_LDO
1 2 PR4810
0R0402-PAD
VCCSA_PWM
PR4810
0R0402-PAD
VCCSA_PWM
1
2
PC4813
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
VCCSA_PWM
PC4813
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
VCCSA_PWM
1
2
PC4826
SCD1U10V2KX-4GP
DY
PC4826
SCD1U10V2KX-4GP
DY
1
2
PR4814
10KR2F-2-GP
VCCSA_LDO
PR4814
10KR2F-2-GP
VCCSA_LDO
1
2
PC4815
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
VCCSA_PWM
PC4815
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
VCCSA_PWM
1
2
PR4815
80K6R2F-GP
VCCSA_LDO
PR4815
80K6R2F-GP
VCCSA_LDO
1 2
PG4808
GAP-CLOSE-PWR
VCCSA_LDO
PG4808
GAP-CLOSE-PWR
VCCSA_LDO
1 2 PR4804
0R0402-PAD
VCCSA_PWM
PR4804
0R0402-PAD
VCCSA_PWM
1
2
PC4825
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
VCCSA_LDO
PC4825
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
VCCSA_LDO
1 2
PR4817 0R2J -2-GP
VCCSA_LDO
PR4817 0R2J -2-GP
VCCSA_LDO
1
2
PC4814 S
C
1
U
1
0
V
2
K
X
-1
G
P
VCCSA_PWM
PC4814 S
C
1
U
1
0
V
2
K
X
-1
G
P
VCCSA_PWM
1 2
PC4811
SCD1U25V3KX-GP
VCCSA_PWM
PC4811
SCD1U25V3KX-GP
VCCSA_PWM
1
2P
C
4
8
1
6
S
C
2
D
2
U
1
0
V
3
K
X
-1
G
P
VCCSA_PWM
P
C
4
8
1
6
S
C
2
D
2
U
1
0
V
3
K
X
-1
G
P
VCCSA_PWM
1 2
PG4807
GAP-CLOSE-PWR
VCCSA_LDO
PG4807
GAP-CLOSE-PWR
VCCSA_LDO
1 2
PG4801
GAP-CLOSE-PWR
VCCSA_LDO
PG4801
GAP-CLOSE-PWR
VCCSA_LDO
1
2
PTC4801
S
T
1
0
0
U
6
D
3
V
B
M
-7
G
P
DY
PTC4801
S
T
1
0
0
U
6
D
3
V
B
M
-7
G
P
DY
1
2
PC4810
SC1U6D3V2KX-GP
DY
PC4810
SC1U6D3V2KX-GP
DY
1
2
PC4801
SCD01U50V2KX-1GP
VCCSA_PWM
PC4801
SCD01U50V2KX-1GP
VCCSA_PWM
G
N
D
1
V
R
E
F
2
C
O
M
P
3
S
L
E
W
4
V
O
U
T
5
M
O
D
E
6
SW#7
7
SW#8
8
SW#9
9
SW#10
10
SW#11
11
BST
12
E
N
1
3
V
ID
0
1
4
V
ID
1
1
5
P
G
O
O
D
1
6
V
5
F
IL
T
1
7
V
5
D
R
V
1
8
PGND
19
PGND
20
PGND
21
VIN
22
VIN
23
VIN
24
GND
25
PU4801
TPS51461RGER-GP
74.51461.043
PCB Footprint = QFN24-G2D25H40
VCCSA_PWM
PU4801
TPS51461RGER-GP
74.51461.043
PCB Footprint = QFN24-G2D25H40
VCCSA_PWM
1 2
PG4809
GAP-CLOSE-PWR
VCCSA_LDO
PG4809
GAP-CLOSE-PWR
VCCSA_LDO
1
2
PR4819
4K7R2J -2-GP
VCCSA_LDO
PR4819
4K7R2J -2-GP
VCCSA_LDO
1 2 PR4807
0R0603-PAD
VCCSA_PWM
PR4807
0R0603-PAD
VCCSA_PWM
1
2
P
C
4
8
0
4
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
VCCSA_PWM
P
C
4
8
0
4
S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
VCCSA_PWM
G
N
D
1
FB
2
VOUT
3
VOUT
4
VIN
5
V
C
N
T
L
6
POK
7
EN
8
VIN
9
PU4802
APL5916KAI-TRL-GP
74.05916.031
VCCSA_LDO
PU4802
APL5916KAI-TRL-GP
74.05916.031
VCCSA_LDO
1
2
PR4802
4K99R2F-L-GP
VCCSA_PWM
PR4802
4K99R2F-L-GP
VCCSA_PWM
1
2
PR4803
2D2R5F-2-GP
DY
PR4803
2D2R5F-2-GP
DY
1 2 PR4805
0R0402-PAD
VCCSA_PWM
PR4805
0R0402-PAD
VCCSA_PWM
1
2
PC4809
SC560P50V-GP
DY
PC4809
SC560P50V-GP
DY
1 2
PR4813
10KR2J -3-GP
DY
PR4813
10KR2J -3-GP
DY
1 2 PR4808
0R0402-PAD
VCCSA_PWM
PR4808
0R0402-PAD
VCCSA_PWM
1
2
PC4818
S
C
1
0
0
P
5
0
V
2
J
N
-3
G
P
VCCSA_LDO
PC4818
S
C
1
0
0
P
5
0
V
2
J
N
-3
G
P
VCCSA_LDO
LCDVDD_EN
USB_CAMERA#
USB_CAMERA
LCD_TST_C
LCD_BRIGHTNESS
LVDSA_DATA0#
LVDSA_DATA0
LVDSA_CLK
LCD_TST_C
LCD_BRIGHTNESS
LVDSA_CLK#
LVDSA_DATA2#
LVDSA_DATA1#
LVDSA_DATA1
LVDSA_DATA2
BLON_OUT_C
USB_PN0_C
USB_PP0_C
USB_CAMERA
USB_CAMERA#
USB_PP0_C
USB_PN0_C
LCD_TST_C
BLON_OUT_C
LCDVDD 3D3V_S0
DCBATOUT_LCD DCBATOUT
3D3V_CAMERA_S0 3D3V_S0
DCBATOUT_LCD
LCDVDD
3D3V_S0
3D3V_CAMERA_S0
3D3V_S0
5V_S0 TPNL_5V
LCD_TST_EN 27
LVDS_VDD_EN 17
LVDSA_DATA1 17
LVDSA_DATA1# 17
LVDSA_DATA2# 17
LVDSA_DATA2 17
L_BKLT_CTRL 17
LVDSA_CLK# 17
LVDSA_CLK 17
LVDSA_DATA0 17
LVDSA_DATA0# 17
LVDS_DDC_DATA_R 17
LVDS_DDC_CLK_R 17
LVDS_DDC_CLK_R 17
LVDS_DDC_DATA_R 17
AUD_DMIC_CLK 29
AUD_DMIC_IN0 29
USB_PP12 18
USB_PN12 18
USB_PP0 18
USB_PN0 18
LCD_TST 27
BLON_OUT 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
LCD Connector
A3
49 108
DN15ATI Whistler
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
LCD Connector
A3
49 108
DN15ATI Whistler
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
LCD Connector
A3
49 108
DN15ATI Whistler
SSID = VIDEO
LCD POWER for ROSA
Layout 40 mil
0902 X01 Modify:
Add 2nd source 74.09724.09F on
U4901 sync with Annie.
SSID = VIDEO
0909 X01 Modify:
Change LCD1 to 20.F1816.030 for 30pin
Re-assign LCD1 pin define base on Roy updated
cable pin define list.
Camera Power
LVDS CONNECTOR
For EMI request
Close to LVDS connector
0913 X01 Modify:
Reserved EC4910~EC4915 on LVDS signal
for EMC suggestion.
TOUCH PANEL CLOSED TO LVDS CONN LCD1
0916 X01 Modify:
Change TPNL1 to 20.F1621.004 from
Double updated EMN&DXF.
0917 X01 Modify:
Add 2nd source 20.F1561.004;3rd source
20.F1686.004 on TPNL1 from updated
connector list.
1122 X02 Modify:
stuff C4908 0.1uF from
EMC Neo suggestion.
1122 X02 Modify:
Change TR4902 CM choke to 69.10103.041
and un-stuff R4908,R4909 from EMC Neo Suggestion.
1122 X02 Modify:
Change RN4901 to 100ohm 4p from 8p
for improve layout place.
1122 X02 Modify:
EMC Neo suggestion.
1122 X02 Modify:
Swap TR4901 pin4,3 and pin2,1 each other
base on Connie swap report.
Change R4911,R4912 to 0603 from 0402.
A00 1229
A00 1230
A00 0103 not co-lay
EN
1
GND
2
OUT
3
IN#4
4
IN#5
5
U4901
G5285T11U-GP
74.05285.07F
2nd = 74.09724.09F
U4901
G5285T11U-GP
74.05285.07F
2nd = 74.09724.09F
1
2
C
4
9
0
5
S
C
D
1
U
5
0
V
3
K
X
-
G
P
C
4
9
0
5
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
3
D4901
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
D4901
BAT54CPT-GP
2ND = 83.00054.Q81
83.R2003.E81
1
2
C4902
SC1U6D3V2KX-GP
C4902
SC1U6D3V2KX-GP
1
2
R
4
9
0
5
4
9
K
9
R
2
F
-
L
-
G
P
R
4
9
0
5
4
9
K
9
R
2
F
-
L
-
G
P
1
2
EC4914
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
EC4914
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
1 2
3 4
TR4901
FILTER-4P-6-GP
69.10103.041
TPNL
2nd = 69.10084.071
TR4901
FILTER-4P-6-GP
69.10103.041
TPNL
2nd = 69.10084.071
1
2 3
4
RN4901
SRN100J -3-GP
RN4901
SRN100J -3-GP
1
2
C
4
9
1
0
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
TPNL
C
4
9
1
0
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
TPNL
1 2 F4902
0R0603-PAD
F4902
0R0603-PAD
1 2 R4907
100KR2J -1-GP
R4907
100KR2J -1-GP
1 TP4904TPAD14-GP TP4904TPAD14-GP
1
2
C
4
9
0
4
S
C
1
K
P
5
0
V
2
K
X
-
1
G
P
C
4
9
0
4
S
C
1
K
P
5
0
V
2
K
X
-
1
G
P
1
2
3
4
5
6
TPNL1
ACES-CON4-17-GP-U
20.F1621.004
TPNL
2nd = 20.F1561.004
3rd = 20.F1686.004
TPNL1
ACES-CON4-17-GP-U
20.F1621.004
TPNL
2nd = 20.F1561.004
3rd = 20.F1686.004
1
2
C
4
9
1
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
TPNL
C
4
9
1
1
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
TPNL
12
3 4
RN9403
SRN2K2J -1-GP
RN9403
SRN2K2J -1-GP
1
2
C4903
SC10U6D3V5KX-1GP
C4903
SC10U6D3V5KX-1GP
1 2 R4902 33R2J -2-GP R4902 33R2J -2-GP
1
2
EC4901
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
EC4901
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
1
2
C
4
9
0
1
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C
4
9
0
1
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
EC4911
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
EC4911
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
1
2
E
C
4
9
0
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
9
0
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
E
C
4
9
0
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
9
0
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
EC4902
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
EC4902
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
1
2
C4908 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
C4908 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
1
2
EC4913
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
EC4913
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
1 2
R4904
0R0402-PAD-2-GP
TPNL
R4904
0R0402-PAD-2-GP
TPNL
1
2
EC4915
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
EC4915
S
C
3
3
P
5
0
V
2
J
N
-
3
G
P
DY
1
2
C4907 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
C4907 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
1
2E
C
4
9
0
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
4
9
0
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1 2
F4901
POLYSW-1D1A24V-GP-U
69.50007.A31
2nd = 69.50007.A41
F4901
POLYSW-1D1A24V-GP-U
69.50007.A31
2nd = 69.50007.A41
1
2E
C
4
9
0
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
4
9
0
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
EC4903
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
EC4903
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
EC4910
S
C
5
D
6
P
5
0
V
2
C
N
-
1
G
P
DY
EC4910
S
C
5
D
6
P
5
0
V
2
C
N
-
1
G
P
DY
1 2
3 4
TR4902
FILTER-4P-6-GP
69.10103.041
2nd = 69.10084.071
TR4902
FILTER-4P-6-GP
69.10103.041
2nd = 69.10084.071
1
2
EC4904
S
C
5
D
6
P
5
0
V
2
C
N
-
1
G
PDY
EC4904
S
C
5
D
6
P
5
0
V
2
C
N
-
1
G
PDY
1
2
EC4905
S
C
5
D
6
P
5
0
V
2
C
N
-
1
G
PDY
EC4905
S
C
5
D
6
P
5
0
V
2
C
N
-
1
G
PDY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NP1
NP2
LCD1
PS-CON30-GP
20.F1816.030
2nd = 20.F1860.030
LCD1
PS-CON30-GP
20.F1816.030
2nd = 20.F1860.030
1
2
EC4912
S
C
5
D
6
P
5
0
V
2
C
N
-
1
G
P
DY
EC4912
S
C
5
D
6
P
5
0
V
2
C
N
-
1
G
P
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CRT Connector
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CRT Connector
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CRT Connector
A3
<Variant Name>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI_CLK
HDMI_DATA0
HDMI_DATA0#
DDC_DATA_HDMI
DDC_CLK_HDMI
HDMI_DATA1
HDMI_DATA2
HDMI_DATA2#
HDMI_DATA1#
HDMI_CLK#
HDMI_PLL_GND
HDMI_PLL_GND
HDMI_DATA2_R_C
HDMI_DATA2_R_C#
HDMI_DATA1_R_C
HDMI_DATA1_R_C#
HDMI_DATA0_R_C
HDMI_DATA0_R_C#
HDMI_CLK_R_C
HDMI_CLK_R_C#
GPU_HDMI_DATA
DDC_DATA_HDMI
DDC_CLK_HDMI GPU_HDMI_CLK
HDMI_OE#
HPD_HDMI_CON
HDMI_DATA0_R_C_CON
HDMI_DATA0_R_C#_CON HDMI_DATA0_R_C#
HDMI_DATA0_R_C
HDMI_CLK_R_C_CON
HDMI_CLK_R_C#_CON HDMI_CLK_R_C#
HDMI_CLK_R_C
HDMI_DATA2_R_C_CON
HDMI_DATA2_R_C
HDMI_DATA1_R_C_CON
HDMI_DATA1_R_C
HDMI_DATA0_R_C_CON
HDMI_CLK_R_C#_CON
HDMI_DATA1_R_C#_CON
HDMI_DATA2_R_C_CON
HDMI_DATA2_R_C#_CON
HDMI_DATA0_R_C#_CON
HDMI_CLK_R_C_CON
HDMI_DATA1_R_C_CON
DDC_DATA_HDMI
HDMI_HPD_E
HDMI_HPD_B
H
P
D
_
H
D
M
I
_
C
O
N
3D3V_VGA_S0
5V_CRT_S0_R
3D3V_VGA_S0
3D3V_S0
5V_CRT_S0_R
3D3V_VGA_S0 5V_S0
3D3V_S0
3D3V_S0
HDMI_CLK# 85
HDMI_CLK 85
HDMI_DATA0# 85
HDMI_DATA0 85
HDMI_DATA1# 85
HDMI_DATA1 85
HDMI_DATA2# 85
HDMI_DATA2 85
GPU_HDMI_DATA 85
GPU_HDMI_CLK 85
HDMI_IN# 27
GPU_HDMI_HPD 85
PEX_RST# 83,85,86
HDMI_IN# 27
HDMI_HPD_DET 85
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
HDMI Level Shifter/Connector
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Variant Name>
SSID = VIDEO
Close to HDMI Connector
HDMI Level Shifter & CONNECTOR
HDMI CONN
Routing Guidelines:
CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm).
The total delay on CTRLDATA should be longer than CTRLCLK.
0629 Modify:
Utilize Q5104 2N7002 instead of PCA9509 Level
shifter base on Intel DG recommand on HDMI DDC.
0630 SWAP RN5106
0630 SWAP RN5107
0707 Modify:
Add Q5101,R5109,R5127 for HDMI_IN# to KBC.
0714 Modify:
Stuff R5109 20K PH to 3D3V_S0.
A00 1223 HDMI leakage
0716 Modify:
Add F5101 1A FUSE for DELL suggesiton.
0720 Modify:
Stuff F5101 FUSE from DELL suggestion.
0721 Modify:
Change HDMI1 part number to 22.10296.271 from
22.10296.211 base on ME latest EMN and DXF.
0726 For NV
0806
0810
0831 X01 Modify:
22.10296.271 base on ME Double updated.
0910 X01 Modify:
22.10296.311 base on ME Double updated.
0913 X01 Modify:
Add R5101~R5108and reserved TR5101~TR5104
on all of HDMI differential pair for EMC suggestion.
0923 SWAP
0927
0629 Modify
X02 10.28
X02 1110
A00
A00 1228
A00 1229
1
2
R5112
10KR2J -3-GP
R5112
10KR2J -3-GP
1
2
C5102
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C5102
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
GS
D
Q5103
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q5103
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
22
23
20
HDMI1
SKT-HDMI23-2-GP-U1
22.10296.331
2nd = 22.10296.311
HDMI1
SKT-HDMI23-2-GP-U1
22.10296.331
2nd = 22.10296.311
1
2
R5113
100KR2J -1-GP
DY
R5113
100KR2J -1-GP
DY
1
2
R5110
1MR2F-GP
R5110
1MR2F-GP
GS
D
Q5101
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
Q5101
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
1
2
3 4
5
6
Q5104
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
Q5104
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
1 2
34
RN5116
SRN2K2J -1-GP
Optimus
RN5116
SRN2K2J -1-GP
Optimus
1 2 R5104
0R0402-PAD-2-GP
R5104
0R0402-PAD-2-GP
1 2
R5101
0R0402-PAD-2-GP
R5101
0R0402-PAD-2-GP
3
1
2
Q5102
PMBS3904-1-GP
84.03904.L06
2nd = 84.03904.P11
3rd = 84.03904.T11
DY
Q5102
PMBS3904-1-GP
84.03904.L06
2nd = 84.03904.P11
3rd = 84.03904.T11
DY
1 2
R5105
0R0402-PAD-2-GP
R5105
0R0402-PAD-2-GP
1234
5 6 7 8
RN5106
SRN470J -5-GP
RN5106
SRN470J -5-GP
1
AFTP5101 TPAD14-GP AFTP5101 TPAD14-GP
1 2
R5107
0R0402-PAD-2-GP
R5107
0R0402-PAD-2-GP
1 2
R5125 0R2F-N1-GP
DY
R5125 0R2F-N1-GP
DY
1 2
34
RN5101
SRN2K2J -1-GP
RN5101
SRN2K2J -1-GP
1 2
R5103
0R0402-PAD-2-GP
R5103
0R0402-PAD-2-GP
1 2
R5102
0R0402-PAD-2-GP
R5102
0R0402-PAD-2-GP
1234
5 6 7 8
RN5107
SRN470J -5-GP
RN5107
SRN470J -5-GP
123
4 5 6
Q5105
2N7002KDW-GP
Q5105
2N7002KDW-GP
1 2
R5116 1KR2F-L-GP R5116 1KR2F-L-GP
1
2
R5109
20KR2J -L2-GP
DY
R5109
20KR2J -L2-GP
DY
1
2
R5123
0R2J -2-GP DY
R5123
0R2J -2-GP DY
1 2
R5106
0R0402-PAD-2-GP
R5106
0R0402-PAD-2-GP
1
2
R5114
0R0402-PAD-2-GP
R5114
0R0402-PAD-2-GP
1 2
R5127 0R0402-PAD R5127 0R0402-PAD
1
2
R5115
0R2J -2-GP
DY
R5115
0R2J -2-GP
DY
1 2 R5108
0R0402-PAD-2-GP
R5108
0R0402-PAD-2-GP
1 2
R5111 1KR2F-L-GP R5111 1KR2F-L-GP
1
2
R5117
10KR2J -3-GP
DY
R5117
10KR2J -3-GP
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
LVDS_Switch
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
LVDS_Switch
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
LVDS_Switch
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
ITP/Fan Connector
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
ITP/Fan Connector
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
ITP/Fan Connector
A3
<Core Design>
SSID = User.Interface
(Blanking)
ODD_PWR_5V
HDD1_20
HDD1_21
HDD1_22
SATA_ODD_PWRGT
SATA_ODD_DA#
SATA_RX4-_C
SATA_RX4+_C
SATA_TXN4_C
SATA_TXP4_C
SATA_TXN0_C
SATA_TXP0_C
SATA_RXP0_C
SATA_RXN0_C
SATA_ODD_DA#_C
SATA_ODD_DA#_C
SATA_ODD_PWRGT SATA_ODD_DA#
O
D
D
_
P
W
R
G
T
#
3D3V_S0
5V_S0
5V_S0
ODD_PWR_5V
ODD_PWR_5V
3D3V_S0
5V_S0
3D3V_S0
SATA_ODD_PRSNT# 22
FFS_INT2 79
SATA_ODD_PWRGT 22
SATA_TXP4 21
SATA_RXN4 21
SATA_TXN4 21
SATA_RXP4 21
SATA_TXN0 21
SATA_TXP0 21
SATA_RXP0 21
SATA_RXN0 21
SATA_ODD_DA# 18
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
HDD/ODD
A3
56 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
HDD/ODD
A3
56 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
HDD/ODD
A3
56 108
<Variant Name>
SATA HDD Connector
SSID = SATA
ODD Connector
SATA Zero Power ODD
Current ||m|t
Act|ve n|gh
typ =>2A
100 mil
0810
0901 Add 2nd.
0906 Add 3rd.
0614 Modify:
Change ODD1 connector part number to
22.10300.421 base on ME EMN and DXF.
0707 Modify:
Change ODD1 connector part number to
62.10065.E01 base on latest EMN and DXF.
SUPPORT ZERO SATA ODD
20100625 V1.2
0629 Modify:
Move R5601 PH 10K to RN5601 PH.
0629 Modify:
Move R5601 PH 10K to RN5601 PH.
20100625 V1.2
SATA_RX- and SATA_RX+ Trace
Length match within 20 mil
Mars:
Exchange ODD and ESATA differential pair each other.
0629 Modify:
Move All of 0.01uF cap closed to ODD
0629 Modify:
Move All of 0.01uF cap closed to HDD
20100625 V1.2
0707 Modify:
Change Q5601 to DUAL 2N7002 for isolate MD/DA signal between PCH and ODD.
When the drive is powered on, the FET to the MD/DA pin drive is OFF.
When the drive is powered off, the FET to the MD/DA pin is ON
1123 X02 Modify:
stuff EC5601 180pF from RF
fine tune result.
A00 delete 62.10065.121
1
2
R5605
100KR2J -1-GP
R5605
100KR2J -1-GP
1
2
C5601
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C5601
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
C5605
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
C5605
S
C
1
0
U
1
0
V
5
Z
Y
-
1
G
P
1
2
C5604
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C5604
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NP1
NP2
HDD1
TYCO-CON22-1-GP-U2
20.F1011.022
2nd = 62.10065.081
HDD1
TYCO-CON22-1-GP-U2
20.F1011.022
2nd = 62.10065.081
GND
1
IN#2
2
IN#3
3
EN/EN#
4
OC#
5
OUT#6
6
OUT#7
7
OUT#8
8
U5601
G547F1P81U-GP
2ND = 74.02191.079
74.00547.C79
U5601
G547F1P81U-GP
2ND = 74.02191.079
74.00547.C79
1
2
R5604
10KR2J -3-GP
DY
R5604
10KR2J -3-GP
DY
1
2
C5609
SC10U6D3V5KX-1GP
C5609
SC10U6D3V5KX-1GP
P1
P2
P3
P4
P5
P6
8
9
NP1
NP2
S1
S2
S3
S4
S5
S6
S7
ODD1
SKT-SATA7P-6P-40-GP-U
62.10065.E01
3rd = 62.10065.D61
2nd = 62.10065.D01
ODD1
SKT-SATA7P-6P-40-GP-U
62.10065.E01
3rd = 62.10065.D61
2nd = 62.10065.D01
123
4 5 6
Q5601
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
Q5601
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
1
2
C5610
SC10U6D3V5KX-1GP
C5610
SC10U6D3V5KX-1GP
1
2 3
4
RN5601
SRN10KJ -5-GP
RN5601
SRN10KJ -5-GP
1
2
C5606
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C5606
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1 2 R5602 0R2J -2-GP
DY
R5602 0R2J -2-GP
DY
1
2
EC5601
SC180P50V2J N-1GP
EC5601
SC180P50V2J N-1GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB_PP8_C
USB_PN8_C
5V_USB1_S3
USB_PN8_C
USB_PP8_C
SATA_TXN5_C
SATA_TXP5_C
SATA_RXN5_C
SATA_RXP5_C
USB_PP8_R
USB_PN8_R
CB
ESATA1_D1 USB_PP8_C
USB_PN8_C
USB_PP8_R
USB_PN8_R
5V_S5
5V_USB1_S3
USBCHARGER_CB0 27
SATA_TXN5 21
SATA_TXP5 21
SATA_RXN5 21
SATA_RXP5 21
USB_PP8 18
USB_PN8 18
USBDET_CON# 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
ESATA
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
ESATA
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
ESATA
A3
<Core Design>
ESATA CONN
SSID = ESATA
close to ESATA1
Switch Control Bit:
CB=0 (AM):auto detection charger identification active.
CB=1 (PM):connect DP/DM to TDP/TDM.
0803 Modify:
Change U5702 USB CHARGER circuit to
PI5USB14550 from MAX14556.
0629 Modify:
Move All of 0.01uF cap closed to ESATA
0706 Modify:
Change ESATA1 part number to 22.10321.F71
base on latest EMN and DXF.
0713 Modify:
Add USBDET_CON# on ESATA1 pin15 for
USB temporary detect solution ESATA1 CONN
should be searched for detect type connector.
0719 Modify:
ME Double provide temporary foxconn ESATA conn
22.10290.141 for SSI stage function test.
E-SATA USB 2.0 Combo
CE/H=-0.16/2.83mm with detect function
0629 Modify
USB CHARGER
S0 S1
0 0
0
0
1
1 1
1
Auto
D+/- connects to Y+/-
0806
0809
0809
0831
1122 X02 Modify:
Change TR5701CM choke to 69.10103.041
1123 X02 Modify:
Change R5718,R5719 to 0603 from 0402.
A00 1229
1
AFTP5715
AFTE14P-GP
AFTP5715
AFTE14P-GP
1
AFTP5716
AFTE14P-GP
AFTP5716
AFTE14P-GP
VBUS
1
D-
2
D+
3
GND
4
GND
5
A+
6
A-
7
GND
8
B-
9
B+
10
GND
11
GND
14
GND
15
GND
16
GND
17
DT1
12
DT2
13
ESATA1
SKT-ESATA-USB-11P-6-GP-U
2nd = 22.10339.261
22.10321.W11
ESATA1
SKT-ESATA-USB-11P-6-GP-U
2nd = 22.10339.261
22.10321.W11
S0
1
D+
2
D-
3
GND
4
A+
5
A-
6
VDD
7
Y-
8
Y+
9
S1
10
GND
11
U5702
PI5USB14550AZEE-GP
U5702
PI5USB14550AZEE-GP
1
2
C5701
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
C5701
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
1 2
3 4
TR5701
FILTER-4P-6-GP
69.10103.041
2nd = 69.10084.071
TR5701
FILTER-4P-6-GP
69.10103.041
2nd = 69.10084.071
1
AFTP5717
AFTE14P-GP
AFTP5717
AFTE14P-GP
1 2
R5721
0R0402-PAD
R5721
0R0402-PAD
1
AFTP5703
AFTE14P-GP
AFTP5703
AFTE14P-GP
1 2
R5722 0R0402-PAD R5722 0R0402-PAD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AUD_SPK_L+_C
AUD_SPK_R-_C
AUD_SPK_L-_C
AUD_SPK_R+_C
AUD_SPK_L+_C
AUD_SPK_L-_C
AUD_SPK_R-_C
AUD_SPK_R+_C
AUD_SPK_L- 29
AUD_SPK_L+ 29
AUD_SPK_R- 29
AUD_SPK_R+ 29
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
SPEAKER CONN
A4
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
SPEAKER CONN
A4
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
SPEAKER CONN
A4
<Core Design>
SSID = AUDIO
0913 X01 Modify:
Change SPK1 to 20.F0772.004 from
20.F1647.004 from Double updated.
0914 X01 Modify:
Re-assign SPK1 pin define base on
Roy updated excel file for 20.F0772.004
8peaker Connector
1110 X02 Modify:
Add 2nd 20.F1804.004 on SPK1 from
1122 X02 Modify:
stuff EC5801~EC5804 470pF from EMC
Neo suggestion.
A00
1 2
R5803 0R0402-PAD-2-GP R5803 0R0402-PAD-2-GP
1 2
R5801 0R0402-PAD-2-GP R5801 0R0402-PAD-2-GP
1
2
E
C
5
8
0
1
S
C
4
7
0
P
5
0
V
-
2
-
G
P
E
C
5
8
0
1
S
C
4
7
0
P
5
0
V
-
2
-
G
P
1 2
R5804 0R0402-PAD-2-GP R5804 0R0402-PAD-2-GP
4
3
2
1
5
6
SPK1
ACES-CON4-7-GP-U
20.F0772.004
2nd = 20.F1804.004
SPK1
ACES-CON4-7-GP-U
20.F0772.004
2nd = 20.F1804.004
1
2
E
C
5
8
0
2
S
C
4
7
0
P
5
0
V
-
2
-
G
P
E
C
5
8
0
2
S
C
4
7
0
P
5
0
V
-
2
-
G
P
1
1
2
E
C
5
8
0
3
S
C
4
7
0
P
5
0
V
-
2
-
G
P
E
C
5
8
0
3
S
C
4
7
0
P
5
0
V
-
2
-
G
P
1
1
2
E
C
5
8
0
4
S
C
4
7
0
P
5
0
V
-
2
-
G
P
E
C
5
8
0
4
S
C
4
7
0
P
5
0
V
-
2
-
G
P
1
1 2
R5802 0R0402-PAD-2-GP R5802 0R0402-PAD-2-GP
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RTC_PWR
+RTC_VCC
SPI_SO
SPI_WP#
SPI_HOLD_0#
RTC_PWR RTC_PWR RTC_PWR RTC_PWR
3D3V_S5
3D3V_S5
3D3V_S5
RTC_AUX_S5
+RTC_VCC
3D3V_AUX_S5
SPI_CLK_R 21,27
SPI_SO_R 21,27
SPI_SI_R 21,27
SPI_CS0#_R 21,27
RTC_DET# 22
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Flash/RTC
A3
60 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Flash/RTC
A3
60 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Flash/RTC
A3
60 108
<Variant Name>
SSID = Flash.ROM
Width=20mils
SSID = RBATT
SPI FLASH ROM (4M byte) for PCH
0615 Modify:
Change RTC1 connector part number to 62.70001.051
base on ME EMN and DXF.
0629 Modify:
Change U6001 part number to 72.25320.C01
base on Sourcer provide recommand ROM list.
0701 Modify:
Change RN6001 4.7K to R6003,R6004,R6005
4.7K 0402 for layout routing.
VccRTC is now connected to VccDSW3_3
through the Schottky diode instead of the 3.3V Sus well.
Notes:
The total SPI interface signal between EC and PCH
cant not exceed 6500mil. The mismatch between
SPI signal must be within 500mil
0917 X01 Modify:
EC6001 change to 10p from 4.7p and
default stuff from Neo suggestion.
X02
X02
1111 X02 Modify:
Add Q6002,R6007 fo FACTORY RTC detect function
X02 1111
A00 1224 Update RTC1
1
2
EC6002
SC4D7P50V2CN-1GP
DY
EC6002
SC4D7P50V2CN-1GP
DY
1
2
C6003
SC1U6D3V2KX-GP
C6003
SC1U6D3V2KX-GP
1 2
R6006
100R2J -2-GP
DY
R6006
100R2J -2-GP
DY
1
2
R6007
10MR2J -L-GP
R6007
10MR2J -L-GP
1
2
R6004
4K7R2J -2-GP
R6004
4K7R2J -2-GP
1
2
R6003
4K7R2J -2-GP
R6003
4K7R2J -2-GP
G
S
D
Q6002
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
Q6002
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
1 2 R6002
1KR2J -1-GP
R6002
1KR2J -1-GP
1
2
EC6001
SC10P50V2J N-4GP
DY
EC6001
SC10P50V2J N-4GP
DY
2
1
3
Q6001
CH715FPT-GP
2nd = 83.00040.E81
83.R0304.B81
Q6001
CH715FPT-GP
2nd = 83.00040.E81
83.R0304.B81
1
2
C6002
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C6002
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1 2
R6001 33R2J -2-GP R6001 33R2J -2-GP
CS#
1
DO
2
WP#
3
VSS
4
DI
5
CLK
6
HOLD#
7
VCC
8
U6001
W25Q32BVSSIG-1-GP
2nd = 72.25320.C01
3rd = 72.25P32.C01
72.25Q32.A01
U6001
W25Q32BVSSIG-1-GP
2nd = 72.25320.C01
3rd = 72.25P32.C01
72.25Q32.A01
1
2
EC6003
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P
DY
EC6003
S
C
4
D
7
P
5
0
V
2
C
N
-
1
G
P
DY
1
2
R6005
4K7R2J -2-GP
R6005
4K7R2J -2-GP
1
2
C6001
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
C6001
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
DY
PWR
1
GND
2
NP1
NP1
NP2
NP2
RTC1
BAT-330DG02PSS0301CE-GP-U
62.70001.051
2nd = 62.70014.001
3rd = 62.70001.061
RTC1
BAT-330DG02PSS0301CE-GP-U
62.70001.051
2nd = 62.70014.001
3rd = 62.70001.061
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5V_USB1_S3
5V_S5
5V_USB2_S3
USB_OC#8_9 18
USB_PWR_EN# 27
USB_OC#0_1 18
USB2_CRT_ON# 22
Title
Date: Sheet of
Wistron Corporation
USB Power SW
<Core Design>
Title
Date: Sheet of
Wistron Corporation
USB Power SW
<Core Design>
Title
Date: Sheet of
Wistron Corporation
USB Power SW
<Core Design>
Support 2A
at least 80 mil
at least 80 mil
at least 160 mil
CRT Board and COMBO USB Power
SSID = USB
1122 X02 Modify:
Change U6101 to dual USB power switch from single
for Layout limitation and placement.
1123 X02 Modify:
Change U6101 1st(74.02182.071);2nd(74.00546.A7D)
;3rd(74.02062.079) from Sourcer Harrison suggestion.
1123 X02 Modify:
Removed C6105,C6103.
A00 1221
1
2
C6101 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C6101 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
C6103 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
C6103 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
1
2
TC6101
ST100U6D3VAM-3-GP
80.10715.B1L
2nd = 77.C1071.20L
TC6101
ST100U6D3VAM-3-GP
80.10715.B1L
2nd = 77.C1071.20L
1
2
C6104
SC1U10V2KX-1GP
C6104
SC1U10V2KX-1GP
1
2
C6102
SC1U10V2KX-1GP
C6102
SC1U10V2KX-1GP
GND
1
IN
2
EN1#
3
EN2#
4
FLG2
5
OUT2
6
OUT1
7
FLG1
8
U6101
AP2182SG-13-GP
3rd = 74.02062.079
2nd = 74.00546.A7D
74.02182.071
U6101
AP2182SG-13-GP
3rd = 74.02062.079
2nd = 74.00546.A7D
74.02182.071
1
2
T
C
6
1
0
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
T
C
6
1
0
2
S
C
1
0
U
6
D
3
V
5
K
X
-
1
G
P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BT_ACT
3D3V_S0
WLAN_ACT
BLUETOOTH_EN
USB_PP3
USB_PN3
BLUETOOTH_GPIO5
BDC_ON
BT_LED
USB_PP3
BLUETOOTH_DET#
WLAN_ACT
BLUETOOTH_EN
BT_ACT
USB_PN3
BLUETOOTH_GPIO3
BT_ACT
WLAN_ACT
BLUETOOTH_EN
BT_LED
WLAN_WWAN_LED#
3D3V_S0
USB_PP3 18
USB_PN3 18
BLUETOOTH_EN 27,82
WLAN_ACT 82
BT_ACT 82
WLAN_WWAN_LED# 68,82
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Bluetooth
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Bluetooth
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Bluetooth
A3
<Core Design>
Bluetooth Module conn.
x01 change tolerant 20091118
0709 Modify:
PM confirmed there is no stand-alone BT module,
so DY BT1 connector, add BT enable signal
and 5V_S5 power option on WLAN connector pin 51.
0712 Modify:
Stuff BT relatek component to verify function.
0721 Modify:
Change C6301 to 78.22510.5BL follow
common parts data base. 0722 Modify:
Add Q6301 and combine BT_LED to
WLAN_WWAN_LED#.
A00 1224 Update BT1
1
2
E
C
6
3
0
1
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
6
3
0
1
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1 AFTP6311 AFTP6311
1
2
R
6
3
0
1
1
0
0
K
R
2
J
-
1
-
G
P
DY
R
6
3
0
1
1
0
0
K
R
2
J
-
1
-
G
P
DY
1
2
C6301
SC2D2U6D3V3MX-1-GP
DY
C6301
SC2D2U6D3V3MX-1-GP
DY
1 AFTP6306 AFTP6306
1 AFTP6312 AFTP6312
1 AFTP6301 AFTP6301
1 AFTP6307 AFTP6307
1 AFTP6309 AFTP6309
1 AFTP6308 AFTP6308
1 2
R6303
0R2J -2-GP
DY
R6303
0R2J -2-GP
DY
1 AFTP6310 AFTP6310
1 AFTP6313 AFTP6313
1
2
R
6
3
0
2
1
0
K
R
2
J
-
3
-
G
P
DY
R
6
3
0
2
1
0
K
R
2
J
-
3
-
G
P
DY
1 AFTP6302 AFTP6302
1 AFTP6304 AFTP6304
1 AFTP6305 AFTP6305
G
S
D
Q6301
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
Q6301
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
15
NP1
2
4
6
8
10
12
14
NP2
16
1
3
5
7
9
11
13
BT1
HRS-CONN14D-GP-U1
DY
2nd = 20.F1500.014
20.F0987.014
BT1
HRS-CONN14D-GP-U1
DY
2nd = 20.F1500.014
20.F0987.014
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Biometric_USBPP
Biometric_USBPN
3D3V_S0
Biometric_USBPP
Biometric_USBPN
Biometric_USBPP
Biometric_USBPN
3D3V_S0
USB_PP2 18
USB_PN2 18
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
RESERVED
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
RESERVED
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
RESERVED
A3
<Core Design>
Finger Printer Connector
0615 Modify:
ChangeFP1 connector part number to 20.K0320.004
baseon ME EMN and DXF.
0630 Modify:
ChangeFP1 connector part number to 20.K0320.006
baseon ME EMN and DXF.
0707 Modify:
Reassign Figer print pin definebaseon EXCEL FILE.
0713 Modify:
Reassign Figer print pin definebaseon EXCEL FILE.
Removed FP_DET#on FP1.
0707 Modify:
Add FP_DET# signal on FP1 pin1.
0715 Modify:
Add FP_DET# signal on FP1 pin1.
0806 Swap pin.
0810 Change to 4 pin.
0827 Change to 6 pin.
0917 X01 Modify:
stuff TR6401 and un-stuff R6403,R6404
at X01 stage from EMC Neo suggestion.
1123 X02 Modify:
Add C6402 0.1uF,C6403 180pF and stuff C6401
47pF from RF fine tune result.
A00 1229
1
2
E
C
6
4
0
2
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
E
C
6
4
0
2
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
1
2
E
C
6
4
0
3
S
C
1
8
0
P
5
0
V
2
J
N
-
1
G
P
E
C
6
4
0
3
S
C
1
8
0
P
5
0
V
2
J
N
-
1
G
P
1
2
3
4
5
6
7
8
FP1
ACES-CON6-13-GP
20.K0320.006
DN15
2nd = 20.K0382.006
FP1
ACES-CON6-13-GP
20.K0320.006
DN15
2nd = 20.K0382.006
1 AFTP42
DY
AFTP42
DY
1
2
E
C
6
4
0
1
S
C
4
7
P
5
0
V
2
J
N
-
3
G
P
E
C
6
4
0
1
S
C
4
7
P
5
0
V
2
J
N
-
3
G
P
1 AFTP43
DY
AFTP43
DY
1 AFTP44
DY
AFTP44
DY
1 2 R6403
0R2J -2-GP
DN15
R6403
0R2J -2-GP
DN15
1 2
R6404
0R2J -2-GP
DN15
R6404
0R2J -2-GP
DN15
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
RESERVED
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
RESERVED
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
RESERVED
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KBC_PWRBTN#_C
POWER_SW_LED_C
POWER_SW_LED_B
POWER_SW_LED_C
POWER_SW_LED_B
FPOWER_LED_A LED_PWR
PWRLED#_C
HDD_LED_A
SATA_LED#_C
SATA_LED_R
WHITE_LED_BAT BAT_WHITE
BAT_AMBER AMBER_LED_BAT
AMBER_LED_BAT#
WHITE_LED_BAT#
Q6804_B
TP_LOCK_LED_R TP_LOCK_LED_A
Q6806_B
WLAN_LED_A WLAN_LED_R
KBC_PWRBTN#_C
POWER_SW_LED_C
POWER_SW_LED_B
KBC_PWRBTN#_C
POWER_SW_LED_B
POWER_SW_LED_C
5V_S5
5V_S5
5V_S5
5V_S0
5V_S0
5V_S0
TP_LOCK_LED# 27
KBC_PWRBTN# 27
PWRLED# 27
SATA_LED# 21
BATT_WHITE_LED# 27
CHG_AMBER_LED# 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
LED Bard/Power Button
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Core Design>
FRONT POWER LED
TPLOCK LED
WLAN_LED
SATA HDD LED(White)
NEED confirm with ME actual
HDD_LED part number.
FPOWER_LED part number.
Battery LED2(WHITE_LED)
Battery LED1(AMBER_LED)
WHITE
ORANGE
Need change to LOW actived from KBC GPIO
0629 Modify
0629 Modify
0702 Modify:
0706 Modify:
WLAN__LED# rename to WLAN_WWAN_LED#.
0706 Modify:
Add PWRBTN2 for DQ15,PWRBTN1 FOR DN15.
0706 Modify:
Change FPOWER_LED part number to
83.01221.R70 base on latest EMN and DXF.
0706 Modify:
Change HDD_LED part number to
0706 Modify:
Change TP_LOCK_LED part number to
83.19217.J70 base on latest EMN and DXF.
0706 Modify:
Change TP_LOCK_LED1 part number to
83.19217.J70 base on latest EMN and DXF.
0706 Modify:
Change WLAN_LED part number to
0715 Modify:
Removed PWR_BTN_LED# control circuit
base on Dell feedback.
0923 X01 Modify:
Add 2nd source 83.00110.J70 on FPOWERLED1
HDDLED1,WLANLED1 from Sourcer Anya suggestion.
0923 X01 Modify:
Add 2nd source 83.00110.J70 on FPOWERLED1
HDDLED1,WLANLED1 from Sourcer Anya suggestion.
0923 X01 Modify:
Add 2nd source 83.00327.D70 on
CHARGERLED1from Sourcer Anya suggestion.
0923 X01 Modify:
Add 2nd source 83.00190.Z70 on TPLOCKLED1
TPLOCKLED2 from Sourcer Anya suggestion.
X02 1116
A00 20110103
A00 delete 83.01108.070
A00 1223
A00 1223
A00 1223
A00 1223
A00 1223
A00 20110103
A00 1223
A00 1229 delete Liteon for package
A00 20110103
1 AFTP6803 AFTP6803
E
B
C
R 1
R 2
Q6805
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
R 1
R 2
Q6805
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
A K
TPLED2
LED-Y-57-GP
83.01921.P70
2nd = 83.00190.S7A
DN15
TPLED2
LED-Y-57-GP
83.01921.P70
2nd = 83.00190.S7A
DN15
1 2
R6813
390R2J -1-GP
R6813
390R2J -1-GP
1 2
3
A K
WLED1
LED-W-27-GP
83.01221.R70
2nd = 83.00110.R70
A K
WLED1
LED-W-27-GP
83.01221.R70
2nd = 83.00110.R70
1
2
3
4
5
6
PWRBT1
ACES-CON4-10-GP-U
20.K0320.004
DQ15
2nd = 20.K0382.004
PWRBT1
ACES-CON4-10-GP-U
20.K0320.004
DQ15
2nd = 20.K0382.004
1
2 3
4
RN6802
SRN15KJ -3-GP
RN6802
SRN15KJ -3-GP
E
B
C
R 1
R 2
Q6808
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
R 1
R 2
Q6808
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
1 2
R6808 1KR2J -1-GP R6808 1KR2J -1-GP
1
2E
C
6
8
0
3
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
6
8
0
3
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
A K
TPLED1
LED-Y-57-GP
83.01921.P70
2nd = 83.00190.S7A
DQ15
TPLED1
LED-Y-57-GP
83.01921.P70
2nd = 83.00190.S7A
DQ15
1 2
R6811 1KR2J -1-GP R6811 1KR2J -1-GP
1 2
R6806 390R2J -1-GP R6806 390R2J -1-GP
E
B
C
R 1
R 2
Q6801
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
R 1
R 2
Q6801
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
1
2E
C
6
8
0
7
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
6
8
0
7
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1 2
R6801 390R2J -1-GP R6801 390R2J -1-GP
1 2
R6803 390R2J -1-GP R6803 390R2J -1-GP
1 2
R6802 100R2J -2-GP R6802 100R2J -2-GP
1
2 3
4
RN6801
SRN15KJ -3-GP
RN6801
SRN15KJ -3-GP
E
B
C
R 1
R 2
Q6807
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
R 1
R 2
Q6807
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
E
B
C
R 1
R 2
Q6804
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
R 1
R 2
Q6804
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
1
2
3
4
5
6
PWRBT2
ACES-CON4-10-GP-U
20.K0320.004
DN15
2nd = 20.K0382.004
PWRBT2
ACES-CON4-10-GP-U
20.K0320.004
DN15
2nd = 20.K0382.004
1 2
3
A K
FPLED1
LED-W-27-GP
83.01221.R70
2nd = 83.00110.R70
A K
FPLED1
LED-W-27-GP
83.01221.R70
2nd = 83.00110.R70
1 AFTP6802 AFTP6802
1
2 E
C
6
8
1
1
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
6
8
1
1
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2
3
W H I T E
O R A N G E
+
+
-
CHLED1
LED-OW-8-GP
83.01222.X80
2nd = 83.00327.D70
W H I T E
O R A N G E
+
+
-
CHLED1
LED-OW-8-GP
83.01222.X80
2nd = 83.00327.D70
1 AFTP6801 AFTP6801
1 2 R6814
15KR2J -1-GP
R6814
15KR2J -1-GP
1
2
EC6801
SC220P50V2KX-3GP
DY
EC6801
SC220P50V2KX-3GP
DY
1 2 R6807
15KR2J -1-GP
R6807
15KR2J -1-GP
1 2
R6812 390R2J -1-GP R6812 390R2J -1-GP
1
2E
C
6
8
1
0
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
6
8
1
0
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
B
C
R 1
R 2
Q6806
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
R 1
R 2
Q6806
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
1 2
R6815
390R2J -1-GP
R6815
390R2J -1-GP
1
2
EC6809
SC220P50V2KX-3GP
DY
EC6809
SC220P50V2KX-3GP
DY
1 2
3
A K
HDLED1
LED-W-27-GP
83.01221.R70
2nd = 83.00110.R70
A K
HDLED1
LED-W-27-GP
83.01221.R70
2nd = 83.00110.R70
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KCOL13
KCOL4
KROW7
KCOL10
KCOL3
KROW5
KCOL12
KCOL5
KCOL11
KCOL8
KROW2
KCOL0
KROW0
KCOL9
KCOL6
KROW4
KCOL2
KROW3
KCOL15
KCOL14
KCOL7
TPDATA
TP_VDD
TPCLK
KROW6
KCOL1
KROW1
KCOL16
CAP_LED_R
CAP_LED_R CAP_LED_Q
Q6902_B
KB_LED_DET_C
K
B
_
B
L
_
C
T
R
L
#
+5V_KB_BL
KB_BL_CTRL#
KB_LED_DET_C
TP_VDD
CAP_LED_R
TP_VDD
5V_S0 TP_VDD
3D3V_S0
CAP_LED_R
5V_S5
+5V_KB_BL 5V_S0
KROW[0..7] 27
KCOL[0..16] 27
KB_DET# 21
TPCLK 27
TPDATA 27
CAP_LED 27
KB_LED_BL_DET 18
KB_BL_CTRL 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Key Board/Touch Pad
A3
69 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Key Board/Touch Pad
A3
69 108
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Key Board/Touch Pad
A3
69 108
<Core Design>
SSID = Touch.Pad
Internal KeyBoard Connector
TouchPad Connector
SSID = KBC
KB Backlight Connector
0624 Modify:
Removed TP LOCKED CONTROL combin
with KEYBOARD Function KEY.
0630 Modify:
Change TPAD1 part number to 20.K0320.006
base on ME updated EMN&DXF.
0712 Modify:
Change TPAD1 part number to 20.K0320.004
from 20.K0320.006.
0630 Modify:
Change KB1 part number to 20.K0565.030
base on ME updated EMN and DXF.
CAP_LED:(Default HIGH actived)
Connect to KB driving internal LED directly.(MAX 25mA)
0707 Modify:
Change TPAD1 pin define to follow
TOUCH PAD DATASHEET.
0713 Modify:
Change TPAD1 pin define to follow
TOUCH PAD DATASHEET.
0713 Modify:
Change TPAD1 power source to 3D3V_S0 from
5V_S0 base on DELL latest spec A02.
0715 Modify:
Add R6908,R6909 for TPAD1 co-lay power option.
0721 Modify:
SWAP RN6901
0915 X01 Modify:
un-stuff R6907 and stuff R6905,Q6902,R6906
for 5V drive CAP LED.
CAP LED CONTROL
High Active from KBC GPIO.
0624 Modify:
Change KB Backlight control all of related
circuit component column to VOSTRO from DY.
0708 Modify:
R6904 change to 51K 0402 from 100ohm for
KB_LED_BL_DET to PCH GPIO.
updated KBLIT1 pin define base on KB DATA SHEET.
MAX 260mA
0901 X01 Modify:
Change KBLIT1 to 20.K0320.004 from
20.K0218.004 base on ME updated X01 DXF&EMN.
Re-assign KBLIT1 pin define sync with DQ15_NV.
0914 X01 Modify:
Add 2nd source 20.K0382.004 on KBLIT1
base on updated connector list.
0923 X01 Modify:
Change KBLIT1 part number to 20.K0589.004
and re-assign pin define base on Roy updated.
0927
X02 1116
1
AFTP51 AFTP51
1 2
R6908
0R2J -2-GP
DY
R6908
0R2J -2-GP
DY
1
2
C6903
SC33P50V2J N-3GP
DY
C6903
SC33P50V2J N-3GP
DY
1
2
R6903
1
0
0
K
R
2
J
-
1
-
G
P
DN15
R6903
1
0
0
K
R
2
J
-
1
-
G
P
DN15
1
AFTP49 AFTP49
G
D
S
Q6901
P8503BMG-GP
DN15
84.P8503.031
2nd = 84.03404.C31
Q6901
P8503BMG-GP
DN15
84.P8503.031
2nd = 84.03404.C31
1
2
C6901
SCD1U10V2KX-5GP
C6901
SCD1U10V2KX-5GP
1
AFTP75 AFTP75
1
AFTP52 AFTP52
1 2
R6904
51KR2J -1-GP
DN15
R6904
51KR2J -1-GP
DN15
1 2
R6909
0R2J -2-GP
R6909
0R2J -2-GP
1
AFTP57 AFTP57
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
KB1
J AE-CON30-7-GP
20.K0565.030
2nd = 20.K0592.030
KB1
J AE-CON30-7-GP
20.K0565.030
2nd = 20.K0592.030
1
2
3
4
5
6
TPAD1
ACES-CON4-10-GP-U
20.K0320.004
2nd = 20.K0382.004
TPAD1
ACES-CON4-10-GP-U
20.K0320.004
2nd = 20.K0382.004
1
AFTP50 AFTP50
1 2
F6901
FUSE-D5A6V-2-GP
DY
F6901
FUSE-D5A6V-2-GP
DY
12
3 4
RN6901
SRN10KJ -5-GP
RN6901
SRN10KJ -5-GP
1
AFTP47 AFTP47
1 AFTP45 AFTP45
1
AFTP65 AFTP65
1
AFTP54 AFTP54
1
AFTP68 AFTP68
1
AFTP60 AFTP60
1
AFTP72 AFTP72
1
2
C6905
SCD1U10V2KX-5GP
DN15
C6905
SCD1U10V2KX-5GP
DN15
1
AFTP59 AFTP59
1
AFTP48 AFTP48
1
2
3
4
6
5
KBLIT1
ACES-CON4-34-GP
20.K0589.004
DN15
2nd = 20.K0613.004
KBLIT1
ACES-CON4-34-GP
20.K0589.004
DN15
2nd = 20.K0613.004
1
AFTP82 AFTP82
1
AFTP73 AFTP73
1
AFTP46 AFTP46
1 2
R6906 1KR2J -1-GP R6906 1KR2J -1-GP
1 2 R6902
0R2J -2-GP
DN15
R6902
0R2J -2-GP
DN15
1
AFTP71 AFTP71
1
AFTP62 AFTP62
1
2
C6902
SC33P50V2J N-3GP
DY
C6902
SC33P50V2J N-3GP
DY
E
B
C
R 1
R 2
Q6902
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
R 1
R 2
Q6902
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
1
AFTP56 AFTP56
1 2
R6907 100R2J -2-GP
DY
R6907 100R2J -2-GP
DY
1
AFTP61 AFTP61
1
AFTP66 AFTP66
1
AFTP58 AFTP58
1
AFTP77 AFTP77
1
AFTP53 AFTP53
1
2
R6901
100KR2J -1-GP
DN15
R6901
100KR2J -1-GP
DN15
1
AFTP67 AFTP67
1
AFTP70 AFTP70
1
AFTP78 AFTP78
1
AFTP55 AFTP55
1
AFTP64 AFTP64
1 2
R6905
15KR2J -1-GP
R6905
15KR2J -1-GP
1
AFTP74 AFTP74
1
2
C6906 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C6906 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
AFTP63 AFTP63
1
AFTP76 AFTP76
1
AFTP69 AFTP69
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LID_CLOSE#
3D3V_S5
3D3V_S5
LID_CLOSE# 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Hall Sensor
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Hall Sensor
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Hall Sensor
A3
<Core Design>
0729
0804 swap
1110 X02 Modify:
Add 2nd 20.F0962.010 on HALL1 from
1
2
3
4
5 6
7
8
9
10
11
1
2
13
14
1
5
16
N
P
1
N
P
2
HALL1
TCN-CONN10C-GP
20.F1655.010
2nd = 20.F0962.010
HALL1
TCN-CONN10C-GP
20.F1655.010
2nd = 20.F0962.010
1
AFTP84 AFTE14P-GP AFTP84 AFTE14P-GP
1
AFTP85
AFTE14P-GP
AFTP85
AFTE14P-GP
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
3D3V_S0
PLT_RST# 5,18,27,75,82,83
LPC_FRAME# 21,27
LPC_AD0 21,27
LPC_AD1 21,27
LPC_AD2 21,27
LPC_AD3 21,27
CLK_PCI_LPC 18
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Dubug connector
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Dubug connector
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Dubug connector
A3
<Core Design>
A00 1229 DB1 change to ZZ.00PAD.Y41(solder kmask type)
and keep un-stuffat X-Build stage
11
1
2
3
4
5
6
7
8
9
10
12
DB1
PAD-10P-177042-GP
ZZ.00PAD.Y41
DY
DB1
PAD-10P-177042-GP
ZZ.00PAD.Y41
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SP2
SP4
SP9
SP12
SP5
SP14
SP6
SP1
SP13
SP7
SP3
SP10
XD_D7
SP8
SP11
XD_CD#
3D3V_CARD_S0
3D3V_CARD_S0
SP6 32
SP1 32
SP3 32
SP4 32
SP5 32
SP7 32
SP14 32
SP8 32
SP12 32
SP9 32
SP8 32
SP2 32
SP9 32
SP5 32
SP10 32
SP1 32
SP11 32
SP12 32
SP13 32
XD_CD# 32
SP1 32
SP2 32
SP3 32
SP4 32
SP5 32
SP6 32
SP7 32
SP8 32
SP9 32
SP10 32
SP11 32
SP12 32
SP13 32
SP14 32
XD_D7 32
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
SD/XD/MS/MMC Card CONN
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
A3
<Core Design>
SSID = SDIO
SD/XD/MS/MMC+ Card Reader
Close to CARD1
For EMI Reserved
0906 X01 Modify:
Change CARD1 to 20.I0129.001 from 62.10051.931
from ME double updated latest DXF&EMN on X01.
1119 X02 Modify:
Add 2nd 20.I0135.001 on HALL1 from
1
2E
C
7
4
0
7
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
0
7
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2
C
7
4
0
3
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
C
7
4
0
3
S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
1
2E
C
7
4
1
7
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
1
7
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
0
8
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
0
8
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2
C
7
4
0
2
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C
7
4
0
2
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2E
C
7
4
0
5
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
0
5
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
1
6
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
1
6
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
1
0
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
1
0
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2
C
7
4
0
5
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
DY
C
7
4
0
5
S
C
1
0
U
6
D
3
V
5
M
X
-
3
G
P
DY
1
2
C
7
4
0
4
S
C
2
D
2
U
6
D
3
V
3
M
X
-
1
-
G
P
C
7
4
0
4
S
C
2
D
2
U
6
D
3
V
3
M
X
-
1
-
G
P
SD_CD
P1
SD_WP
P2
SD_DAT1
P3
MMC_DATA7
P5
MS_GND
P6
SD_GND
P7
MMC_DATA6
P8
MS_BS
P9
SD_CLK
P10
MS_DATA1
P11
SD_VCC
P13
MS_DATA2
P14
SD_GND
P15
MS_INS
P16
MMC_DATA5
P17
MS_DATA3
P18
SD_CMD
P19
MS_SCLK
P20
MMC_DATA4
P21
MS_VCC
P22
SD_DATA3
P23
MS_GND
P24
SD_DAT2
P25
SD_WP_COM/SDIO_GND
P26
SD_CD_COM/SDIO_GND
P27
XD_CD
1
XD_R/B
2
XD_RE
3
XD_CE
4
XD_CLE
5
XD_ALE
6
XD_WE
7
XD_WP_IN
8
XD_GND
9
XD_D0
10
XD_D1
11
XD_D2
12
XD_D3
13
XD_D4
14
XD_D5
15
XD_D6
16
XD_D7
17
XD_VCC
18
XD_GND
19
SD_DAT0
P4
MS_DATA0
P12
NP1
NP1
NP2
NP2
CARD1
CARD-PUSH-46P-1-GP-U
20.I0129.001
2nd = 20.I0135.001
CARD1
CARD-PUSH-46P-1-GP-U
20.I0129.001
2nd = 20.I0135.001
1
2E
C
7
4
0
9
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
0
9
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
1
3
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
1
3
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
1
1
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
1
1
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
0
3
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
0
3
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
1
4
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
1
4
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
0
4
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
0
4
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
1
5
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
1
5
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
0
6
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
0
6
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2E
C
7
4
0
2
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
0
2
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
1
2
C
7
4
0
1
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C
7
4
0
1
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2E
C
7
4
1
2
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
E
C
7
4
1
2
S
C
2
2
0
P
5
0
V
2
K
X
-
3
G
P
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1D5V_S0
PCIE_WAKE#_CON
USB_PP13_R
USB_PN13_R
3D3V_S0
PM_SLP_S4#
PM_SLP_S3#
CLK_PCIE_NEW_C
CLK_PCIE_NEW#_C
3D3V_S5
PLT_RST#
SMB_DATA
SMB_CLK
CLK_PCIE_NEW_REQ#_CON
PCIE_TXN8_CON
PCIE_TXP8_CON
PCIE_RXP8_CON
PCIE_RXN8_CON
PCIE_TXP8_CON
CLK_PCIE_NEW_REQ#_CON
PCIE_TXN8_CON
SMB_CLK
SMB_DATA
PM_SLP_S3#
PM_SLP_S4#
USB_PP13_R
USB_PN13_R
CLK_PCIE_NEW_C
CLK_PCIE_NEW#_C
PCIE_RXN8_CON
PCIE_RXP8_CON
PLT_RST#
PCIE_WAKE#_CON
PCIE_RXP8
PCIE_RXN8
CLK_PCIE_NEW_REQ#
PCIE_WAKE#
CLK_PCIE_NEW#_C
CLK_PCIE_NEW_C PCIE_TXN8_CON
PCIE_TXP8_CON
USB_PP13_R
USB_PN13_R
3D3V_S5
1D5V_S0
3D3V_S0
PM_SLP_S3# 19,27,36,37,47
PM_SLP_S4# 19,27,46
PCIE_WAKE# 27,82
CLK_PCIE_NEW# 20
CLK_PCIE_NEW 20
PCIE_RXN8 20
PCIE_TXP8 20
PCIE_TXN8 20
PCIE_RXP8 20
CLK_PCIE_NEW_REQ# 20
SMB_DATA 20
SMB_CLK 20
PLT_RST# 5,18,27,71,82,83
USB_PN13 18
USB_PP13 18
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Express Card
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Express Card
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Express Card
A3
<Core Design>
0913 X01 Modify:
Rename NEW1 pin24,25 to USB_PP13_R&USB_PN13_R.
Rename NEW1 pin8,9 to CLK_PCIE_NEW_C&CLK_PCIE_NEW#_C
0824 X01 Modify:
Due to our NEW1 change to Express card to
bottom side so re-assign NEW1 pin define same
as DQ15-NV.
0906 X01 Modify:
Add 2nd source 20.K0382.026 on NEW1 base on
updated connector list.
SB-25
1D5V_S0_CARD Max. 650mA, Average 500mA.
3D3V_S0_CARD Max. 1300mA, Average 1000mA
3D3V_S5_CARDAUX Max. 275mA
For EMI
0913 X01 Modify:
Add R7503,R7504 and reserved EC7501,EC7502 on
CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.
0921 X01 Modify:
Add R7505~R7508 0ohm and reserved EC7503~EC7506
on PCIE_TX8&RX8 signal base on EMC Lance suggestion.
Add R7509,R7510 0ohm and reserved EC7507,EC7508
on CLK_PCIE_NEW_REQ#&PCIE_WAKE# signal base
on EMC Lance suggestion.
1122 X02 Modify:
Change R7501,R7502 to 0603 from 0402.
A00 1229
1
1
1
2
EC7505
SC4D7P50V2CN-1GP
DY
EC7505
SC4D7P50V2CN-1GP
DY
1 2
R7505 0R2J -2-GP
DN15
R7505 0R2J -2-GP
DN15
1 2
R7510 0R2J -2-GP
DN15
R7510 0R2J -2-GP
DN15
1
1 2
R7508 0R2J -2-GP
DN15
R7508 0R2J -2-GP
DN15
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NEW1
ACES-CON26-6GP-U
20.K0320.026
DN15
2nd = 20.K0382.026
NEW1
ACES-CON26-6GP-U
20.K0320.026
DN15
2nd = 20.K0382.026
1
1 2
R7504 0R2J -2-GP
DN15
R7504 0R2J -2-GP
DN15
1 2
3 4
TR7501
FILTER-4P-6-GP
69.10103.041
DN15
2nd = 69.10084.071
TR7501
FILTER-4P-6-GP
69.10103.041
DN15
2nd = 69.10084.071
1
1
1
1
1
1 2
R7506 0R2J -2-GP
DN15
R7506 0R2J -2-GP
DN15
1
2
EC7501
SC4D7P50V2CN-1GP
DY
EC7501
SC4D7P50V2CN-1GP
DY
1
AFTP117 AFTE14P-GP AFTP117 AFTE14P-GP 1
2
EC7504
SC4D7P50V2CN-1GP
DY
EC7504
SC4D7P50V2CN-1GP
DY
1
2
EC7502
SC4D7P50V2CN-1GP
DY
EC7502
SC4D7P50V2CN-1GP
DY
1 2
R7509 0R2J -2-GP
DN15
R7509 0R2J -2-GP
DN15
1
1 2
R7507 0R2J -2-GP
DN15
R7507 0R2J -2-GP
DN15
1 2
R7503 0R2J -2-GP
DN15
R7503 0R2J -2-GP
DN15
1
1
1
1
1
2
EC7503
SC4D7P50V2CN-1GP
DY
EC7503
SC4D7P50V2CN-1GP
DY
1
1
2
EC7507
SC4D7P50V2CN-1GP
DY
EC7507
SC4D7P50V2CN-1GP
DY
1
1
2
EC7508
SC4D7P50V2CN-1GP
DY
EC7508
SC4D7P50V2CN-1GP
DY
1
2
EC7506
SC4D7P50V2CN-1GP
DY
EC7506
SC4D7P50V2CN-1GP
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FFS_INT2_R
FALL_INT2
HDD_FALL_SDO
HDD_FALL_INT1 PCH_SMBCLK
PCH_SMBDATA
5V_S0 3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
FFS_INT2 56
FFS_INT2_R 18
HDD_FALL_INT1 18
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Free Fall Sensor
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Free Fall Sensor
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Free Fall Sensor
A3
<Core Design>
Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
Free Fall Sensor
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
09/0422
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild
(#2) FAE/ DY is ok, chip internal pull-up resistors
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b
Pull GND SAD is 0011100b
0701 Modify:
Change G-SENSOR U7901 back to DE351DLTR8.
0705 Modify:
Change DUMMY column to:MAIN source->ADI solution.
second source->ST solution.
0706 Modify:
R2220 and R7904 double PH.
0802
1
2
R7902
100KR2J -1-GP
DY
R7902
100KR2J -1-GP
DY
1
2
R7903
100KR2J -1-GP
DY
R7903
100KR2J -1-GP
DY
1 2 3
456
Q7901
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
DY
Q7901
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
DY
1
2
R7906
10KR2J -3-GP
DY
R7906
10KR2J -3-GP
DY
SCL/SPC
14
SDA/SDI/SDO
13
SDO
12
CS
7
RESERVED#3
3
V
D
D
6
V
D
D
_
I
O
1
INT1
8
INT2
9
GND
2
GND
4
GND
5
GND
10
RESERVED#11
11
U7901
DE351DLTR8-GP
74.00351.0B3
DY
U7901
DE351DLTR8-GP
74.00351.0B3
DY
1 2
R7901
100KR2J -1-GP
DY
R7901
100KR2J -1-GP
DY
1
2
R7904
100KR2J -1-GP
DY
R7904
100KR2J -1-GP
DY
1
2
C7901
SC10U6D3V5MX-3GP
DY
C7901
SC10U6D3V5MX-3GP
DY
1
2
C7902
SCD1U10V2KX-4GP
DY
C7902
SCD1U10V2KX-4GP
DY
1 2 R7905
0R2J -2-GP
DY
R7905
0R2J -2-GP
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Reserved
A3
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CRT_RED
CRT_GREEN
CRT_DDC_DATA
CRT_DDC_CLK
CRT_BLUE
MEDIA1_2
MEDIA1_3
MEDIA1_1
MEDIA1_2
MEDIA1_1
MEDIA1_3
5V_S5
DATA_RECOVERY#
INSTANT_ON#
MEDIA_BTN3#
CRT_VSYNC_CON
CRT_HSYNC_CON
CRT_DDC_DATA
CRT_DDC_CLK
CRT_GREEN
CRT_BLUE
CRT_RED
MEDIA_LED1#
MEDIA_LED2#
MEDIA_LED3#
MEDIA_LED1#
MEDIA_LED2#
MEDIA_LED3#
CRT_VSYNC_CON
CRT_HSYNC_CON
5V_S5
5V_CRT_S0_R 5V_CRT_S0 5V_S0
5V_S5
3D3V_S5
AD+ AD+
3D3V_S0
5V_CRT_S0_R
5V_S5
AUD_AGND
3D3V_S5
3D3V_S0
1D5V_S0
5V_S5
5V_USB2_S3
3D3V_S5
CRT_GREEN 17
CRT_BLUE 17
CRT_RED 17
CRT_DDC_CLK 17
CRT_DDC_DATA 17
MEDIA_LED1# 27
INSTANT_ON# 27
DATA_RECOVERY# 27
MEDIA_BTN3# 27
PSID_EC 27
RCID 27
USB_PP1 18
USB_PN1 18
PCIE_TXN3 20
PCIE_TXP3 20
PCIE_RXP3 20
PCIE_RXN3 20
PCIE_TXN2 20
PCIE_RXP2 20
PCIE_TXP2 20
PCIE_RXN2 20
PCIE_RXN4 20
PCIE_RXP4 20
PCIE_TXP4 20
PCIE_TXN4 20
PCIE_TXN5 20
PCIE_RXN5 20
PCIE_RXP5 20
PCIE_TXP5 20
USB_PP11 18
USB_PN11 18
USB_PP4 18
USB_PN4 18
WLAN_ACT 63
USB3_PEGB_CLKREQ# 20
CLK_PCIE_WWAN_REQ# 20
PCIE_CLK_LAN_REQ# 20
USB30_SMI# 18
CLK_PCIE_WLAN# 20
CLK_PCIE_WLAN 20
CLK_PCIE_WWAN# 20
CLK_PCIE_WWAN 20
PM_LAN_ENABLE 27
PLT_RST# 5,18,27,71,75,83
BT_ACT 63
CLK_PCIE_USB3# 20
CLK_PCIE_USB3 20
3G_EN 22
E51_TXD 27
E51_RXD 27
WIFI_RF_EN 27
CLK_PCIE_WLAN_REQ# 20
PCIE_WAKE# 27,75
BLUETOOTH_EN 27,63
CLK_PCIE_LAN 20
CLK_PCIE_LAN# 20
AUD_HP1_J D# 29
EXT_MIC_J D# 29
MIC_IN_L 29
MIC_IN_R 29
AUD_HP1_J ACK_R2 29
AUD_HP1_J ACK_L2 29
USB3_PWR_ON 27
CRT_HSYNC 17
CRT_VSYNC 17
MEDIA_LED2# 27
MEDIA_LED3# 27
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
IO Board Connector
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
IO Board Connector
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
IO Board Connector
A3
<Core Design>
0625 Modify:
Change CRTBD1 part number to 20.F0957.030
from 20.F1521.030 base on EMN updated part number.
0720 Modify:
Change CRTBD1 connector to 20.F1121.040 from
30pin base on ME Double provide final solution.
0721 Modify:
re-assign CRTBD1 pin define to follow Joseph
release PIN define.
0810
High active
0814
U8B3.0 PCE
U8B3.0 PCE
0913 X01 Modify:
Change R8201~R8203 to 470ohm from 100ohm.
Add RN8209 PH 5V_S5 on MEDIA_LED1~3# for
PWM OD mode.
CRT Board Connector
0906 X01 Modify:
Add 2nd source 20.F0085.040 on CRTBD1
base on updated connector list.
0915 X01 Modify:
Re-assign CRTBD1 pin define base on
EMC suggestion.
IO Board CONN 80 pin
WWAN/WLAN 8MBU8
WWAN PCE
WWAN U8B
WLAN U8B
U8B3.0 PCE
U8B3.0 PCE
LAN PCE
LAN PCE
WWAN PCE
WLAN PCE
WLAN PCE
0916 X01 Modify:
Keep original X00 IOBD1 pin define.
0917 X01 Modify:
Change IOBD1 part number to 20.F1849.080
base on Double updated latest DXF&EMN.
0920 X01 Modify:
Re-assign IOBD1 pin define due to updated
connector pin define is different as before.
Add R8206,R8207 to isolated AGND and DGND.
WWAN CLK
LAN CLK
U8B3.0 CLK
WLAN CLK
1110 X02 Modify:
Add 2nd 20.K0465.008 on MEDIA1 from
1112 X02 Modify:
change Media resistor from 430 ohm to 1K on
both DQ/DN15(R8201, R8202, R8203)
for Media button LED light spot issue
X02 1116
1112 X02 Modify:
Dell required us to disable PCIE port of WWAN slot
,If PCIE port 1 is disabled, it will cause all PCIE port
disabled,so change WWAN to PCIE port 3 from port1
at ST stage.
1122 X02 Modify:
stuff EC8201,EC8202 0.1u(closed H3)
between GND and GND from EMC Neo suggestion.
stuff EC8206 between 3D3V_S5 and GND from
EMC Neo suggestion.
X02 1122
1119 X02 Modify:
Reserved EC8203~EC8205 470p on all of
MEDIA_LED# signal from EMC Neo suggestion.
A00 1224
1120 X02 Modify:
Add RN8205
base on HSYNC&VSYNC report.
1120 X02 Modify:
Reserved R8211,R8212 0ohm 0805 on CRTBD1
pin37,39 to separate EATA and CRT USB power in
ST build.
1122 X02 Modify:
Swap RN8205 pin4,3 and pin2,1 each other
base on Connie swap report.
1123 X02 Modify:
Removed R8211,R8212 and connect
5V_USB2_S3 to CRTBD1 pin 37 directly.
A00
A00
A00
A00 1224
A00 1229
A00 0103 add 3rd T-conn(20.F1932.040) at XBuild batch run
1 2
R8211
0R3J -0-U-GP
DY
R8211
0R3J -0-U-GP
DY
2 1
D8201
CH551H-30PT-GP
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
83.R5003.C8F
D8201
CH551H-30PT-GP
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
83.R5003.C8F
1 2
R8204 10KR2J -3-GP
DY
R8204 10KR2J -3-GP
DY
1 AFTP8203 AFTP8203
1 AFTP8204 AFTP8204
1 2
R8205 10KR2J -3-GP
DY
R8205 10KR2J -3-GP
DY
1 2
R8208 10KR2J -3-GP
DY
R8208 10KR2J -3-GP
DY
1 AFTP8206 AFTP8206
1
2
E
C
8
2
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
8
2
0
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1 AFTP8205 AFTP8205
1
2
E
C
8
2
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
8
2
0
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1 2
F8201
FUSE-1D1A6V-4GP-U
69.50007.691
2nd = 69.50007.771
F8201
FUSE-1D1A6V-4GP-U
69.50007.691
2nd = 69.50007.771
1 AFTP8207 AFTP8207
1 2 R8206
0R0603-PAD-2-GP
R8206
0R0603-PAD-2-GP
1 AFTP8202 AFTP8202
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
NP1
NP2
81
82
IOBD1
ACES-CONN80D-1-GP
20.F1849.080
2nd = 20.F1908.080
IOBD1
ACES-CONN80D-1-GP
20.F1849.080
2nd = 20.F1908.080
1 2 R8207
0R0603-PAD-2-GP
R8207
0R0603-PAD-2-GP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
4
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
41 43
44
4
5
46
N
P
1
N
P
2
CRTBD1
ACES-CONN40D-GP
20.F1121.040
2nd = 20.F0085.040
3rd = 20.F1932.040
CRTBD1
ACES-CONN40D-GP
20.F1121.040
2nd = 20.F0085.040
3rd = 20.F1932.040
1 2
EC8203 SC470P50V-2-GP EC8203 SC470P50V-2-GP 1 2
EC8204 SC470P50V-2-GP EC8204 SC470P50V-2-GP
1
2
E
C
8
2
0
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
E
C
8
2
0
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
1
2
3
4
5
6
7
8
9
10
MEDIA1
ACES-CON8-19-GP
20.K0320.008
2nd = 20.K0465.008
MEDIA1
ACES-CON8-19-GP
20.K0320.008
2nd = 20.K0465.008
1 2 R8201
1KR2J -1-GP
R8201
1KR2J -1-GP 1
2 3
4
RN8201
SRN1KJ -7-GP
RN8201
SRN1KJ -7-GP
1 2
EC8205 SC470P50V-2-GP EC8205 SC470P50V-2-GP
1
2 3
4
RN8205
SRN22-3-GP
RN8205
SRN22-3-GP
1 AFTP8201 AFTP8201
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEX_TESTMODE
PEX_TERMP
STRAP_3V3
STRAP_MIOB
HDCP_CLK
HDCP_SDA
GPU_ROM_CS#
GPU_ROM_SO
GPU_ROM_SI
GPU_ROM_SCLK
GPU_ROM_SO
GPU_ROM_SCLK
GPU_ROM_SI STRAP0
STRAP2
STRAP1
VIO_PLLVDD
XTALSSIN
XTALOUT
XTALOUTBUFF
CEC
PEX_RST#
PLT_RST#
NV_PEG_CLKREQ#
XTALOUT_R
XTALIN
PEX_RST#
HDCP_CLK
HDCP_SDA
PEX_PLLVDD
PEG_RXP2
PEG_RXN2
PEG_RXP14
PEG_RXN11
PEG_RXN13
PEG_RXP15
PEG_RXP12
PEG_RXN15
PEG_RXP13
PEG_RXP11
PEG_RXN12
PEG_RXN14
PEG_C_RXP12
PEG_C_RXN12
PEG_C_RXP7
PEG_C_RXN7
PEG_TXP9
PEG_TXN9
PEG_C_RXP2
PEG_C_RXN2
PEG_TXP4
PEG_TXN4
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP8
PEG_RXP10
PEG_RXN10
PEG_TXP15
PEG_TXN15
PEG_TXP14
PEG_TXN14
PEG_TXP13
PEG_TXN13
PEG_C_RXP11
PEG_C_RXN11
PEG_TXP12
PEG_TXN12
PEG_C_RXP6
PEG_C_RXN6
PEG_TXP11
PEG_TXN11
PEG_C_RXP15
PEG_TXP5
PEG_TXN5
PEG_TXP10
PEG_TXN10
PEG_C_RXP1
PEG_C_RXN1
PEG_TXP0
PEG_TXN0
PEG_C_RXP10
PEG_C_RXN10
PEG_C_RXN15
PEG_C_RXP5
PEG_C_RXN5
PEG_TXP6
PEG_TXN6
PEG_TXN1
PEG_TXP1
PEG_C_RXP0
PEG_C_RXN0
PEG_C_RXP14
PEG_C_RXN14
PEG_C_RXP9
PEG_C_RXN9
PEG_C_RXP4
PEG_C_RXN4
PEG_TXP7
PEG_TXN7
PEG_TXP2
PEG_TXN2
PEG_RXN7
PEG_RXP7
PEG_RXP6
PEG_RXN6
PEG_C_RXP13
PEG_C_RXN13
PEG_C_RXP8
PEG_C_RXN8
PEG_RXP5
PEG_RXN5
PEG_TXP8
PEG_TXN8
PEG_C_RXP3
PEG_C_RXN3
PEG_TXP3
PEG_TXN3
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
STRAP0
STRAP1
STRAP2
PEXTSTCLK_OUT
PEXTSTCLK_OUT#
NV_PEG_CLKREQ#
1V_VGA_S0
1V_VGA_S0
3D3V_VGA_S0
3D3V_VGA_S0
3D3V_S5
3D3V_VGA_S0
1V_VGA_S0
3D3V_VGA_S0
3D3V_VGA_S0 3D3V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0
CLK_PCIE_VGA 20
CLK_PCIE_VGA# 20
DGPU_HOLD_RST# 18
PLT_RST# 5,18,27,71,75,82
PEG_RXP[0..15] 4
PEG_RXN[0..15] 4
PEG_TXP[0..15] 4
PEG_TXN[0..15] 4
VGA_SENSE 92
GND_SENSE 92
CLK_27M_VGA 20
PEG_CLKREQ# 20
DGPU_PWROK 22,92,93
PEX_RST# 51,85,86
Title
Date: Sheet of
Wistron Corporation
A00
N12P(1/6)_PEG
A2
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(1/6)_PEG
A2
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(1/6)_PEG
A2
QUEEN 15
<Variant Name>
Logical Strap Bit Mapping
Resistor Pull-up Pull-down
5Kohms 1000 0000
10Kohms 1001 0001
15Kohms 1010 0010
20Kohms 1011 0011
25Kohms 1100 0100
30Kohms 1101 0101
35Kohms 1110 0110
45Kohms 1111 0111
USER[0]=1
USER[1]=1
USER[2]=1
USER[3]=1
3GIO_PADCFG[0]=0
3GIO_PADCFG[1]=1
3GIO_PADCFG[2]=1
3GIO_PADCFG[3]=0
PCI_DEVID[0]=0
PCI_DEVID[1]=0
PCI_DEVID[2]=1
PCI_DEVID[3]=0
VGA_DEVICE =1
SMB_ALT_ADDR =0
FB_0_BAR_SIZE =0
XCLK_417 =0
for Samsung VRAM
(64Mx16) (0x3)
RAM_CFG[0]=1
RAM_CFG[1]=1
RAM_CFG[2]=0
RAM_CFG[3]=0
PEX_PLL_EN_TERM =0
SLOT_CLK_CFG =1
SUB_VENDOR =0
PCI_DEVID[4] =1
GPU_ROM_SI
GPU_ROM_SO
GPU_ROM_SCLK
STRAP0
STRAP1
STRAP2
for Hynix VRAM
(64Mx16) (0x2)
RAM_CFG[0]=0
RAM_CFG[1]=1
RAM_CFG[2]=0
RAM_CFG[3]=0
Near BALLS Near BGA
N12P-GE N12P-GV1 N12M-GE N11P-GE N11P-GS
[0] 1 1 TBD 1 0
[1] 0 1 0 0
[2] 1 1 0 0
[3] 0 0 0 0
Need check panel resolution
1366x768
GPU_ROM_SCLK: DIS_DID_H
N12P-GE PH = 15K(64.15025.6DL), PL = NC
N12P-GV1 PH = 15K(64.15025.6DL), PL = NC
N12M-GE PH = TBD, PL = TBD
N11P-GE-A1 PH = 15K(64.15025.6DL), PL = NC
N11P-GS-A1 PH = 15K(64.15025.6DL), PL = NC
STRAP 2: DIS_DID_L
N12P-GE PH = NC, PL = 30K(64.30025.6DL)
N12P-GV1 PH = NC, PL = 15K(64.15025.6DL)
N12M-GE PH = TBD, PL = TBD
N11P-GE-A1 PH = TBD, PL = 10K
N11P-GS-A1 PH= NC, PL = 4.99K
Near BALLS
Near BALLS Near BGA
Stuff PD on XTAL_SSIN and
XTAL_OUTBUFF when EXT_SS is not
used.
STRAPPING MODE TABLE
PIN NAME MULTI-LEVEL BINARY PRODUCTION BINARY BRINGUP
MULTI_STRAP_REF1_GND
40.2K TO GND
40.2K TO GND
40.2K TO GND
NC
NC
NC
for Hynix VRAM
(128Mx16) (0x6)
RAM_CFG[0]=0
RAM_CFG[1]=1
RAM_CFG[2]=1
RAM_CFG[3]=0
for Samsung VRAM
(128Mx16) (0x7)
RAM_CFG[0]=1
RAM_CFG[1]=1
RAM_CFG[2]=1
RAM_CFG[3]=0
Notebook configure.
N12P-GE N12P-GV1 N12M-GE N11P-GE N11P-GS
[4] 1 1 TBD 1 1
GPU_ROM_SI
Hynix 64x16 = PL 15K
Samsung 64x16 = PL 20K
120mA
150mA
Near BALLS
0723
0723
0728
0728
0728
0901
0xDF5
0818
De-cap
0818
De-cap
0818
De-cap
0818
De-cap
0927
1009
X02 11/29
A00
A00
1 2 C8306 SCD1U10V2KX-5GP Optimus C8306 SCD1U10V2KX-5GP Optimus
1 2 R8305
30KR2F-GP
DIS_DID_L
R8305
30KR2F-GP
DIS_DID_L
1
2
C8355
S
C
1
0
U
6
D
3
V
3
M
X
-G
P
Optimus
C8355
S
C
1
0
U
6
D
3
V
3
M
X
-G
P
Optimus
1
2
C8352S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
C8352S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
1
2
C8357S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
C8357S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
1
2
R8303
40K2R2F-GP
Optimus
R8303
40K2R2F-GP
Optimus
1
2
C8344S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
C8344S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
1
2
C8349S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
C8349S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
1 2 R8326
34K8R2F-1-GP DY
R8326
34K8R2F-1-GP DY
1
2
C8351S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8351S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
1 2
R8315 200R2F-L-GP DY R8315 200R2F-L-GP DY
1
2
C8362 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
C8362 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
1
2
R8313
10KR2J -3-GP
Optimus
R8313
10KR2J -3-GP
Optimus
1 2
R8323
0R0402-PAD-2-GP
Optumus
R8323
0R0402-PAD-2-GP
Optumus
1 2 R8325
2KR2J -1-GP DY
R8325
2KR2J -1-GP DY
G
S
D
PQ8309
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
PQ8309
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
1
2
R8306
10KR2J -3-GP
Optimus
R8306
10KR2J -3-GP
Optimus
1 2 R8312
15KR2F-GP DIS_SAM_HYX
R8312
15KR2F-GP DIS_SAM_HYX
1
2
C8334S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
C8334S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
12
3 4
RN8301
SRN4K7J -8-GP Optimus
RN8301
SRN4K7J -8-GP Optimus
1
2
R8301
2K49R2F-GP
Optimus
R8301
2K49R2F-GP
Optimus
1
2
C8345S
C
D
1
U
1
0
V
2
K
X
-4
G
P
Optimus
C8345S
C
D
1
U
1
0
V
2
K
X
-4
G
P
Optimus
1 2 R8307
45K3R2F-L-GP Optimus
R8307
45K3R2F-L-GP Optimus
1 2
L8303
EBMS160808A121-GP
Optimus
2ND = 68.00119.101
68.00375.101
L8303
EBMS160808A121-GP
Optimus
2ND = 68.00119.101
68.00375.101
1 2 R8310
15KR2F-GP DIS_DID_H
R8310
15KR2F-GP DIS_DID_H
1
2
C8348
S
C
1
0
U
6
D
3
V
3
M
X
-G
P
Optimus
C8348
S
C
1
0
U
6
D
3
V
3
M
X
-G
P
Optimus
1
2
C8364 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
C8364 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
1
2
R8318
10KR2J -3-GP
Optimus
R8318
10KR2J -3-GP
Optimus
1
2
R8320
1MR2F-GP
R8320
1MR2F-GP
1
2
C8360S
C
D
1
U
1
0
V
2
K
X
-4
G
P
DY
C8360S
C
D
1
U
1
0
V
2
K
X
-4
G
P
DY
1
2
C8350 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
DY
C8350 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
DY
1
2
C8343S
C
D
1
U
1
0
V
2
K
X
-4
G
P
Optimus
C8343S
C
D
1
U
1
0
V
2
K
X
-4
G
P
Optimus
1 2 R8316
10KR2F-2-GP Optimus
R8316
10KR2F-2-GP Optimus
1
2
C8330S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
C8330S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
1 2 R8311
15KR2F-GP DY
R8311
15KR2F-GP DY
1
2
C8361 S
C
1
0
U
6
D
3
V
5
K
X
-1
G
P
Optimus
C8361 S
C
1
0
U
6
D
3
V
5
K
X
-1
G
P
Optimus
1 2 R8322
0R2J -2-GP
DY
R8322
0R2J -2-GP
DY
1 2
R8302
0R2J -2-GP
DY
R8302
0R2J -2-GP
DY
B
1
A
2
GND
3
Y
4
VCC
5
U8301
74LVC1G08GW-1-GP
73.01G08.L04
2nd = 73.7SZ08.DAH
DY
U8301
74LVC1G08GW-1-GP
73.01G08.L04
2nd = 73.7SZ08.DAH
DY
PEX_RX15#
AP34
PEX_RX15
AR34
PEX_TX15#
AP32
PEX_TX15
AN32
PEX_RX14#
AR32
PEX_RX14
AR31
PEX_TX14#
AM32
PEX_TX14
AM31
PEX_RX13#
AP31
PEX_RX13
AN31
PEX_TX13#
AM30
PEX_TX13
AM29
PEX_RX12#
AN29
PEX_RX12
AP29
PEX_TX12#
AL29
PEX_TX12
AK29
PEX_RX11#
AR29
PEX_RX11
AR28
PEX_TX11#
AK28
PEX_TX11
AL28
PEX_RX10#
AP28
PEX_RX10
AN28
PEX_TX10#
AM28
PEX_TX10
AM27
PEX_RX9#
AN26
PEX_RX9
AP26
PEX_TX9#
AM26
PEX_TX9
AL26
PEX_RX8#
AR26
PEX_RX8
AR25
PEX_TX8#
AK25
PEX_TX8
AL25
PEX_RX7#
AP25
PEX_RX7
AN25
PEX_TX7#
AM25
PEX_TX7
AM24
PEX_RX6#
AN23
PEX_RX6
AP23
PEX_TX6#
AM23
PEX_TX6
AL23
PEX_RX5#
AR23
PEX_RX5
AR22
PEX_TX5#
AK22
PEX_TX5
AL22
PEX_RX4#
AP22
PEX_RX4
AN22
PEX_TX4#
AM22
PEX_TX4
AM21
PEX_RX3#
AN20
PEX_RX3
AP20
PEX_TX3#
AM20
PEX_TX3
AL20
PEX_RX2#
AR20
PEX_RX2
AR19
PEX_TX2#
AK19
PEX_TX2
AL19
PEX_RX1#
AP19
PEX_RX1
AN19
PEX_TX1#
AM19
PEX_TX1
AM18
PEX_RX0#
AN17
PEX_RX0
AP17
PEX_TX0#
AM17
PEX_TX0
AL17
PEX_REFCLK#
AR17
PEX_REFCLK
AR16
PEX_TSTCLK_OUT#
AJ 18
PEX_TSTCLK_OUT
AJ 17
PEX_CLKREQ#
AR13
PEX_RST#
AM16
TESTMODE
AP35
PEX_TERMP
AG21
NC#AG20
AG20
PEX_PLLVDD
AG14
GND_SENSE#E35
E35
GND_SENSE#R7
R7
GND_SENSE#AD19
AD19
VDD_SENSE#AD20
AD20
VDD_SENSE#P7
P7
VDD_SENSE#D35
D35
VDD33
J 9
VDD33
J 13
VDD33
J 12
VDD33
J 11
VDD33
J 10
NC#Y4
Y4
NC#V6
V6
NC#U7
U7
NC#E5
E5
NC#D7
D7
NC#D6
D6
NC#C7
C7
NC#AK15
AK15
NC#AJ 5
AJ 5
NC#AG6
AG6
NC#AF6
AF6
NC#AD6
AD6
NC#AC5
AC5
NC#AB7
AB7
NC#AB4
AB4
NC#AA4
AA4
NC#A7
A7
NC#A2
A2
NC#F7
F7
PEX_SVDD_3V3
AG19
PEX_IOVDDQ
AL16
PEX_IOVDDQ
AK26
PEX_IOVDDQ
AK23
PEX_IOVDDQ
AK20
PEX_IOVDDQ
AK18
PEX_IOVDDQ
AJ 27
PEX_IOVDDQ
AJ 25
PEX_IOVDDQ
AJ 24
PEX_IOVDDQ
AJ 22
PEX_IOVDDQ
AJ 21
PEX_IOVDDQ
AJ 19
PEX_IOVDDQ
AJ 15
PEX_IOVDDQ
AJ 14
PEX_IOVDDQ
AG26
PEX_IOVDDQ
AG25
PEX_IOVDDQ
AG24
PEX_IOVDDQ
AG23
PEX_IOVDDQ
AG22
PEX_IOVDDQ
AG18
PEX_IOVDDQ
AG17
PEX_IOVDDQ
AG16
PEX_IOVDDQ
AG15
PEX_IOVDDQ
AG13
PEX_IOVDDQ
AG12
PEX_IOVDDQ
AG11
PEX_IOVDD
AK27
PEX_IOVDD
AK24
PEX_IOVDD
AK21
PEX_IOVDD
AK17
PEX_IOVDD
AK16
NC#E7
E7
NC#F4
F4
NC#G5
G5
NC#H32
H32
NC#AL7
AL7
NC#B7
B7
NC#P6
P6
NC#D5
D5
PCI_EXPRESS
1 OF 16 VGA2A
N12P-GE-A1-GP
OPTIMUS
PCI_EXPRESS
1 OF 16 VGA2A
N12P-GE-A1-GP
OPTIMUS
4
12
3
X8301
XTAL-27MHZ-85-GP
MUXLESS
2nd = 82.30034.651
3rd = 82.30034.681
82.30034.641
X8301
XTAL-27MHZ-85-GP
MUXLESS
2nd = 82.30034.651
3rd = 82.30034.681
82.30034.641
1
2
C8347 S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8347 S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
1
2
C8341S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8341S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
1
2
R8304
40K2R2F-GP
Optimus
R8304
40K2R2F-GP
Optimus
1 2 R8308
34K8R2F-1-GP Optimus
R8308
34K8R2F-1-GP Optimus
1
2
R8319
10KR2J -3-GP
Optimus
R8319
10KR2J -3-GP
Optimus
1 2
C8353 SC15P50V2J N-2-GP
Optimus
C8353 SC15P50V2J N-2-GP
Optimus
XTAL_SSIN
D2
SP_PLLVDD
AF9
VID_PLLVDD
AD9
PLLVDD
AE9
XTAL_OUT
B2
XTAL_OUTBUFF
D1
XTAL_IN
B1
XTAL_PLL
14 OF 16 VGA2N
N12P-GE-A1-GP
OPTIMUS
XTAL_PLL
14 OF 16 VGA2N
N12P-GE-A1-GP
OPTIMUS
1
2
C8338S
C
1
U
6
D
3
V
2
K
X
-G
P
DY
C8338S
C
1
U
6
D
3
V
2
K
X
-G
P
DY
1 2 R8327
2KR2J -1-GP DY
R8327
2KR2J -1-GP DY
1
2
C8342S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
C8342S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
1 2 R8317
10KR2F-2-GP DY
R8317
10KR2F-2-GP DY
1
2
C8356 S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
DY
C8356 S
C
2
2
U
6
D
3
V
5
M
X
-2
G
P
DY
1
2
C8358 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
C8358 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
1
2
C8339S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8339S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
1
2
C8326S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8326S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
M9
N9
CEC
AB5
NC#J 25
J 25
NC#J 26
J 26
GND
K9
GND
AK14
NC#C5
C5
BUFRST#
A4
NC#A5
A5
I2CH_SDA
G6
I2CH_SCL
F6
ROM_SCLK
D4
ROM_SO
C4
ROM_SI
D3
ROM_CS#
C3
STRAP0
W5
STRAP1
W7
STRAP2
V7
MISC2
13 OF 16 VGA2M
N12P-GE-A1-GP
OPTIMUS
MISC2
13 OF 16 VGA2M
N12P-GE-A1-GP
OPTIMUS
1 2
C8354 SC15P50V2J N-2-GP
Optimus
C8354 SC15P50V2J N-2-GP
Optimus
1
2
C8340S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8340S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
1
2
R8321
0R2J -2-GP
Optimus
R8321
0R2J -2-GP
Optimus
1 2 R8314 100KR2J -1-GP
DY
R8314 100KR2J -1-GP
DY
1
2
C8317
S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P Optimus
C8317
S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P Optimus
1 2 L8301
0R0603-PAD-2-GP
Optiums
L8301
0R0603-PAD-2-GP
Optiums
1
2
C8346S
C
D
1
U
1
0
V
2
K
X
-4
G
P
Optimus
C8346S
C
D
1
U
1
0
V
2
K
X
-4
G
P
Optimus
1 2 R8309
10KR2F-2-GP DY
R8309
10KR2F-2-GP DY
1
2
R8324
1
0
K
R
2
J
-3
-G
P
Optimus
R8324
1
0
K
R
2
J
-3
-G
P
Optimus
1
2
C8359 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
C8359 S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
1
2
C8363S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
C8363S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
1
2
C8321S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8321S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FBAD31
FBAD17
FBAD19
FBAD18
FBAD21
FBAD23
FBAD22
FBAD20
FBAD16
FBAD25
FBAD27
FBAD26
FBAD29
FBAD30
FBAD28
FBAD24
FBAD15
FBAD47
FBAD33
FBAD35
FBAD34
FBAD37
FBAD39
FBAD38
FBAD36
FBAD32
FBAD41
FBAD43
FBAD42
FBAD45
FBAD46
FBAD44
FBAD40
FBAD1
FBAD3
FBAD2
FBAD5
FBAD7
FBAD6
FBAD4
FBAD0
FBAD9
FBAD11
FBAD10
FBAD13
FBAD14
FBAD12
FBAD8
FBAD63
FBAD49
FBAD51
FBAD50
FBAD53
FBAD55
FBAD54
FBAD52
FBAD48
FBAD57
FBAD59
FBAD58
FBAD61
FBAD62
FBAD60
FBAD56
FBA_CLK1#
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_DEBUG0
FBCAL_PD_VDDQ
FBCAL_PU_GND
FB_VREF
FBB_CLK1#
FBB_CLK0
FBB_CLK0#
FBB_CLK1
FBC_DEBUG0
FB_CAL_TERM_GND
FBA_CMD_20
FBBD0
FBBD1
FBBD2
FBBD3
FBBD4
FBBD5
FBBD6
FBBD7
FBBD8
FBBD12
FBBD13
FBBD14
FBBD15
FBBD9
FBBD10
FBBD11
FBBD16
FBBD20
FBBD21
FBBD22
FBBD23
FBBD17
FBBD18
FBBD19
FBBD24
FBBD28
FBBD29
FBBD30
FBBD31
FBBD25
FBBD26
FBBD27
FBBD32
FBBD36
FBBD37
FBBD38
FBBD39
FBBD56
FBBD60
FBBD61
FBBD62
FBBD63
FBBD57
FBBD58
FBBD59
FBBD33
FBBD40
FBBD44
FBBD45
FBBD46
FBBD47
FBBD41
FBBD42
FBBD43
FBBD34
FBBD35
FBBD48
FBBD52
FBBD53
FBBD54
FBBD55
FBBD49
FBBD50
FBBD51
FBA_DEBUG1 FBC_DEBUG1
FB_PLLAVDD0
FB_PLLAVDD1
FBA_CMD_0
FBA_CMD_3
FBA_CMD_19
FBA_CMD_16
FBB_CMD_16
FBB_CMD_19
FBB_CMD_20
FBB_CMD_0
FBB_CMD_3
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1V_VGA_S0
1V_VGA_S0
FBADQM6 89
FBADQM7 89
FBADQSP6 89
FBADQSP7 89
FBADQSP2 88
FBADQSP3 88
FBADQSP0 88
FBADQSP1 88
FBADQSP4 89
FBADQSP5 89
FBADQM2 88
FBADQM3 88
FBAD[32..63] 89
FBAD[0..31] 88
FBADQSN6 89
FBADQSN7 89
FBADQSN2 88
FBADQSN3 88
FBADQSN0 88
FBADQSN1 88
FBADQSN4 89
FBADQSN5 89
FBADQM0 88
FBADQM1 88
FBADQM4 89
FBADQM5 89
FBA_CLK1 89
FBA_CLK0# 88
FBA_CLK0 88
FBA_CLK1# 89
FBA_CMD_9 88,89
FBA_CMD_24 88,89
FBA_CMD_18 89
FBA_CMD_19 89
FBA_CMD_10 88,89
FBA_CMD_25 88,89
FBA_CMD_5 88,89
FBA_CMD_8 88,89
FBA_CMD_0 88
FBA_CMD_21 88,89
FBA_CMD_22 88,89
FBA_CMD_20 88,89
FBA_CMD_2 88
FBA_CMD_12 88
FBA_CMD_13 88,89
FBA_CMD_6 88,89
FBA_CMD_3 88
FBBDQM6 91
FBBDQM7 91
FBBDQSP6 91
FBBDQSP7 91
FBBDQSP2 90
FBBDQSP3 90
FBBDQSP0 90
FBBDQSP1 90
FBBDQSP4 91
FBBDQSP5 91
FBBDQM2 90
FBBDQM3 90
FBBD[32..63] 91
FBBD[0..31] 90
FBBDQSN6 91
FBBDQSN7 91
FBBDQSN2 90
FBBDQSN3 90
FBBDQSN0 90
FBBDQSN1 90
FBBDQSN4 91
FBBDQSN5 91
FBBDQM0 90
FBBDQM1 90
FBBDQM4 91
FBBDQM5 91
FBB_CLK1 91
FBB_CLK0# 90
FBB_CLK0 90
FBB_CLK1# 91
FBB_CMD_16 91
FBB_CMD_27 90
FBB_CMD_9 90,91
FBB_CMD_24 90,91
FBB_CMD_18 91
FBB_CMD_19 91
FBB_CMD_10 90,91
FBB_CMD_25 90,91
FBB_CMD_5 90,91
FBB_CMD_8 90,91
FBB_CMD_0 90
FBB_CMD_21 90,91
FBB_CMD_22 90,91
FBB_CMD_20 90,91
FBB_CMD_2 90
FBB_CMD_12 90
FBB_CMD_13 90,91
FBB_CMD_11 90,91
FBB_CMD_6 90,91
FBB_CMD_3 90
FBA_CMD_26 88,89
FBA_CMD_28 88,89
FBA_CMD_29 88,89
FBA_CMD_30 89
FBB_CMD_26 90,91
FBB_CMD_28 90,91
FBB_CMD_30 91
FBB_CMD_29 90,91
FBA_CMD_11 88,89
FBA_CMD_16 89
FBA_CMD_27 88
FBA_CMD_15 88,89
FBA_CMD_23 88,89
FBB_CMD_15 90,91
FBB_CMD_23 90,91
FBA_CMD_14 89
FBA_CMD_4 88,89
FBB_CMD_14 91
FBB_CMD_4 90,91
FBA_CMD_7 88,89 FBB_CMD_7 90,91
Title
Date: Sheet of
Wistron Corporation
A00
N12P(2/6)_MEMORY
Custom
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(2/6)_MEMORY
Custom
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(2/6)_MEMORY
Custom
QUEEN 15
<Variant Name>
Differential write clocks
for GDDR5 for Frame Buffers.
Reference for read and write
data.
Near BALLS
Near BGA
Mode E is necessary for DDR3
that require compatibility
with previous generation
GPUs (GB1-128) and only
applies to GB2-128 package.
ODTx & CKEx & RST termination.
ODTx & CKEx & RST termination.
GB1-128 do not need.
0723
0802 swap
0810
0818
De-cap
0818
De-cap
0818
De-cap
0818
De-cap
1009
A00
A00
1
2
C8410S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
DY
C8410S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
DY
1
2
C8409 S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
Optimus
C8409 S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
Optimus
NC#J 27
J 27
FBA_WCK3#
AE29
FBA_WCK3
AD29
FBA_WCK2#
AH29
FBA_WCK2
AG29
FBA_WCK1#
M29
FBA_WCK1
L29
FBA_WCK0#
R29
FBA_WCK0
P29
FBA_DQS_RN7
AC34
FBA_DQS_RN6
AJ 35
FBA_DQS_RN5
AJ 31
FBA_DQS_RN4
AD32
FBA_DQS_RN3
N32
FBA_DQS_RN2
H31
FBA_DQS_RN1
G35
FBA_DQS_RN0
L35
FBA_DQS_WP7
AC33
FBA_DQS_WP6
AJ 34
FBA_DQS_WP5
AJ 32
FBA_DQS_WP4
AE31
FBA_DQS_WP3
N31
FBA_DQS_WP2
J 32
FBA_DQS_WP1
H35
FBA_DQS_WP0
L34
FBA_DQM7
AF35
FBA_DQM6
AL34
FBA_DQM5
AL32
FBA_DQM4
AF32
FBA_DQM3
P30
FBA_DQM2
J 30
FBA_DQM1
H34
FBA_DQM0
P32
FBA_D63
AC35
FBA_D62
AB32
FBA_D61
AE33
FBA_D60
AE34
FBA_D59
AE35
FBA_D58
AF34
FBA_D57
AE32
FBA_D56
AF33
FBA_D55
AM35
FBA_D54
AM34
FBA_D53
AL35
FBA_D52
AJ 33
FBA_D51
AH32
FBA_D50
AH34
FBA_D49
AH35
FBA_D48
AH33
FBA_D47
AH30
FBA_D46
AJ 30
FBA_D45
AK32
FBA_D44
AK30
FBA_D43
AL33
FBA_D42
AM33
FBA_D41
AL31
FBA_D40
AN33
FBA_D39
AD30
FBA_D38
AC32
FBA_D37
AE30
FBA_D36
AF30
FBA_D35
AF31
FBA_D34
AH31
FBA_D33
AG32
FBA_D32
AG30
FBA_D31
R30
FBA_D30
R32
FBA_D29
P31
FBA_D28
M30
FBA_D27
N30
FBA_D26
M32
FBA_D25
L30
FBA_D24
L31
FBA_D23
K31
FBA_D22
H30
FBA_D21
K32
FBA_D20
K30
FBA_D19
G32
FBA_D18
G30
FBA_D17
F30
FBA_D16
G31
FBA_D15
E33
FBA_D14
E34
FBA_D13
G33
FBA_D12
G34
FBA_D11
H33
FBA_D10
K34
FBA_D9
K33
FBA_D8
K35
FBA_D7
P34
FBA_D6
P33
FBA_D5
P35
FBA_D4
N35
FBA_D3
N34
FBA_D2
L33
FBA_D1
N33
FBA_D0
L32
FB_PLLAVDD
AF27
FB_DLLAVDD
AG27
FBA_DEBUG0
T30
FBA_CLK1#
AC30
FBA_CLK1
AC31
FBA_CLK0#
T31
FBA_CLK0
T32
FBA_CMD30
W29
FBA_CMD14
T33
FBA_CMD20
AB33
FBA_CMD16
AB30
FBA_CMD5
U33
FBA_CMD0
U30
FBA_CMD11
U35
FBA_CMD1
V30
FBA_CMD9
W34
FBA_CMD25
Y35
FBA_CMD10
U34
FBA_CMD28
Y31
FBA_CMD12
U32
FBA_CMD22
Y33
FBA_CMD19
AA32
FBA_CMD17
AA30
FBA_CMD6
W32
FBA_CMD27
Y34
FBA_CMD29
Y30
FBA_CMD18
AB31
FBA_CMD4
T35
FBA_CMD13
T34
FBA_CMD15
W30
FBA_CMD7
W33
FBA_CMD26
W35
FBA_CMD23
AB34
FBA_CMD24
AB35
FBA_CMD21
Y32
FBA_CMD2
U31
FBA_CMD8
W31
FBA_CMD3
V32
FBVDDQ
J 29
FBVDDQ
J 24
FBVDDQ
J 23
FBVDDQ
J 22
FBVDDQ
J 21
FBVDDQ
J 20
FBVDDQ
J 17
FBVDDQ
J 16
FBVDDQ
J 15
FBVDDQ
J 14
FBVDDQ
H29
FBVDDQ
G9
FBVDDQ
G8
FBVDDQ
G22
FBVDDQ
G18
FBVDDQ
G17
FBVDDQ
E21
FBVDDQ
B18
FBVDDQ
AJ 28
FBVDDQ
AE27
FBVDDQ
AD27
FBVDDQ
AC27
FBVDDQ
AB29
FBVDDQ
AB27
FBVDDQ
AA31
FBVDDQ
AA29
FBVDDQ
AA27
FBA_DEBUG1
T29
FBA_CMD31
Y29
FB_DLLAVDD
J 19
FB_PLLAVDD
J 18
FBA
2 OF 16 VGA2B
N12P-GE-A1-GP
OPTIMUS
FBA
2 OF 16 VGA2B
N12P-GE-A1-GP
OPTIMUS
1
2
C8426 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8426 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
3
4 5
6
7
8
RN8402
SRN10KJ -6-GP
Optimus RN8402
SRN10KJ -6-GP
Optimus
FBB_WCK3#
G25
FBB_WCK3
G24
FBB_WCK2#
G28
FBB_WCK2
G27
FBB_WCK1#
G12
FBB_WCK1
G11
FBB_WCK0#
G15
FBB_WCK0
G14
FBB_DQS_RN7
A26
FBB_DQS_RN6
A31
FBB_DQS_RN5
D31
FBB_DQS_RN4
F26
FBB_DQS_RN3
E14
FBB_DQS_RN2
D9
FBB_DQS_RN1
B10
FBB_DQS_RN0
B14
FBB_DQS_WP7
B26
FBB_DQS_WP6
A32
FBB_DQS_WP5
D32
FBB_DQS_WP4
E26
FBB_DQS_WP3
D14
FBB_DQS_WP2
E10
FBB_DQS_WP1
A10
FBB_DQS_WP0
C14
FBB_DQM7
D28
FBB_DQM6
A34
FBB_DQM5
D34
FBB_DQM4
D27
FBB_DQM3
D15
FBB_DQM2
F11
FBB_DQM1
D10
FBB_DQM0
A16
FBB_D63
A25
FBB_D62
B25
FBB_D61
D25
FBB_D60
C26
FBB_D59
C28
FBB_D58
A28
FBB_D57
B28
FBB_D56
A29
FBB_D55
B34
FBB_D54
B35
FBB_D53
B32
FBB_D52
C32
FBB_D51
B31
FBB_D50
C29
FBB_D49
C31
FBB_D48
B29
FBB_D47
E29
FBB_D46
D30
FBB_D45
F29
FBB_D44
C33
FBB_D43
E31
FBB_D42
D33
FBB_D41
F32
FBB_D40
E32
FBB_D39
E25
FBB_D38
D24
FBB_D37
F25
FBB_D36
D26
FBB_D35
E28
FBB_D34
F28
FBB_D33
F27
FBB_D32
D29
FBB_D31
F17
FBB_D30
F16
FBB_D29
E16
FBB_D28
F15
FBB_D27
F14
FBB_D26
F13
FBB_D25
E13
FBB_D24
D12
FBB_D23
E11
FBB_D22
D11
FBB_D21
D8
FBB_D20
F12
FBB_D19
F9
FBB_D18
F10
FBB_D17
F8
FBB_D16
E8
FBB_D15
A8
FBB_D14
B8
FBB_D13
C8
FBB_D12
C10
FBB_D11
A11
FBB_D10
C11
FBB_D9
B11
FBB_D8
C13
FBB_D7
D16
FBB_D6
A17
FBB_D5
B16
FBB_D4
C16
FBB_D3
A14
FBB_D2
A13
FBB_D1
D13
FBB_D0
B13
FB_CAL_TERM_GND
M27
FB_CAL_PU_GND
L27
FB_CAL_PD_VDDQ
K27
FBB_DEBUG0
G19
FBB_CLK1#
E23
FBB_CLK1
D23
FBB_CLK0#
D17
FBB_CLK0
E17
FBB_CMD9
D20
FBB_CMD8
B19
FBB_CMD7
E20
FBB_CMD6
B17
FBB_CMD5
C19
FBB_CMD4
F19
FBB_CMD30
A20
FBB_CMD3
C17
FBB_CMD29
A22
FBB_CMD28
B22
FBB_CMD27
C22
FBB_CMD26
B23
FBB_CMD25
D22
FBB_CMD24
A23
FBB_CMD23
D21
FBB_CMD22
E22
FBB_CMD21
F21
FBB_CMD20
C23
FBB_CMD2
D18
FBB_CMD19
C25
FBB_CMD18
F23
FBB_CMD17
F24
FBB_CMD16
F22
FBB_CMD15
G21
FBB_CMD14
B20
FBB_CMD13
F20
FBB_CMD12
C20
FBB_CMD11
D19
FBB_CMD10
A19
FBB_CMD1
E19
FBB_CMD0
F18
FBVDDQ
Y27
FBVDDQ
W27
FBVDDQ
V34
FBVDDQ
V29
FBVDDQ
V27
FBVDDQ
U29
FBVDDQ
U27
FBVDDQ
T27
FBVDDQ
R27
FBVDDQ
P27
FBVDDQ
N27
FBB_DEBUG1
G16
FBB_CMD31
G20
FBB
3 OF 16 VGA2C
N12P-GE-A1-GP
OPTIMUS
FBB
3 OF 16 VGA2C
N12P-GE-A1-GP
OPTIMUS
1
2
C8424 S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
Optimus
C8424 S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
Optimus
1 2
L8401
0R0603-PAD-2-GP
Optimus
L8401
0R0603-PAD-2-GP
Optimus
1 2
R8404 40D2R2F-GP
Optimus
R8404 40D2R2F-GP
Optimus
1 2
R8401
10KR2J -3-GP
Optimus
R8401
10KR2J -3-GP
Optimus
1
2
C8414 S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
C8414 S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
1
2
C8419S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8419S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1 2
R8403
10KR2J -3-GP
Optimus
R8403
10KR2J -3-GP
Optimus
1 2
R8405 40D2R2F-GP
Optimus
R8405 40D2R2F-GP
Optimus
1 2
L8402
0R0603-PAD-2-GP
Optimus
L8402
0R0603-PAD-2-GP
Optimus
1
2
C8422 S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
DY
C8422 S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
DY
1
2
C8413 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
C8413 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
1
2
C8421S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8421S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
3
4 5
6
7
8
RN8401
SRN10KJ -6-GP
Optimus RN8401
SRN10KJ -6-GP
Optimus
1
2
C8412 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8412 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8411S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
C8411S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
1 TP8415
TPAD14-GP
TP8415
TPAD14-GP
1
2
C8423 S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
C8423 S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
1 2
R8402 60D4R2F-GP
Optimus
R8402 60D4R2F-GP
Optimus
1
2
C8425
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8425
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8415 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8415 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8417S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8417S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8420S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8420S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8418S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8418S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8416 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
C8416 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IFPCD_PLLVDD
IFPC_RSET
IFPCD_IOVDD
IFPCD_PLLVDD
IFPCD_IOVDD
IFPD_RSET
DACB_VDD DACA_VDD
U8501_2
GPU_HDMI_HPD
NV_I2CA_SCL
NV_I2CA_SDA
NV_I2CA_SCL
NV_I2CA_SDA
SMBC_INA219_C
SMBD_INA219_C
IFPAB_IOVDD
IFPAB_PLLVDD
IFPEF_IOVDD
IFPEF_PLLVDD
IFPAB_PLLVDD
IFPAB_IOVDD
IFPAB_IOVDD
IFPEF_PLLVDD
IFPEF_IOVDD
IFPEF_IOVDD
3D3V_VGA_S0
1V_VGA_S0
3D3V_S0
3D3V_VGA_S0
3D3V_VGA_S0
GPU_HDMI_CLK 51
GPU_HDMI_DATA 51
HDMI_DATA0 51
HDMI_DATA0# 51
HDMI_DATA1 51
HDMI_DATA1# 51
HDMI_DATA2 51
HDMI_DATA2# 51
HDMI_CLK 51
HDMI_CLK# 51
HDMI_HPD_DET 51
9025_PGOOD_1V 93
PEX_RST# 51,83,86
SMBD_INA219 43,92
SMBC_INA219 43,92
GPU_HDMI_HPD 51
Title
Date: Sheet of
Wistron Corporation
A00
N12P(3/6)_DAC
A2
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(3/6)_DAC
A2
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(3/6)_DAC
A2
QUEEN 15
<Variant Name>
If either IFPC or IFPD is used, then the whole IFPCD interface is
considered as being used. This is because IFPC and IFPD share one
macro design so one IO interface cannot be independently disabled.
In Optimus mode the GPU does not drive certain
interfaces. These interfaces should be treated as
unused and appropriate terminations per the GPU design
guide should be applied th the signal or the power
supply block.
If a DAC interface is not required, it should be disabled by:
1. Adding a pull-down to the DACx_VDD with a 10 kilohm resistor to GND.
2. All other DAC I/O pins can be left floating.
The following guidelines only apply to a fully unused IFP macro:
1. Pull down IFPxy_IOVDD with 10 kilohm resistor.
2. Pull down IFPxy_PLLVDD with 10 kilohm resistor.
3. The other IO pins can be NC; this includes unused data lines.
NEED CHECK PAGE 51.
Optimus systems with HDMI connected to GPU.
(Option A).
Ventura I2C must connect to I2CB_SCL & I2CB_SDA.
220mA
280mA
0723
NV suggest un-used I2C pull-up.
0804 swap
0927
0927
220ohm@100MHz ESR=0.05
300ohm@100MHz ESR=0.25
1009
10.28
X02 1110
A00
A00
A00
A00
A00
1
2
C8505S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
C8505S
C
1
U
6
D
3
V
2
K
X
-G
P
Optimus
IFPC_IOVDD
AJ 8
IFPC_RSET
AK7
IFPC_PLLVDD
AJ 9
GPIO1
K2
IFPC_L0
AM7
IFPC_L0#
AM6
IFPC_L1
AL5
IFPC_L1#
AM5
IFPC_L2
AM3
IFPC_L2#
AM4
IFPC_L3
AP1
IFPC_L3#
AR2
IFPC_AUX_I2CW_SCL
AP2
IFPC_AUX_I2CW_SDA#
AN3
IFPC
8 OF 16 VGA2H
N12P-GE-A1-GP
OPTIMUS
IFPC
8 OF 16 VGA2H
N12P-GE-A1-GP
OPTIMUS
1
2
C8516S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
C8516S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
1
2
R8515
2K2R2J -2-GP
VENTURA
R8515
2K2R2J -2-GP
VENTURA
1 2
L8502
0R0603-PAD-2-GP Optimus
L8502
1
2
C8507S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8507S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
1
2
R8505
100KR2J -1-GP
DY
R8505
100KR2J -1-GP
DY
1
2 3
4
RN8501
SRN2K2J -1-GP
Optimus
RN8501
SRN2K2J -1-GP
Optimus
1 2 R8513
0R2J -2-GP
DY
R8513
0R2J -2-GP
DY
IFPB_IOVDD
AG10
IFPA_IOVDD
AG9
IFPAB_RSET
AJ 11
IFPAB_PLLVDD
AK9
GPIO0
K1
IFPB_TXC
AP13
IFPB_TXC#
AN13
IFPB_TXD7
AN11
IFPB_TXD7#
AP11
IFPB_TXD6
AR11
IFPB_TXD6#
AR10
IFPB_TXD5
AP10
IFPB_TXD5#
AN10
IFPB_TXD4
AN8
IFPB_TXD4#
AP8
IFPA_TXC
AM11
IFPA_TXC#
AM12
IFPA_TXD3
AK11
IFPA_TXD3#
AL11
IFPA_TXD2
AK10
IFPA_TXD2#
AL10
IFPA_TXD1
AM10
IFPA_TXD1#
AM9
IFPA_TXD0
AM8
IFPA_TXD0#
AL8
IFPAB
7 OF 16 VGA2G
N12P-GE-A1-GP
OPTIMUS
IFPAB
7 OF 16 VGA2G
N12P-GE-A1-GP
OPTIMUS
1
2
C8511S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
C8511S
C
4
D
7
U
6
D
3
V
3
K
X
-G
P
Optimus
1 2 R8510
0R2J -2-GP
DY
R8510
0R2J -2-GP
DY
1
2
R8503
10KR2J -3-GP
Optimus R8503
10KR2J -3-GP
Optimus
B
1
A
2
GND
3
Y
4
VCC
5
U8501
74LVC1G08GW-1-GP
2ND = 73.7SZ08.DAH
73.01G08.L04
DY
U8501
74LVC1G08GW-1-GP
2ND = 73.7SZ08.DAH
73.01G08.L04
DY
IFPF_IOVDD
AD7
IFPE_IOVDD
AE7
IFPEF_RSET
AL1
IFPEF_PLLVDD
AJ 6
GPIO21
K6
IFPF_L0
AL2
IFPF_L0#
AL3
IFPF_L1
AJ 3
IFPF_L1#
AJ 2
IFPF_L2
AJ 1
IFPF_L2#
AH1
IFPF_L3
AH2
IFPF_L3#
AH3
IFPF_AUX_I2CZ_SCL
AF3
IFPF_AUX_I2CZ_SDA#
AF2
GPIO15
L1
IFPE_L0
AH6
IFPE_L0#
AH5
IFPE_L1
AH4
IFPE_L1#
AG4
IFPE_L2
AF4
IFPE_L2#
AF5
IFPE_L3
AE6
IFPE_L3#
AE5
IFPE_AUX_I2CY_SCL
AE4
IFPE_AUX_I2CY_SDA#
AD4
IFPEF
9 OF 16 VGA2I
N12P-GE-A1-GP
OPTIMUS
IFPEF
9 OF 16 VGA2I
N12P-GE-A1-GP
OPTIMUS
1
2
R8508
1KR2F-3-GP Optimus
R8508
1KR2F-3-GP Optimus
DACB_RSET
AH7
DACB_VREF
AK6
DACB_VDD
AG7
DACB_BLUE
AJ 4
DACB_GREEN
AL4
DACB_RED
AK4
DACB_VSYNC
AM2
DACB_HSYNC
AM1
I2CB_SDA
G2
I2CB_SCL
G3
DACB
6 OF 16 VGA2F
N12P-GE-A1-GP
OPTIMUS
DACB
6 OF 16 VGA2F
N12P-GE-A1-GP
OPTIMUS
12
3 4
RN8502
SRN10KJ -5-GP Optimus
RN8502
1 2 R8512 0R0402-PAD-2-GP
VENTURA
R8512 0R0402-PAD-2-GP
VENTURA
12
3 4
RN8503
RN8503
1
2
C8512S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8512S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
1
2
C8508S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
C8508S
C
D
1
U
1
0
V
2
K
X
-5
G
P
Optimus
1
2
R8507
10KR2J -3-GP Optimus
R8507
10KR2J -3-GP Optimus
1
2
R8509
1KR2F-3-GP
Optimus
R8509
1KR2F-3-GP
Optimus
IFPD_IOVDD
AK8
IFPD_RSET
AB6
IFPD_PLLVDD
AC6
GPIO19
L7
IFPD_L0
AR8
IFPD_L0#
AR7
IFPD_L1
AP7
IFPD_L1#
AN7
IFPD_L2
AN5
IFPD_L2#
AP5
IFPD_L3
AR5
IFPD_L3#
AR4
IFPD_AUX_I2CX_SCL
AP4
IFPD_AUX_I2CX_SDA#
AN4
IFPD
5 OF 16 VGA2E
N12P-GE-A1-GP
OPTIMUS
IFPD
5 OF 16 VGA2E
N12P-GE-A1-GP
OPTIMUS
1
2
C8506S
C
1
U
6
D
3
V
2
K
X
-G
P
DY
C8506S
C
1
U
6
D
3
V
2
K
X
-G
P
DY
DACA_RSET
AK13
DACA_VREF
AK12
DACA_VDD
AJ 12
DACA_BLUE
AL14
DACA_GREEN
AM14
DACA_RED
AM15
DACA_VSYNC
AL13
DACA_HSYNC
AM13
I2CA_SDA
G4
I2CA_SCL
G1
DACA
4 OF 16 VGA2D
N12P-GE-A1-GP
OPTIMUS
DACA
4 OF 16 VGA2D
N12P-GE-A1-GP
OPTIMUS
1 2 R8511 0R0402-PAD-2-GP
VENTURA
R8511 0R0402-PAD-2-GP
VENTURA 1
2
R8514
2K2R2J -2-GP
VENTURA
R8514
2K2R2J -2-GP
VENTURA
1 2
L8503
L8503
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SMBC_THERM_NV
SMBD_THERM_NV
PWRCNTL_0
NV_OVERTEMP#
NV_GPIO9
PWRCNTL_1
MIOA_CLKIN_NC
MIOB_CLKIN_NC
NV_LCD_EDID_CLK
NV_LCD_EDID_DAT
SMBC_THERM_NV
SMBD_THERM_NV
MIOB_VDDQ
NV_OVERTEMP#
NV_GPIO9
MIOB_CLKIN_NC
MIOA_CLKIN_NC
J TAG_TCK_VGA
J TAG_TRST#
NV_TMS
NV_TDI
NV_TDO
NV_GPIO7
PWR_LEVEL
GPU_GPIO23
PWR_LEVEL
MIOA_VDDQ
NV_OVERTEMP#
Q8602_G
P2800_VGA_DXN
P2800_VGA_DXP
3D3V_VGA_S0
3D3V_VGA_S0
3D3V_VGA_S0
3D3V_VGA_S0
3D3V_VGA_S0
3D3V_VGA_S0
PWRCNTL_0 92
PWRCNTL_1 92
SML1_CLK 20,27
SML1_DATA 20,27
J TAG_TCK_VGA 20
AC_PRESENT 19,27
PEX_RST# 51,83,85
Title
Date: Sheet of
Wistron Corporation
A00
N12P(5/6)_MIO/ GPIO
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(5/6)_MIO/ GPIO
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(5/6)_MIO/ GPIO
A3
QUEEN 15
<Variant Name>
MIOx_CLKIN signals should
have 10K pull-down
resistors.
MIOA/B Support
GB1-192
GB2-128
Package MIOA MIOB
15-bit, available TBD
Not available Not available
0728
GPIO12
1 - > AC mode.
0 -> Battery mode.
0723
0728 Reserve for N12M.
0728 Reserve for N12M.
0915
0915
0915
A00 1231 add probe point
1
2
C8601S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
DY
C8601S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
DY
1 2
34
RN8606
SRN10KJ -5-GP
Optimus
RN8606
SRN10KJ -5-GP
Optimus
1 2
R8606
0R2J -2-GP
DY R8606
0R2J -2-GP
DY
NC#AF1
AF1
NC#AA6
AA6
NC#AA7
AA7
NC#Y9
Y9
NC#W9
W9
NC#AB9
AB9
NC#AA9
AA9
NC#AE1
AE1
NC#W4
W4
NC#V4
V4
NC#Y5
Y5
NC#W2
W2
NC#W1
W1
NC#W3
W3
NC#Y6
Y6
NC#W6
W6
NC#U6
U6
NC#AE2
AE2
NC#AE3
AE3
NC#AC3
AC3
NC#AC2
AC2
NC#AC1
AC1
NC#AC4
AC4
NC#AB1
AB1
NC#AB2
AB2
NC#AB3
AB3
NC#Y3
Y3
NC#Y2
Y2
NC#Y1
Y1
11 OF 16 VGA2K
N12P-GE-A1-GP
OPTIMUS
11 OF 16 VGA2K
N12P-GE-A1-GP
OPTIMUS
1 2
R8602 0R2J -2-GP
DY
R8602 0R2J -2-GP
DY
1TP8609 TPAD14-GP TP8609 TPAD14-GP
J TAG_TRST#
AP16
J TAG_TDO
AN16
J TAG_TDI
AN14
J TAG_TMS
AR14
J TAG_TCK
AP14
THERMDP
B5
THERMDN
B4
GPIO23
M6
GPIO22
L6
GPIO20
L5
GPIO18
M4
GPIO17
L4
GPIO16
L2
GPIO14
J 6
GPIO13
J 4
GPIO12
H7
GPIO11
K5
GPIO10
K4
GPIO9
J 7
GPIO8
H6
GPIO7
H5
GPIO6
H4
GPIO5
H1
GPIO4
H2
GPIO3
H3
GPIO2
K3
I2CC_SDA
E4
I2CC_SCL
E3
I2CS_SDA
E1
I2CS_SCL
E2
GPIO24
M7
MISC1
12 OF 16 VGA2L
N12P-GE-A1-GP
OPTIMUS
MISC1
12 OF 16 VGA2L
N12P-GE-A1-GP
OPTIMUS
1
2
R8603
10KR2J -3-GP
Optimus
R8603
10KR2J -3-GP
Optimus
1
2
3 4
5
6
Q8601
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
Optimus
Q8601
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
Optimus
1
2
C8603
SCD1U10V2KX-4GP
DY
C8603
SCD1U10V2KX-4GP
DY
1 2
34
RN8603
SRN2K2J -1-GP
Optimus
RN8603
SRN2K2J -1-GP
Optimus
1
2
C8602S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
DY
C8602S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
DY
1
2
R8605
10KR2J -3-GP
Optimus
R8605
10KR2J -3-GP
Optimus
1
2
3
D8601
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
D8601
BAS16-6-GP
2ND = 83.00016.F11
83.00016.K11
NC#N5
N5
NC#T5
T5
NC#U5
U5
NC#U9
U9
NC#T9
T9
NC#R9
R9
NC#P9
P9
NC#N4
N4
NC#T4
T4
NC#R4
R4
NC#N2
N2
NC#L3
L3
NC#N3
N3
NC#P5
P5
NC#N6
N6
NC#T6
T6
NC#R6
R6
NC#U3
U3
NC#U2
U2
NC#U1
U1
NC#U4
U4
NC#T1
T1
NC#T2
T2
NC#T3
T3
NC#P3
P3
NC#P2
P2
NC#P1
P1
NC#P4
P4
NC#N1
N1
10 OF 16 VGA2J
N12P-GE-A1-GP
OPTIMUS
10 OF 16 VGA2J
N12P-GE-A1-GP
OPTIMUS
1
TP8611
TPAD14-GP
TP8611
TPAD14-GP
1
2 3
4
RN8601
SRN10KJ -5-GP
Optimus
RN8601
SRN10KJ -5-GP
Optimus
1
2 3
4
RN8605
SRN2K2J -1-GP
Optimus
RN8605
SRN2K2J -1-GP
Optimus
1 2
R8601 0R2J -2-GP
DY
R8601 0R2J -2-GP
DY
1 2
34
RN8602
RN8602
G
S
D
Q8602
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
Q8602
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
DY
1
2
R8604
10KR2J -3-GP
Optimus
R8604
10KR2J -3-GP
Optimus
1
TP8612
TPAD14-GP
TP8612
TPAD14-GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VGA_CORE VGA_CORE
VGA_CORE
VGA_CORE
Title
Date: Sheet of
Wistron Corporation
A00
N12P(6/6)_POWER
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(6/6)_POWER
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
N12P(6/6)_POWER
A3
QUEEN 15
<Variant Name>
0728
Under GPU
0728
Near GPU
0818
De-cap
0818
De-cap
VDD
P19
VDD
P17
VDD
P15
VDD
P13
VDD
P11
VDD
M24
VDD
M22
VDD
M20
VDD
M18
VDD
M16
VDD
M14
VDD
M12
VDD
L25
VDD
L24
VDD
L23
VDD
L22
VDD
L21
VDD
L20
VDD
L19
VDD
L18
VDD
L17
VDD
L16
VDD
L15
VDD
L14
VDD
L13
VDD
L12
VDD
L11
VDD
AD24
VDD
AD22
VDD
AD18
VDD
AD16
VDD
AD14
VDD
AD12
VDD
AC25
VDD
AC24
VDD
AC23
VDD
AC22
VDD
AC21
VDD
AC20
VDD
AC19
VDD
AC18
VDD
AC17
VDD
AC16
VDD
AC15
VDD
AC14
VDD
AC13
VDD
AC12
VDD
AC11
VDD
AB25
VDD
AB23
VDD
AB21
VDD
AB19
VDD
AB17
VDD
AB15
VDD
AB13
VDD
AB11
VDD
Y24
VDD
Y22
VDD
Y20
VDD
Y18
VDD
Y16
VDD
Y14
VDD
Y12
VDD
W25
VDD
W24
VDD
W23
VDD
W22
VDD
W21
VDD
W20
VDD
W19
VDD
W18
VDD
W17
VDD
W16
VDD
W15
VDD
W14
VDD
W13
VDD
W12
VDD
W11
VDD
V25
VDD
V23
VDD
V21
VDD
V19
VDD
V17
VDD
V15
VDD
V13
VDD
V11
VDD
T24
VDD
T22
VDD
T20
VDD
T18
VDD
T16
VDD
T14
VDD
T12
VDD
R25
VDD
R24
VDD
R23
VDD
R22
VDD
R21
VDD
R20
VDD
R19
VDD
R18
VDD
R17
VDD
R16
VDD
R15
VDD
R14
VDD
R13
VDD
R12
VDD
R11
VDD
P25
VDD
P23
VDD
P21
NVVDD
16 OF 16 VGA2P
N12P-GE-A1-GP
OPTIMUS
NVVDD
16 OF 16 VGA2P
N12P-GE-A1-GP
OPTIMUS
1
2
C8721
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8721
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
GND
E12
GND
C34
GND
C2
GND
B9
GND
B6
GND
B33
GND
B30
GND
B3
GND
B27
GND
B24
GND
B21
GND
B15
GND
B12
GND
AP9
GND
AP6
GND
AP33
GND
AP30
GND
AP3
GND
AP27
GND
AP24
GND
AP21
GND
AP18
GND
AP15
GND
AP12
GND
AN34
GND
AN2
GND
AL9
GND
AL6
GND
AL30
GND
AL27
GND
AL24
GND
AL21
GND
AL18
GND
AL15
GND
AL12
GND
AK5
GND
AK34
GND
AK31
GND
AK2
GND
AG5
GND
AG34
GND
AG31
GND
AG2
GND
AE25
GND
AE24
GND
AE23
GND
AE22
GND
AE21
GND
AE20
GND
AE19
GND
AE18
GND
AE17
GND
AE16
GND
AE15
GND
AE14
GND
AE13
GND
AE12
GND
AE11
GND
AD5
GND
AD34
GND
AD31
GND
AD25
GND
AD23
GND
AD21
GND
AD2
GND
AD17
GND
AD15
GND
AD13
GND
AD11
GND
AC9
GND
AB24
GND
AB22
GND
AB20
GND
AB18
GND
AB16
GND
AB14
GND
AB12
GND
AA5
GND
AA34
GND
AA25
GND
AA24
GND
AA23
GND
AA22
GND
AA21
GND
AA20
GND
AA2
GND
AA19
GND
AA18
GND
AA17
GND
AA16
GND
AA15
GND
AA14
GND
AA13
GND
AA12
GND
AA11
GND
Y25
GND
Y23
GND
Y21
GND
Y19
GND
Y17
GND
Y15
GND
Y13
GND
Y11
GND
V9
GND
V5
GND
V31
GND
V24
GND
V22
GND
V20
GND
V2
GND
V18
GND
V16
GND
V14
GND
V12
GND
U25
GND
U24
GND
U23
GND
U22
GND
U21
GND
U20
GND
U19
GND
U18
GND
U17
GND
U16
GND
U15
GND
U14
GND
U13
GND
U12
GND
U11
GND
T25
GND
T23
GND
T21
GND
T19
GND
T17
GND
T15
GND
T13
GND
T11
GND
R5
GND
R34
GND
R31
GND
R2
GND
P24
GND
P22
GND
P20
GND
P18
GND
P16
GND
P14
GND
P12
GND
N25
GND
N24
GND
N23
GND
N22
GND
N21
GND
N20
GND
N19
GND
N18
GND
N17
GND
N16
GND
N15
GND
N14
GND
N13
GND
N12
GND
N11
GND
M5
GND
M34
GND
M31
GND
M25
GND
M23
GND
M21
GND
M2
GND
M19
GND
M17
GND
M15
GND
M13
GND
M11
GND
L9
GND
J 5
GND
J 34
GND
J 31
GND
J 2
GND
F5
GND
F34
GND
F31
GND
F2
GND
E9
GND
E6
GND
E30
GND
E27
GND
E24
GND
E18
GND
E15
GND
15 OF 16 VGA2O
N12P-GE-A1-GP
OPTIMUS
GND
15 OF 16 VGA2O
N12P-GE-A1-GP
OPTIMUS
1
2
C8710S
C
4
D
7
U
1
0
V
3
K
X
-
G
P
Optimus
C8710S
C
4
D
7
U
1
0
V
3
K
X
-
G
P
Optimus
1
2
C8708 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8708 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8711
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8711
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8716S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8716S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8712
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8712
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8725 S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
Optimus
C8725 S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
Optimus
1
2
C8703 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8703 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8724 S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
Optimus
C8724 S
C
2
2
U
6
D
3
V
5
M
X
-
2
G
P
Optimus
1
2
C8709 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C8709 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
C8713
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8713
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8702 S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
C8702 S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
1
2
C8717
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8717
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8701 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8701 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8714
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8714
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8718
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C8718
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
C8722
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
C8722
S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
DY
1
2
C8706 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8706 S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8705 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8705 S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8715
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8715
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8719
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C8719
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
C8707
S
C
D
0
4
7
U
2
5
V
2
K
X
-
G
P
DY
C8707
S
C
D
0
4
7
U
2
5
V
2
K
X
-
G
P
DY
1
2
C8723 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
C8723 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
1
2
C8720
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8720
S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8704S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8704S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FBA_VREF12
FBA_VREF12
FBA_ZQ0 FBA_ZQ1
FBA_VREF12
FBA_CMD_25
FBA_CMD_10
FBA_CMD_21
FBA_CMD_22
FBA_CMD_8
FBA_CMD_24
FBA_CMD_9
FBA_CMD_12
FBA_CMD_23
FBA_CMD_26
FBA_CMD_7
FBA_CMD_4
FBA_CMD_5
FBA_CMD_6
FBA_CMD_13
FBA_CMD_29
FBA_CMD_27
FBA_CMD_3
FBA_CMD_28
FBA_CMD_15
FBA_CMD_11
FBA_CMD_20
FBA_CMD_0
FBA_CMD_2
FBA_CMD_0
FBA_CMD_2
FBA_CMD_20
FBA_CMD_25
FBA_CMD_10
FBA_CMD_21
FBA_CMD_22
FBA_CMD_8
FBA_CMD_24
FBA_CMD_9
FBA_CMD_12
FBA_CMD_23
FBA_CMD_26
FBA_CMD_7
FBA_CMD_4
FBA_CMD_5
FBA_CMD_6
FBA_CMD_13
FBA_CMD_29
FBA_CMD_27
FBA_CMD_3
FBA_CMD_15
FBA_CMD_11
FBA_CMD_28
FBAD20
FBAD23
FBAD13
FBAD9
FBAD12
FBAD10
FBAD8
FBAD15
FBAD14
FBAD11
FBAD25
FBAD29
FBAD27
FBAD7
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD1
FBAD0
FBAD19
FBAD30
FBAD16
FBAD26
FBAD18
FBAD28
FBAD17
FBAD24
FBAD21
FBAD31
FBAD22
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0 1D5V_VGA_S0
1D5V_VGA_S0
FBAD[0..31] 84
FBA_CLK0# 84
FBA_CLK0 84
FBAD[0..31] 84
FBA_CLK0# 84
FBA_CLK0 84
FBA_CMD_25 84,89
FBA_CMD_10 84,89
FBA_CMD_21 84,89
FBA_CMD_22 84,89
FBA_CMD_8 84,89
FBA_CMD_24 84,89
FBA_CMD_9 84,89
FBA_CMD_12 84
FBA_CMD_23 84,89
FBA_CMD_26 84,89
FBA_CMD_7 84,89
FBA_CMD_4 84,89
FBA_CMD_5 84,89
FBA_CMD_6 84,89
FBA_CMD_13 84,89
FBA_CMD_29 84,89
FBA_CMD_27 84
FBA_CMD_3 84
FBA_CMD_28 84,89
FBA_CMD_15 84,89
FBA_CMD_11 84,89
FBA_CMD_20 84,89
FBA_CMD_0 84
FBA_CMD_2 84
FBA_CMD_0 84
FBA_CMD_2 84
FBA_CMD_20 84,89
FBA_CMD_25 84,89
FBA_CMD_10 84,89
FBA_CMD_21 84,89
FBA_CMD_22 84,89
FBA_CMD_8 84,89
FBA_CMD_24 84,89
FBA_CMD_9 84,89
FBA_CMD_12 84
FBA_CMD_23 84,89
FBA_CMD_26 84,89
FBA_CMD_7 84,89
FBA_CMD_4 84,89
FBA_CMD_5 84,89
FBA_CMD_6 84,89
FBA_CMD_13 84,89
FBA_CMD_29 84,89
FBA_CMD_27 84
FBA_CMD_3 84
FBA_CMD_15 84,89
FBA_CMD_11 84,89
FBA_CMD_28 84,89
FBADQM1 84
FBADQM2 84
FBADQSN1 84
FBADQSP1 84
FBADQSP2 84
FBADQSN2 84
FBADQM3 84
FBADQM0 84
FBADQSN3 84
FBADQSP3 84
FBADQSN0 84
FBADQSP0 84
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(1/4)
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(1/4)
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(1/4)
A3
QUEEN 15
<Variant Name>
Modified in SB
A15
A10
BA2
BA0
RST
ODT
BA1
A13
CKE
RAS*
CAS*
CS0*
CS1*
DRAMFunction
A11
32..63
A7
A9
A6
CS0*
CS1*
0..31
ODT
CKE
A3
A8
A1
A12
A3
A2
BA1
A13
CMD7
CMD6
CMD0
CMD1
CMD2
CMD3
Mode E
GB2-128
CMD4
CMD5
CMD2
Single Rank
GB1-128 Mode C
CMD10
CMD25
CMD23
CMD26
CMD14
CMD0
CMD8
CMD9
CMD7
CMD27
CMD16
CMD11
CMD15
CMD29
CMD18
CMD24
CMD20
CMD22
A5
A6
A1
A9
A15
WE*
BA2
BA0
A7
A5
CMD27
CMD23
CMD28
CMD25
CMD24
CMD26
CMD22
CMD21 CMD3
CMD4
CMD5
CMD6
CMD28
CMD17
CMD30
CMD21
CMD13
CMD19
CMD12
A4
WE*
CMD20
CMD19
CMD18
CMD17
CMD16
CMD15
CMD14
CMD13
CMD12
CMD11
CMD8
A0 A12
A8
A0
A14
CAS*
RST
A4
A11
A2
A10
CMD29
CMD30
A14
RAS*
CMD10
CMD9
CMD1
Frame Buffer Patition A Lower 32 bits.
0729
0729
0729
0729
0730 swap pin
0818
De-cap
0818
De-cap
0818
De-cap
0818
De-cap
0818
De-cap
0818
De-cap
0818
De-cap
1112 X02 Modify:
All of VRAM PCB footprint change to CO-LAY type
(DUMMY-BGA96D075133H48) from BGA96D0913H48
1112 X02 Modify:
1
2
C8821S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
DY
C8821S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
DY
1
2
C8823
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
C8823
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
1
2
C8820
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8820
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8839
SCD01U50V2KX-1GP
Optimus
C8839
SCD01U50V2KX-1GP
Optimus
1
2
R8801
1K05R2F-GP
Optimus
R8801
1K05R2F-GP
Optimus
1
2
R8802
1K05R2F-GP
Optimus
R8802
1K05R2F-GP
Optimus
1
2
C8806S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8806S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8811S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8811S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8814
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8814
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8816
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8816
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8836 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
C8836 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
1
2
C8813
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8813
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8803S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8803S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8809S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8809S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8818
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
C8818
S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
1
2
TC8801
ST100U6D3VBM-16GP
DY
TC8801
ST100U6D3VBM-16GP
DY
1 2 R8807
160R3F-1-GP
OptimusR8807
160R3F-1-GP
Optimus
1
2
C8835S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
Optimus
C8835S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
Optimus
1
2
C8822S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
C8822S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
DY
1
2
TC8802
ST100U6D3VBM-16GP
DY
TC8802
ST100U6D3VBM-16GP
DY
1
2
C8826
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8826
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8812S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8812S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8834S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
Optimus
C8834S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
Optimus
1
2
C8824
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8824
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8808S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8808S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8840S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
C8840S
C
D
1
U
1
0
V
2
K
X
-
4
G
P
Optimus
1
2
C8815S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8815S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
DQSL
F3
DQSL#
G3
DQSU#
B7
DQSU
C7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
ODT
K1
RESET#
T2
CS#
L2
NC#J 1
J 1
NC#J 9
J 9
NC#L1
L1
NC#L9
L9
NC#M7
M7
NC#T7
T7
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J 2
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
ZQ
L8
VDD
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VREFCA
M8
VREFDQ
H1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
A13
T3
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK#
K7
CKE
K9
DML
E7
DMU
D3
CAS#
K3
WE#
L3
RAS#
J 3
DQL7
H7
DQL6
G2
DQL5
H8
DQL4
H3
DQL3
F8
DQL2
F2
DQL1
F7
DQL0
E3
FBRAM1
H5TQ2G63BFR-11C-GP
Optimus
PCB Footprint = BGA96D0913H48
72.52G63.A0U
2nd = 72.41164.I0U
FBRAM1
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
1
2
C8804S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
C8804S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
1
2
C8810S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8810S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8829
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8829
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1 2
R8804
243R2F-2-GP
Optimus
R8804
243R2F-2-GP
Optimus
1
2
C8817
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8817
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
DQSL
F3
DQSL#
G3
DQSU#
B7
DQSU
C7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
ODT
K1
RESET#
T2
CS#
L2
NC#J 1
J 1
NC#J 9
J 9
NC#L1
L1
NC#L9
L9
NC#M7
M7
NC#T7
T7
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J 2
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
ZQ
L8
VDD
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VREFCA
M8
VREFDQ
H1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
A13
T3
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK#
K7
CKE
K9
DML
E7
DMU
D3
CAS#
K3
WE#
L3
RAS#
J 3
DQL7
H7
DQL6
G2
DQL5
H8
DQL4
H3
DQL3
F8
DQL2
F2
DQL1
F7
DQL0
E3
FBRAM2
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
FBRAM2
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
1
2
C8837 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
C8837 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
1
2
C8838S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
Optimus
C8838S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
Optimus
1
2
C8802S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8802S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1 2
C8801
SCD01U50V2KX-1GP
Optimus C8801
SCD01U50V2KX-1GP
Optimus
1
2
C8830 S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
Optimus
C8830 S
C
D
0
1
U
1
6
V
2
K
X
-
3
G
P
Optimus
1
2
C8807S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8807S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8828S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
DY
C8828S
C
D
0
1
U
5
0
V
2
K
X
-
1
G
P
DY
1
2
C8827
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8827
S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1
2
C8833 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
C8833 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
1
2
C8819S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
C8819S
C
D
1
U
1
0
V
2
K
X
-
5
G
P
Optimus
1
2
C8831S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
Optimus
C8831S
C
1
0
U
6
D
3
V
3
M
X
-
G
P
Optimus
1
2
C8805S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
C8805S
C
1
U
6
D
3
V
2
K
X
-
G
P
Optimus
1 2 R8803
243R2F-2-GP
Optimus
R8803
243R2F-2-GP
Optimus
1
2
C8825
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
C8825
S
C
1
U
6
D
3
V
2
K
X
-
G
P
DY
1
2
C8832 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
C8832 S
C
4
D
7
U
6
D
3
V
3
K
X
-
G
P
Optimus
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FBA_VREF34
FBA_VREF34
FBA_ZQ2
FBA_VREF34
FBA_ZQ3
FBA_CMD_7
FBA_CMD_14
FBA_CMD_24
FBA_CMD_10
FBA_CMD_5
FBA_CMD_8
FBA_CMD_21
FBA_CMD_28
FBA_CMD_4
FBA_CMD_23
FBA_CMD_9
FBA_CMD_26
FBA_CMD_22
FBA_CMD_13
FBA_CMD_29
FBA_CMD_6
FBA_CMD_30
FBA_CMD_16
FBA_CMD_25
FBA_CMD_15
FBA_CMD_11
FBA_CMD_20
FBA_CMD_19
FBA_CMD_18
FBA_CMD_7
FBA_CMD_14
FBA_CMD_24
FBA_CMD_10
FBA_CMD_5
FBA_CMD_8
FBA_CMD_21
FBA_CMD_28
FBA_CMD_4
FBA_CMD_23
FBA_CMD_9
FBA_CMD_26
FBA_CMD_22
FBA_CMD_13
FBA_CMD_29
FBA_CMD_6
FBA_CMD_30
FBA_CMD_16
FBA_CMD_15
FBA_CMD_11
FBA_CMD_25
FBA_CMD_18
FBA_CMD_20
FBA_CMD_19
FBAD41
FBAD40
FBAD42
FBAD44
FBAD46
FBAD47 FBAD37
FBAD32
FBAD38
FBAD33
FBAD39
FBAD36
FBAD45
FBAD43
FBAD34
FBAD56
FBAD58
FBAD57
FBAD60
FBAD55
FBAD53
FBAD54
FBAD62
FBAD63
FBAD59
FBAD35
FBAD61
FBAD50
FBAD48
FBAD51
FBAD49
FBAD52
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
FBAD[32..63] 84
FBA_CLK1# 84
FBA_CLK1 84 FBA_CLK1# 84
FBA_CLK1 84
FBAD[32..63] 84
FBA_CMD_7 84,88
FBA_CMD_14 84
FBA_CMD_24 84,88
FBA_CMD_10 84,88
FBA_CMD_5 84,88
FBA_CMD_8 84,88
FBA_CMD_21 84,88
FBA_CMD_28 84,88
FBA_CMD_4 84,88
FBA_CMD_23 84,88
FBA_CMD_9 84,88
FBA_CMD_26 84,88
FBA_CMD_22 84,88
FBA_CMD_13 84,88
FBA_CMD_29 84,88
FBA_CMD_6 84,88
FBA_CMD_30 84
FBA_CMD_16 84
FBA_CMD_25 84,88
FBA_CMD_15 84,88
FBA_CMD_11 84,88
FBA_CMD_20 84,88
FBA_CMD_19 84
FBA_CMD_18 84
FBA_CMD_7 84,88
FBA_CMD_14 84
FBA_CMD_24 84,88
FBA_CMD_10 84,88
FBA_CMD_5 84,88
FBA_CMD_8 84,88
FBA_CMD_21 84,88
FBA_CMD_28 84,88
FBA_CMD_4 84,88
FBA_CMD_23 84,88
FBA_CMD_9 84,88
FBA_CMD_26 84,88
FBA_CMD_22 84,88
FBA_CMD_13 84,88
FBA_CMD_29 84,88
FBA_CMD_6 84,88
FBA_CMD_30 84
FBA_CMD_16 84
FBA_CMD_15 84,88
FBA_CMD_11 84,88
FBA_CMD_25 84,88
FBA_CMD_18 84
FBA_CMD_20 84,88
FBA_CMD_19 84
FBADQM4 84
FBADQSN4 84
FBADQSP4 84 FBADQSN5 84
FBADQSP5 84
FBADQM5 84
FBADQSN6 84
FBADQSP6 84
FBADQSP7 84
FBADQSN7 84
FBADQM6 84
FBADQM7 84
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(2/4)
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(2/4)
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(2/4)
A3
QUEEN 15
<Variant Name>
Frame Buffer Patition A Upper 32 bits.
0729
0729
0729
0729
0730 swap pin
0730 swap pin
0730 swap pin
0730 swap pin
0730 swap pin
0730 swap pin
0802 swap pin
1112 X02 Modify:
1112 X02 Modify:
DQSL
F3
DQSL#
G3
DQSU#
B7
DQSU
C7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
ODT
K1
RESET#
T2
CS#
L2
NC#J 1
J 1
NC#J 9
J 9
NC#L1
L1
NC#L9
L9
NC#M7
M7
NC#T7
T7
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J 2
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
ZQ
L8
VDD
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VREFCA
M8
VREFDQ
H1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
A13
T3
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK#
K7
CKE
K9
DML
E7
DMU
D3
CAS#
K3
WE#
L3
RAS#
J 3
DQL7
H7
DQL6
G2
DQL5
H8
DQL4
H3
DQL3
F8
DQL2
F2
DQL1
F7
DQL0
E3
FBRAM4
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
FBRAM4
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
1
2
R8901
1K05R2F-GP
Optimus R8901
1K05R2F-GP
Optimus
1 2 R8904
160R3F-1-GP
OptimusR8904
160R3F-1-GP
Optimus
1 2
C8901
SCD01U50V2KX-1GP
Optimus
C8901
SCD01U50V2KX-1GP
Optimus
1
2
C8902
SCD01U50V2KX-1GP
Optimus C8902
SCD01U50V2KX-1GP
Optimus
1 2 R8905
243R2F-2-GP
Optimus
R8905
243R2F-2-GP
Optimus
DQSL
F3
DQSL#
G3
DQSU#
B7
DQSU
C7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
ODT
K1
RESET#
T2
CS#
L2
NC#J 1
J 1
NC#J 9
J 9
NC#L1
L1
NC#L9
L9
NC#M7
M7
NC#T7
T7
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J 2
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
ZQ
L8
VDD
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VREFCA
M8
VREFDQ
H1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
A13
T3
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK#
K7
CKE
K9
DML
E7
DMU
D3
CAS#
K3
WE#
L3
RAS#
J 3
DQL7
H7
DQL6
G2
DQL5
H8
DQL4
H3
DQL3
F8
DQL2
F2
DQL1
F7
DQL0
E3
FBRAM3
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
FBRAM3
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
1 2 R8903
243R2F-2-GP
Optimus
R8903
243R2F-2-GP
Optimus
1
2
R8902
1K05R2F-GP
Optimus R8902
1K05R2F-GP
Optimus
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FBB_VREF12
FBB_ZQ0
FBB_VREF12
FBB_ZQ1
FBB_VREF12
FBB_CMD_25
FBB_CMD_10
FBB_CMD_21
FBB_CMD_22
FBB_CMD_8
FBB_CMD_24
FBB_CMD_9
FBB_CMD_12
FBB_CMD_23
FBB_CMD_26
FBB_CMD_7
FBB_CMD_4
FBB_CMD_5
FBB_CMD_6
FBB_CMD_0
FBB_CMD_2
FBB_CMD_20
FBB_CMD_13
FBB_CMD_29
FBB_CMD_27
FBB_CMD_3
FBB_CMD_15
FBB_CMD_11
FBB_CMD_28
FBB_CMD_0
FBB_CMD_2
FBB_CMD_20
FBB_CMD_25
FBB_CMD_10
FBB_CMD_21
FBB_CMD_22
FBB_CMD_8
FBB_CMD_24
FBB_CMD_9
FBB_CMD_12
FBB_CMD_23
FBB_CMD_26
FBB_CMD_7
FBB_CMD_4
FBB_CMD_5
FBB_CMD_6
FBB_CMD_13
FBB_CMD_29
FBB_CMD_27
FBB_CMD_3
FBB_CMD_15
FBB_CMD_11
FBB_CMD_28
FBBD18
FBBD21
FBBD10
FBBD9
FBBD8
FBBD11
FBBD2
FBBD6
FBBD1
FBBD28
FBBD26
FBBD31
FBBD22
FBBD29
FBBD20
FBBD0
FBBD7
FBBD5
FBBD4
FBBD15
FBBD12
FBBD14
FBBD13
FBBD16
FBBD19
FBBD23
FBBD17
FBBD25
FBBD3
FBBD27
FBBD24
FBBD30
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
FBB_CLK0 84
FBB_CLK0# 84
FBBD[0..31] 84
FBBDQSP2 84
FBBDQSN2 84
FBBDQM2 84
FBBDQSP3 84
FBBDQM3 84
FBBD[0..31] 84
FBBDQSN3 84
FBB_CLK0 84
FBB_CLK0# 84
FBB_CMD_25 84,91
FBB_CMD_10 84,91
FBB_CMD_21 84,91
FBB_CMD_22 84,91
FBB_CMD_8 84,91
FBB_CMD_24 84,91
FBB_CMD_9 84,91
FBB_CMD_12 84
FBB_CMD_23 84,91
FBB_CMD_26 84,91
FBB_CMD_7 84,91
FBB_CMD_4 84,91
FBB_CMD_5 84,91
FBB_CMD_6 84,91
FBB_CMD_0 84
FBB_CMD_2 84
FBB_CMD_20 84,91
FBB_CMD_13 84,91
FBB_CMD_29 84,91
FBB_CMD_27 84
FBB_CMD_3 84
FBB_CMD_15 84,91
FBB_CMD_11 84,91
FBB_CMD_28 84,91
FBB_CMD_0 84
FBB_CMD_2 84
FBB_CMD_20 84,91
FBB_CMD_25 84,91
FBB_CMD_10 84,91
FBB_CMD_21 84,91
FBB_CMD_22 84,91
FBB_CMD_8 84,91
FBB_CMD_24 84,91
FBB_CMD_9 84,91
FBB_CMD_12 84
FBB_CMD_23 84,91
FBB_CMD_26 84,91
FBB_CMD_7 84,91
FBB_CMD_4 84,91
FBB_CMD_5 84,91
FBB_CMD_6 84,91
FBB_CMD_13 84,91
FBB_CMD_29 84,91
FBB_CMD_27 84
FBB_CMD_3 84
FBB_CMD_15 84,91
FBB_CMD_11 84,91
FBB_CMD_28 84,91
FBBDQSN1 84 FBBDQSN0 84
FBBDQSP0 84 FBBDQSP1 84
FBBDQM1 84 FBBDQM0 84
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(3/4)
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(3/4)
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(3/4)
A3
QUEEN 15
<Variant Name>
Frame Buffer Patition B Lower 32 bits.
0729
0729 0729
0729
0730 swap pin 0730 swap pin
0730 swap pin 0730 swap pin
0802 swap
1112 X02 Modify:
1112 X02 Modify:
DQSL
F3
DQSL#
G3
DQSU#
B7
DQSU
C7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
ODT
K1
RESET#
T2
CS#
L2
NC#J 1
J 1
NC#J 9
J 9
NC#L1
L1
NC#L9
L9
NC#M7
M7
NC#T7
T7
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J 2
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
ZQ
L8
VDD
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VREFCA
M8
VREFDQ
H1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
A13
T3
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK#
K7
CKE
K9
DML
E7
DMU
D3
CAS#
K3
WE#
L3
RAS#
J 3
DQL7
H7
DQL6
G2
DQL5
H8
DQL4
H3
DQL3
F8
DQL2
F2
DQL1
F7
DQL0
E3
FBRAM6
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
FBRAM6
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
1
2
C9002
SCD01U50V2KX-1GP
Optimus
C9002
SCD01U50V2KX-1GP
Optimus
1 2 R9005
160R3F-1-GP
OptimusR9005
160R3F-1-GP
Optimus
1
2
R9003
1K05R2F-GP
Optimus
R9003
1K05R2F-GP
Optimus
DQSL
F3
DQSL#
G3
DQSU#
B7
DQSU
C7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
ODT
K1
RESET#
T2
CS#
L2
NC#J 1
J 1
NC#J 9
J 9
NC#L1
L1
NC#L9
L9
NC#M7
M7
NC#T7
T7
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J 2
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
ZQ
L8
VDD
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VREFCA
M8
VREFDQ
H1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
A13
T3
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK#
K7
CKE
K9
DML
E7
DMU
D3
CAS#
K3
WE#
L3
RAS#
J 3
DQL7
H7
DQL6
G2
DQL5
H8
DQL4
H3
DQL3
F8
DQL2
F2
DQL1
F7
DQL0
E3
FBRAM5
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
FBRAM5
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
1
2
R9004
1K05R2F-GP
Optimus
R9004
1K05R2F-GP
Optimus
1 2 R9001
243R2F-2-GP
Optimus
R9001
243R2F-2-GP
Optimus
1 2
C9001
SCD01U50V2KX-1GP
Optimus
C9001
SCD01U50V2KX-1GP
Optimus
1 2 R9002
243R2F-2-GP
Optimus
R9002
243R2F-2-GP
Optimus
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FBB_VREF34
FBB_ZQ2
FBB_VREF34
FBB_VREF34
FBB_ZQ3
FBB_CMD_18
FBB_CMD_20
FBB_CMD_19
FBB_CMD_7
FBB_CMD_14
FBB_CMD_24
FBB_CMD_10
FBB_CMD_5
FBB_CMD_8
FBB_CMD_21
FBB_CMD_28
FBB_CMD_4
FBB_CMD_23
FBB_CMD_9
FBB_CMD_26
FBB_CMD_22
FBB_CMD_13
FBB_CMD_29
FBB_CMD_6
FBB_CMD_30
FBB_CMD_16
FBB_CMD_15
FBB_CMD_11
FBB_CMD_25
FBB_CMD_18
FBB_CMD_20
FBB_CMD_19
FBB_CMD_7
FBB_CMD_14
FBB_CMD_24
FBB_CMD_10
FBB_CMD_5
FBB_CMD_8
FBB_CMD_21
FBB_CMD_28
FBB_CMD_4
FBB_CMD_23
FBB_CMD_9
FBB_CMD_26
FBB_CMD_22
FBB_CMD_13
FBB_CMD_29
FBB_CMD_6
FBB_CMD_30
FBB_CMD_16
FBB_CMD_15
FBB_CMD_11
FBB_CMD_25
FBBD42
FBBD45
FBBD41
FBBD46
FBBD44
FBBD43
FBBD51
FBBD50
FBBD48
FBBD49
FBBD54
FBBD35
FBBD34
FBBD33
FBBD47
FBBD63
FBBD59
FBBD58
FBBD56
FBBD60
FBBD57
FBBD62
FBBD39
FBBD37
FBBD32
FBBD36
FBBD38
FBBD40
FBBD61
FBBD52
FBBD55
FBBD53
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
1D5V_VGA_S0
FBB_CLK1 84
FBB_CLK1# 84
FBBD[32..63] 84
FBBDQSN4 84
FBBDQSP4 84
FBBDQM4 84
FBBDQSN5 84
FBB_CLK1 84
FBB_CLK1# 84
FBBDQSP5 84
FBBDQM5 84
FBBD[32..63] 84
FBB_CMD_18 84
FBB_CMD_20 84,90
FBB_CMD_19 84
FBB_CMD_7 84,90
FBB_CMD_14 84
FBB_CMD_24 84,90
FBB_CMD_10 84,90
FBB_CMD_5 84,90
FBB_CMD_8 84,90
FBB_CMD_21 84,90
FBB_CMD_28 84,90
FBB_CMD_4 84,90
FBB_CMD_23 84,90
FBB_CMD_9 84,90
FBB_CMD_26 84,90
FBB_CMD_22 84,90
FBB_CMD_13 84,90
FBB_CMD_29 84,90
FBB_CMD_6 84,90
FBB_CMD_30 84
FBB_CMD_16 84
FBB_CMD_15 84,90
FBB_CMD_11 84,90
FBB_CMD_25 84,90
FBB_CMD_18 84
FBB_CMD_20 84,90
FBB_CMD_19 84
FBB_CMD_7 84,90
FBB_CMD_14 84
FBB_CMD_24 84,90
FBB_CMD_10 84,90
FBB_CMD_5 84,90
FBB_CMD_8 84,90
FBB_CMD_21 84,90
FBB_CMD_28 84,90
FBB_CMD_4 84,90
FBB_CMD_23 84,90
FBB_CMD_9 84,90
FBB_CMD_26 84,90
FBB_CMD_22 84,90
FBB_CMD_13 84,90
FBB_CMD_29 84,90
FBB_CMD_6 84,90
FBB_CMD_30 84
FBB_CMD_16 84
FBB_CMD_15 84,90
FBB_CMD_11 84,90
FBB_CMD_25 84,90
FBBDQSN6 84
FBBDQSP6 84 FBBDQSN7 84
FBBDQSP7 84
FBBDQM6 84
FBBDQM7 84
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(4/4)
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(4/4)
A3
QUEEN 15
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
A00
VRAM(4/4)
A3
QUEEN 15
<Variant Name>
Frame Buffer Patition B Upper 32 bits.
0729
0729
0729
0729
0730 swap pin
0730 swap pin
0730 swap pin
0730 swap pin
0730 swap pin
0730 swap pin
0802 swap pin
1112 X02 Modify:
1112 X02 Modify:
DQSL
F3
DQSL#
G3
DQSU#
B7
DQSU
C7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
ODT
K1
RESET#
T2
CS#
L2
NC#J 1
J 1
NC#J 9
J 9
NC#L1
L1
NC#L9
L9
NC#M7
M7
NC#T7
T7
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J 2
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
ZQ
L8
VDD
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VREFCA
M8
VREFDQ
H1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
A13
T3
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK#
K7
CKE
K9
DML
E7
DMU
D3
CAS#
K3
WE#
L3
RAS#
J 3
DQL7
H7
DQL6
G2
DQL5
H8
DQL4
H3
DQL3
F8
DQL2
F2
DQL1
F7
DQL0
E3
FBRAM8
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
FBRAM8
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
1 2
R9101
243R2F-2-GP
Optimus
R9101
243R2F-2-GP
Optimus
1
2
C9102
SCD01U50V2KX-1GP
Optimus
C9102
SCD01U50V2KX-1GP
Optimus
DQSL
F3
DQSL#
G3
DQSU#
B7
DQSU
C7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
ODT
K1
RESET#
T2
CS#
L2
NC#J 1
J 1
NC#J 9
J 9
NC#L1
L1
NC#L9
L9
NC#M7
M7
NC#T7
T7
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J 2
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
ZQ
L8
VDD
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VREFCA
M8
VREFDQ
H1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
A13
T3
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK#
K7
CKE
K9
DML
E7
DMU
D3
CAS#
K3
WE#
L3
RAS#
J 3
DQL7
H7
DQL6
G2
DQL5
H8
DQL4
H3
DQL3
F8
DQL2
F2
DQL1
F7
DQL0
E3
FBRAM7
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
FBRAM7
H5TQ2G63BFR-11C-GP
Optimus
72.52G63.A0U
2nd = 72.41164.I0U
1 2 R9105
243R2F-2-GP
Optimus
R9105
243R2F-2-GP
Optimus
1
2
R9102
1K05R2F-GP
Optimus
R9102
1K05R2F-GP
Optimus
1 2
C9101
SCD01U50V2KX-1GP
Optimus
C9101
SCD01U50V2KX-1GP
Optimus
1 2 R9103
160R3F-1-GP
OptimusR9103
160R3F-1-GP
Optimus
1
2
R9104
1K05R2F-GP
Optimus
R9104
1K05R2F-GP
Optimus
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
J J
I I
H H
G G
F F
E E
D D
C C
B B
A A
8209A_EN/DEM_VGA
G
N
D
_
S
E
N
S
E
_
1
P
W
R
_
V
G
A
_
C
O
R
E
_
D
0
P
W
R
_
V
G
A
_
C
O
R
E
_
D
1
VGA_SENSE_R
PWR_VGA_CORE_VOUT
8209A_PGOOD_VGA
VGA_CORE_UGATE
VGA_CORE_LGATE
PWR_VGA_CORE_VOUT
PWR_VGA_CORE_D0
PWR_VGA_CORE_D1
PWR_VGA_CORE_FB
PWR_VGA_CORE_LGATE
PWR_VGA_CORE_UGATE
PWR_VGA_CORE_BOOT PWR_VGA_CORE_BOOT_C
PWR_VGA_CORE_PHASE
PWR_VGA_CORE_TON
PWR_VGA_CORE_VDD
8209A_PGOOD_VGA
PWR_VGA_CORE_CS
8209A_EN/DEM_VGA
PWR_VGA_CORE_FB
PU9205_A0
PU9205_A1
P
U
9
2
0
5
_
V
IN
-
P
U
9
2
0
5
_
V
IN
+
PWRCNTL_0
PWRCNTL_1
PWR_VGA_CORE_EN_R#
8209A_EN/DEM_VGA PQ9206_3
P
W
R
_
V
G
A
_
S
N
U
B
DCBATOUT_GPU
5V_S5
VGA_CORE
3D3V_VGA_S0
3D3V_VGA_S0
DCBATOUT DCBATOUT_GPU
3D3V_VGA_S0
3D3V_VGA_S0
3D3V_VGA_S0
VGA_CORE
3D3V_S5
DGPU_PWR_EN 93
VGA_SENSE 83
GND_SENSE 83
DGPU_PWROK 22,83,93
PWRCNTL_1 86
PWRCNTL_0 86
SMBC_INA219 43,85
SMBD_INA219 43,85
Title
Date: Sheet of
Wistron Corporation
A00
DC/DC_VGA CORE_RT8208A
QUEEN 15
J V10-CS
Title
Date: Sheet of
Wistron Corporation
A00
QUEEN 15
J V10-CS
Title
Date: Sheet of
Wistron Corporation
A00
QUEEN 15
J V10-CS
SSID = PWR.Plane.Regulator_GFX
Vout=0.75V*(R1+R2)/R2
Design Current = 32A
45<OCP<50A
ES
P8 & P12
P-State
P0(Hot)
L
L
PWRCNTL_0
0.853V
0.954V
(default boot up)
H
VGA_CORE_PWR
0.878V H
L
L
PWRCNTL_1
RT8208B
Frequency setting
470K -->165KHz
200K -->323KHz
100K -->500KHz
H H
20100702_PWR
P0(Cold)
Modify to PCMC135T-R36MF
0728
FOR NVIDIA VENTURA
0705 Modify
0705 Modify
0702 Modify:
Change U4306 power source to
3D3V_VGA_S0 from 3D3V_S0.
0712 Modify:
Change VENTURA solution part number to
74.00900.079 from 74.00219.079.
0705 Modify:
Removed PR9222 sense Resistor.
Add PR9215,PR9216,PC9201
0728
0607
0927
PL9201 change
like CPU core
power choke.
0.975V
(GPIO6) (GPIO5)
0805
0809
0915
0923 update table
PR9210//R9209//PR9213
PR9210//PR9213
R9210//PR9209
PR9210
0923
Update value of PR9210, PR9209 and PR9213
for N12P.
0928
Follow Brian suggestion.
A00 1223 not co-lay
A00 1224
1
2
PC9215
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
MUXLESS
PC9215
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
MUXLESS
1
2
PR9227
10KR2J -3-GP
DY
PR9227
10KR2J -3-GP
DY
1
2
PR9208
10KR2F-2-GP
MUXLESS
PR9208
10KR2F-2-GP
MUXLESS
1 2 PR9202 249KR2F-GP
MUXLESS
PR9202 249KR2F-GP
MUXLESS
1
2
R9226
3K3R2J -3-GP
VENTURA
R9226
3K3R2J -3-GP
VENTURA
1 2 PR9201
10R2F-L-GP
MUXLESS
PR9201
10R2F-L-GP
MUXLESS
1 2 PR9219
0R0402-PAD
PR9219
0R0402-PAD
1
2
PC9202
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
MUXLESS
PC9202
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
MUXLESS
1
2
P
C
9
2
0
8
S
C
D
1
U
1
0
V
2
K
X
-4
G
P
MUXLESS
P
C
9
2
0
8
S
C
D
1
U
1
0
V
2
K
X
-4
G
P
MUXLESS
1
2
PC9209
S
C
1
0
P
5
0
V
2
J
N
-4
G
P
DY
PC9209
S
C
1
0
P
5
0
V
2
J
N
-4
G
P
DY
1
2
PC9201
SC1U10V2KX-1GP
MUXLESS
PC9201
SC1U10V2KX-1GP
MUXLESS
123
4 5 6
PQ9206
DMN66D0LDW-7-GP DY
PQ9206
DMN66D0LDW-7-GP DY
1
2
PR9212
10KR2J -3-GP
MUXLESS
PR9212
10KR2J -3-GP
MUXLESS
1
2
PR9221
10R2F-L-GP
VENTURA
PR9221
10R2F-L-GP
VENTURA
1
2
PC9218
SC330P50V3KX-GP
DY
PC9218
SC330P50V3KX-GP
DY
1
2
PR9209
300KR2F-GP
MUXLESS
PR9209
300KR2F-GP
MUXLESS
1
2
PC9214
S
C
4
D
7
U
2
5
V
5
K
X
-G
P MUXLESS
PC9214
S
C
4
D
7
U
2
5
V
5
K
X
-G
P MUXLESS
1
2
PC9207
SC1U10V2KX-1GP
MUXLESS
PC9207
SC1U10V2KX-1GP
MUXLESS
1
2
PG9205
G
A
P
-C
L
O
S
E
-P
W
R
-3
-G
P
PG9205
G
A
P
-C
L
O
S
E
-P
W
R
-3
-G
P
1
2
PC9216
SCD1U10V2KX-5GP
VENTURA
PC9216
SCD1U10V2KX-5GP
VENTURA
1
2
PR9228
100KR2J -1-GP
DY
PR9228
100KR2J -1-GP
DY
1
2
R9213
75KR2F-GP
MUXLESS
R9213
75KR2F-GP
MUXLESS
1
2
R9227
3K3R2J -3-GP
DY
R9227
3K3R2J -3-GP
DY
1
2
PC9203
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
MUXLESS
PC9203
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
MUXLESS
1 2
PR9205
2D2R3-1-U-GP
MUXLESS
PR9205
2D2R3-1-U-GP
MUXLESS
1 2 PR9211
0R0402-PAD
PR9211
0R0402-PAD
1
2
PR9224
10KR2J -3-GP
DY
PR9224
10KR2J -3-GP
DY
1
2
PC9212
SC100P50V2J N-3GP
MUXLESS
PC9212
SC100P50V2J N-3GP
MUXLESS
1
23
PT9203
S
T
4
7
0
U
2
V
D
M
-6
-G
P
-U
2nd = 79.47719.9BL
77.24771.15L
MUXLESS
PT9203
S
T
4
7
0
U
2
V
D
M
-6
-G
P
-U
2nd = 79.47719.9BL
77.24771.15L
MUXLESS
1
2
PC9205
S
C
4
D
7
U
2
5
V
5
K
X
-G
P MUXLESS
PC9205
S
C
4
D
7
U
2
5
V
5
K
X
-G
P MUXLESS
1
2
PR9226
10KR2J -3-GP
MUXLESS
PR9226
10KR2J -3-GP
MUXLESS
1
2
PC9211
SCD1U10V2KX-4GP
MUXLESS
PC9211
SCD1U10V2KX-4GP
MUXLESS
1 2
PC9217
SCD1U25V2KX-GP
VENTURA
PC9217
SCD1U25V2KX-GP
VENTURA
1 2 PR9218
0R0402-PAD
PR9218
0R0402-PAD
1
2
PC9204
S
C
D
1
U
2
5
V
3
K
X
-G
P
MUXLESS
PC9204
S
C
D
1
U
2
5
V
3
K
X
-G
P
MUXLESS
1 2
PR9204 6K2R2F-GP
MUXLESS
PR9204 6K2R2F-GP
MUXLESS
1
2
P
R
9
2
0
3
1
0
R
2
J
-2
-G
P
MUXLESS
P
R
9
2
0
3
1
0
R
2
J
-2
-G
P
MUXLESS
1
23
PT9202
S
T
4
7
0
U
2
V
D
M
-6
-G
P
-U
2nd = 79.47719.9BL
77.24771.15L
MUXLESS
PT9202
S
T
4
7
0
U
2
V
D
M
-6
-G
P
-U
2nd = 79.47719.9BL
77.24771.15L
MUXLESS
1
2
PR9210
82KR2F-1-GP
MUXLESS
PR9210
82KR2F-1-GP
MUXLESS
1
2
PC9210
S
C
1
0
P
5
0
V
2
J
N
-4
G
P
DY
PC9210
S
C
1
0
P
5
0
V
2
J
N
-4
G
P
DY
1
2
PR9215
10R2F-L-GP
VENTURA
PR9215
10R2F-L-GP
VENTURA
1 2
PR9216
0R0402-PAD
PR9216
0R0402-PAD
1
2
PR9229
100R2J -2-GP DY
PR9229
100R2J -2-GP DY
1 2
PL9201
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
MUXLESS
PL9201
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
MUXLESS
1
23
PT9204
S
T
4
7
0
U
2
V
D
M
-6
-G
P
-U
2nd = 79.47719.9BL
77.24771.15L
MUXLESS
PT9204
S
T
4
7
0
U
2
V
D
M
-6
-G
P
-U
2nd = 79.47719.9BL
77.24771.15L
MUXLESS
1
2
R9225
3K3R2J -3-GP
DY
R9225
3K3R2J -3-GP
DY
1
2
PR9207
10R2J -2-GP
MUXLESS
PR9207
10R2J -2-GP
MUXLESS
1 2
3 4 5
6 7
S S G
DDDD
PU9205
IRF6725MTRPBF-GP-U
84.06725.030
MUXLESS
2nd = 84.17N03.030
S S G
DDDD
PU9205
IRF6725MTRPBF-GP-U
84.06725.030
MUXLESS
2nd = 84.17N03.030
1 2
3 4
5 6
S G
DDDD
PU9203
IRF6721SPBF-GP-U
84.06721.030
MUXLESS
2nd = 84.45N03.A30
S G
DDDD
PU9203
IRF6721SPBF-GP-U
84.06721.030
MUXLESS
2nd = 84.45N03.A30
1 2
3 4
5 6
S G
DDDD
PU9202
IRF6721SPBF-GP-U
84.06721.030
MUXLESS
2nd = 84.45N03.A30
S G
DDDD
PU9202
IRF6721SPBF-GP-U
84.06721.030
MUXLESS
2nd = 84.45N03.A30
V
IN
+
1
V
IN
-
2
G
N
D
3
V
S
4
S
C
L
5
S
D
A
6
A
0
7
A
1
8
PU9206
HPA00900AIDCNR-GP
VENTURA
74.00900.079
PU9206
HPA00900AIDCNR-GP
VENTURA
74.00900.079
1
2
PR9230
2D2R5F-2-GP
DY
PR9230
2D2R5F-2-GP
DY
VOUT
1
VDD
2
FB
3
PGOOD
4
D1
5
D0
6
G0
7
LGATE
8
VDDP
9
CS
10
PHASE
11
UGATE
12
BOOT
13
G1
14
EM/DEM
15
TON
16
GND
17
PU9201
RT8208BGQW-GP
MUXLESS
PU9201
RT8208BGQW-GP
MUXLESS
2 1
PD9201
CH551H-30PT-GP
DY
PD9201
CH551H-30PT-GP
DY
1
2
R9228
3K3R2J -3-GP
VENTURA
R9228
3K3R2J -3-GP
VENTURA
1 2 PR9206 10KR2J -3-GP
MUXLESS
PR9206 10KR2J -3-GP
MUXLESS
1 2
PR9217 D004R3720F-GP PR9217 D004R3720F-GP
1
2
PC9213
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
MUXLESS
PC9213
S
C
4
D
7
U
2
5
V
5
K
X
-G
P
MUXLESS
1 2
PC9206
SCD1U25V3KX-GP
MUXLESS
PC9206
SCD1U25V3KX-GP
MUXLESS
1
2
PR9225
10KR2J -3-GP
MUXLESS
PR9225
10KR2J -3-GP
MUXLESS
1 2 PR9214
0R0402-PAD
DY
PR9214
0R0402-PAD
DY
1 2
3 4 5
6 7
S S G
DDDD
PU9204
IRF6725MTRPBF-GP-U
84.06725.030
MUXLESS
2nd = 84.17N03.030
S S G
DDDD
PU9204
IRF6725MTRPBF-GP-U
84.06725.030
MUXLESS
2nd = 84.17N03.030
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1
D
5
V
_
E
N
A
B
L
E
_
R
C
D
IS
_
1
D
5
V
_
V
G
A
_
S
0
1D5V_VGA_EN#
1D5V_VGA_EN
1D5V_VGA_EN#
1D5V_ENABLE
9025_PGOOD_1V PWR_1V_PGOOD
PWR_1V_EN
3.3V_RUN_VGA_1
D
G
P
U
_
P
W
R
_
E
N
PWR_1V_VDD
PWR_1V_ADJ
PWR_1V_EN
PQ9308_3
PWR_1V_EN#
PR9319_1
PQ9302_G
1D5V_S3 1D5V_VGA_S0
1D5V_VGA_S0 3D3V_AUX_S5
15V_S5
3D3V_VGA_S0
3D3V_VGA_S0
3D3V_S0
3D3V_S0
3D3V_VGA_S0
1V_PWR 1V_VGA_S0
5V_S5
1D5V_S3
1V_VGA_S0
3D3V_S5
DGPU_PWROK 22,83,92
DGPU_PWR_EN 92
DGPU_PWR_EN 92
DGPU_PWR_EN# 18
DGPU_PWR_EN 92
9025_PGOOD_1V 85
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
DISCRETE VGA POWER
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
DISCRETE VGA POWER
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
DISCRETE VGA POWER
A2
<Core Design>
AO4468, SO-8
Id=?A, Qg=9~12nC
Rdson=17.4~22m ohm
Discharge Circuit
change low Rds(on) MOSFET
0628 Modify:
Change PU9305 part number to 84.04468.037 same as U3601&U3602.
1D5V_VGA_S0
0629 Modify:
Add PC9332 10uF 0603.
0628 Modify:
Simplify 1D5V_ENABLE control circuit.
Rmoved PQ9305,PR9327,PR9328 PQ9306.
G
G D
D
S
S
Park_Madison Does Not Support BACO, So follow Old Sequence
Seymour_Whistler_Robson Support BACO, So Change Sequence
0629 Modify:
Reserved PD9301 connect DGPU_PWR_EN to
PWR_1D5V_EN for power down sequence.
0629 Modify:
Reserved PD9302 connect DGPU_PWR_EN to
PWR_1V_EN for power down sequence.
VGA_Core should ramp-up before 1V_VGA_S0
1V_VGA_S0 should ramp up before 1D8V_VGA_S0
G9731F11U-GP for 1V_S0
so 1V_VGA_S0 EN have to fine tune RC delay
after VGA_Core
3D3V_VGA_S0 should ramp-up before VGA_Core
3D3V_S0 to 3D3V_VGA_S0 Transfer
3D3V_VGA discharge
dGPU mode
IGPU
IGPU with BACO
DGPU_PWR_EN#
L
H
L
0630 Modify
Change PR9312 to 10K 0402 from
0ohm and stuff PC9318.
0630 Modify:
Rename PWR_1D8V_EN to 1D8V_VGA_EN.
Rename PWR_1D5V_EN to 1D5V_VGA_EN.
NV do not need 1.8V
Vo(cal.)=1.05V
Iomax<4A
0714 Modify:
Change LDO to Max 4A.
Vout = 0.8 x
higih-side R + low-side R
low-side R
0728
0806
0915
0927
A00
A00 1224
A00 1224
A00 1224
A00 1224
2 1
PD9301
CH551H-30PT-GP
DY
PD9301
CH551H-30PT-GP
DY
1
2
3
4 5
6
7
8 S
S
S
G D
D
D
D
PU9305
AO4468-GP
84.04468.037
2nd = 84.08882.037
MUXLESS
S
S
S
G D
D
D
D
PU9305
AO4468-GP
84.04468.037
2nd = 84.08882.037
MUXLESS
1 2 PR9326
0R0402-PAD-2-GP
MUXLESS
PR9326
0R0402-PAD-2-GP
MUXLESS
1 2
PR9322 4K7R2F-GP
MUXLESS
PR9322 4K7R2F-GP
MUXLESS
1 2
PR9337
100KR2J -1-GP
MUXLESS
PR9337
100KR2J -1-GP
MUXLESS
1
2
PC9314
SC10U6D3V5MX-3GP MUXLESS
PC9314
SC10U6D3V5MX-3GP MUXLESS
1 2
PR9317
470R2J -2-GP
DY
PR9317
470R2J -2-GP
DY
1 2
PC9315
SC100P50V2J N-3GP
DY
PC9315
SC100P50V2J N-3GP
DY
G
S
D
PQ9304
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
MUXLESS
PQ9304
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
MUXLESS
1 2
PG9307
GAP-CLOSE-PWR
PG9307
GAP-CLOSE-PWR
1
2
PR9336
470R2J -2-GP
MUXLESS
PR9336
470R2J -2-GP
MUXLESS
1
2
PC9327
S
C
1
0
U
6
D
3
V
3
M
X
-G
P
MUXLESS
PC9327
S
C
1
0
U
6
D
3
V
3
M
X
-G
P
MUXLESS
1
2
PC9316
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
DY
PC9316
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
DY
2 1
PD9302
CH551H-30PT-GP
DY
PD9302
CH551H-30PT-GP
DY
1
2
P
C
9
3
1
8
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
P
C
9
3
1
8
S
C
D
1
U
1
0
V
2
K
X
-5
G
P
DY
GND
1
VEN
8
VIN
5
VO#4
4
POK
7
VO#3
3
ADJ
2
VPP
6
GND
9
PU9303
G9731F11U-GP
MUXLESS
2nd = 74.05930.03D
74.G9731.03D
PU9303
G9731F11U-GP
MUXLESS
2nd = 74.05930.03D
74.G9731.03D
1
2
PR9331
100KR2J -1-GP
MUXLESS
PR9331
100KR2J -1-GP
MUXLESS
1
2
PC9326
SCD01U50V2KX-1GP
MUXLESS
PC9326
SCD01U50V2KX-1GP
MUXLESS
1 2 PR9301
0R2J -2-GP
DY
PR9301
0R2J -2-GP
DY
1
2
PR9316
10KR2F-2-GP
MUXLESS
PR9316
10KR2F-2-GP
MUXLESS
1 2
PG9305
GAP-CLOSE-PWR
PG9305
GAP-CLOSE-PWR
1
2
PC9332
SC10U6D3V3MX-GP
MUXLESS
PC9332
SC10U6D3V3MX-GP
MUXLESS
1
2
PR9324
2K2R2J -2-GP
MUXLESS
PR9324
2K2R2J -2-GP
MUXLESS
123
4 5 6
PQ9305
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
MUXLESS
PQ9305
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
MUXLESS
1
2
PR9314
470R2J -2-GP
MUXLESS
PR9314
470R2J -2-GP
MUXLESS
1 2
PR9318
100KR2J -1-GP
DY
PR9318
100KR2J -1-GP
DY
123
4 5 6
PQ9303
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
MUXLESS
PQ9303
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
MUXLESS
1 2
PR9332 100KR2J -1-GP
MUXLESS
PR9332 100KR2J -1-GP
MUXLESS
1 2
PR9321
10KR2J -3-GP
DY
PR9321
10KR2J -3-GP
DY
1 2
PR9313
0R0402-PAD-2-GP
MUXLESS
PR9313
0R0402-PAD-2-GP
MUXLESS
1 2
PR9311
0R0402-PAD-2-GP
MUXLESS
PR9311
0R0402-PAD-2-GP
MUXLESS
1 2
PR9312
0R0402-PAD-2-GP
MUXLESS
PR9312
0R0402-PAD-2-GP
MUXLESS
1
2
PR9315
15KR2F-GP
MUXLESS
PR9315
15KR2F-GP
MUXLESS
1 2
PR9330
20KR2F-L-GP
MUXLESS
PR9330
20KR2F-L-GP
MUXLESS
1
2
PC9317
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
MUXLESS
PC9317
S
C
1
0
U
6
D
3
V
5
M
X
-3
G
P
MUXLESS
123
4 5 6
PQ9311
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
DY
PQ9311
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
DY
1
2
PC9324
SCD1U10V2KX-5GP
MUXLESS
PC9324
SCD1U10V2KX-5GP
MUXLESS
1 2
PG9306
GAP-CLOSE-PWR
PG9306
GAP-CLOSE-PWR
1
2
PC9313 S
C
1
U
6
D
3
V
2
K
X
-G
P
MUXLESS PC9313 S
C
1
U
6
D
3
V
2
K
X
-G
P
MUXLESS
1 2
PG9308
GAP-CLOSE-PWR
PG9308
GAP-CLOSE-PWR
S
D
G
G
D
PQ9302
DMP2130L-7-GP
2ND = 84.03413.A31
MUXLESS
84.02130.031 G
D
PQ9302
DMP2130L-7-GP
2ND = 84.03413.A31
MUXLESS
84.02130.031
1 2
PR9319
10KR2F-2-GP
MUXLESS
PR9319
10KR2F-2-GP
MUXLESS
G
S
D
PQ9307
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
MUXLESS
PQ9307
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
MUXLESS
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
LVDS_Switch
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
LVDS_Switch
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
LVDS_Switch
A3
<Variant Name>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CRT_Switch
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CRT_Switch
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
CRT_Switch
A3
<Variant Name>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TOUCH PANEL
A3
96 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TOUCH PANEL
A3
96 108
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
TOUCH PANEL
A3
96 108
<Variant Name>
SSID = SDIO
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
3D3V_S0 1D8V_S0
1D8V_S0
DCBATOUT DCBATOUT
3D3V_S0
DCBATOUT
1D5V_S3 1D5V_S3 1D5V_S3 1D5V_S0
1D5V_S3 5V_S5 5V_S0 5V_S0 3D3V_S5 5V_S5 DCBATOUT
DCBATOUT DCBATOUT 3D3V_S53D3V_S5 1D05V_VTT 5V_S5 3D3V_S0 3D3V_S0 1D5V_S3 5V_S0 5V_S0
1D5V_S3 3D3V_S5 3D3V_S5 3D3V_S0 3D3V_S0
3D3V_S0
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
UNUSED PARTS/EMI Capacitors
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Variant Name>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
A3
<Variant Name>
CPU Thermal module hole
stand off
Check test point
0624 Modify:
Removed AFTP1,AFTP7~AFTP13.
GPU Thermal module hole
0721 Modify:
Removed SPR1
0802 For EMI/ESD.
0818
0901
RF CAP
0915 X01 Modify:
Reserved EC9701~EC9723 0.1uF for
RF suggestion.
A00 0103 add 3rd LIDON(34.4CK01.501) on HDD1,HDD4,HGPU1,HGPU2 at XBuild batch run
1
H10
HOLE335R115-GP
DY
ZZ.00PAD.D01
H10
HOLE335R115-GP
DY
ZZ.00PAD.D01
1
2
EC9714
SCD1U10V2KX-4GP
DY
EC9714
SCD1U10V2KX-4GP
DY
1
HGPU1
STF237R117H83-1-GP
34.4CK01.001
2nd = 34.4CK01.401
3rd = 34.4CK01.501
HGPU1
STF237R117H83-1-GP
34.4CK01.001
2nd = 34.4CK01.401
3rd = 34.4CK01.501
1
2
E
C
9
7
2
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
E
C
9
7
3
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
3
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
E
C
9
7
3
0
S
C
4
7
0
P
5
0
V
-
2
-
G
P
E
C
9
7
3
0
S
C
4
7
0
P
5
0
V
-
2
-
G
P
1
2
EC9711
SCD1U50V3KX-GP
DY
EC9711
SCD1U50V3KX-GP
DY
1
2
EC9707
SCD1U50V3KX-GP
DY
EC9707
SCD1U50V3KX-GP
DY
1
2
EC9712
SCD1U10V2KX-4GP
DY
EC9712
SCD1U10V2KX-4GP
DY
1
2
E
C
9
7
2
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
H15
HT10X10BE10R32-D-5-GP
DY
ZZ.00PAD.J91
H15
DY
ZZ.00PAD.J91
1
2
E
C
9
7
1
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
1
7
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
EC9710
SCD1U50V3KX-GP
DY
EC9710
SCD1U50V3KX-GP
DY
1
H1
DY
ZZ.00PAD.J91
H1
DY
ZZ.00PAD.J91
1
2
EC9701
SCD1U10V2KX-4GP
DY
EC9701
SCD1U10V2KX-4GP
DY
1
HHD4
STF237R117H83-1-GP
34.4CK01.001
2nd = 34.4CK01.401
3rd = 34.4CK01.501
HHD4
STF237R117H83-1-GP
34.4CK01.001
2nd = 34.4CK01.401
3rd = 34.4CK01.501
1
HGPU2
STF237R117H83-1-GP
34.4CK01.001
2nd = 34.4CK01.401
3rd = 34.4CK01.501
HGPU2
STF237R117H83-1-GP
34.4CK01.001
2nd = 34.4CK01.401
3rd = 34.4CK01.501
1
2
E
C
9
7
1
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
1
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
E
C
9
7
2
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
8
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
EC9702
SCD1U10V2KX-4GP
DY
EC9702
SCD1U10V2KX-4GP
DY
1
H5
DY
ZZ.00PAD.J91
H5
DY
ZZ.00PAD.J91
1
2
E
C
9
7
3
4
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
3
4
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
E
C
9
7
2
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
3
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
E
C
9
7
3
7
S
C
4
7
P
5
0
V
3
J
N
-
G
P
E
C
9
7
3
7
S
C
4
7
P
5
0
V
3
J
N
-
G
P
1
2
E
C
9
7
3
8
S
C
D
2
2
U
5
0
V
3
Z
Y
-
1
G
P
E
C
9
7
3
8
S
C
D
2
2
U
5
0
V
3
Z
Y
-
1
G
P
1
H4
HOLE256R126-GP
ZZ.00PAD.J01
H4
HOLE256R126-GP
ZZ.00PAD.J01
1
HBT1
STF237R117H123-GP
34.4DM11.001
2nd = 34.4A902.001
DY
HBT1
STF237R117H123-GP
34.4DM11.001
2nd = 34.4A902.001
DY
1
2
E
C
9
7
3
9
S
C
4
7
P
5
0
V
3
J
N
-
G
P
E
C
9
7
3
9
S
C
4
7
P
5
0
V
3
J
N
-
G
P
1
H9
HOLE335R115-GP
ZZ.00PAD.D01
DY
H9
HOLE335R115-GP
ZZ.00PAD.D01
DY
1
2
E
C
9
7
1
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
1
9
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
EC9703
SCD1U10V2KX-4GP
DY
EC9703
SCD1U10V2KX-4GP
DY
1
2
E
C
9
7
2
4
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
4
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
EC9713
SCD1U10V2KX-4GP
DY
EC9713
SCD1U10V2KX-4GP
DY
1
H11
HOLE256R126-GP
ZZ.00PAD.J01
H11
HOLE256R126-GP
ZZ.00PAD.J01
1
H2
HOLE335R115-GP
ZZ.00PAD.D01
DY
H2
HOLE335R115-GP
ZZ.00PAD.D01
DY
1
2
EC9704
SCD1U50V3KX-GP
DY
EC9704
SCD1U50V3KX-GP
DY
1
2
E
C
9
7
2
5
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
5
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
H12
HOLE256R126-GP
ZZ.00PAD.J01
H12
HOLE256R126-GP
ZZ.00PAD.J01
1
2
E
C
9
7
3
5
S
C
4
7
P
5
0
V
3
J
N
-
G
P
E
C
9
7
3
5
S
C
4
7
P
5
0
V
3
J
N
-
G
P
1
H7
DY
ZZ.00PAD.J91
H7
DY
ZZ.00PAD.J91
1
2
E
C
9
7
2
0
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
0
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
HTML1
HOLE197R166-GP
DY
HTML1
HOLE197R166-GP
DY
1
2
EC9705
SCD1U50V3KX-GP
DY
EC9705
SCD1U50V3KX-GP
DY
1
2
EC9708
SCD1U50V3KX-GP
DY
EC9708
SCD1U50V3KX-GP
DY
1
2
EC9715
SCD1U10V2KX-4GP
DY
EC9715
SCD1U10V2KX-4GP
DY
1
2
E
C
9
7
3
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
3
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
E
C
9
7
3
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
3
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
H13
DY
ZZ.00PAD.J91
H13
DY
ZZ.00PAD.J91
1
2
E
C
9
7
2
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
HTML2
HOLE197R166-GP
DY
HTML2
HOLE197R166-GP
DY
1
2
E
C
9
7
1
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
1
6
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
HTML3
HOLE197R166-GP
DY
HTML3
HOLE197R166-GP
DY
1
H3
HOLE256R126-GP
ZZ.00PAD.J01
H3
HOLE256R126-GP
ZZ.00PAD.J01
1
H6
HOLE237R95-GP
DY
ZZ.00PAD.921
H6
HOLE237R95-GP
DY
ZZ.00PAD.921
1
2
E
C
9
7
2
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
2
1
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
EC9706
SCD1U50V3KX-GP
DY
EC9706
SCD1U50V3KX-GP
DY
1
HHD1
STF237R117H83-1-GP
34.4CK01.001
2nd = 34.4CK01.401
3rd = 34.4CK01.501
HHD1
STF237R117H83-1-GP
34.4CK01.001
2nd = 34.4CK01.401
3rd = 34.4CK01.501
1
2
EC9709
SCD1U50V3KX-GP
DY
EC9709
SCD1U50V3KX-GP
DY
1
2
E
C
9
7
3
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
E
C
9
7
3
2
S
C
D
1
U
5
0
V
3
K
X
-
G
P
DY
1
2
E
C
9
7
2
9
S
C
4
7
0
P
5
0
V
-
2
-
G
P
E
C
9
7
2
9
S
C
4
7
0
P
5
0
V
-
2
-
G
P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Power Sequence
A1
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Power Sequence
A1
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Power Sequence
A1
<Core Design>
T3
3D3V_AUX_KBC
DCBATOUT
S5_ENABLE
KBC GPIO43 to PCH
(DC mode)
(AC mode)
T4
EC_ENABLE#_1(GPIO31) keep low
T5
T7
PCH_SUSCLK_KBC
PCH to KBC GPIO00
T8
Huron River Platform Power Sequence
5V_S5
S5_ENABLE
3D3V_S5
KBC GPIO34 control power on by 3V_5V_EN
3D3V_AUX_S5
T3
PM_PWRBTN#
KBC_PWRBTN#
KBC GPIO20 to PCH
T9
T4
RTC_RST#
DCBATOUT
+RTC_VCC
T2
T1
RTC_RST#
+RTC_VCC
T1
>10ms
+5V_ALW & +3.3V_ALW need meet 0.7V difference
T5 +5VA_PCH_VCC5REFSUS
T6
+5V_ALW & +3.3V_ALW need meet 0.7V difference
+5VA_PCH_VCC5REFSUS
PM_RSMRST#
Press Power button
3D3V_AUX_S5
T2
red word: KBC GPIO
Platform to KBC PSL_IN2
KBC GPIO34 control power on by 3V_5V_EN
red word: KBC GPIO
>9ms
Within logic high level and disable if
it is less than the logic low level.
V5REF_Sus must be powered up before
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.
V5REF_Sus must be powered up before
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.
>9ms
Sense the power button status
>5ms
5V_S5
3D3V_S5
KBC GPIO43 to PCH
PCH_SUSCLK_KBC
PCH to KBC GPIO00
PM_RSMRST#(EC Delay 40ms)
<90ms
T7
T8
T6
AC_PRESENT
>10ms
>5ms
KBC GPO84 to PCH
0ms< Not floating.
3D3V_AUX_KBC
>16ms
AC
Platform to KBC PSL_IN2
PM_PWRBTN#
KBC_PWRBTN#
T9
AC
Press Power button
KBC GPIO20 to PCH
Sense the power button status
This signal has an internal
pull-up resistor and has an
internal 16 ms de-bounce on the
input.
Enable by PM_SLP_S4#
>30us
KBC GPIO23 to LAN
PM_SLP_S3#
PM_SLP_S4#
T11
PM_LAN_ENABLE
T12
T10
AC PM_PWRBTN#
PCH to KBC GPIO44
PCH to KBC GPIO01
1D8V_S0
DDR_VREF_S3(0.75V)
5V_S0
1D5V_S0
3D3V_S0
1D5V_S3
+5V_RUN & +3.3V_RUN need meet 0.7V difference
+5VS_PCH_VCC5REF
V5REF must be powered up before
Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.
T13
T17
T23
0D85V_S0
T24
D85V_PWRGD
TPS51461RGER PGOOD
0D85V_S0
CPU SVID BUS
VCC_CORE
VCC_GFXCORE
T25<2000us 50us<
IMVP_PWRGD
ISL95831 PGOOD to system
T26
<5ms
DMI
<200us
PLT_RST#
T36
PCH to all system
H_CPUPWRGD
T35 <100ms
PCH to CPU
1ms<
T28>0us
PWROK
KBC GPIO77 to PCH
PCH to CPU
1D8V_S0
T32 5ms< <650ms
T27>99ms
ALL_SYS_PWRGD=D85V_PWRGD
This signal represents the Power
Good for all the non-CORE and
non-graphics power rails.
D85V_PWRGD
T29 2ms< <650ms
T16
T14
T15
VT357FCX PGOOD
1D05V_VTT T21
T22
RUNPWROK T20
1.05VTT_PWRGD
0D75V_S0
T18
T19
CLK_EXP_P
T30
DC PCH_RSMRST#
>16ms
SetVID ACK
VDDPWRGOOD
SYS_PWROK
>1ms
T31 >2ms
T34>1ms+60us
T10
T33 >0ms
Enable by PM_SLP_S4#
>30us
KBC GPIO23 to LAN
PM_SLP_S3#
PM_SLP_S4#
T11
PM_LAN_ENABLE
T12
PCH to KBC GPIO01
PCH to KBC GPIO44
1D8V_S0
DDR_VREF_S3(0.75V)
5V_S0
1D5V_S0
3D3V_S0
1D5V_S3
+5V_RUN & +3.3V_RUN need meet 0.7V difference
+5VS_PCH_VCC5REF
V5REF must be powered up before
Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.
T13
T17
T23
0D85V_S0
T24
D85V_PWRGD
TPS51461RGER PGOOD
0D85V_S0
CPU SVID BUS
VCC_CORE
VCC_GFXCORE
T25<2000us 50us<
IMVP_PWRGD
ISL95831 PGOOD to system
T26
<5ms
DMI
<200us
PLT_RST#
T36
PCH to all system
H_CPUPWRGD
T35 <100ms
PCH to CPU
1ms<
T28>0us
PWROK
KBC GPIO77 to PCH
PCH to CPU
1D8V_S0
T32 5ms< <650ms
T27>99ms
ALL_SYS_PWRGD=D85V_PWRGD
This signal represents the Power
Good for all the non-CORE and
non-graphics power rails.
D85V_PWRGD
T29 2ms< <650ms
T16
T14
T15
VT357FCX PGOOD
1D8V_S0 & 1D5V_S3 power ready
1D05V_VTT T21
T22
RUNPWROK T20
1.05VTT_PWRGD
0D75V_S0
T18
T19
CLK_EXP_P
T30
SetVID ACK
VDDPWRGOOD
SYS_PWROK
>1ms
T31 >2ms
T34>1ms+60us
T33 >0ms
1D8V_S0 & 1D5V_S3 power ready
N12P-GE Power-Up/Down Sequence
8209A_EN/DEM_VGA(Discrete only)
DGPU_PWR_EN#(Discrete only)
PCH GPIO54 output
3D3V_VGA_S0(VDD33)
VGA_CORE(NVVDD)
3D3V_S0
tNV-FBVDDQ >0ms
For power-down, reversing the ramp-up sequence is recommended.
tNVVDD >0ms
RT8208 PGOOD
DGPU_PWROK(Discrete only)
1D5V_VGA_S0(FBVDDQ)
tPOWER-OFF <10ms
First rail to power down
Last rail to power down
VGA_CORE,1V_VGA_S0
1D5V_VGA_S0,3D3V_VGA_S0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Power Sequence Diagram
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
A2
<Core Design>
DCBATOUT 5V_S5
8
11
13
IMVP_PWRGD
H_CPUPWRGD
DCBATOUT
AC
SWITCH
Adapter in
Page38
PWR_CHG_ACOK
Charger
BQ24745
AD+
Page40
DCBATOUT
+RTC_VCC
Page40
VIN
(3V/5V)
RT8223MGQW
ENC
Page41
DC/DC
RTC battery
-8
APWROK
SYS_PWROK
PWROK
TPS51218DSCR
VOUT
PWRBTN#
RSMRST#
VR_ON
SVID
3D3V_AUX_S5
RTC_AUX_S5
-7
3
DC
Battery
Page39
BT+
PLTRST#
PM_RSMRST#
PM_PWRBTN#
-6
-5
ACOK
3D3V_AUX_S5
5V_AUX_S5
3D3V_S5
5V_S5
VREG5
VREG3
PWR_5V3D3V_ENC
Page27
GPIO20
GPIO43
GPIO6
KBC
NPCE795P
GPIO34
LL1
LL2
-3.2
PUMP
15V_S5
-3.3
PGOOD
3V_5V_POK
-1
Power Button
1
-2.1
SLP_S4# SLP_S3#
PM_SLP_S4#
EN
EN
PM_SLP_S3#
SWITCH
Page37
3D3V_S0
SWITCH
Page37
5V_S0
REF
VTT
0D75V_S0
PGD
RUNPWROK
VCC_CORE
VCC_GFXCORE
PGOOD
PM_SLP_S3#
EN
PGD
RUNPWROK
TPS53311RGTR
VOUT
5
VDD VIN
5V_S5 3D3V_S5
1D8V_S0
4
5
S0_PWR_GOOD
S5_ENABLE
3
KBC_PWRBTN#
VR
PM_SLP_S4#
4
DDR_VREF_S3
RUNPWROK
5
5a
Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM
V5IN VIN
5V_S5 DCBATOUT
RT8208BGQW
VOUT
VIN
1.05VTT_PWRGD
EN
DCBATOUT
0D85_S0
PGOOD
D85V_PWRGD
5a
OUTPUT
PGOOD
1.05VTT_PWRGD
1D05_VTT
DRAMPWRGD
PROCPWRGD
7
Cougar Point
PCH
-4
GPIO70
AC_IN#
9
PLT_RST#
Page46
Page47
Page45
Page48
Page42 & 43 & 44
12
2
PM_SLP_S3#
PM_SLP_S4#
GPIO44
GPIO01
GPIO77
SWITCH
Page37
1D5V_S0
VDDP
5V_S5
Power Up Sequence: -8 ~ 13
PM_DRAM_PWRGD
OUTPUT
ISL95831HRTZ
IMVP_VR_ON
SVID
VIN
1D5V_S3
TPS51116RGER
VOUT
VDDP VIN
6
-6.1
-5
-2
3V_5V_EN S5_ENABLE
3D3V_AUX_KBC
-3
-3.1
-3.1 -3.1 -3.1
D85V_PWRGD
6
S0_PWR_GOOD
IMVP_PWRGD
AND GATE
A
B
Y
10
SYS_PWROK
SYS_PWROK
10
SVID
S
V
I
D
8
RSTIN#
SM_DRAMPWROK
UNCOREPWRGOOD
Sandy Bridge
CPU
AND GATE
A
B
Y
0D75V_EN
VDDPWRGOOD
H_CPUPWRGD_R
BUF_CPU_RST#
BJT
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Power Block Diagram
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Power Block Diagram
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Power Block Diagram
A3
<Core Design>
Charger
BQ24745
+PBATT
Adapter
Battery
TPS51123RGER
5V_AUX_S5
Regulator LDO Switch
5V_S5
3D3V_AUX_S5
AO4468
5V_S0
3D3V_S5
ISL95831HRTZ
VCC_CORE
TPS51218DSCR
DCBATOUT TPS51216RUKR
0D75V_S0 DDR_VREF_S3
1D5V_S0
1D5V_S3
Power Shape
AO4407A
15V_S5
1D05V_VTT
1D8V_S0
1D8V_VGA_S0
TPCA8062
G547F2P81U
5V_USB1_S3
PA102FMG
3D3V_LAN_S5
AO4468
3D3V_S0
RTS5138
3D3V_CARD_S0 LCDVDD
DMP2130L
3D3V_AUX_KBC
For Discrete
+1.2V_LOM
RTL8111E
CRT Board USB Power
RT8208B
VGA_CORE
3D3V_VGA_S0
For Discrete For Discrete
For Discrete
1D5V_DDR_S0
RT9025
1V_VGA_S0
VCC_GFXCORE
For UMA
0D85V_S0
AO4468
TPS51311RGTR
DMP2130L G5285T11U AO4468
APL5916KAI
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
SMBUS Block Diagram
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
SMBUS Block Diagram
A2
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
SMBUS Block Diagram
A2
<Core Design>
3D3V_VGA_S0
E
TPDATA
TPCLK
3D3V_S0
E
E
E
TouchPad Conn.
TPDATA
TPCLK PSCLK1
PSDAT1
VGA
LCD CONN
PCH SMBus Block Diagram
PCH
SMBCLK
SMBDATA
GPIO74/SDA2
GPIO73/SCL2
KBC
CLK_SMB
3D3V_S0
E
SRN2K2J-1-GP
3D3V_S5
E
E
E
SRN2K2J-1-GP
3D3V_S0
2N7002SPT
E
E
E
DAT_SMB
BAT_SCL
BAT_SDA
DDC1DATA
DDC1CLK
Minicard
WLAN
SMB_DATA
SMB_CLK
GPIO17/SCL1
GPIO22/SDA1
SML1_CLK
SML1_DATA
SMBus address:xx
SMBus Address:A0
SMBus Address:A4
DIMM 1
SCL
SDA
3D3V_AUX_KBC
E
DIMM 2
SCL
SDA
SMBus address:16
SMB_CLK
SMB_DATA
PCH_SMBCLK
PCH_SMBDATA
BATA_SCL_1
BATA_SDA_1
KBC SMBus Block Diagram
Battery Conn.
PCH_SMBCLK
PCH_SMBDATA
G-Sensor
SCLK
SDATA
PCH_SMBCLK
PCH_SMBDATA
BQ24745
SCL
SDA
TPDATA
TPCLK
PCH_SMBDATA
PCH_SMBCLK
E
E
SMBus address:12
2N7002DW-1-GP
E
E
3D3V_S0
SRN2K2J-1-GP
CRT CONN
CRT_DDCCLK_CON
CRT_DDCDATA_CON
CRT_DDC_CLK
CRT_DDC_DATA
DDC2CLK
DDC2DATA
SRN10KJ-5-GP
SRN4K7J-8-GP
SRN2K2J-1-GP
NPCE795P
SRN100J-3-GP
SRN2K2J-1-GP
GPU_HDMI_CLK
GPU_HDMI_DATA
3D3V_VGA_S0
E
HDMI CONN
DDC2DATA
DDC2CLK
SML0CLK
SML0DATA
SML0_CLK
SML0_DATA
3D3V_S5
E
SRN2K2J-1-GP
Minicard
W-WAN
SMB_DATA
SMB_CLK
PCH_SMBDATA
PCH_SMBCLK
E
E
E
E
VGA_CRT_DDCDATA
VGA_CRT_DDCCLK
UMA
LVDS_DDC_CLK_R
LVDS_DDC_DATA_R
SRN0J-6-GP
L_DDC_DATA
L_DDC_CLK
CRT_DDC_DATA
CRT_DDC_CLK
SDVO_CTRLDATA
SDVO_CTRLCLK
5V_HDMI
E
SRN1K5J-GP
PCH_HDMI_DATA
PCH_HDMI_CLK Level
Shift
DDC_CLK_HDMI
DDC_DATA_HDMI
DIS
E
3D3V_S0
SRN2K2J-1-GP
SRN0J-6-GP
UMA
UMA
UMA
UMA
UMA
SRN0J-6-GP
DIS
UMA
E
3D3V_S0
SRN2K2J-1-GP
DIS
3D3V_S0
SRN2K2J-8-GP
3D3V_S5
E
3D3V_S0
5V_S0
E
SRN10KJ-6-GP
SML1_CLK
SML1_DATA To KBC SML1DATA
SML1CLK
PCH
SCL
SDA
LVDS_DDC_CLK
LVDS_DDC_DATA
CLK
DATA
SRN0J-6-GP
DIS
GPU_LVDS_CLK
GPU_LVDS_DATA
DDC_CLK_HDMI
DDC_DATA_HDMI
SRN0J-6-GP
DIS
Level
Shift
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Thermal/Audio Block Diagram
Custom
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Custom
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15
A00
Custom
<Core Design>
Thermal Block Diagram
UMA
Thermal
P2800
DXP
DXN
Audio Block Diagram
Codec
92HD79B1
HP
OUT
MIC
IN
SPEAKER
HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_OR_F
SPKR_PORT_D_L-
SPKR_PORT_D_R+
DMIC_CLK/GPIO1
DMIC0/GPIO2
MMBT3904-3-GP
HP1_PORT_B_L
HP1_PORT_B_R
Analog
MIC
PORTC_L
PORTC_R
VREFOUT_C
Put under CPU(T8 HW shutdown)
P2800_DXP
P2800_DXN
THRMDC
THRMDA
VGA
MMBT3904-3-GP
Place near CPU
PWM CORE
Place near GPU(DISCRETE only).
VGA
Thermal
P2800
DXP
DXN
P2800_VGA_DXP
P2800_VGA_DXN
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
MMBT3904-3-GP
TDR
TDL
KBC
NPCE795P
GPIO5
GPIO92
SYS_THRM
CPU_THRM
GPIO4 TDR VGA_THRM
PAGE28
PAGE28
PAGE27
OTZ
2N7002
THERM_SYS_SHDN#
S
D
G
IMVP_PWRGD
PURE_HW_SHUTDOWN#
VR
3V/5V
EN
PGOD
OTZ
T8
PH
FAN CONTROL
PAGE28
V
I
NVSET
F
A
N
1
_
D
A
C
GPIO94
5V
VOUT
FAN
VIN
TACH
GPIO56
F
A
N
_
T
A
C
H
1
P2793
Digital
MIC
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
DATA PAGE Change Iteam
08/25 14 SWAP SA0_DM1 and SA1_DIM1 each other for DM2 can't boot up issue.
08/29 28 Change U2802 Main source to 74.00991.031, 2nd 74.02793.A31,3rd 74.05606.071
08/29 61 Add 2nd 77.C1071.20L on TC6101.
08/29 64 Re-assign FP1 pin define.
08/29 71 Un-stuff Debug port connector(DB1) on X01.
08/29 37
Change U3701 pin2 to RUNPWROK from 0D75V_EN. Reserved R3717 0ohm between
PM_DRAM_PWRGD and VDDPWRGOOD_R.
08/29 37 Change R2724 to 20K 0402 from 10K for X01 stage.
08/29 40 Change 3D3V_AUX_S5 to 3D3V_AUX_KBC to avoid leakage Voltage to 3D3V_AUX_KBC under DC mode.
08/31 51 HDMI1 change to 22.10296.311 from 22.10296.271
08/31 28 FAN1 change to 20.F0772.003 from 20.F1639.004
08/31 57 E-SATA1 change to 22.10321.W11 from 22.10290.141
09/01 41 PU4104 and PU 4105 horizontally mirror.
09/01 83 R8305 Change to 30K ohm.
09/01 97 H1, H5, H13, H7 and H15 change to ZZ.00PAD.J91 from ZZ.00PAD.D01.
09/01 56 HDD1 add 2nd=62.10065.121.
09/01 79 U7901 change main source to 74.00351.0B3.
09/01 42 PR4226 change to 5.62K ohm.
09/01 45 PTC4502 change to 79.3971V.30L.
09/03 61 U6101 add 2nd=74.00547.079.
09/03 49 U4901 add 2nd=74.09724.09F.
09/03 40 PU4002 and PU4003 add 2nd=84.P1403.B37.
09/03 24 L2401,L2402,L2403 add 2nd=68.10090.10B.
09/03 27 DY C2713. Add C2722.
09/03 47 Add PR4702
09/03 22 Change FFS_INT2_R from PCH GPIO48 to GPIO15
Removed R2220 and change R2201 default pull up to pull down.
09/06 20 X2001 add 3rd=82.30020.A31.
09/06 56 U5601 add 2nd=74.02191.079.
09/06 PU9303 add 2nd=74.05930.03D. 93
09/06 37 U3701 add 2nd=73.7SZ08.DAH.
09/06 23 Add 2nd and 3rd for L2301.
09/06 23 R434 change name to PR9321. Add PC9324 and PR9319 for soft start.
09/06 61 TC6101=80.10715.B1L, 2nd=77.C1071.21L, 3rd=77.C1071.20L.
09/06 56 ODD1 add 2nd and 3rd source. HDD1 add 3rd source.
09/06 49 LCD1 add 2nd source.
09/06 69 TPAD1 add 2nd.
09/06 15 DM1 2nd=62.10017.Q31, 3rd=62.10017.K01.
09/06 14 DM2 2nd=62.10017.P31, 3rd=62.10017.K11.
09/07 68 Add 2nd source 20.K0343.004 on PWRBTN1& PWRBTN2 base on updated connector list.
09/07 69 Add 2nd source 20.K0343.004 on KBLIT1 base on updated connector list.
09/07 82 Add 2nd source 20.F0085.040 on CRTBD1 base on updated connector list.
09/07 64 Add 2nd source 20.K0382.006 on FP1 base on updated connector list.
09/07 75 Add 2nd source 20.K0382.026 on NEW1 base on updated connector list.
09/07 4~10 Updated CPU1 footprint to SKT-BGA989C470395-1H180 from SKT-BGA989C470395-1H186 base on data
base updated.
Add 2nd source 62.10040.771 on CPU1 base on updated connector list.
09/07 75 Change CARD1 to 20.I0129.001 from 62.10051.931 from ME double updated latest DXF&EMN on X01.
09/07 93 PQ9308 change name to PQ9311.
09/07 ALL Change all of single 2N7002 to 84.2N702.J31 from 84.2N702.D31 due to 84.2N702.D31 will EOL.
28 09/07 Change U2801,U2803 to 74.02800.A71 from 74.02800.071 from vender updated parts.
Change R2803&R2817 to 107K from 499K,R2804&R2818 to 226K from 102K base on updated ADJ Table.
09/08 18, 22 Change FFS_INT2_R from PCH GPIO48 to GPIO14 Keep PCH_GPIO5 PH R2201,PCH_GPIO48 PH R2220.
Add R1818.
09/08 82 1.Rename IOBD1 pin20,22,26,28 to IOBD1_20,22,26,28 from PCIE_TXN5,PCIE_TXP5,PCIE_RXP5,PCIE_RXN5.
2.Add RN8207,RN8208 for optional USB3.0 PCIE or USB2.0 signal.
09/08 18 Reserved USBP9~USBP10 to IOBD1 pin20,22,26,28.
09/08 37 Stuff Q3704,R3710; un-stuff R3716. U3701 pin2 change to 1.05VTT_PWRGD from RUNPWROK.
09/08 20 DY R2002.
09/08 47 Mount PC4710.
09/08 98 Update N12P power sequence.
09/09 82 R8201, R8202 and R8203 change to 62 ohm.
09/10 45 Change PL4501 to 68.2R210.20C from IND-D56UH-27-GP base on Brian updated.
09/10 41 Change PL4101,PL4102 to 68.2R210.20B from 68.2R210.20Q base on Brian updated.
09/10 82 Rename IOBD1 pin14 to IOBD1_14 from USB30_SMI#.
Add R8207 for USB20 USB_OC#10_11
Add R8206 for USB30 USB30_SMI#
Add R8208 for USB20 USB signal.
Add R8207 for USB30 PCIE signal.
09/10 49 Add TPNL1 for touch panel solution 4pin connector.
Change LCD1 to 20.F1816.030 for 30pin
Re-assign LCD1 pin define base on Roy updated cable pin define list.
09/10 51 Change HDMI1 part number to 22.10296.331 from 22.10296.311 base on ME Double updated.
X01
X01
VERSION VERSION
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
09/13 83 Change X8501 to 82.30034.641;2nd 82.30034.651;3rd 82.30034.681 from sourcer suggestion.
09/13 Change KBLIT1, PWRBTN2 and TPAD1 2nd source from 20.K0343.004 to 20.K0382.004.
09/13 Change 1.8V power solution. 47
09/14 82 Change R8201~R8203 to 470ohm from 100ohm.
Add RN8209 PH 5V_S5 on MEDIA_LED1~3# for PWM OD mode.
09/14 40 Add 2nd source 84.04835.H37 on PU4002,PU4003 base on Brian updated 2nd source excel file.
09/14 58 Change SPK1 to 20.F0772.004 from 20.F1647.004 from Double updated.
09/14 51 Add R5101~R5108and reserved TR5101~TR5104 on all of HDMI differential pair for EMC suggestion.
Rename HDMI1 CONN NET name.
09/14 29 Add R2920,R2921 and reserved EC2901,EC2902 on AUD_DMIC_CLK &AUD_DMIC_IN0 for EMC suggestion.
09/14 75 Add R7503,R7504 and reserved EC7501,EC7502 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.
Rename NEW1 pin24,25 to USB_PP13_R&USB_PN13_R.
Rename NEW1 pin8,9 to CLK_PCIE_NEW_C&CLK_PCIE_NEW#_C
09/14 20 Reserved EC2004,EC2005 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.
09/14 49 Reserved EC4910~EC4915 on LVDS signal for EMC suggestion.
09/15 58 Re-assign SPK1 pin define base on Roy updated excel file for 20.F0772.004
09/15 51 Add 2nd source 22.10296.311 on HDMI1 from updated connector list.
09/15 68 Add 2nd source 20.K0382.004 on PWRBTN1& PWRBTN2 base on updated connector list.
09/15 82 Re-assign CRTBD1 pin define base on EMC suggestion.
09/15 49 Change BLON_OUT_C to pin 15 and pin 4 to NC on LCD1.
09/15 28, 51,82 Add test point for WKS AFTE request.
09/15 All ADD 2nd source follow Power team suggestion.
09/15 92, 93 Modify PR9318 and PR9228 power source from 3D3V_AUX_S5 to 3D3V_S5.
09/15 86 Reserve Q8602, C8603 and R8606 for VGA over temp.
09/15 20 RN2005 swap net.
09/15 19 RN2005 swap net.
09/15 48 Change PR4809 to 10K from 100K PH power source change to 3D3V_S0 from S5.
09/15 82 Re-assign CRTBD1 pin define base on EMC suggestion.
09/15 97 Reserved EC9701~EC9723 0.1uF for RF suggestion.
09/15 41 Un-stuff PU4101,PD4105,PR4124, PR4125,PR4101 at X01 stage for 5mW issue.
09/15 69 un-stuff R6907 and stuff R6905,Q6902,R6906 for 5V drive CAP LED.
09/17 82 Change IOBD1 part number to 20.F1849.080 base on Double updated latest DXF&EMN.
09/17 49,57
32,64
stuff TR4901 and un-stuff R4911,R4912 at X01 stage from EMC Neo suggestion.
09/17 20 Change RN2010~RN2016 to 33ohm from 0ohm from EMC Neo suggestion.
09/17 40,41 Stuff EC4002 0.1uF from EMC Neo suggestion.
Stuff EC4008 0.1uF from EMC Neo suggestion.
Stuff EC4102,EC4103 0.1uF from EMC Neo suggestion.
Stuff EC4107 0.1uF from EMC Neo suggestion.
Stuff PC4119,PC4120 0.1uF from EMC Neo suggestion.
Stuff EC4006,EC4007 0.1uF from EMC Neo suggestion.
09/17 37 Change R3710 to 100K from 0ohm to avoid impact 1.05VTT_PWRGD turn off sequence directly.
09/17 17 Add R1703~R1705 on RGB signal and reserved EC1701~EC1703 0.1u from EMC Neo suggestion.
09/17 EC6001 change to 10p from 4.7p and default stuff from Neo suggestion.
EC1801 change to 10p from 4.7p and default stuff from Neo suggestion.
60,18
09/17 44 default stuff EC4407,EC4405,EC4403,EC4410 base on EMC Neo suggestion.
09/17 49 Add 2nd source 20.F1561.004;3rd source 20.F1686.004 on TPNL1 from updated connector list.
09/17 49 Add 2nd source 20.F1561.004;3rd source 20.F1686.004 on TPNL1 from updated connector list.
09/17 82 Change R8201~R8203 to 430ohm.
09/17 48 Change PR4809 to 4.7K from 100K PH power source change to 3D3V_S0 from S5.
09/17 40,27,83 Rename PCIE_RST# to AD_IA_HW2 on KBC GPIO50 for power Tom suggest.
Reserved PQ4004,PR4036,PR4037 for AD_IA_HW2 function.
09/17 68 Rename CHARGER_LED1 to CHARGERLED1.
Rename FPOWER_LED1 to FPOWERLED1.
Rename HDD_LED1 to HDDLED1.
Rename TP_LOCK_LED1 to TPLOCKLED1.
Rename TP_LOCK_LED2 to TPLOCKLED2.
Rename WLAN_LED1 to WLANLED1
09/17 21,22 Base on layout routing,Add RN2104 10K instead of R2111 10K.
Move EC_SCI#,DBC_EN to RN2201. Move S_GPIO to RN2103. Move PSW_CLR# to RN2104.
09/17 56 Change R5605 to 100K from 10K and PH to 5V_S0 from 3D3V_S0 to meet Vgs>2V turn on.
09/17 56 Add Q2706 2N7002 to avoid leakage loop from 3D3V_S5 to 3D3V_AUX_KBC issue when 10mW latched fail timing.
09/17 ALL Change all of 0402 0ohm to 0R0402 short pad.
PR4008,PR4010,PR4012,PR4020,PR4023,PR4024,PR4027,PR4028,PR4029,PR4225PR4102,PR4113,PR4118,
PR4121,PR4203,PR4204,PR4215,PR4222,PR4231,PR4243,PR4301,PR4509,PR4510,PR4801,PR4804,PR4805,
PR4808,PR4810,PR9211
F4902,PR4017,PR4018,PR4106,PR4611,PR4710,PR4807,R2304,R2403,R2406,R2409,R2702,R2902,R2903,R2904
R2305
09/20 9 Add 2nd for TC901.
09/20 83 Add 2nd for L8303.
09/20 82 Add 2nd for LD8201.
09/20 86 Add 2nd for Q8601.
09/20 83 Add R8321. C8353 and C8354 change to 12pF.
09/20 82 Redefine IOBD1.
09/20 75 AFTP111 and AFTP110 connect to USB_PP13_R and USB_PN13_R.
09/20 51 Change P/N of Q5102.
09/21 42 Change PU4201 VDD power source to 5V_S5 from 5V_S0 to avoid abnormal MVP_PWRGD waveform.
09/21 47 stuff PC4714 22uF from Brian updated.
VERSION VERSION
X01
X01
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
DATA PAGE Change Iteam DATA PAGE Change Iteam
09/21 45 Change PR4507 to 20K from 20.5K from Brian updated.
09/21 46 Change PR4602 to 110K from 68K from Brian updated.
09/21 42 Change PR4217 to 1.27K from 1K from Brian updated.
Change PR4213 to 3.6K from 3.16K from Brian updated.
Change PR4236 to 3.01K from 3.32K from Brian updated.
09/21 44 Change PC4410 to 0.01u from 0.022uF from Brian updated.
09/21 39 Add 2nd 83.00099.K11;3rd 83.00099.T11 on D3901,D3902,D3903 from Sourcer Eden suggestion.
09/21 39 Add 2nd 84.02143.011;3rd 84.00143.N11 on 6801,Q6804,Q6805,Q6806,Q6807,Q6808
from Sourcer Eden suggestion.
09/21 43 Change PU4303,PU4306,PU4309 dummy field only for QC CPU stuff.
Change PC4307,PC4316 dummy field only for QC CPU stuff.
Add 2nd for PTC4306.
09/21 41 PD4101, PD4103, PD4104 and PD4105 add 2nd source.
09/21 69 Q6902 add 2nd source.
09/21 40 PD4001 add 2nd source.
09/21 19 move PCH_WAKE# to RN1901 pin4;Add R1909 PH 100K on AC_PRESENT.
09/21 37 R3710 change to 0ohm. Remove R3701 and C3701.
09/21 42 Add PR4214, PC4230, PR4216 and PC4231 from Brian updated.
09/23 20 RN2016, RN2010, RN2011, RN2012, RN2014 and RN 2013 keep 0ohm.
09/23 ALL PR9216, R504, R1812,R1813,R1815,R1817, R1903, R1906,R1910,R1912,R1913,R1924,R1925, R2213,R2219,
R2711,R2720,R2733,R2761, R2807,R2814, R3708, R5125, R5127, R5721, R5722.
09/23 75 Add R7505~R7508 0ohm and reserved EC7503~EC7506 on PCIE_TX8&RX8 signal base on EMC Lance suggestion.
Add R7509,R7510 0ohm and reserved EC7507,EC7508 on CLK_PCIE_NEW_REQ#&PCIE_WAKE# signal base
on EMC Lance suggestion.
09/23 ALL RN5101, RN2201, RN1702, RN1901, RN1705 swap pin.
09/23 79 DUMMY G-SENSOR.
09/23 92 Update value of PR9210, PR9209 and PR9213 for N12P.
09/23 43 PR4320 change to 4 m ohm.
09/23 68 Add 2nd source 83.00110.J70 on FPOWERLED1,HDDLED1,WLANLED1 from Sourcer Anya suggestion.
Add 2nd source 83.00326.G70 on CHARGERLED1from Sourcer Anya suggestion.
Add 2nd source 83.00190.Z70 on TPLOCKLED1,TPLOCKLED2 from Sourcer Anya suggestion.
09/23 69 Change KBLIT1 part number to 20.K0589.004 and re-assign pin define base on Roy updated.
09/23 42, 44 Add 2nd source 69.60011.201 on PR4405,PR4245 from Sourcer Kitty suggestion.
09/23 42 Add 2nd source 69.60037.021 on PR4246,PR4247 from Sourcer Kitty suggestion.
09/24 23 Add 2nd source 68.00214.211 on L2301 updated from DN13ATI.
09/24 68, 69 Change R6806,R6808,R6811~R6813,R6801,R6803,R6815,R6906 to 390ohm from 1K to fine tune all of MB LED
for 5mA spec.
09/27 51 Reserve R5114 and R5115.
09/27 85 Reserve R8510 and R8513.
09/27 83 DY U8301, mount R8323.
09/27 92 R9206 change to 10K, PC9211 mount 0.1u.
09/27 93 R9312 change to 1K.
09/27
49, 57
32, 64
TR4901, TR4902, TR5701, TR3201 and TR6401 DY. Stuff 0 ohm.
09/27 69 AFTP73 connect to TP_VDD.
09/27 85 U8501 power change to 3D3V_S0.
09/27 92 PL9201 change like CPU core power choke.
09/28 83, 84 L8303, L8401, L8402, L8502 and L8503 follow NV DG spec.
09/28 46 Change PR4606 to 4.02K from 240ohm for fine tune 1.5V output Voltage.
09/28 92 PTC9202, PTC9203 and PTC9204 2nd=79.47719.9BL
09/28 22 Change R2220 to 10K from 100K.
09/28 60
EC6001 change to 10p from 4.7p and default un-stuff from Neo suggestion.
EC1801 change to 10p from 4.7p and default un-stuff from Neo suggestion
09/28 27 Change R2710, R2739, R2724 and R2726 change to 1%.
09/29 27 Default mount R2756, Dummy R2734.
10/04 24 Add 2nd source 68.1001E.10N on L2401,L2402,L2403 from sourcer Renee Lee updated.
10/07 43 PTC4306 cahnge second source to 79.47612.60L.
VERSION VERSION
X01
X01
10/09
10/09
10/09
10/09
10/09
85
85
84
83
83
Change L8503 to 68.00375.091,and add second source 68.00206.171
Change L8401 and L8402 to 68.00115.181,and add second source 68.00206.341
10/09
10/09
10/09
10/09
42
42
42
42
Change PR4217 to 64.84505.6DL for Dual-core OCP
Change PR4213 to 64.23715.6DL for Dual-core loadline
Change PR4207 to 64.22025.6DL for CPU(35W) Turbo setting
Change PR4202 to 64.22025.6DL for GFX Turbo setting
10/09 20,83 Dummy R2004 R2003 and PQ8309, stuff R2005
10/25
10/19 28 Change R2817 from 107K to 124K (64.12435.6DL) for VGA temperature setting change
84 Change R8402 from 40D2R to 60D4R (64.60R45.6DL) for meeting the spec
Add DM1 and DM2 second source:62.10017.Q41 and 62.10017.P61 14 15 10/25
10/25 85 Ventura SMBC_INA219_C and SMBD_INA219_C add 3.3V pull high schematic
11/01 51 85 Change HDMI HPD schematic for cost down
X02
11/10 27 Change R2724 to 64.33025.6DL for PCB version change
11/10 83 Change L8301 to 68.00115.181,and add second source 68.00206.341
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
VERSION VERSION
X02
11/11 14 DM2 1st change to 62.10017.P61; 2nd change to 62.10017.N41 on ST stage from ME updated connector list.
11/11 15 DM1 1st change to 62.10017.Q41; 2nd change to 62.10017.N11 on ST stage from ME updated connector list.
11/11 60 U6001 1st change to 72.25Q32.A01; 2nd change to 72.25320.C01; 3rd change to 72.25P32.C01 on ST stage
11/11 68 Change CHARGERLED1 2nd to 83.00327.D70 from Sourcer updated.
11/11 37 Change U3701 1st to 73.7SZ08.EAH;2nd to 73.01G08.L04;3rd to 73.7SZ08.DAH from
Sourcer Eason updated.
11/11 69 Add 2nd 20.K0592.030 on KB1 from ME updated connector list.
11/11 82 Add 2nd 20.K0465.008 on MEDIA1 from ME updated connector list.
Add 2nd 20.F1804.004 on SPK1 from ME updated connector list. 58 11/11
11/11 28 Add 2nd 20.F1841.003 on FAN1 from ME updated connector list.
11/11 70 Add 2nd 20.F0962.010 on HALL1 from ME updated connector list.
11/11 23 Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue.
Change VCCADAC power source to 3D3V_DAC_S0 from 3D3V_S0.
11/11 60 Add Q6002,R6007 fo FACTORY RTC detect function
11/11 28 ADJ&ADJ_VGA power source change to 3D3V_DAC_S0 from 3D3V_S0 to solve T8 shut down issue.
11/11 28 Reserved G709T1UF for T8 solution sync with DN13.
11/12 82
Change R8201, R8202, R8203 from 430 ohm to 1K ohm (63.10234.1DL) for soluting media board LED
brightness is too light issue
11/15 49 Add 2nd 20.F1860.030 on LCD1 from ME updated connector list.
11/15 8 Reserved C802~C804,C806,C807 10uF 0603 for power team fine tune Vcore quality
11/15 88 89
90 91
All of VRAM(VRAM1~VRAM8) PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from
BGA96D0913H48 same as DW30.
11/15
68
69
Change R6813, R6906 from 390 ohm to 1K ohm (63.10234.1DL) for soluting LED
Change R6808, R6811 from 390 ohm to 1K ohm (64.10234.1DL) for soluting LED
68 11/16
11/16 28 stuff both G709T1UF and P2800 related circuit, add R2805 0ohm default un-stuff at ST stage.
11/16 97 Change HHD1 HDD4 HGPU1 HGPU2 2nd from 34.4CK01.201 to 34.4CK01.401 from ME update connector list
11/17 48 CO-LAY APL5916 related circuit for VCCSA LDO solution.
11/15 20
Dell required us to disable PCIE port of WWAN slot ,If PCIE port 1 is disabled, it will cause all PCIE port
disabled,so change WWAN to PCIE port 3 from port1 at ST stage.
11/18 23
Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue.
Change VCCADAC power source to 3D3V_DAC_S0 from 3D3V_S0.
Stuff R2301 and un-stuff L2301.
11/18 28 Add R2805 0hm between THERM_SYS_SHDN#_OTZ and THERM_SYS_SHDN#.
Add R2812 0ohm between THERM_SYS_SHDN# and U2805 pin3.
11/18 28 Rename U2801&U2804 pin 8 to THERM_SYS_SHDN#_OTZ from HERM_SYS_SHDN#.
X02
11/18 20 Change X2001 to 82.30020.D41 from 82.30020.851 from Sourcer Dick updated.
11/18 23 Reserved R2308,R2309 on VCCVRM power rail.Reserved U2302 LDO circuit on VCCVRM power rail
11/18 22 82
Rename USB3_PWR_ON to PCH_GPIO57.
Add R8209,R8210 for PM_SLP_S4# and VGA_THRM to control USB3_PWR_ON
11/18 48 Change PTC4801 to 100u(77.21071.07L) from 150u from power team Brian updated
11/19
11/19
74
82
Add 2nd 20.I0135.001 on CARD1 from ME updated connector list.
Add 2nd 20.F1908.080 on IOBD1 from ME updated connector list.
11/20 3 Updated PCIE ROUTING
11/20 28
Change U2801,U2804,U2805 VCC power to 3D3V_DAC_S0 from 3D3V_S0.
Stuff R2812, un-stuff R2805
11/20 23
Reserved R2308 on VCCVRM power rail.
Reserved U2302 LDO circuit on VCCVRM power rail.
11/20 48
Set TPS51461 PWM solution dummy field for VCCSA_PWM and APL5916 LDO solution dummy field for
VCCSA_LDO. defualt stuff VCCSA_LDO at ST stage
11/20 22 Rename GFX_CRB_DET to GSENSOR_DET on GPIO39.
11/20 60 Un-stuff R6007 10M.
11/20 82 Reserved EC8201,EC8202 0.1u(closed H3) between AGND and GND from EMC Neo suggestion.
11/20 82 Reserved EC8203~EC8205 470p on all of MEDIA_LED# signal from EMC Neo suggestion.
11/20 82 Add RN8205 base on HSYNC&VSYNC report
11/20 61 Removed R6101 and connect USB_PWR_EN# to U6101 pin4 directly.
11/20 22 Rename PCH_GPIO12 to RTC_DET# on GPIO12.
11/20
61 22
18
Reserved U6102 USB POWER related circuit to separate EATA and CRT USB power in ST build.
Reserved USB2_CRT_ON# to control U6102 USB power switch from PCH GPIO57.
11/20 82 Reserved R8211,R8212 0ohm 0805 on CRTBD1 pin37,39 to separate EATA and CRT USB power in ST build.
11/22
11/22 82
82 Swap RN8205 pin4,3 and pin2,1 each other base on Connie swap report.
11/22 23
stuff EC8201,EC8202 0.1u(closed H3) between GND and GND from EMC Neo suggestion.
stuff EC8206 between 3D3V_S5 and GND from EMC Neo suggestion.
base on layout condition change 3D3V_DAC_S0 circuit. Stuff R2301 and un-stuff L2301.
11/22
11/22
82 stuff EC8203~EC8205 470p on all of MEDIA_LED# signal from EMC Neo suggestion.
23 Removed U2302 LDO for VCCVRM.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
11/22 83 84 85 Change L8301 L8401 L8402 to 0 ohm resistor (63.00000.00L)
11/22 57 Change TR5701 to 69.10103.041 and un-stuff R5718,R5719 from EMC Neo Suggestion.
11/22 75 Change TR7501 CM choke to 69.10103.041 and un-stuff R7501,R7502 from EMC Neo Suggestion.
VERSION VERSION
X02
11/22 29 change R2920,R2921 to 22ohm from 0ohm and stuff EC2901,EC2902 22p from EMC Neo updated.
11/22 61
Change U6101 to dual USB power switch from single for Layout limitation and placement.
Reserved USB2_CRT_ON# to control U6102 USB power switch from PCH GPIO57.
11/22 49 stuff C4908 0.1uF from EMC Neo suggestion.
stuff EC5801~EC5804 470pF from EMC Neo suggestion. 58 11/22
11/22 9 39
45 49
stuff EC901, EC3903, EC4501, EC4909, EC4907 0.1uF from EMC Neo suggestion.
11/22 48 Updated VCCSA_LDO circuit from Power team Brian updated.
11/22 49 Change RN4901 to 100ohm 4p from 8p for improve layout place.
11/22 49 Change TR4902 CM choke to 69.10103.041 and un-stuff R4908,R4909 from EMC Neo Suggestion.
11/22 49
Swap TR4901 pin4,3 and pin2,1 each other base on Connie swap report.
Change TR4901 CM choke to 69.10103.041 and un-stuff R4911,R4912 from EMC Neo Suggestion.
11/23 49 57 75 SWAPTR4901 TR4902 TR5701 TR7501 pin1&4 and pin2&3 each other base on Connie swap report.
11/22 60 stuff R6007 10M.
11/23 60 Change U6101 1st(74.02182.071);2nd(74.00546.A7D);3rd(74.02062.079) from Sourcer Harrison suggestion.
11/23 64 Add C6402 0.1uF,C6403 180pF and stuff C6401 47pF from RF fine tune result.
11/23 57 49 75 Change R5718,R5719,R4908,R4909,4911,R4912,R7501,R7502 to 0ohm 0603 from 0402.
11/23 56 97
stuff EC9739,EC9737,EC9735 47pF from RF fine tune result.
stuff EC5601 180pF from RF fine tune result.
Stuff EC9738 0.22uF closed EC9739 from RF fine tune result.
11/23 97 stuff ECEC9729,EC9730 470pF from EMC Neo suggestion.
11/23 45 Change PR4501 to 75K from 45.3K for 1.05V OCP set to 20A from Brian.
11/23 82 Removed R8211,R8212 and connect 5V_USB2_S3 to CRTBD1 pin 37 directly.
11/23 61 Removed C6105,C6103.
11/23 69 70 Change AFTP 80 81 to AFTP 83 84; change AFTP 83 to AFTP82; change AFTP 82 to AFTP85.
11/24 20 Add 2nd(82.30020.G71);3rd(82.30020.G61) on X2001 from Sourcer Dick updated.
11/24 69 Add 2nd(20.K0613.004)on KBLIT1 from Karl updated.
11/24 57 Add 2nd(22.10339.261)on ESATA1 from Karl updated.
X02
11/24 28 un-stuff VGA P2800 related circuit from Niki confirmed.
11/24 64 rename C6401,C6402,C6403 to EC6401,EC6402,EC6403
11/24 22 Dummy R2206
11/25 28 Dummy R2817 R2818 C2816
11/25 69 Add 3rd(83.00110.R70) on FPOWERLED1,HDDLED1,WLANLED1 from Anya provide
11/25 69 Add 3rd(83.00192.J70) on TPLOCKLED1 and TPLOCKLED2 from Anya provide.
11/25 69 Add 3rd(83.01108.070) on CHARGERLED1 from Anya provide.
11/26 43 92 Change PC9217 PC4319 to 0.1u 50V
11/29 83 Change C8353 C8354 to 15PF ,R8320 stuff from vendor suggestion.
11/29 36 Stuff D3602
11/30 68 Change 2nd source to 83.00322.070 from 83.00110.J70
11/30 85 Change L8502 L8503 to 0 ohm
11/30 92 Stuff PR9237 DY PR9321
12/01 8 Change C837,C826 to 22uF from 10uF and default stuff from Power Brian updated.
12/01 8 Change C801~C807 and C817 10uF stuff at QC CONFIG from power Brian updated.
12/21 Change 0402 pad(ZZ.00PAD.M11): R1404 R1405 R1503 R1504 R1703 R1704 R1705 R1807 R2301 R2306
R2307 R2308 R2404 R2405 R2735 R2737 R2758 R2759 R2760 R2762 R3614 R3710 R5114 R5801
R5802 R5803 R5804 R8210 R8323 R8511 R8512
12/21
12/21
12/21
Change 0603 pad(ZZ.00PAD.M21): R8206 R8207
Change resistor pad(ZZ.0R04P.ZZZ): RN1704 RN2010 RN2011 RN2012 RN2013 RN2014 RN2015 RN2016
Change L8301, L8401,L8402,L8502,L8503 to 0R0603 pad(ZZ.00PAD.M21)
Change to Parallel resistor
R1501 ,R1502; R2739 ,R2774;R8202 ,R8203;R8501 ,R8502;R8506 ,R8507;R2123 ,R2124
12/21
12/21 RN8205 change to R8201, R8202
12/21 PR9237 rename to PR9337
12/21 Delete 77.C1071.21L(TC6101), delete 83.01108.070(CHARGERLED) , delete 62.10065.121(HDD1)
A00
82
17 20
83 84 85
82
93
ALL
ALL
56 61 68
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
Title
Date: Sheet of
Wistron Corporation
QUEEN 15 A00
Change History
A3
<Core Design>
VERSION
A00
R2724 change to 47K resistor for XBulid 12/22 27
12/22 27 R2301 change to 0 resistor for CRT debug
12/22 40
1.Change PR4032,PR4034,PR4037 to ZZ.00PAD.M11
2.Stuff PQ4003,PQ4004
3.Change PR4047 to 174K(64.17435.6DL)
4.Change PR4035 to 300K(64.30035.6DL)
5.Change PR4036 t0 76.8K(64.76825.6DL)
6.Change PR4031 to 150K(64.15035.6DL)
12/23 68
1.FPOWERLED1 rename to FPLED1
2.HDDLED1 rename to HDLED1
3.CHARGERLED1 renamtpe to CHLED1
4.WLANLED1 rename to WLED1
5.TPLOCKLED2 rename to TPLED2
6.TPLOCKLED1 rename to TPLED1
7.PWRBTN1 rename to PWRBT1
8.PWRBTN2 rename to PWRBT2
12/23 43
Delete PR4323,PR4324,PR4325;
Stuff PR4320 for all BOM ,not co-lay Ventura
12/23 92
Delete PR9220,PR9222,PR9223;
Stuff PR9217 for all BOM ,not co-lay Ventura
12/23 51 Change 5V_HDMI to 5V_CRT_S0_R for HDMI power leakage
12/24 All
PRN3901 rename to PN3901
PTC9202~04 rename to PT9202~04
PTC4306 rename to PT4306
12/24 28 Change U2802 3rdto 74.05606.A71 at X-Build batch run
12/24 82 Change RN8205 to 66.22036.04L from 66.22036.040at X-Build stage
12/24 82 Reserved R8211 0603 0ohm on F8201
12/24 36 Reserved Q3603 2N702 on IMVP_PWRGD to fine tune glitch waveform when AC lose and DC lose.
12/24 28 Change 3D3V_S0 to 3D3V_DAC_S0
12/24 45 46 93
Change to short pad:
PR4502,PR4607,PR9311,PR9312,PR9326.
DUMMY PC4501
12/27 28 If stuff P2800EA1 then must stuff R2803,R2804,C2805 but if stuff P28003B0 should be unstuff.
12/27 42 PR4207,PR4213,PR4217 DUMMY field set to DC&QC option
12/28 51 Change 5V_HDMI to 5V_CRT_S0_R on RN5101
12/28 28 Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at XBuild
A00
VERSION DATA PAGE Change Iteam
12/28 27 Change R2756, R2763, R2766 to short pad
12/28 36 Stuff Q3603
12/28 28 86 Cancel VGA Thermal sensor P2800 ciruit
12/28 27 28 82 Change to VGA_THRM to USB3_PWR_ON
12/28 23 Change R2301 to short pad
12/29 51 Change HDMI resistor to short pad
12/29 49,57,75 Delete USB DUMMY resistor for no-lay
12/29 32 Change USB 0 resistor to short pad for no-lay
12/29 5 Reserve EC502 ,EC504 for EMI suggestion,add DUMMY EC505 for EMI
12/29 82 Delete PM_SLP_S4# line, directly link to USB3_PWR_ON
Add 3rd Richtek(74.09198.G7F) on U2301 at XBuild batch run config 12/29 23
12/29 68 Not use Liteon LED(83.00322.070) for package
12/30 5 Add DUMMY diode EC506 for BUF_CPU_RST# as EMI suggestion
12/30 42 PC4227 change to 78.33420.5FL as 78.33423.5FL obsoleted
12/30 49 Change R4904 to short pad
12/31 86 Add probe point for P2800_VGA_DXN/P2800_VGA_DXP
01/03 68 Change TPLED1,2 1st to 83.01921.P70 ,2nd to 83.00190.S7A,3rd to 83.00191.H70;
R6813 change to 390R from 1K same as DN13 LED part.
01/03 49 Delete R4908, R4909 for USB_Camera not co-lay
01/03 4~10 Add 3rd foxconn(62.10055.321) on CPU1 at X-Build batch run config
01/03 82 Add 3rd T-conn(20.F1932.040) on CRTDB1at X-Build batch run config
01/03 97 Add 3rd LIDON(34.4CK01.501) on HHD1,HHD4,HGPU1,HGPU2 at X-Build batch run config
01/04 68 Delete 83.00191.H70 for TPLED1,2 as cost high
01/04 49,57,75 Add 2nd TAI-TECH(69.10084.071) on TR4901,TR4902,TR5701,TR7501 at X-Build batch run config

Scheme Dell Inspiron n5110 m5110 Dq15 Wistron Queen 15 Intel Discrete Uma Sandy Bridge

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Scheme Dell Inspiron n5110 m5110 Dq15 Wistron Queen 15 Intel Discrete Uma Sandy Bridge

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