SR Flip-Flop

The SR Flip-Flop How it works Where does it fit with others Master-Slave Flip-Flops

Negative Edge Triggered Flip-Flops

The SR Flip-Flop

S Q

Q R

S 0 0 1 1

R 0 1 0 1

Action Keep state Q=0 Q=1 Undefined

Clocked SR Flip-Flop

Q CLK Q R

Clocked D Flip-Flop

CLK

JK Flip-Flop

J Q CLK Q K

T Flip-Flop

T CLK Q

Master-Slave Flip-Flop

J Q CLK Q K

Master-Slave Flip-Flop

Happens only once per clock cycle Acts as a double check

Negative Edge Triggered D Flip-Flop

Q CLK Q

Negative Edge Triggered D Flip-Flop

Same benefits as a Master-Slave More efficient

Finite State Machines

What they are Build One

What it is

A way of modelling using states

States Transitions Actions

Example From Book (Pg. 464)

Modulo-4 Synchronous Counter

00 to 11 and repeats Has one input to reset the counter and start over 0 0 0 0 1 1 1 1

R S1S0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

T+1 T+1 01 10 11 00 00 00 00 00

01 10 11 00 00 00 00 00

How Do We Build This?

Facts

Two Bites of storage One input Two output

Start with two D Flip-Flops Four states so four ANDs Two outputs so two ORs Plug it all together and fill in the gaps

The Build (Pg. 467)

RESET

D Q q1 CLK Q

D Q
q0 Q