Hardware Description Language

(HDL)

Introduction to HDL :

► In electronics a HDL is a language from a class of

computer language for formal description of electronic
circuit.

► It can describe circuit operation, its design and tests to

verify its operation at any level

► VHDL and VERILOG are popular HDL’s

 Hardware Description Language
(HDL)

► The automatic translation of design description into a set of

logic equation is performed by HDL

► HDL are used to describe the architecture and behavior of

discrete electronic system

► HDL are programming language that have been designed

and optimized for digital circuit design and modeling.
 Advantages of Hardware Description
Language (HDL)
HDL’s has several advantages over traditional design methodology ,they
are:

► We can verify design functionality early in the design written as an HDL

description.

► Design simulation at this higher level before implementation at gate

level, allow you to test architecture and design decision.

► Reduced non-recurring engineering costs.

► Design reused is enabled.

► Increase flexibility to design changes.

► Better and easier design auditing and verification.

 Introduction to VHDL
► Very High Speed Integrated Circuit (VHSIC) HDL (VHDL) was
developed by US army in 1982.

► VHDL is a programming language for describing the behavior

of digital systems.

► VHDL has many features appropriate for describing the

behavior of electronic components ranging from simple logic
gates to complete microprocessors and custom chips.

► VHDL allows the behavior of complex electronics circuits to be

captured into a design system for automatic circuit synthesis
or for system simulation.

► One of the most important applications of VHDL is to capture

the performance specification for circuit.
 Features of VHDL

► VHDL has powerful constructs.

► In VHDL, design may be decomposed hierarchically.
► Each design element has a well defined interface useful for
connecting it to other elements.
► Each design element has a precise behavioral specification
useful for simulating it.
► VHDL handles asynchronous as well as synchronous
sequential circuits.
► In VHDL, timing and clocking can be modeled.
► In VHDL, design is target independent.
► VHDL supports design library.
► The language is not case sensitive.
 Library (May
2007)
► Library is basically a subdirectory in the host environment for
compiled entities, architectures, packages and configurations.
► When you write VHDL description, you write them into design file
► One or more design units make up a design file
► A design unit may be an entity declaration, an architecture body,
a configuration declaration, a package declaration or a package
body declaration.
► A design library is an implementation dependent storage facility
for previously analyzed design units.
► Library units fall into two categories:
1. primary unit
a) entity declaration
b) configuration declaration
c) package declaration
2. Secondary Units
a) Architecture body
b) Package body
 Library Clause
► A library clause defines logical names for design libraries in the
host environment
► A set of utility packages can be put inside the library.
► The present working directory is identified by the keyword ‘WORK’
► A package name STANDARD containing some basic definitions is
automatically included in every program.
► In many situations we need to see multivalued logic to represent
don’t care values and tristate buses. In such a cases, it is
recommended that one should use a package called std_logic_1164
from the IEEE library.
► For using a library for a design unit, we need to type the “library”
and “use” statement before that design unit.
► The keyword ALL causes all definitions in the std_logic_1164
packages to be used
► The syntax for library clause is

library LIBRARY_NAME;
use LIBRARY_NAME.PACKAGE NAME <list of definitions>
 Library Clause
► The syntax for library clause is

library LIBRARY_NAME;
use LIBRARY_NAME.PACKAGE NAME <list of definitions>

Example:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 The work Library

► work is the default name of the current library.

► The work library is where, in a simulation system,

all of your design units( entities, architectures,
packages and configuration) will be placed after
they are analyzed, unless you have specified an
alternative library.

► Unlike simulation environments, the VHDL

synthesizer only considers design units that are
currently being compiled to be in the work library.
 USE Clause
► The use clause makes visible item specified as suffixes in
selected names listed in the clause.
► If a designer wants to have all declarations in a package
visible, then the item clause should be substituted by the
reserved word all.
► The syntax of use clause is:

use library_name.package_name.item;

use library_name.package_name;

use library_name.package_name.all;
 USE Clause
► Example 1.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
► Example 2.

library IEEE;
use IEEE.STD_LOGIC_1164.STD_ULOGIC;
use IEEE.STD_LOGIC_1164.RISING_EDGE;
► In the first example all the declarations specified in
st_logic_1164(which belongs to the library IEEE) have been
made visible.
► The second example makes visible the RISING_EDGE function
which is declare in same package. The function uses the type
STD_ULOGIC, therefore declaration of this type is also made
visible
 Packages
► A package is a collection of declarations that more than one
design can use.
► You can collect constant, data types, component declarations,
and subprograms into a VHDL package that can then be used
by more than one design or entity.

Package structure:
Packages have two parts, the declaration and the body.

► Package Declaration:
Holds public information, including constant, type and
subprogram declarations.
► Package body :
holds private information, including local types and
subprogram implementations.
 Package declarations:
► Package declaration defines the interface to a package.
► Package declarations collect information that is needed by
one or more entities in a design.
► This information includes data type declaration, signal
declarations, subprogram declarations and components
declarations.
► Signal declared in packages cannot be shared across entities.
► The syntax of package declaration is:

package package_name is
{ use clause ( to include other package)
type declaration
subtype declaration
constant declaration
signal declaration
subprogram declaration
component declaration }
end [package_name]
 Package body:
► A package body is the bodies of subprograms and the values
of constant declared in the package.
► A package body includes, implementation of subprograms
declared in the package declaration and internal support
programs
► The syntax of package body is

package body package_name is

{ use clause
subprogram declaration
subtype declaration
type declaration
constant declaration}
end [package_name]
 Structure of VHDL program:
► Every VHDL program consists of at least one
entity/architecture pair

► Combination of an entity and its corresponding architecture is

referred as a design entity.

► In large design, you will typically write many

entities/architecture pairs and connect them together to form
a complete circuit.

► An entity declaration describes the circuit as it appears from

the “outside”- from the perspective of its input and output
interfaces

► The second part of the minimal VHDL design description is the

architecture declaration

► The architecture describes the actual function of the entity to

which it bound