-------

-------------------------------------------------------------

------

------------------------------------------------------------HDL Code Generation Options:

Module: filter
Generated by MATLAB(R) 8.1 and the Filter Design HDL Coder 2.9.3.
Generated on: 2013-10-17 22:29:40
-------------------------------------------------------------

TargetLanguage: VHDL
TestBenchStimulus: impulse step ramp chirp noise

-- -------------------------------------------------------------- HDL Implementation

: Fully parallel
-- Multipliers
: 14
-- Folding Factor
: 1
-- -------------------------------------------------------------- Filter Settings:
--- Discrete-Time FIR Filter (real)
-- -------------------------------- Filter Structure : Direct-Form FIR
-- Filter Length
: 14
-- Stable
: Yes
-- Linear Phase
: Yes (Type 2)
-- ------------------------------------------------------------LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY filter IS
PORT( clk
clk_enable
reset
filter_in
filter_out
);

:
:
:
:
:

IN
IN
IN
IN
OUT

std_logic;
std_logic;
std_logic;
real; -- double
real -- double

END filter;
-----------------------------------------------------------------Module Architecture: filter
---------------------------------------------------------------ARCHITECTURE rtl OF filter IS
-- Local Functions
-- Type Definitions
TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF real; -- double
-- Constants
CONSTANT coeff1
: real := -9.2583358358079414E-03; -double
CONSTANT coeff2
: real := -4.2578803660682708E-02; -double
CONSTANT coeff3
: real := -7.9076254725300943E-02; -double
CONSTANT coeff4
: real := -6.8376521632396423E-02; -double
CONSTANT coeff5
: real := 3.6354642699981329E-02; -- d
ouble

CONSTANT
ouble
CONSTANT
ouble
CONSTANT
ouble
CONSTANT
ouble
CONSTANT
ouble
CONSTANT
double
CONSTANT
double
CONSTANT
double
CONSTANT
double

coeff6

: real := 2.0739275443548477E-01; -- d

coeff7

: real := 3.4166373290193952E-01; -- d

coeff8

: real := 3.4166373290193952E-01; -- d

coeff9

: real := 2.0739275443548477E-01; -- d

coeff10

: real := 3.6354642699981329E-02; -- d

coeff11

: real := -6.8376521632396423E-02; --

coeff12

: real := -7.9076254725300943E-02; --

coeff13

: real := -4.2578803660682708E-02; --

coeff14

: real := -9.2583358358079414E-03; --

-- Signals
SIGNAL delay_pipeline
: delay_pipeline_type(0 TO 13) := (0.0
,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0, 0.0); -- double
SIGNAL product14
: real := 0.0; -- double
SIGNAL product13
: real := 0.0; -- double
SIGNAL product12
: real := 0.0; -- double
SIGNAL product11
: real := 0.0; -- double
SIGNAL product10
: real := 0.0; -- double
SIGNAL product9
: real := 0.0; -- double
SIGNAL product8
: real := 0.0; -- double
SIGNAL product7
: real := 0.0; -- double
SIGNAL product6
: real := 0.0; -- double
SIGNAL product5
: real := 0.0; -- double
SIGNAL product4
: real := 0.0; -- double
SIGNAL product3
: real := 0.0; -- double
SIGNAL product2
: real := 0.0; -- double
SIGNAL product1_cast
: real := 0.0; -- double
SIGNAL product1
: real := 0.0; -- double
SIGNAL sum1
: real := 0.0; -- double
SIGNAL sum2
: real := 0.0; -- double
SIGNAL sum3
: real := 0.0; -- double
SIGNAL sum4
: real := 0.0; -- double
SIGNAL sum5
: real := 0.0; -- double
SIGNAL sum6
: real := 0.0; -- double
SIGNAL sum7
: real := 0.0; -- double
SIGNAL sum8
: real := 0.0; -- double
SIGNAL sum9
: real := 0.0; -- double
SIGNAL sum10
: real := 0.0; -- double
SIGNAL sum11
: real := 0.0; -- double
SIGNAL sum12
: real := 0.0; -- double
SIGNAL sum13
: real := 0.0; -- double
SIGNAL output_register
: real := 0.0; -- double
BEGIN
-- Block Statements
Delay_Pipeline_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
delay_pipeline(0 TO 13) <= (OTHERS => 0.0000000000000000E+00);

ELSIF clk'event AND clk = '1' THEN

IF clk_enable = '1' THEN
delay_pipeline(0) <= filter_in;
delay_pipeline(1 TO 13) <= delay_pipeline(0 TO 12);
END IF;
END IF;
END PROCESS Delay_Pipeline_process;
product14 <= delay_pipeline(13) * coeff14;
product13 <= delay_pipeline(12) * coeff13;
product12 <= delay_pipeline(11) * coeff12;
product11 <= delay_pipeline(10) * coeff11;
product10 <= delay_pipeline(9) * coeff10;
product9 <= delay_pipeline(8) * coeff9;
product8 <= delay_pipeline(7) * coeff8;
product7 <= delay_pipeline(6) * coeff7;
product6 <= delay_pipeline(5) * coeff6;
product5 <= delay_pipeline(4) * coeff5;
product4 <= delay_pipeline(3) * coeff4;
product3 <= delay_pipeline(2) * coeff3;
product2 <= delay_pipeline(1) * coeff2;
product1_cast <= product1;
product1 <= delay_pipeline(0) * coeff1;
sum1 <= product1_cast + product2;
sum2 <= sum1 + product3;
sum3 <= sum2 + product4;
sum4 <= sum3 + product5;
sum5 <= sum4 + product6;
sum6 <= sum5 + product7;
sum7 <= sum6 + product8;
sum8 <= sum7 + product9;
sum9 <= sum8 + product10;
sum10 <= sum9 + product11;
sum11 <= sum10 + product12;

sum12 <= sum11 + product13;

sum13 <= sum12 + product14;
Output_Register_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
output_register <= 0.0000000000000000E+00;
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
output_register <= sum13;
END IF;
END IF;
END PROCESS Output_Register_process;
-- Assignment Statements
filter_out <= output_register;
END rtl;