Program for gate level modelling Half adder

module half_adder(sum,c,inp1,inp2); input inp1,inp2; output sum,c; and(c,inp1,inp2); xor(sum,inp1,inp2); endmodule

Fulla adder

module full_adder(sum,cout,cin,inp1,inp2); input cin, inp1, inp2; output sum,cout; wire w1,w2,w3; xor x1(w1,inp1,inp2); xor x2(sum,w1,cin); and a1(w2,inp1,inp2); and a2(w3,w1,cin); or(cout,w2,w3); endmodule

jk flip flop module jkffgl(j,k,clk,cl,q,qb);

input j,k,clk; input cl; output q,qb; wire j1,k1,q1,qb1,j2,k2,q2,qb2,clk2; not n(clk2,clk); nand n1(j1,j,clk,qb2,cl); nand n2(k1,k,clk,q2); nand n3(q1,j1,qb1); nand n4(qb1,k1,q1); nand n5(j2,q1,clk2); nand n6(k2,qb1,clk2); nand n7(q2,j2,qb2); nand n8(qb2,k2,q2,cl); assign q=q2; assign qb=qb2; endmodule

latches

module SR_latch_gate (input R, input S, output Q, output Qbar); nor (Q, R, Qbar);

nor (Qbar, S, Q); endmodule

SR flip flop module SR_latch_gate (input R, input S, output Q, output Qbar); nor (Q, R, Qbar); nor (Qbar, S, Q); endmodule

half subtractor module half_subtractor ( a ,b ,diff ,borrow ); output diff ; output borrow ; input a ; input b ; assign diff = a ^ b; assign borrow = (~a) & b;

endmodule

2x1 mux

module multiplexer_2_1 ( a ,b ,sel ,dout ); output dout ; input a ; input b ; input sel ; wire m; wire n; wire o;

and u0 (n,m,a); and u1 (o,b,sel); not u2 (m,sel); or u3 (dout,n,o); endmodule

2 bit magnitude comparator module mc2bit(a0,a1,b0,b1,f0,f1,f2); input a0,a1,b0,b1; output f0,f1,f2; wire x,y,u,v,p,q,r,j,k,c,f,g; not(x,a0); not(y,a1); not(u,b0); not(v,b1); //Gate level model

and(p,x,y,b0); and(q,x,b0); and(r,b0,b1,y); or(f0,p,q,r); and(j,a1,b1); and(k,y,v); or(f1,j,k); and(c,a1,u,v); and(f,a0,u); and(g,v,x,y); or(f2,c,f,g);

endmodule JK flip flop Verilog Code for JK-FF Gate level Verilog Code for JK-FF Gate level:

module jkffgl(j,k,clk,cl,q,qb); input j,k,clk; input cl; output

q,qb; wire j1,k1,q1,qb1,j2,k2,q2,qb2,clk2; not n(clk2,clk); nand n1(j1,j,clk,qb2,cl); nand n2(k1,k,clk,q2); nand n3(q1,j1,qb1); nand n4(qb1,k1,q1); nand n5(j2,q1,clk2); nand n6(k2,qb1,clk2); nand n7(q2,j2,qb2); nand n8(qb2,k2,q2,cl); assign q=q2; assign qb=qb2; endmodule encoder ENCODER module encodermod(d, a, b, c); input [0:7] d; output a;

output b; output c; or(a,d[4],d[5],d[6],d[7]); or(b,d[3],d[2],d[6],d[7]); or(c,d[1],d[3],d[5],d[7]); endmodule