library ieee; use ieee.std_logic_1164.

all; entity bejoy_fs is port(x,y,bi: in bit; b2,do,bo: out bit; d,b: inout bit); end bejoy_fs; architecture arc of bejoy_fs is begin d<=x xor y; b<=x and (not y); do<=bi xor d; b2<=bi and (not b); end arc;