ELECTRONICA DIGITAL

UNIDAD 1 ACTIVIDAD 2 COMPARATIVO DE CIRCUITOS DIGITALES.

Facilitador: Gerardo Pazos Rodriguez Alumno: Jos Alberto Snchez Snchez Matricula: AL12507423

Cuadro comparativo de circuitos digitales. Diagrama 1 Funcin Procesador de datos Timer Memoria multifuncional Seal Digital Tipo Conbinacional

2 3

Digital Digital

Secuencial Programado

4 5

Memoria multifuncional Biestable Flip-flop Memoria multifuncional Contador

Digital digital

Conbinacional Secuencial

6 7 8

Secuencial Digital

Conbinacinal Programable Secuencial

Diagrama 1
74259 EasyHDL Model
This sample design shows how a digital part (a 74259) can be modelled by a script written in EasyHDL. This is an alternative to modelling the device as an equivalent circuit and allows for great flexibility in creating your models. The script is held on the schematic and can be seen below the 74259 and above the graph. Most of the script is hidden to avoid clutter - to see it fully point at it with the mouse (you may need to zoom in to point at it accurately) and press CTRL+E to Edit it. Notice that the script not only models the functional behaviour of the device but also its timing based on a set of values selected from the 'value' of the device the script is attached to (in this example, a standard TTL family 74259). For another example of EasyHDL modelling, see the 7493.DSN sample.
U1(D)

U1
U1(A0) U1(A1) U1(A2) 13 1 2 3 14 15 U1(LE) W IDTH=32u START=16u U1(MR) W IDTH=32u START=32u D A0 A1 A2 LE MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 5 6 7 9 10 11 12

U1(Q0) U1(Q1) U1(Q2) U1(Q3) U1(Q4) U1(Q5) U1(Q6) U1(Q7)

74259 PRIMITIVE=DIGITAL,SCRIPT SCRIPT=74XX259 INIT=1

*SCRIPT PROGRAM 74XX259 // This is the model for the 74XX259. To avoid cluttering the diagram // most of the script is hidden. To see the full script point at it with the // mouse (you may need to zoom in first) and press CTRL+E to Edit it. *ENDSCRIPT

74259 EasyHDL Model

E l e c t r o n i c s
Labcenter Electronics, 53-55 Main Street, Grassington, North Yorkshire, BD23 5AA Fax: +44 (0)1756 752857 Tel: +44 (0)1756 753440 http://www.labcenter.co.uk/ Email: info@labcenter.co.uk WWW:

Diagrama 2
AVR External Memory Access
This design demonstrates the VSM simulation of an AT8515 performing external memory access cycles. Note that the clock signal is including as a reference for the timing waveforms but does not actually clock the processor. The CPU clock rate is set by a component property. Note also that being a graph based simulation, this design cannot be simulated with Proteus VSM Lite.

D[0..7]

D[0..7]

U2(XTAL1) 19 18 9

U2
XTAL1 XTAL2 RESET AD[0..7] A[8..15] ALE WR RD 1 2 3 4 5 6 7 8 PD0/RXD PD1/TXD PD2/INT0 PD3/INT1 PD4 PD5/OC1A OC1B ICP 30 U2(WR) 16 17 10 11 12 13 14 15 29 31 U2(RD) U2(ALE) 1 11

U1
D[0..7] Q[0..7]

A[0..7] A[0..7] A[0..15]

U3
A[0..12] 20 26 27 22 D[0..7]

OE LE 74LS373 A[8..15] A[8..15]

A15

CE CS WE OE 6264

PB0/T0 PB1/T1 PB2/AIN0 PB3/AIN1 PB4/SS PB5/MOSI PB6/MISO PB7/SCK

AT90S8515 PROGRAM=EXTRAM1.HEX DBG_PORDELAY=0

AVR External Memory Access

E l e c t r o n i c s
Labcenter Electronics, 53-55 Main Street, Grassington, North Yorkshire, BD23 5AA Fax: +44 (0)1756 752857 Tel: +44 (0)1756 753440 http://www.labcenter.co.uk/ Email: info@labcenter.co.uk WWW:

Diagrama 3
I2C Memory Test
This sample shows the functioning of the a 24C04A I2C serial memory. The source code writes a series of values to address 0x0100-0x010F and then reads them back again verifying each byte as it is read. If an error occurs then the error code is written to Port D and the Status (RA0) line is toggled. A switch on RA5 controls whether or not the write portion of the test is performed. When the switch is closed only a read test is done. This can be used to verify memory persistence.

U2 R2
PULLUP 13 14 1 2 3 4 5 6 7 8 9 10 OSC1/CLKIN OSC2/CLKOUT MCLR/Vpp/THV RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD 33 34 35 36 37 38 39 40 15 16 17 18 23 24 25 26 19 20 21 22 27 28 29 30 D0 D1 D2 D3 D4 D5 D6 D7

STATUS

WRITE MEMORY?

RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RE0/AN5/RD RC2/CCP1 RE1/AN6/WR RC3/SCK/SCL RE2/AN7/CS RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PIC16F877

R1
PULLUP SCK SDA

R3
PULLUP

U1
6 5 7 SCK SDA WP 24C04A A1 A2 2 3

D[0..7]
ErrCode

Diagrama 4

Diagrama 5
SEQUENTIAL LOGIC CIRCUITS - RS FLIP-FLOP

U1 SET

0
NAND

Q-OUTPUT

U2 RESET

0
NAND

Q-OUTPUT

The RS (reset-set) flip-flop is the simplest logic circuit that can exhibit memory behaviour. If the SET input is changed to logic 0, the Q output becomes set to logic 1. When the SET input returns to logic 1, the Q output 'remembers' its state. Similarly, the RESET input will clear the Q output to logic 0. The circuits ability to remember its state derives from the feedback connections from each NAND gate to the other.

Diagrama 6

Diagrama 7

Diagrama 8
7493 EasyHDLModel
This sample shows a 7493 counter modelled using an EasyHDL script. The script is a complete model of both the functional as well as timing behaviour of the 7493. For another example of EasyHDL modelling see the 74259.DSN sample file.
*SCRIPT PROGRAM 7493 ALIAS RA=R0(1), RB=R0(2) IPROP INIT=0 TPROP TDRA, TDRB, TDRC, TDRD TPROP TDLHQA, TDLHQB, TDLHQC, TDLHQD TPROP TDHLQA, TDHLQB, TDHLQC, TDHLQD PIN CKA, CKB, RA, RB PIN QA,QB,QC,QD INT counta = INIT & 1, countb = INIT >> 1 CLOCK 14 1 RESET 2 3 R0(1) R0(2) 7493 PRIMITIVE=DIGITAL SCRIPT=7493

U1
CKA CKB QA QB QC QD 12 9 8 11

A B C D

MAP ON VALUE CASE 7493 : TDRA=26n : TDRB=26n : TDRC=26n : TDRD=26n TDLHQA=10n : TDHLQA=12n : TDLHQB=10n : TDHLQB=14n TDLHQC=21n : TDHLQC=23n : TDLHQD=34n : TDHLQD=34n BREAK ENDMAP IF EVTID=EI_BOOT QA = counta & 1 QB = countb & 1 QC = countb & 2 QD = countb & 4 ELSIF RA & RB counta = 0 QA = FALSE AFTER TDRA countb = 0 QB = FALSE AFTER TDRB QC = FALSE AFTER TDRC QD = FALSE AFTER TDRD ELSE IF CKA=NEGEDGE counta = counta+1 QA = counta & 1 AFTER TDLHQA,TDHLQA ENDIF IF CKB=NEGEDGE countb = countb+1 QB = countb & 1 AFTER TDLHQB,TDHLQB QC = countb & 2 AFTER TDLHQC,TDHLQC QD = countb & 4 AFTER TDLHQD,TDHLQD ENDIF ENDIF *ENDSCRIPT

7493 EasyHDLModel
E l e c t r o n i c s
Labcenter Electronics, 53-55 Main Street, Grassington, North Yorkshire, BD23 5AA Fax: +44 (0)1756 752857 Tel: +44 (0)1756 753440 http://www.labcenter.co.uk/ Email: info@labcenter.co.uk WWW: