Anda di halaman 1dari 2

module FIFO(clk,rst,read,write,in,out,empty,full

);
input clk,rst,read,write;
input [3:0] in;
output [3:0] out;
output empty,full;
reg [3:0] out;
reg [3:0] read_ptr,write_ptr;
reg [3:0] mem [3:0];
wire empty,full;
always@(posedge clk)
begin
if (rst==0)
begin
read_ptr=0;
write_ptr=0;
out=0;
end
else
begin
case({read,write})
2'b00: begin
end
2'b01:
begin
mem[write_ptr]=in;
write_ptr=write_ptr+1;
end
2'b10:
begin
out=mem[read_ptr];
read_ptr=read_ptr+1;
end
2'b11:
begin
/* full chha bhane pahila write garne ani read garne ,
empty chha bhane pahila write ani read otherwise
j gare pani bho */
out=mem[read_ptr];
mem[write_ptr]=in;
write_ptr=write_ptr+1;
read_ptr=read_ptr+1;
end
endcase
end
if (read_ptr[2:0]==write_ptr[2:0])
begin
if (read_ptr[3]==write_ptr[3])
$display ("empty");
else
$display ("Full");
end
end
endmodule