Lenovo Ideapad s10-2 (Kiun0, La-5071p)

A
Compal Confidential
2
KIUN0 Schematics Document

Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
2009-03-31
3
REV: 1.0
2006/08/18
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/8/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Cover Page
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Monday, April 06, 2009
Sheet
E
of
42
Diamondville SC
Compal Confidential
Z ZZ
Model Name : KIUN0

File Name : LA-5071P
PCB
ZZZ1
ZZZ2
FCBGA8
437Pins
ZZZ3
PCB
PCB
PCB
DAZ@
DAZ@
DAZ@
22x22mm
CRT Conn
H_A#(3..31)
page 16
RGB
EMC1402
FSB
H_D#(0..63)
400/533MHz
Memory BUS(DDRII)
DDRII-SO-DIMM
page 13
1.8V DDRII 400/533
LVDS
LCD Conn.
page 4
page 4,5
Calistoga GSE
FCBGA998
Thermal Sensor
Clock Generator
CK505 page 14
27x27mm
page 15
page 6,7,8,9,10
MINI Card x2
DMI
X2 mode
2
page 21
USB
HDA
ICH7M
BGA652
PCI-Express
31x31mm
USB Port X3
page 30
SATA
page 17,18,19,20
MINI Card x1
page 21
BlueTooth
10/100 Ethernet
RTL8103E(L)
page21
page 25
SSD
LPC BUS
HDD
page 21
CMOS CAM
page 24
page24
Transfermer
page 25
Aralia Codec
ALC272
Power ON/OFF
page 22
RJ45
DC/DC Interface
page 31
Card Reader
RTS5159
page 25
page 28
ENE KBC
KB926page
3VALW/5VALW
DC IN
page 37
page 34
1.5VS/0.9VS/
2.5VS
BATT IN
page 39
page 35
CHARGER
27
Int.KBD
AMP & INT

Speaker
page 22
SPI ROM
page 29
1.8V/VCCP
page 36
INT MIC
page 22
HeadPhone &
MIC Jack
SD/MMC/MS
CONN page 26
page 23
page 27
Touch Pad
page 29
page 38
page 26
SPI
CPU_CORE
page 40
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
A
Title
Block Diagrams
Size
B
Date:
Document Number
R ev
0.1
LA-4421P
Sheet
E
of
42
Voltage Rails
External PCI Devices
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+0.9VS
0.9V switched power rail for DDR terminator
ON
OFF
OFF
+VCCP
VCCP switched power rail
ON
OFF
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
DEVICE
+1.8V
1.8V power rail for DDR
ON
ON
OFF
+2.5VS
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
SIGNAL
SLP_S3# SLP_S4# SLP_S5#
PIRQ
EC SM Bus1 address
+VALW
+V
+VS
Clock
Full ON
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
HIGH
HIGH
HIGH
ON
ON
ON
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
ON
OFF
OFF
OFF
S3 (Suspend to RAM)
REQ/GNT #
No PCI Device
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
IDSEL #
EC SM Bus2 address
Device
Address
Device
Address
Smart Battery
0001 011X b
EMC1402
100_1100
ICH7M SM Bus address
BOARD ID Table(Page 25)

ID
0
1
2
3
BRD ID
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
Ra
NC
100K
100K
100K
Rb
0
8.2K
18K
NC
Vab
0V
0.25V
0.50V
3.3V
Device
Address
Clock Generator
(SLG8SP556VTR)
1101 001Xb
DDR DIMMA
1010 000Xb
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
A
Title
Notes List
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Sheet
E
of
42
<18>
H_A20M#
<18>
H_FERR#
<18> H_IGNNE#
<18> H_STPCLK#
<18>
H_INTR
<18>
H_NMI
<18>
H_SMI#
H_IERR#
H_INIT#_R
LOCK#
W20
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
D15
W18
Y17
U20
W19
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
AA17
V20
H_HIT#
H_HITM#
HIT#
HITM#
N280
N280@
<6>
R2441
2 1K_0402_5%
H_LOCK# <6>
H_INIT#
<18>
Close to CPU
H_RS#[0..2] <6>
H_RESET# <6>
<6>
<6>
<6>
H_DSTBN#0
H_DSTBP#0
H_DINV#0
<6>
H_D#[16..31]
H_TRDY# <6>
H_HIT#
H_HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
BR1#
K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15
PROCHOT#
THRMDA
THRMDC
G17
E4
E5
H_PROCHOT#_R
H_THERMDA
H_THERMDC
THERMTRIP#
H17
H_THERMTRIP#
BCLK[0]
BCLK[1]
R242
330_0402_5%
T6
PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
2
22_0402_5%
<6>
<6>
<6>
H_PROCHOT# <40>
Close to CPU
T9
+CPU_GTLREF
CLK_CPU_BCLK
CLK_CPU_BCLK#
V11
V12
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_THERMTRIP# <6,18>
CLK_CPU_BCLK <14>
CLK_CPU_BCLK# <14>
R52
R50
@
@
1
1
Y11
W10
Y12
AA14
AA11
W12
AA16
Y10
Y9
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
V9
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_DP#1
AA5
Y8
W3
U1
W7
W6
Y7
AA6
Y3
W2
V3
U2
T3
AA8
V2
W4
Y4
Y5
Y6
R4
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
A7
U5
V5
T17
R6
M6
N15
N6
P17
T6
J6
H5
G5
GTLREF
COMP[0]
ACLKPH
COMP[1]
DCLKPH
COMP[2]
BINIT#
COMP[3]
MISC
EDM
EXTBGREF
DPRSTP#
FORCEPR#
DPSLP#
HFPLL
DPWR#
MCERR#
PWRGOOD
RSP#
SLP#
BSEL[0]
CORE_DET
BSEL[1]
CMREF[1]
BSEL[2]
PAD
<6>
<6>
1
R24
PAD
2 1K_0402_5%
2 1K_0402_5%
ACLKPH
DCLKPH
+CPU_EXTBGREF
+VCCP
This shall place near CPU

RSVD3
RSVD2
RSVD1
R21
R19
R23
R20
C21
C1
A3
R28
R36
1
1
1
1
1
1
2
2
2
2
ITP_TMS
ITP_TDI
PREQ#
ITP_TDO
56_0402_5%
56_0402_5%
56_0402_5%
56_0402_5%
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
<14> CPU_BSEL0
<14> CPU_BSEL1
<14> CPU_BSEL2
2 100P_0402_50V8J
H_INTR
C394 1
2 100P_0402_50V8J
H_NMI
C395 1
2 100P_0402_50V8J
H_STPCLK# C396 1
2 100P_0402_50V8J
2 100P_0402_50V8J
H_IGNNE# C393 1
R241
1K_0402_1%
+CPU_CMREF
C397 1
2 100P_0402_50V8J
C71
1U_0603_10V4Z
R49
2K_0402_1%
2.2U_0603_10V6K
+5VS
1
U12
EN
VIN
VOUT
VSET
GND
GND
GND
GND
8
7
6
5
1
2
3
4
D19
C296
0.1U_0402_16V4Z
R240
2K_0402_1%
Close to CPU pin

within 500mils.
Zo=55ohm
2
2
1
1
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
H_DPRSTP# <18,40>
H_DPSLP# <18>
H_DPWR# <6>
H_PWRGOOD <18>
H_CPUSLP# <6>
+CPU_CMREF
Zo=27.4ohm +/-15%, make

than 0.5"
Zo=55ohm +/-15%, make
than0.5"
R238
2K_0402_1%
DIODE
Closed to
Connector
+3VS
1SS355_SOD323
@
D20
@ 1N4148_SOT23
1
2
CPU THERMAL SENSOR
1
C80
U2
2
1
VDD
SMCLK
EC_SMB_CK2
H_THERMDA
DP
SMDATA
EC_SMB_DA2
H_THERMDC
2200P_0402_50V7K
DN
ALERT#
C79
C313
1000P_0402_50V7K
1
2
T8
R243
R53
R26
R25
H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil
C314
2.2U_0603_10V6K
1
2
H_DSTBN#3 <6>
H_DSTBP#3 <6>
H_DINV#3 <6>
APL5607KI-TRG_SO8
+3VS
H_D#[48..63] <6>
Close to CPU pin

within 500mils.
Zo=55ohm
0.1U_0402_16V4Z~D
C312
1
+VCC_FAN1
EN_FAN1
Close to CPU pin

within 500mils.
Zo=55ohm
+5VS
<27> EN_FAN1
FAN1 Conn
H_SMI#
1K_0402_5% H_A20M#
1K_0402_5% H_IGNNE#
R18
R17
U4
V17
N18
A13
B7
T7
1
C295
0.1U_0402_16V4Z
2
2
1
1
T1
T2
F20
F21
H_DSTBN#2 <6>
H_DSTBP#2 <6>
H_DINV#2 <6>
2
R48
1K_0402_1%
+CPU_EXTBGREF
+VCCP
R31
R55
R237
1K_0402_1%
+CPU_GTLREF
H_A#32
H_A#33
H_A#34
H_A#35
C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4
H_FERR# C392 1
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DP#3
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_DP#2
PAD
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
H_DP#3
PAD
COMP0
1
COMP1
1
COMP2
2
COMP3
2
2
2
2
2
1
1
1
1
+VCCP
R233
R231
R232
R230
+VCCP
+VCCP
2 100P_0402_50V8J
R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
K2
K3
L1
M4
Layout note:
COMP0,2 connect with
trace length shorter
COMP1,3 connect with
trace length shorter
+VCCP
ESD request
AU80586GE025512_FCBGA437
H_A20M#
C391 1
N270@
.
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DP#2
AU80586GE025512_FCBGA437
N270@
ITP_TCK
ITP_TRST#
2 56_0402_5%
2 56_0402_5%
H_D#[32..47] <6>
U9B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_DP#0
DATA GRP 2
NC1
NC2
NC3
NC4
NC5
NC6
NC7
F16
V16
H_BR0#
H_D#[0..15]
D6
G6
H6
K4
K5
M15
L16
IERR#
INIT#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
H_BR0#
R22
56_0402_5%
H_DEFER# <6>
H_DRDY# <6>
H_DBSY# <6>
<6>
U9
+VCCP
U18
T16
J4
R16
T15
R15
U17
CONTROL
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
PAD
T20
BR0#
THERM
XDP/ITP SIGNALS
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1
H_DEFER#
H_DRD Y#
H_DBSY#
+VCCP
H_ADS# <6>
H_BNR# <6>
H_BPRI# <6>
DATA GRP 1
T4
C19
F19
E21
A16
D19
C14
C18
C20
E20
D20
B18
C15
B16
B17
C16
A17
B14
B15
A14
B19
M18
T21
T19
Y18
DEFER#
DRDY#
DBSY#
ADDR GROUP 1
<6> H_ADSTB#1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_AP1
H_ADS#
H_BNR#
H_BPRI#
H CLK
<6> H_A#[17..31]
V19
Y19
U21
ADS#
BNR#
BPRI#
NC
<6> H_ADSTB#0
<6> H_REQ#[0..4]
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
AP0
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
DATA GRP 0
P21
H20
N20
R20
J19
N19
G20
M19
H21
L20
M20
K19
J20
L21
K20
D17
N21
J21
G19
P20
R19
ADDR
GROUP
0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_AP0
T5
H_REQ#0
PAD
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
DATA GRP 3
U9A
H_A#[3..16]
<6>
THERM#
GND
EC_SMB_CK2 <27>
EC_SMB_DA2 <27>
R58 1
10K_0402_5%
@
+3VS
R256
1K_0402_5%
EMC1402-1-ACZL-TR_MSOP8
40mil
1
2
3
Address:100_1100
JP12
+VCC_FAN1
<27> FAN_SPEED1
1
2
3
G1
G2
4
5
ACES_85204-03001
ME@
C311
100P_0402_50V8J
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
5
Title
Diamondville(1/2)
Size Document Number
Custom
Date:
R ev
0.2
LA-4421P
Sheet
1
of
42
U 9D
A2
A4
A8
A15
A18
A19
A20
B1
B2
B5
B8
B13
B20
B21
C8
C17
D1
D5
D8
D14
D18
D21
E3
E6
E7
E8
E15
E16
E19
F4
F5
F6
F7
F17
F18
G1
G4
G7
G9
G13
G21
H3
H4
H7
H9
H13
H16
H18
H19
J5
J7
J9
J13
J17
K1
K6
K7
K9
K13
K15
K21
L3
L4
L5
L6
L7
L9
L13
L15
L18
L19
M1
M5
M7
M9
M13
M21
N4
VSS1
VSS2
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS41
VSS42
VSS45
VSS46
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14
VCCPC64
VCCPC63
VCCPC62
VCCPC61
F14
F13
E14
E13
+VCCP
V10
A9
B9
VCCF
VCCQ1
VCCQ2
+CPU_CORE
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12
+VCCP
U 9C
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45
0.1U_0402_10V7K
1U_0402_6.3V6K
1
C41
C45
C68
0.1U_0402_10V7K
C72
1U_0402_6.3V6K
PLACE IN CAVITY
+1.5VS
130mA
VCCA
D7
+1.5VS
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
F15
D16
E18
G15
G16
E17
G18
CPU_ VID0
CPU_ VID1
CPU_ VID2
CPU_ VID3
CPU_ VID4
CPU_ VID5
CPU_ VID6
VCCSENSE
C13
V CCSENSE
VCCSENSE <40>
VSSSENSE
D13
VSSSENSE
VSSSENSE <40>
1
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
<40>
<40>
<40>
<40>
<40>
<40>
<40>
C67
0.1U_0402_10V7K
Length match within 25 mils

The trace space 7 mils,
Zo=27.4ohm
AU80586GE025512_FCBGA437
N270@
+CPU_CORE
+CPU_CORE
2 x 330uF(9mohm/2)
PLACE IN CAVITY
1U_0402_6.3V6K
C46
AU80586GE025512_FCBGA437
N270@
C47
C48
1U_0402_6.3V6K
C49
C50
1U_0402_6.3V6K
C51
C52
1U_0402_6.3V6K
C58
C59
1U_0402_6.3V6K
C60
C61
1U_0402_6.3V6K
C62
C64
1U_0402_6.3V6K
C65
C63
1U_0402_6.3V6K
C53
+ C275
+ C278
330U 2.5V Y
2
1U_0402_6.3V6K
C70
C78
2
10U_0805_10V6K
1U_0402_6.3V6K
10U_0805_10V6K
220U_B2_2.5VM_R35
C289
C77
2
1U_0402_6.3V6K
10U_0805_10V6K
C286
2
10U_0805_10V6K
C291
1U_0402_6.3V6K
10U_0805_10V6K
C284
10U_0805_10V6K
C40
2
1U_0402_6.3V6K
10U_0805_10V6K
C76
C294
10U_0805_10V6K
2
1U_0402_6.3V6K
10U_0805_10V6K
C75
10U_0805_10V6K
C280
1U_0402_6.3V6K
330U 2.5V Y
1U_0402_6.3V6K
10U_0805_10V6K
C290
2
A
10U_0805_10V6K
PLACE IN CORRIDOR AND CLOSE TO CPU
Compal Secret Data
2006/08/18
Issued Date
Deciphered Date
2007/8/18
5
Title
Diamondville(2/2)
Size
B
D ate:
Document Number
R ev
0.2
LA-4421P
Sheet
1
of
42
R226
54.9_0402_1%
2
1
+VCCP
H_XRCOMP
H_XSCOMP
+H_SWNG0
H_YRCOMP
H_YSCOMP
+H_SWNG1
R35
24.9_0402_1%
2
1
R227
24.9_0402_1%
2
1
A10
A6
C15
J1
K1
H1
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF0
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_VREF1
F10
C12
H16
E2
B9
C7
G8
B10
E1
H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_VREF
AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DBSY#
H_DEFER#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DPWR#
H_DRD Y#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10
H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_TRDY#
HCLKN
HCLKP
H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
U8B
<19>
<19>
<19>
<19>
DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1
<19>
<19>
<19>
<19>
DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1
DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1
Y29
Y32
Y28
Y31
DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1
V28
V31
V29
V32
M_CLK_DDR0
M_CLK_DDR1
<13> M_CLK_DDR0
<13> M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
<13> M_CLK_DDR#0
<13> M_CLK_DDR#1
SM_CK_0
SM_CK_1
AJ1
AM30
SM_CK_2
SM_CK_3
AG33
AF1
<13> DDR_CS0#
<13> DDR_CS1#
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_RESET# <4>
CLK_MCH_BCLK# <14>
CLK_MCH_BCLK <14>
H_DBSY# <4>
H_DEFER# <4>
H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>
H_DPWR# <4>
H_DRDY# <4>
<13>
<13>
+1.8V
R56
1
1
R54
M_ODT0
M_ODT1
2 80.6_0402_1%
2
80.6_0402_1%
+DIMM_VREF
RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
DDR_CKE0
DDR_CKE1
AN21
AN22
AF26
AF25
DDR_CS0#
DDR_CS1#
AG14
AF12
AK14
AH12
AJ21
AF11
SM_OCDCOMP_0
SM_OCDCOMP_1
M_ODT0
M_ODT1
AE12
AF14
AJ14
AJ12
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SMRCOMPN
SMRCOMPP
AN12
AN14
AA33
AE1
SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1
10uA
1
CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6
DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1
AF33
AG1
AK1
AN30
<13> DDR_CKE0
<13> DDR_CKE1
DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
Layout Note:
+DIMM_VREF trace
width and spacing
is 20/20.
CFG/RSVD
F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17
DMI
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
DDR2 MUXING
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
C18
E18
G20
G18
J20
J18
E31
G21
F26
H26
J15
AB29
W27
D_REFCLKN
D_REFCLKP
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#
A27
A26
J33
H33
J22
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
MCH_CLKSEL0 <14>
MCH_CLKSEL1 <14>
MCH_CLKSEL2 <14>
2
2.2K_0402_5%
MCH_ICH_SYNC# <17>
PM_BMBUSY# <19>
PM_EXTTS#0
PM_EXTTS#0 <13>
PM_EXTTS#1 2
1
PM_DPRSLPVR <19,40>
R44 0_0402_5%
H_THERMTRIP#
H_THERMTRIP# <4,18>
ICH_POK
ICH_POK
<19,27>
PLTRST_R# 1
2
PLTRST# <17,19,21,25>
R47 100_0402_5%
CLK_MCH_DREFCLK# <14>
CLK_MCH_DREFCLK <14>
MCH_SSCDREFCLK# <14>
MCH_SSCDREFCLK <14>
MCH_CLKREQ# <14>
Calistoga-GSE_FCBGA998
H_DSTBN#[0..3] <4>
H_DSTBP#[0..3] <4>
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
T2
C FG5
1 PAD
R34
PAD T3
K32
K31
C17
F18
A3
PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
THRMTRIP#
PWROK
RSTIN#
PM
C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
M5
K5
J5
H3
J4
N3
M4
M3
N8
N6
K3
N9
M1
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
W2
W1
V2
W4
W7
W5
V5
AB4
AB8
W8
AA9
AA8
AB1
AB7
AA2
AB5
H_A#[3..31] <4>
U8A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
R37
54.9_0402_1%
2
1
C293
0.1U_0402_16V4Z
H_D#[0..63]
HOST
<4>
CLK
Strap Pin Table
H_HIT#
<4>
H_HITM# <4>
H_LOCK# <4>
CFG5
Low
= DMI x 2
High = DMI x 4
H_REQ#[0..4] <4>
H_RS#[0..2] <4>
H_CPUSLP# <4>
H_TRDY# <4>
+3VS
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
PM_EXTTS#0
PM_EXTTS#1
+VCCP
1
R42
1
R43
2
10K_0402_5%
2
10K_0402_5%
+VCCP
1
R33
2
221_0402_1%~D
1
2
221_0402_1%~D
R18
100_0402_1%
+H_SWNG0
+H_SWNG1
0.1U_0402_16V4Z
C33
1
R30
2
100_0402_1%
0.1U_0402_16V4Z
C29
1
2
C be placed <100mils
from GMCH pin
100_0402_1%
R17
C31
+H_VREF
0.1U_0402_16V4Z
R29
200_0402_1%
R27
+VCCP
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
5
Title
Calistoga(1/5)-GTL/DMI/DDR
Custom
Date:
R ev
0.2
LA-4421P
Sheet
1
of
42
U8C
<13> DDR_A_BS0
<13> DDR_A_BS1
<13> DDR_A_BS2
<13> DDR_A_DM[0..7]
<13> DDR_A_DQS[0..7]
<13> DDR_A_DQS#[0..7]
AK12
AH11
AG17
SA_BS_0
SA_BS_1
SA_BS_2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
AB30
AL31
AF30
AK26
AL9
AG7
AK5
AH3
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AC28
AJ30
AK33
AL25
AN9
AH8
AM2
AE3
DDR_A_DQS#0 AC29
DDR_A_DQS#1 AK30
DDR_A_DQS#2 AJ33
DDR_A_DQS#3 AM25
DDR_A_DQS#4 AN8
DDR_A_DQS#5 AJ8
DDR_A_DQS#6 AM3
DDR_A_DQS#7 AE2
<13> DDR_A_MA[0..13]
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
AJ15
AM17
AM15
AH15
AK15
AN15
AJ18
AF19
AN17
AL17
AG16
AL18
AG18
AL14
DDR_A_CAS# AJ17
DDR_A_RAS# AK18
AN28
AM28
DDR_A_WE# AH17
<13> DDR_A_CAS#
<13> DDR_A_RAS#
<13> DDR_A_WE#
AH21
AJ20
AE27
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
DDR2 SYSTEM MEMORY
SB_BS_0
SB_BS_1
SB_BS_2
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
SB_CAS#
SB_RAS#
SB_WE#
AG19
AG21
AG20
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D[0..63] <13>
Compal Secret Data
2006/08/18
Issued Date
Deciphered Date
2007/8/18
5
Title
Calistoga(2/5)-DDR2
Custom
Date:
R ev
0.2
LA-4421P
Sheet
1
of
42
U 8F
H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL
LVDS_ACLK#
LVDS_ACLK
D30
C30
A30
A29
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
<15> LVDS_A0#
<15> LVDS_A1#
<15> LVDS_A2#
LVDS_A0#
LVDS_A1#
LVDS_A2#
G31
F32
D31
LA_DATAN_0
LA_DATAN_1
LA_DATAN_2
<15> LVDS_A0
<15> LVDS_A1
<15> LVDS_A2
LVDS_A0
LVDS_A1
LVDS_A2
H31
G32
C31
LA_DATAP_0
LA_DATAP_1
LA_DATAP_2
F33
D33
F30
LB_DATAN_0
LB_DATAN_1
LB_DATAN_2
E33
D32
F29
LB_DATAP_0
LB_DATAP_1
LB_DATAP_2
<16> GMCH_CRT_R
2
R39
1
255_0402_1%
R224 2
<16> GMCH_CRT_VSYNC
<16> GMCH_CRT_HSYNC
2
R38
<15> LVDS_SCL
<15> LVDS_SDA
<15> GMCH_ENVDD
1
1.5K_0402_1%
<15> LVDS_ACLK#
<15> LVDS_ACLK
+3VS
1
R32
1
R40
GMCH_CRT_R
CRT_ IREF
1 100K_0402_5%
<27> GMCH_ENBKL
GMCH_CRT_G
LCTLA_CLK
2
10K_0402_5%
LCTLB_DATA
2
10K_0402_5%
LCTLA_CLK
LCTLB_DATA
LVDS_SCL
LVDS_SDA
L_IBG
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
N30
R30
T29
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
M30
P30
T30
SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN
P28
N32
P32
T32
SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP
N28
M32
P33
R32
PEGCOMP
+1.5VS_PCIE
R45
24.9_0402_1%
2
+1.5VS
TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
A21
C20
E20
G23
B21
C21
D21
TV_DCONSEL0
TV_DCONSEL1
G26
J26
TV
<16> GMCH_CRT_G
EXP_A_COMPI
EXP_A_ICOMPO
R28
M28
SDVO
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF
GMCH_CRT_B
VGA
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
<16> GMCH_CRT_CLK
<16> GMCH_CRT_DATA
<16> GMCH_CRT_B
Close to U8.H25
SDVO_CTRLDATA
SDVO_CTRLCLK
G_CLKN
G_CLKP
MISC
<14> CLK_MCH_3GPLL#
<14> CLK_MCH_3GPLL
GMCH_CRT_R
150_0402_1%
GMCH_CRT_G
1
150_0402_1%
GMCH_CRT_B
1
150_0402_1%
LVDS
2
R225
2
R223
2
R222
H27
J27
Y26
AA26
Disable TV
Compal Secret Data
2006/08/18
Issued Date
Deciphered Date
2007/8/18
5
Title
Calistoga(3/5)-VGA/LVDS/TV
Size
B
D ate:
Document Number
R ev
0.2
LA-4421P
Sheet
1
of
42
+1.5VS
U8E
+VCCP
T10
R10
P10
N10
L10
D1
M10
A18
AB10
AA10
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
RSVD_3
RSVD_4
RSVD_5
RSVD_6
NCTF
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
CFG_19
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25
AH33
Y33
V33
R33
G33
AK32
AG32
AE32
AC32
AA32
U32
H32
E32
C32
AM31
AJ31
AA31
U31
T31
R31
P31
N31
M31
J31
F31
AL30
AG30
AE30
AC30
AA30
Y30
V30
U30
G30
E30
B30
AA29
U29
R29
P29
N29
M29
H29
E29
B29
AK28
AH28
AE28
AA28
U28
T28
J28
D28
AM27
AF27
AB27
AA27
Y27
U27
T27
R27
P27
N27
M27
G27
E27
C27
B27
AL26
AH26
W26
U26
AN25
AK25
AG25
AE25
J25
G25
A25
H23
F23
B23
AM22
AJ22
AF22
G22
E22
J21
H21
F21
AM20
AK20
AH20
AF20
D20
W19
R19
AM18
AH18
AF18
U18
H18
D18
AK17
V17
T17
F17
B17
AH16
U16
AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1
K28
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15
U8G
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS
U8H
T25
R25
P25
N25
M25
P24
N24
M24
Y22
W22
V22
U22
T22
R22
P22
N22
M22
Y21
W21
V21
U21
T21
R21
P21
N21
M21
Y20
W20
V20
U20
T20
R20
P20
N20
M20
Y19
P19
N19
M19
Y18
P18
N18
M18
Y17
P17
N17
M17
Y16
P16
N16
M16
Y15
P15
N15
M15
Y14
W14
V14
U14
T14
R14
P14
N14
M14
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1
W33
AM33
AL33
C33
B33
AN32
A32
AN31
W28
V27
W29
J24
H24
W32
G24
F24
E24
D24
K33
A31
E21
C23
AN19
AM19
AL19
AK19
AJ19
AH19
AN3
Y9
J19
H19
G19
F19
E19
D19
C19
B19
A19
Y8
G16
F16
E16
D16
C16
B16
AN2
A16
Y7
AM4
AF4
AD4
AL4
AK4
W31
AJ4
AH4
AG4
AE4
AM1
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55
NC56
NC57
NC58
NC59
NC60
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72
W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18
NC
+VCCP
RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42
Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
5
Title
Calistoga(4/5)-PWR/GND
Custom
Date:
R ev
0.2
LA-4421P
Sheet
1
of
42
10mil
U1_AA1
U1_F1
10mil
2
C66
0.47U_0603_16VY5V
VTT41
VTT42
VTT43
VTT44
VTT45
10mil
1
C85
1U_0603_10V4Z
C69
0.1U_0402_16V4Z
L9
1
+1.5VS
FBMA-L10-160808-301LMT_2P
1
+2.5VS60mA
+2.5VS
1
Route +2.5VS from GMCH pinN33 to

decoupling cap <200mil to the edge.
C39
2
400mA
+1.5VS
FBMA-L10-160808-301LMT_2P
1
+
2
+1.5VS_PCIE
+1.5VS_3GPLL
+2.5VS
+2.5VS_CRTDAC
+VCCP
+2.5VS
70mA
70mA
1
R229 1
2
10_0603_5%
1
+2.5VS
CRTDAC: Route FB
within 3" of Calistoga
R239
2
1
0_0805_5%
+1.5VS
1
+
2
+2.5VS
C30
0.47U_0603_16VY5V
Route VSSACRTDAC gnd from GMCH to

decoupling cap ground lead and then
connect to the gnd plane.
+2.5VS
close pin C29/D29
2006/08/18
Issued Date
2007/8/18
Deciphered Date
4
2
A
close pin B31
Compal Secret Data
40mA Max.
+1.5VS_MPLL 45mA
+1.5VS_HPLL 45mA
+1.5VS_DPLLA 50mA
+1.5VS_DPLLB 50mA
+1.5VS150mA
+2.5VS
+1.5VS_DPLLA
L10
1
C281
10U_0805_10V4Z
C282
0.1U_0402_16V4Z
C288
0.1U_0402_16V4Z
C74
4.7U_0603_6.3V4Z
C287
10U_0805_10V4Z
40mA Max.
+1.5VS_DPLLB
C81
1U_0603_10V4Z
10mil
C54
10U_0805_10V4Z
C56
0.1U_0402_16V4Z
C265
10U_0805_10V4Z
C20
0.1U_0402_16V4Z
C24
0.1U_0402_16V4Z
C269
10U_0805_10V4Z
C83
4.7U_0603_6.3V4Z
P1
L1
G1
U1
Y1
+1.5VS
C272
0.1U_0402_16V4Z
R235
0_0603_5%
2
1
+1.5VS
C271
0.01U_0402_25V7K
45mA Max.
+1.5VS_HPLL
C42
4.7U_0603_6.3V4Z
R236
0_0603_5%
2
1
C35
0.1U_0402_16V4Z
10mil
C292
220U_B2_2.5VM_R35
C57
4.7U_0603_6.3V4Z
C38
4.7U_0603_6.3V4Z
C273
220U_B2_2.5VM_R35
0.47U_0603_16VY5V
+1.8V
533 MTS=1720mA
45mA Max.
+1.5VS_MPLL
2
C283
10U_0805_10V4Z
U1_A7
210mil
C285
10U_0805_10V4Z
C267
1
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40
C270
10U_0805_10V4Z
0.47U_0603_16VY5V
A14
D10
P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6
G6
D6
U5
P5
L5
G5
D5
Y4
U4
P4
L4
G4
D4
Y3
U3
P3
L3
G3
D3
Y2
U2
P2
L2
G2
D2
AA1
F1
C263
U1_A14
0_0603_5%
1
330U_D2E_2.5VM
C21
10mil
+1.5VS
0.1U_0402_16V4Z~D
10mil
C264
10mil
U1_AB33
U1_AM32
330U_D2E_2.5VM
C36
780mA
C268
+3VS
0.1U_0402_16V4Z
+VCCP
40mA
C34
0.1U_0402_16V4Z
+1.5VS
C84
1U_0603_10V4Z
20mA
C25
10U_0805_10V4Z
+1.5VS
R46
+1.5VS_3GPLL
C28
0.1U_0402_16V4Z
C32
0.1U_0402_16V4Z
1250mA
+1.5VS_3GPLL
C27
0.022U_0402_16V7K
+1.5VS
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
PCI-E/MEM/PSB PLL decoupling

Disable TV
0.1U_0402_16V4Z~D
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15
J14
J10
H10
AE9
AD9
U9
AD8
AD7
AD6
B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26400mA
N33 2mA
M33
J23
C24
B24
B25
B31 10mA
B32
C73
1U_0603_10V4Z
VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1
VCCATVBG
VSSATVBG
VCCDTVDAC
VCCDQTVDAC
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCAMPLL
VCCAHPLL
VCCADPLLA
VCCADPLLB
VCCDHMPLL1
VCCDHMPLL2
VCCTXLVDS0
VCCTXLVDS1
VCC3G0
VCC3G1
VCCA3GPLL
VCCA3GBG
VSSA3GBG
VCCSYNC
VCCACRTDAC0
VCCACRTDAC1
VSSACRTDAC
VCCALVDS
VSSALVDS
C82
1U_0603_10V4Z
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
C297
1U_0603_10V4Z
T26
R26
P26
N26
M26
V19
U19
T19
W18
V18
T18
R18
W17
U17
R17
W16
V16
T16
R16
V15
U15
T15
POWER
C43
0.1U_0402_16V4Z
C55
0.1U_0402_16V4Z
C37
0.1U_0402_16V4Z
144mA
U8D
C274
10U_0805_10V4Z
C279
10U_0805_10V4Z
C44
220U_B2_2.5VM_R35
2940mA
+1.5VS
+VCCP
Title
Calistoga(5/5)-PWR/GND
Custom
Date:
R ev
0.2
LA-4421P
Sheet
1
10
of
42
+1.8V
+1.8V
JDIM1
<7> DDR_A_DQS#[0..7]
+DIMM_VREF
+1.8V
<7> DDR_A_D[0..63]
<7> DDR_A_DM[0..7]
DDR_A_D0
DDR_A_D1
Layout Note:
Place near JDIM1
<7> DDR_A_DQS[0..7]
DDR_A_D2
DDR_A_D3
1K_0402_1%
2
<7> DDR_A_MA[0..13]
DDR_A_DQS#0
DDR_A_DQS0
R61
+DIMM_VREF
DDR_A_D9
DDR_A_D8
Share +DIMM_VREF for

1.DDRII VREF
2.GMCH SM_VREF_0
SM_VREF_1
R62
1K_0402_1%
C130
2.2U_0603_6.3V4Z
C109
2.2U_0603_6.3V4Z
C107
0.1U_0402_16V4Z
C108
0.1U_0402_16V4Z
C110
2.2U_0603_6.3V4Z
C105
0.1U_0402_16V4Z
C129
2.2U_0603_6.3V4Z
C106
0.1U_0402_16V4Z
C94
220U_B2_2.5VM_R35
C128
2.2U_0603_6.3V4Z
+1.8V
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
20mils
DDR_A_D16
DDR_A_D17
1
C111
0.1U_0402_16V4Z
2
DDR_A_DQS#2
DDR_A_DQS2
C112
2.2U_0603_6.3V4Z
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
2
DDR_A_D26
DDR_A_D27
<6>
DDR_CKE0
<7> DDR_A_BS2
DDR_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
<7> DDR_A_BS0
<7> DDR_A_WE#
<7> DDR_A_CAS#
<6> DDR_CS1#
<6>
M_ODT1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1#
M_ODT1
DDR_A_D32
DDR_A_D33
+0.9VS
C89
0.1U_0402_16V4Z
C118
0.1U_0402_16V4Z
C120
0.1U_0402_16V4Z
C90
0.1U_0402_16V4Z
C91
0.1U_0402_16V4Z
C115
0.1U_0402_16V4Z
C122
0.1U_0402_16V4Z
C88
0.1U_0402_16V4Z
C87
0.1U_0402_16V4Z
C121
0.1U_0402_16V4Z
C86
0.1U_0402_16V4Z
C117
0.1U_0402_16V4Z
C119
0.1U_0402_16V4Z
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
1
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
+0.9VS
1
2
3
4
RP5
8
7
6
5
56_0804_8P4R_5%
RP2
1
8
2
7
3
6
4
5
8
7
6
5
1
2
3
4
DDR_A_RAS#
DDR_A_MA4
DDR_A_MA2
DDR_A_BS1
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_CAS#
56_0804_8P4R_5%
RP4
DDR_CKE1
8
1
DDR_A_MA7
7
2
DDR_A_MA6
6
3
DDR_A_MA11
5
4
56_0804_8P4R_5%
RP3
DDR_A_WE# 1
8
DDR_A_BS0 2
7
M_ODT1
3
6
DDR_CS1#
4
5
56_0804_8P4R_5%
RP1
8
1 DDR_A_MA12
7
2 DDR_A_MA9
6
3 DDR_A_MA8
5
4 DDR_A_MA10
56_0804_8P4R_5%
DDR_A_BS2
1 R60
2
56_0402_5%
1 R59
2
56_0402_5%
DDR_CKE0
DDR_A_D56
DDR_A_D57
DDR_A_DM7
Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil
DDR_A_D58
DDR_A_D59
<14> CLK_SMBDATA
<14> CLK_SMBCLK
+3VS
CLK_SMBDATA
CLK_SMBCLK
+3VS
C116
56_0804_8P4R_5%
Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"
0.1U_0402_16V4Z
RP6
DDR_A_MA0
DDR_A_MA13
DDR_CS0#
M_ODT0
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
D
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>
DDR_A_D14
DDR_A_D15
+DIMM_VREF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
DDR_A_D20
DDR_A_D21
R64
DDR_A_DM2
2
0_0402_5%
PM_EXTTS#0 <6>
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1
DDR_CKE1 <6>
C
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0#
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0# <6>
M_ODT0
DDR_A_MA13
M_ODT0 <6>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
B
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R66
R65
1
1
2 10K_0402_5%
2 10K_0402_5%
FOX_AS0A426-N4SN-7F
DIMMA
Compal Secret Data

2006/08/18
2007/8/18
Deciphered Date
3
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
ME@
Issued Date
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Title
DDRII-SODIMMA
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Sheet
1
13
of
42
FSB
FSA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
266
100
33.3
14.318
DOT_96 USB
MHz
MHz
96.0
1
R137
+3VS
2
0_0805_5%
48.0
2
133
100
33.3
14.318
96.0
48.0
200
100
33.3
14.318
96.0
48.0
+3VM_CK505
+3VS
C174
10U_0805_10V4Z
C172
0.1U_0402_16V4Z
C138
0.1U_0402_16V4Z
C148
0.1U_0402_16V4Z
C140
0.1U_0402_16V4Z
C160
0.1U_0402_16V4Z
C169
R72
0.1U_0402_16V4Z
+1.05VM_CK505
0
1
166
100
333
33.3
100
14.318
33.3
14.318
96.0
96.0
2
0_0805_5%
48.0
48.0
C175
10U_0805_10V4Z
<19> ICH_SMBDATA
C139
0.1U_0402_16V4Z
C167
0.1U_0402_16V4Z
C137
0.1U_0402_16V4Z
C146
0.1U_0402_16V4Z
C165
0.1U_0402_16V4Z
C173
100
100
33.3
14.318
96.0
48.0
400
100
33.3
14.318
96.0
48.0
SDA
VDD_SRC
SCL
6
+VCCP
CLK_SMBDATA
10
CLK_SMBCLK
71
CLK_CPU_BCLK
70
CLK_CPU_BCLK#
68
CLK_MCH_BCLK
VDD_PCI
CPU_0
VDD_CPU
CPU_0#
67
CLK_MCH_BCLK#
24
CLK_MCH_DREFCLK
25
CLK_MCH_DREFCLK#
28
MCH_SSCDREFCLK
29
MCH_SSCDREFCLK#
32
CLK_MCH_3GPLL
33
CLK_MCH_3GPLL#
72
CPU_BSEL0
1K_0402_5%
@
C386
10P_0402_50V8J
1
@
C387
33_0402_5% 1
1
2
R113
FSB
<19> CLK_ICH_14M
C390
MCH_CLKSEL1 <6>
R115
1K_0402_5%
VDD_PLL3_IO
SRC_0#/DOT_96#
62
VDD_SRC_IO
LCDCLK/27M
VDD_SRC_IO
LCDCLK#/27M_SS
38
VDD_SRC_IO
2 R104
20
FSB
F SC
USB_0/FS_A
SRC_3
FS_B/TEST_MODE
SRC_3#
REF_1
SRC_4
12P_0402_50V8J
VGATE
SRC_4#
NC
SRC_6
SRC_6#
<19> H_STP_CPU#
<19> H_STP_PCI#
53
H_STP_PCI#
54
CLK_XTAL_IN
CPU_STOP#
SRC_7
PCI_STOP#
SRC_7#
+VCCP
CLK_XTAL_OUT
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
CLK_MCH_DREFCLK <6>
CLK_MCH_DREFCLK# <6>
MCH_SSCDREFCLK <6>
MCH_SSCDREFCLK# <6>
CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>
PORT
DEVICE
SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11
MCH_DREFCLK
MCH_3GPLL
C
PCIE_SATA
PCIE_WLAN
PCIE_LAN
PCIE_ICH
35
36
39
CLK_PCIE_SATA
40
CLK_PCIE_SATA#
CLK_PCIE_SATA <18>
CLK_PCIE_SATA# <18>
CKPWRGD/PD#
11
H_STP_CPU#
CLK_CPU_BCLK <4>
REF_0/FS_C/TEST_
<19,27,40> VGATE
R110
@
0_0402_5%
SRC_2
SRC_2#
FSA
SRC PORT LIST
CLK_SMBCLK <13>
VDD_IO
2
2
22_0402_5%
R75 1
2
22_0402_5%
2
10P_0402_50V8J
<19> CLK_ICH_48M
1K_0402_5%
@
1
2
31
CLK_48M_CR 1
<26> CLK_48M_CR
+VCCP
SRC_0/DOT_96
23
R74
1
2
R119
0_0402_5%
CPU_1#
VDD_CPU_IO
52
CPU_BSEL1
CPU_1
1
R73
<4>
VDD_PLL3
66
+1.05VM_CK505
MCH_CLKSEL0 <6>
R67
1K_0402_5%
1
2
R69
0_0402_5%
VDD_48
27
<4>
19
R68
@
56_0402_5%
CLK_SMBDATA <13>
VDD_REF
12
CLK_SMBCLK
U4
55
SA000020K00 (Silego : SLG8SP556VTR )

SA000020H10 (ICS : ICS9LPRS387AKLFT)
+3VM_CK505
CLK_SMBDATA
Q10B
2N7002DW-T/R7_SOT363-6
Reserved
R76
2.2K_0402_5%
FSA 2
1
+3VS
0.1U_0402_16V4Z
<19> ICH_SMBCLK
2.2K_0402_5%
1
R138
+VCCP
R91
2.2K_0402_5%
2N7002DW-T/R7_SOT363-6
Q10A
FSC
XTAL_IN
SRC_8/CPU_ITP
XTAL_OUT
SRC_8#/CPU_ITP#
57
CLK_PCIE_WLAN
56
CLK_PCIE_WLAN#
CLK_PCIE_WLAN <21>
CLK_PCIE_WLAN# <21>
61
60
64
63
+3VS
1
2
R84
0_0402_5%
MCH_CLKSEL2 <6>
R79
1K_0402_5%
R87
@
0_0402_5%
<27> CLK_PCI_LPC
33_0402_5% 1
2 R86
PCI4_SEL
16
<17> CLK_PCI_ICH
33_0402_5% 1
2 R80
ITP_EN
17
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25
Pin28/29
1 = Pin24/25
Pin28/29
14
15
:
:
:
:
C389 1
@
DOT96 / DOT96#
LCDCLK / LCDCLK#
SRC_0 / SRC_0#
27M/27M_SS
10P_0402_50V8J
CPU_BSEL2
PCI2_TME
10P_0402_50V8J
<4>
13
1K_0402_5%
@
1
2
F SC
R92
R98
10K_0402_5%
2
1
C388
@
SRC_10
SRC_10#
SRC_11
18
VSS_PCI
42
R85
R95
R71
10K_0402_5%
@
10K_0402_5%
Routing the trace at least 10mil
50
CLK_PCIE_ICH
51
CLK_PCIE_ICH#
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>
CLK_PCIE_ICH <19>
MCH_CLKREQ#
W LAN_CLKREQ#
SATA_CLKREQ#
CLKREQ_LAN#
R78
R121
R105
R106
2
2
2
2
1
1
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
CLK_PCIE_ICH# <19>
SRC_11#
REQ PORT LIST
48
47
PORT
37
VSS_IO
CLKREQ_4#
41
SATA_CLKREQ#
VSS_CPU
CLKREQ_6#
58
W LAN_CLKREQ#
VSS_PLL3
CLKREQ_7#
VSS_SRC
CLKREQ_9#
VSS_SRC
SLKREQ_10#
VSS_SRC
CLKREQ_11#
VSS
USB_1/CLKREQ_A#
SATA_CLKREQ# <19>
W LAN_CLKREQ# <21>
65
43
CLKREQ_LAN#
CLKREQ_LAN# <25>
49
46
21
MCH_CLKREQ#
MCH_CLKREQ# <6>
DEVICE
REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#
PCIE_SATA
PCIE_WLAN
PCIE_LAN
A
MCH_3GPLL
SLG8SP556VTR_QFN72_10X10
PCI2_TME
CLK_XTAL_OUT
22P_0402_50V8J
PCI4_SEL
R89
R90
@
R77
10K_0402_5%
10K_0402_5%
10K_0402_5%
C164
ITP_EN
73
Issued Date
Compal Secret Data
Y1
14.31818MHZ_16PF_DSX840GA
CLK_PCIE_LAN#
CLKREQ_3#
VSS_48
59
10K_0402_5%
@
22P_0402_50V8J
CLK_PCIE_LAN
45
VSS_REF
22
30
CLK_XTAL_IN
C161
44
PCIF_5/ITP_EN
69
+3VS
+3VS
SRC_9#
PCI_4/SEL_LCDCL
34
+3VS
SRC_9
PCI_2
PCI_3
26
For PCI2_TME:0=Overclocking of CPU and SRC allowed

(ICS only)
1=Overclocking of CPU and SRC NOT allowed
PCI_1
2007/10/15
Deciphered Date
2008/10/15
3
Title
Clock Generator CK505

Size
Document Number
Rev
0.2
LA-4421P
Date:
Sheet
1
14
of
42
LCD POWER CIRCUIT

+3VS
+3VALW
+LCDVDD
1
W=20mils
3
1
Q20
DTC124EK_SC59
Q22
SI2301BDS_SOT23
100K_0402_5%
C262
2
G
S
+LCDVDD
0.1U_0402_16V4Z
W=20mils
<8> GMCH_ENVDD
C260
@
4.7U_0805_10V4Z
R221
G
1 2
R219
47K_0402_5%
D
Q21
2N7002_SOT23
R218
150_0603_5%
C261
0.1U_0402_16V4Z
C12
+LCDVDD_L 1
C18
JLVDS1
21
GND
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+INVPWR_B+
1
L8
+LCDVDD_L
INVT_PWM
BKOFF#
LVDS_SDA
LVDS_SCL
LVDS_SCL <8>
LVDS_SDA
LVDS_SDA <8>
B+
+LCDVDD
INVT_PWM <27>
BKOFF#
+3VS
BKOFF# <27>
INVT_PWM
BKOFF#
LVDS_ACLK#
LVDS_ACLK
LVDS_A2#
LVDS_A2
LVDS_A1#
LVDS_A1
LVDS_A0#
LVDS_A0
LVDS_ACLK# <8>
LVDS_ACLK <8>
LVDS_A2# <8>
LVDS_A2 <8>
C11
220P_0402_50V7K
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
LVDS_SCL
FBMA-L11-201209-221LMA30T_0805
2
FBMA-L11-201209-221LMA30T_0805
2
22
L1
2
4.7U_0805_10V4Z
0.1U_0603_50V4Z
R6
10K_0402_5%
LCD/PANEL BD. Conn.
R7
10K_0402_5%
1
2
+3VS
C10
220P_0402_50V7K
LVDS_A1# <8>
LVDS_A1 <8>
LVDS_A0# <8>
LVDS_A0 <8>
ACES_87213-2000G
ME@
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
5
Title
LVDS /INVERTER
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Sheet
1
15
of
42
PSOT24C_SOT23-3
L15
1
<8> GMCH_CRT_R
L14
<8> GMCH_CRT_G
<8> GMCH_CRT_B
R250
150_0402_1%
2
1
R253
150_0402_1%
2
1
R255
150_0402_1%
2
1
L12
C310
C308
C303
P
2
A
3
GREEN
BK1608LL121-T_2P
2
BLUE
L13
1
FCM1608CF-121T03_2P
2
L11
1
FCM1608CF-121T03_2P
2
C306
10P_0402_50V8J
2
@
C304
10P_0402_50V8J
@
JVGA_HS
JVGA_VS
2
U11
CRT_HSYNC_1
C302
10P_0402_50V8J
@
<8> GMCH_CRT_HSYNC
39_0402_5%
1 R249
2
2
0.1U_0402_16V4Z
R ED
BK1608LL121-T_2P
2
C307
10P_0402_50V8J
2
@
2 @
2 @
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
OE#
1
C301
2 @
+CRT_VCC
BK1608LL121-T_2P
2
@
D17
PSOT24C_SOT23-3
@
D18
Close to CRT CONN for ESD.
SN74AHCT1G125DCKR_SC70-5
C300
10P_0402_50V8J
2
@
1
C298
2
0.1U_0402_16V4Z
Place closed to chipset
+CRT_VCC
U10
OE#
@
1 R247
2
39_0402_5%
CRT_VSYNC_1
SN74AHCT1G125DCKR_SC70-5
<8> GMCH_CRT_VSYNC
CRT PORT
+3VS
1.1A_6V_SMD1812P110TF
2.2K_0402_5%
R248
+3VS
D2
1
W=40mils
0.1U_0402_16V4Z
F1
2
C123
1
2
ME@
JCRT1
R245
2.2K_0402_5%
R246
R251
RB491D_SOT23-3
R ED
VGA_DDC_DAT
GREEN
VGA_DDC_DAT
JVGA_HS
BLUE
Q24B
2N7002DW-T/R7_SOT363-6
VGA_DDC_CLK
6
<8> GMCH_CRT_DATA
2.2K_0402_5%
2
2.2K_0402_5%
<8> GMCH_CRT_CLK
+CRT_VCC
+5VS
+CRT_VCC
3
JVGA_VS
Q24A
2N7002DW-T/R7_SOT363-6
VGA_DDC_CLK
@
C305
100P_0402_50V8J
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
SUYIN_070546FR015SX28XR
C299
100P_0402_50V8J
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
A
Title
CRT PORT
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Sheet
E
16
of
42
+3VS
U17B
2 8.2K_0402_5%
PCI_STOP#
R153 1
2 8.2K_0402_5%
PCI_TRD Y#
R151 1
2 8.2K_0402_5%
P CI_FRAME#
R155 1
2 8.2K_0402_5%
PCI_PLOCK#
R158 1
2 8.2K_0402_5%
P C I_ I RDY#
R156 1
2 8.2K_0402_5%
PCI_SERR#
R157 1
2 8.2K_0402_5%
PCI_PERR#
+3VS
R160 1
2 8.2K_0402_5%
PCI_ PIRQA#
R159 1
2 8.2K_0402_5%
PCI_ PIRQB#
R132 1
2 8.2K_0402_5%
PCI_PIRQC#
R133 1
2 8.2K_0402_5%
PCI_PIRQD#
R126 1
2 8.2K_0402_5%
PCI_ PIRQE#
R131 1
2 8.2K_0402_5%
PCI_PIRQF#
R127 1
2 8.2K_0402_5%
PCI_ PIRQG#
R130 1
2 8.2K_0402_5%
PCI_PIRQH#
R129 1
2 8.2K_0402_5%
P CI_REQ#0
R150 1
2 8.2K_0402_5%
P CI_REQ#1
R146 1
2 8.2K_0402_5%
P CI_REQ#2
R154 1
2 8.2K_0402_5%
P CI_REQ#3
R125 1
2 8.2K_0402_5%
P CI_REQ#4
R128 1
2 8.2K_0402_5%
P CI_REQ#5
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
P CI_REQ#0
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
C/BE0#
C/BE1#
C/BE2#
C/BE3#
B15
C12
D12
C15
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
PLTRST#
PCICLK
PME#
C26
A9
B19
PLTRST#
CLK_PCI_ICH
G8
F7
F8
G7
PCI_ PIRQE#
PCI_PIRQF#
PCI_ PIRQG#
PCI_PIRQH#
PCI
P CI_REQ#1
P CI_REQ#2
For EMI, close to ICH7
P CI_REQ#3
P CI_REQ#4
PCI_RST#
P CI_REQ#5
PLTRST#
@
P C I_ I RDY#
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRD Y#
P CI_FRAME#
2
@
C187
0.1U_0402_16V4Z
R152 1
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
PCI_RST# <27>
1 R169
100K_0402_5%
For EC request.
Place closely pin A9
CLK_PCI_ICH <14>
CLK_PCI_ICH
PCI_ PIRQA#
PCI_ PIRQB#
PCI_PIRQC#
PCI_PIRQD#
Interrupt
A3
B4
C5
B5
PIRQA#
PIRQB#
PIRQC#
PIRQD#
AE5
AD5
AG4
AH4
AD9
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
I/F
GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#
PCI_DEVSEL#
@
R167
10_0402_5%
2 8.2K_0402_5%
C203
0.1U_0402_16V4Z
R162 1
MISC
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
AE9
AG8
AH8
F21
AH20
@
C186
8.2P_0402_50V8D
MCH_ICH_SYNC# <6>
2
B
ICH7_BGA652
PLTRST#
<6,19,21,25>
PLTRST#
R142
100K_0402_5%
Compal Secret Data
2006/08/18
Issued Date
Deciphered Date
2007/8/18
5
Title
ICH7M(1/4)HUB,PCI,HOST
Size
Document Number
R ev
0.2
LA-4421P
D ate:
Sheet
1
17
of
42
C368
15P_0402_50V8J
2
1
+RTCBATT
NC
OUT
C371
15P_0402_50V8J
2
1
R196 1
20K_0402_5%
+RTCBATT
U17A
ICH_RTCX2
ICH_RTCRST#
J3
1
<22> HDA_SYNC_AUDIO
<22> HDA_BITCLK_AUDIO
<22> HDA_RST_AUDIO#
T11 PAD
W1
Y1
Y2
W3
HDA_SYNC_ICH
2
39_0402_5%
HDA_BITCLK_ICH
2
39_0402_5%
HDA_RST_ICH#
2
39_0402_5%
HDA_SDOUT_ICH
2
39_0402_5%
C363
39P_0402_50V8J
@
V3
LAN_CLK
LAN_RSTSYNC
U5
V4
T5
LAN_RXD0
LAN_RXD1
LAN_RXD2
HDA_RST_ICH#
R5
ACZ_RST#
T2
T3
T1
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
2
HDA_SDOUT_ICH
<24> SATA_ITX_C_DRX_N0
C379
SATA_ITX_C_DRX_P0 1
2
SATA_ITX_DRX_P0
C378
SATA_ITX_C_DRX_N0 1
2
SATA_ITX_DRX_N0
<24> SATA_DTX_C_IRX_N0
<24> SATA_DTX_C_IRX_P0
AF18
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
AF3
AE3
AG2
AH2
C382
SATA_ITX_C_DRX_P1 1
2
SATA_ITX_DRX_P1
C384
SATA_ITX_C_DRX_N1 1
2
SATA_ITX_DRX_N1
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1
AF7
AE7
AG6
AH6
<14> CLK_PCIE_SATA#
<14> CLK_PCIE_SATA
3900P_0402_50V7K
B
CLK_PCIE_SATA#
CLK_PCIE_SATA
AF1
AE1
R205
1
+3VS
AH10
AG10
AG26
H_FERR#
2 R212 IDE_DIORDY
1 R201 SATA_LED#
2 8.2K_0402_5% ID E_IRQ
IDE_DIORDY AG16
ID E_IRQ
AH16
AF16
AH15
AF15
AG24
H_PWRGOOD
IGNNE#
INIT3_3V#
INIT#
INTR
AG22
AG21
AF22
AF25
H_IGNNE#
H_INIT#
H_INTR
RCIN#
AG23
KB_RST#
SMI#
NMI
AF23
AH24
H_SMI#
H_NMI
AH22
H_STPCLK#
AF26
THRMTRIP_ICH#
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
IDE
LPC_FRAME# <27>
2
1 R200 10K_0402_5%
+3VS
GATEA20 <27>
H_A20M# <4>
1 56_0402_5%
R208
H_DPRSTP# <4,40>
H_DPSLP# <4>
+VCCP
H_FERR# <4>
H_PWRGOOD <4>
C
H_IGNNE# <4>
H_INIT#
H_INTR
<4>
<4>
+VCCP
STPCLK#
DCS1#
DCS3#
24.9_0402_1%
4.7K_0402_5% 1
10K_0402_5% 2
R204 1
GATEA20
H_A20M#
FERR#
DA0
DA1
DA2
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AE22
AH28
LPC_FRAME#
H_DPRSTP#
H_DPSLP#
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AB3
AF24
AH25
THERMTRIP#
ACZ_SDOUT
AC3
AA5
AG27
SATA
3900P_0402_50V7K
<21> SATA_ITX_C_DRX_P1
SATA_LED#
<28> SATA_LED#
3900P_0402_50V7K
T4
ACZ_BCLK
ACZ_SYNC
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
CPUSLP#
GPIO49 / CPUPWRGD
U1
R6
<22> HDA_SDIN0
A20GATE
A20M#
AA6
AB5
AC4
Y6
TP1 / DPRSTP#
TP2 / DPSLP#
LAN_TXD0
LAN_TXD1
LAN_TXD2
HDA_BITCLK_ICH
HDA_SYNC_ICH
3900P_0402_50V7K
LFRAME#
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
C364
39P_0402_50V8J
1 @
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LDRQ1# / GPIO23
U3
U7
V6
V7
2
INTVRMEN
INTRUDER#
AC-97/AZALIA
<22> HDA_SDOUT_AUDIO
1
R277
1
R284
1
R268
1
R282
RTCRST#
W4
Y5
2
3MM
C230
1U_0603_10V4Z
1
2
0.1U_0402_16V4Z
AA3
LPC_AD[0..3] <27>
LAN
C231
RTXC1
RTCX2
ICH_INTVRMEN
SM_INTRUDER#
@
2
AB1
AB2
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DDREQ
KB_RST# <27>
1
332K_0402_1%
2 ICH_INTVRMEN
H_SMI#
H_NMI
<4>
<4>
R203
56_0402_5%
H_STPCLK# <4>
2
R197
1
LPC
1M_0402_5%
2 SM_INTRUDER#
RTC
R198
1
ICH_RTCX1
Y3
32.768K_1TJS125BJ4A421P
2
1
NC
IN
CPU
+RTCBATT
R288
10M_0402_5%
2
1
1 R202
2
24.9_0402_1%
H_THERMTRIP# <4,6>
Layout note: R202 needs to placed

within 2" of ICH7, R203 must be placed
within 2" of R194 w/o stub.
AH17
AE17
AF17
AE16
AD16
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AE15
ICH7_BGA652
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
5
Title
ICH7M(2/4)LAN,ATA,LPC,RTC
Custom
Date:
R ev
0.2
LA-4421P
Sheet
1
18
of
42
Place closely pin B2
+3VS
Place closely pin AC1
CLK_ICH_48M
ICH _RI#
A28
SB_SPKR
A19
A27
A22
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP
1
R168
R199
@ 10_0402_5%
@ 10_0402_5%
AF19
AH18
AH19
AE19
C189
@ 4.7P_0402_50V8C
C240
@ 4.7P_0402_50V8C
R261
1
2
8.2K_0402_5%
<22>
SB_SPKR
ITP_DBRESET#
10K_0402_5%
R148 1
2 OCP#
<6> PM_BMBUSY#
PM_BMBUSY#
OCP#
<14> H_STP_PCI#
<14> H_STP_CPU#
@ 10K_0402_5%
R193 1
2 SB_SPI_CS#
1K_0402_5%
R184 1
2 ICH_PCIE_WAKE#
H_STP_PCI#
H_STP_CPU#
PM_CLKRUN#
8.2K_0402_5%
R149 2
1 ICH_LOW_BAT#
B23
AC20
AF21
<21> ICH_PCIE_WAKE#
<27>
SERIRQ
<27> EC_THERM#
<14,27,40> VGATE
<27>
EC_SMI#
GPIO18 / STPPCI#
GPIO20 / STPCPU#
GPIO26
B21
E23
GPIO27
GPIO28
AG18
ICH_PCIE_WAKE# F20
SERIRQ
AH21
EC_THERM#
AF20
VGATE
AD22
EC_SMI#
AC21
AC18
E21
CLK14
CLK48
AC1
B2
GPIO32 / CLKRUN#
C20
B24
D23
F22
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PWROK
AA4
ICH_POK
AC22
PM_DPRSLPVR
C21
ICH_LOW_BAT#
C23
PBTN_OUT#
C19
PLTRST#
Y4
EC_RSMRST#
R206 10K_0402_5%
1
2
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
EC_SCI#
AC IN
GPIO16 / DPRSLPVR
TP0 / BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
VRMPWRGD
GPIO
GPIO6
GPIO7
GPIO8
CLK_ICH_14M <14>
CLK_ICH_48M <14>
SUSCLK
GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#
WAKE#
SERIRQ
THRM#
CLK_ICH_14M
CLK_ICH_48M
SLP_S3#
SLP_S4#
SLP_S5#
GPIO11 / SMBALERT#
A21
AC19
U2
@ 10K_0402_5%
R195 1
2 SPI_MOSI
GPIO0 / BM_BUSY#
GPIO
@ 10K_0402_5%
R192 1
2 SPI_MISO
AB18
SPKR
SUS_STAT#
SYS_RST#
SYS
10K_0402_5%
R145 1
2 ITP_DBRESET#
RI#
Clocks
+3VALW
10K_0402_5%
R144 1
2 LINKALERT#
1
C22
B22
A26
B25
A25
POWER MGT
+3VALW
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
SMB
<14> ICH_SMBCLK
<14> ICH_SMBDATA
U17C
SATA
GPIO
10K_0402_5%
1
10K_0402_5%
2.2K_0402_5%
2
2.2K_0402_5%
D
R211
8.2K_0402_5%
R143
R258
R259
1
2
2
R147
+3VS
10K_0402_5%
R209 1
2 SERIRQ
8.2K_0402_5%
R210 1
2 PM_CLKRUN#
CLK_ICH_14M
+3VALW
1
+3VALW
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39
PM_SLP_S3# <27>
PM_SLP_S4# <27>
PM_SLP_S5# <27>
R207
ICH_POK <6,27>
1
2 10K_0402_5%
PM_DPRSLPVR <6,40>
PBTN_OUT# <27>
PLTRST#
<6,17,21,25>
EC_RSMRST# <27>
EC_SCI#
ACIN
EC_LID_OUT#
<27>
<27,34>
EC_LID_OUT# <27>
PAD T10
SATA_CLKREQ#
SATA_CLKREQ# <14>
ICH7_BGA652
WLAN
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2
C341 2
C337 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2
H26
H25
G28
G27
<25>
<25>
<25>
<25>
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3
C350 2
C346 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3
K26
K25
J28
J27
M26
M25
L28
L27
USB_OC#7
A
USB_OC#0
R164 2
1
10K_0402_5%
<30>
<30>
USB_OC#0
USB_OC#1
<30>
USB_OC#7
R163 2
1
10K_0402_5%
R161 2
1
10K_0402_5%
PERn3
PERp3
PETn3
PETp3
PERn4
PERp4
PETn4
PETp4
P26
P25
N28
N27
PERn5
PERp5
PETn5
PETp5
T25
T24
R28
R27
PERn6
PERp6
PETn6
PETp6
SB_SPI_CS#
R2
P6
P1
SPI_CLK
SPI_CS#
SPI_ARB
SPI_MOSI
SPI_MISO
P5
P2
SPI_MOSI
SPI_MISO
D3
C4
D5
D4
E5
C3
A2
B3
OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
SPI
+3VALW
USB_OC#6
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
PERn2
PERp2
PETn2
PETp2
PCI-EXPRESS
LAN
<21>
<21>
<21>
<21>
PERn1
PERp1
PETn1
PETp1
DIRECT MEDIA INTERFACE
U17D
F26
F25
E28
E27
USB
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS#
USBRBIAS
V26
V25
U28
U27
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
Y26
Y25
W28
W27
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
<6>
<6>
<6>
<6>
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
<6>
<6>
<6>
<6>
AB26
AB25
AA28
AA27
AD25
AD24
AC28
AC27
AE28
AE27
CLK_PCIE_ICH#
CLK_PCIE_ICH
C25
D25
DMI_IRCOMP
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
D2
D1
USBRBIAS
CLK_PCIE_ICH# <14>
CLK_PCIE_ICH <14>
R180 24.9_0402_1%
1
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
Within 500 mils

+1.5VS
<30>
<30>
<30>
<30>
<24>
<24>
<26>
<26>
<21>
<21>
<21>
<21>
<21>
<21>
<30>
<30>
USB1(Right)
USB2(Right)
CMOS
Card reader
WWAN
WiMAX
BT
USB3(Left)
R181 22.6_0402_1%
1
2
A
Within 500 mils
ICH7_BGA652
USB_OC#1
Issued Date
Compal Secret Data
2006/08/18
2007/8/18
Deciphered Date
5
Title
ICH7M(3/4)USB,GPIO,PCIE
Custom
Date:
R ev
0.2
LA-4421P
Sheet
1
19
of
42
100_0402_5%
C228
C204
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
Place closely pin

D28,T28,AD28.
C216
ICH_V5REF_RUN
C215
1U_0603_10V4Z
+5VALW +3VALW
D10
@
R186
10_0402_5%
RB751V-40TE17_SOD323-2
ICH_V5REF_SUS
C207
0.1U_0402_16V4Z
+3VS
C192
0.1U_0402_16V4Z
Place closely pin AG28 within 100mlis.

+1.5VS_DMIPLLR
+1.5VS_DMIPLL
0.5_0805_1%
2
0_0805_5%
+1.5VS_DMIPLL
1
C217
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C399
0.1U_0402_16V4Z
C400
0.1U_0402_16V4Z
1
C398
C257
0.1U_0402_16V4Z
1
A
+VCCP
+3VS
1
C239
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C241
+3VALW
+1.5VS
AG28
0.64A
C245
0.1U_0402_16V4Z
Place closely pin AG5.
+3VS
+1.5VS
+1.5VS
+5VS
B27
R290
2
C246
0.01U_0402_25V7K
R291
1
C381
10U_0805_10V4Z
+1.5VS
50mA
1U_0603_10V4Z
Place closely pin AG9.

10mA
1
+1.5VS
2
C238
C188
0.1U_0402_16V4Z
AD2
VccSATAPLL
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccRTC
VccSus3_3[1]
Vcc3_3[2]
VccSus1_05[2]
VccSus1_05[3]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
1U_0603_10V4Z
+3VS56mA
+3VALW
10mA
+VCCP
2
14mA
+3VS0.27A
1
C235
0.1U_0402_16V4Z
+RTCBATT
+3VALW45mA
C225
0.1U_0402_16V4Z
2
C224
0.1U_0402_16V4Z
2
AB17
AC17
C213
0.1U_0402_16V4Z
+3VALW
C206
0.1U_0402_16V4Z
+1.5VS
T7
F17
G17
AB8
AC8
C236 0.1U_0402_16V4Z
K7
C28
G20
A1
H6
H7
J6
J7
+1.5VS
1
C214
0.1U_0402_16V4Z
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
ICH7_BGA652
A
ICH7_BGA652
C232
0.1U_0402_16V4Z
Compal Secret Data

2006/08/18
Issued Date
0.1U_0402_16V4Z
Deciphered Date
2007/8/18
5
C243
+3VS
P7
EMI Request
W5
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
VccSus1_05[1]
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
Vcc1_5_A[24]
Vcc1_5_A[25]
C227
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
A24
C24
D19
D22
G19
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
AE23
AE26
AH26
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
Vcc1_5_A[19]
Vcc1_5_A[20]
VccSus3_3[19]
V5
V1
W2
W7
+3VS
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
E3
AA2
Y7
2
R7
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
C1
U6
VccDMIPLL
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
Vcc3_3 / VccHDA
VccSus3_3/VccSusHDA
Vcc3_3[1]
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
AH11
+1.5VS
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
C222
C237
0.1U_0402_16V4Z
@
RB751V-40TE17_SOD323-2
V5REF_Sus
C247
4.7U_0805_10V4Z
D12
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
C242
0.1U_0402_16V4Z
R189
0.1U_0402_16V4Z
V5REF[2]
C233
0.1U_0402_16V4Z
C367
220U_B2_2.5VM_R35
+3VS
2
+5VS
F6
U17E
0.94A
0.1U_0402_16V4Z
C248
10mAICH_V5REF_SUS
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C244
0.1U_0402_16V4Z
+1.5VS
0.77A
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
220U_B2_2.5VM_R35
AD17
V5REF[1]
C212
0.1U_0402_16V4Z
G10
C193
0.1U_0402_16V4Z
ICH_V5REF_RUN
+VCCP
U17F
6mA
C195
0.1U_0402_16V4Z
Title
ICH7M(4/4)POWER/GND
Custom
Date:
R ev
0.2
LA-4421P
Sheet
1
20
of
42
Mini-Express Card for WLAN

+1.5VS
+3VS_WLAN
1
1
C145
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
1
C190
C158
C151
C178
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
0.01U_0402_25V7K
1
JP14
ICH_PCIE_WAKE#
BT_ACTIVE
WLAN_ACTIVE
WLAN_CLKREQ#
<19> ICH_PCIE_WAKE#
<14> WLAN_CLKREQ#
R182 1
R174 1
@
@
0_0402_5%
0_0402_5%
2
2
<14> CLK_PCIE_WLAN#
<14> CLK_PCIE_WLAN
<19> PCIE_PTX_C_IRX_N2
<19> PCIE_PTX_C_IRX_P2
<19> PCIE_ITX_C_PRX_N2
<19> PCIE_ITX_C_PRX_P2
+3VS_WLAN
0.1U_0402_16V4Z
2
C163
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
+3VS_WLAN
R252 1
2 0_0805_5%
+3VS
+1.5VS
WL_OFF#
PLTRST#
1
2
0_0402_5%
R124
1
2
0_0402_5%
R122 @
WL_OFF# <27>
PLTRST# <6,17,19,25>
+3VS
+3VALW
USB20_N5 <19>
USB20_P5 <19>
D6
WLAN_LED#
2
WW_LED# <24>
RB751V_SOD323
D5
BT_LED#
ACES_88910-5204
ME@
RB751V_SOD323
BT@
D4
Mini-Express Card for WWAN
SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1
+3VS_WWAN
PIN 45 NC for SATA SSD DA/DSS
TO EC
100K_0402_5% 1 @ R117 2
+3VALW
<27> EC_TX_P80_DATA
J5
2
@ JUMP_43X39
J6
2
1 1
1 WWAN@
53
<27> EC_RX_P80_CLK
@ JUMP_43X39
WXMIT_OFF#
+3VS
GND1
GND2
ACES_88910-5204
ME@
For EMI request
BT@ +3VS_BT
Q26
SI2301BDS_SOT23
DTC124EK_SC59
+1.5VS
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
BT@
C309
2
1
0.1U_0402_16V4Z
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS_BT
WXMIT_OFF# <27>
BT_LED#
+1.5VS
JP5
USB20_N4 <19>
USB20_P4 <19>
Q11
DTC124EK_SC59
BT@
WWAN_LED#
+1.5VS
<19>
<19>
0.1U_0402_16V4Z
C200
+3VS_WWAN
<27> DETECTION
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
BT_OFF#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
<27>
SB RXSB TXSB TX+
JP13
3900P_0402_50V7K
C318
SATA_DTX_C_IRX_P1
1
2 SATA_DTX_IRX_P1
SATA_DTX_C_IRX_N1
1
2 SATA_DTX_IRX_N1
C319
3900P_0402_50V7K
SB RX+
3
Q25
BT@
C202
WWAN@
0.01U_0402_25V7K
USB20_N6
USB20_P6
USB20_N6
USB20_P6
BTON_LED
BT_ACTIVE
WLAN_ACTIVE
2
10U_0805_10V4Z
0.1U_0402_16V4Z
WWAN@
C153
@
1 JOPEN
1
2
3
4
5
6
7
8
1 GND
2
3
4
5
6
7
8 GND
10
R254
10K_0402_5%
BT@
WWAN@
+3VS_WWAN
J2
2
BT MODULE CONN
1 1
+3VS_WWAN
+5VS
2
RB751V_SOD323
+3VS
1 WWAN@
C149
WWAN_LED#
R102
10K_0402_5%
@
ACES_87213-0800G
ME@
54
+1.5VS
0.1U_0402_16V4Z
1
C168
0.1U_0402_16V4Z
1
C159
JP1
R228
10K_0402_5%
2
1
GND
VPP
I/O
DET
VCC
RST
CLK
1
2
3
GND
GND
8
9
+UIM_PWR
UIM_RST
UIM_CLK
WWAN@
+UIM_PWR
TAITW_PMPAT6-06GLBS7N14N0
2006/08/05
Issued Date
Compal Secret Data
ME@
Reserve for SIM card does not meet rise time

and pull-up is needed.
C266
1U_0603_10V4Z
4
5
6
7
UIM_VPP
UIM_DATA
2007/08/05
Deciphered Date
B
Title
Mini-Card/BT CONN
Size
Document Number
R ev
0.2
LA-4421P
Date:
Sheet
E
21
of
42
HDA_RST_AUD IO#
Adjustable Output
2 @
HDA_BITCLK_AUDIO
1
2
R262 @
33_0402_5%
FBMA-L11-160808-800LMT_0603
2
2
@2
C321
<BOM Structure>
G9191-475T1U_SOT23-5
@
0.1U_0402_16V4Z
C349
J O PEN
4
10U_0805_10V4Z
BYP
C344
SHDN
+5VDDA_CODEC
C325
OUT
GND
+3VDD_CODEC
0.1U_0402_16V4Z
+3VS
L16
22P_0402_50V8J
C331
EMI
H D A_S YNC_AUDIO
+5VDDA_CODEC
@
1
22P_0402_50V8J
C343
IN
J4
2
C361
4.7U_0805_10V4Z
+5VDDA_CODEC
C323
0.01U_0402_25V7K
1
0.1U_0402_16V4Z
C 329
10U_0805_10V4Z
C330
2
1
0_0805_5%
+5VAMP
10U_0805_10V4Z
U 14
C327
+5VAMP
R260
22P_0402_50V8J
C340
+5VS
0.1U_0402_16V4Z
Place near Pin1
Place near Pin25
Place near Pin38
+MIC2_VREFO
+5VDDA_CODEC
+3VDD_CODEC
+MIC1_VREFO_L
MIC_I NL
16
1 C353
MIC_INR
17
R280
2
2.2U_0603_6.3V6K
23
24
1
1K_0402_5%
1
1K_0402_5%
<23> EXT_MIC_L
<23> EXT_MIC_R
2.2U_0603_6.3V6K 2
1 C354
MIC_EXTL_C
21
2.2U_0603_6.3V6K 2
1 C355
MI C_EXTR_C
22
R278
2
R265
1
PC_BEEP
2
100P_0402_50V8J
12
<18> HDA_SDOUT_AUDIO
1
R 263
<18> H D A_SDIN0
<18> HDA_RST_AUDIO#
<18> H D A_S YNC_AUDIO
2
39_0402_5%
HDA_RST_AUD IO#
11
H D A_S YNC_AUDIO
10
Pin Assignment
B
Function
LINE-OUT (Pin35/36)
Internal
Int Speaker
Capless HP-OUT (Pin32/33)
External
Headphone out
LINE1 (Pin23/24)
External
MIC1(Pin21/22)
External
MONO-OUT(Pin37)
Internal
MIC2(Pin16/17)
Internal
1
DVDD
SPDIFO2
MIC1_L
HPOUT_L
MIC1_R
HPOUT_R
2
20K_0402_1%
2
5.1K_0402_1%
1
0_0402_5%
<23> MIC_JD
<23> PLUG_IN
<27>
E APD
1
R271
1
R170
2
R 166
SENSEA
13
SENSEB
34
MONO_OUT
BITCLK
DMIC_CLK1/2
SDATA_OUT
DMIC_CLK3/4
SDATA_IN
LINE2_VREFO
RESET#
LINE1_VREFO
MIC1_VREFO
GPIO0/DMIC_DATA1/2
CPVREF
GPIO1/DMIC_DATA3/4
VREF
SENSE A
JDREF
SENSE B
CBN
47
C326
C324 1
2 0.01U_0603_16V7K
LINE_OUTL
C_LINE_OUTR
C322 1
2 0.01U_0603_16V7K
LINE_OUTR
EAPD
CBP
41
48
45
33
1
R175
1
R183
62_0402_5%
32
2
62_0402_5%
HP_OUTL <23>
Headphone
HP_OUTR <23>
37
46
44
20
18
28
+MIC1_VREFO_L
19
+MIC2_VREFO
31
1
C 328
2
2.2U_0603_6.3V4
27
40
30
29
NC
4
7
DVSS
DVSS
AVSS1
AVSS2
Internal Speaker
39
1
C332
R 257
20K_0402_1%
2
2.2U_0603_6.3V4
GNDA
Location
LINE1_R
MIC2_VREFO
43
GND
SPDIFO1
SYNC
MIC Sense
R271 place near pin13
Capless HP Sense
R170 place near pin34
LOUT2_R
LINE1_L
BEEP_IN
<18> HDA_BITCLK_AUDIO
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
LOUT2_L
MIC2_R
C_LINE_OUTL
36
C345
external MIC
R140
1
R269
1
R136
1
R171
1
R135
1
MIC2_L
35
26
42
0.1U_0402_16V4Z
Internal MIC / Array MIC
LOUT1_R
10U_0805_10V4Z
C339
1
1K_0402_5%
LOUT1_L
LINE2-R
C334
INT _MIC_L
LINE2-L
10U_0805_10V4Z
C336
15
DVDD_IO
14
2.2U_0603_6.3V6K
MIC _INTL
2
1 C352
2
GN DA
38
1
1
R279
4.7K_0402_5%
C209
47P_0402_50V8J
R266
4.7K_0402_5%
AVDD2
1
1
INT _MIC_L
<28> INT_MIC_L
U 15
25
D 23
RB751V_SOD323
AVDD1
D 22
RB751V_SOD323
0.1U_0402_16V4Z
R188
4.7K_0402_5%
Place near Pin9
Close Pin27
ALC272-GR_LQFP48
B
+5VAMP
Mic in
W=40mil
U 16
C338
4.7U_0805_10V4Z
16
6
15
PC Beep
VDD
PVDD
PVDD
NC
SHUTDOWN
G AIN0
G AIN1
GAIN0
LOUTGAIN1
ROUTLOUT+
<27>
R267
1
BEEP#
C348
PC_BEEP1
LINE_OUTR
17
PC_BEEP
9
2
47K_0402_5%
0.1U_0402_16V4Z
1
C347
0.47U_0603_16VY5V
47K_0402_5%
ICH Beep
2
1
R270
10K_0402_5%
ROUT+
RINLIN+
RIN+
GND
GND
GND
GND
GND
BYPASS
R264
1
<19> SB_SPKR
LIN-
C 351
0.47U_0603_16VY5V
19
EC_MUTE#
SPKL-
8
14
4
20mil
18
GAIN0
0
0
1
1
EC_MUTE# <27>
SPKL-
<23>
<23>
SPKR-
SPKR-
SPKL+
SPKL+
<23>
SPKR+
SPKR+
<23>
+5VAMP
1
11
13
20
21
10
TPA6017A2PWPR_TSSOP20
GAIN1
0
1
0
1
+5VAMP
R194
100K_0402_5%
C 342
0.47U_0603_16VY5V
R 191
100K_0402_5%
G AIN0
R283
100K_0402_5%
G AIN1
R 281
100K_0402_5%
@
C362
0.1U_0402_16V4Z
Issued Date
Compal Electronics,Ltd.
Compal Secret Data
2008/03/25
Deciphered Date
2008/04/
Title
HD Audio Codec_ALC272
Size
C
Document Number
R ev
0 .1
KIWB1/B2_LA4601P
Date: Monday, April 06, 2009

5
6dB
10dB
15.6dB
21.6dB
EC Beep
LINE_OUTL
12
2 1
C 360
0.1U_0402_16V4Z
2 1
Internal Mic
Sheet
1
22
of
42
D8
D9
1
2
PSOT24C_SOT23-3
@
PSOT24C_SOT23-3
@
ME@
ACES_87213-0400G
<22>
<22>
<22>
<22>
SPKL+
SPKLSPKR+
SPKR-
SPKL+
SPKLSPKR+
SPKR-
20mil
R176
R177
R178
R179
1
1
1
1
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
SPK_L1+
SPK_L1SPK_R1+
SPK_R1-
4
3
2
1
Speaker Conn.
6
5
@ C199 22P_0402_50V8J
@ C198 22P_0402_50V8J
@ C197 22P_0402_50V8J
@ C196 22P_0402_50V8J
4 GND
3 GND
2
1
JP7
W=20mils
<22> EXT_MIC_L
L5
EXT_MIC_L
EXT_MIC_L-2
FBMA-L10-160808-121LMT_2P
C226
47P_0402_50V8J
W=20mils
<22> EXT_MIC_R
2
GN DA
@ C220
10P_0402_50V8J
2
GN DA
Audio Jack
L4
EXT_MIC_R
EXT_MIC_R-2
FBMA-L10-160808-121LMT_2P
1
C205
47P_0402_50V8J
JMIC1
@ C335
10P_0402_50V8J
2
GN DA
1
2
2
GN DA
MIC_ JD
MIC_JD
C333
@
GN DA
@
D11
PSOT24C_SOT23-3
2
GN DA
6
GN DA
G
SINGA_2SJ-0960-C02
ME@
10P_0402_50V8J
<22>
MIC IN
220P_0402_50V7K
220P_0402_50V7K
C229
C234
GN DA
Headphone
JHP1
W=20mils
<22> HP_OUTL
HP_OUTL
L7
1
2
FBMA-L10-160808-121LMT_2P
L6
1
2
FBMA-L10-160808-121LMT_2P
HP_OUTR
<22> HP_OUTR
PL-OUT
1
2
PR-OUT
PLU G_IN
<22> PLUG_IN
PSOT24C_SOT23-3
2008/03/25
Issued Date
Deciphered Date
GN DA
G
SINGA_2SJ-0960-C02
ME@
Compal Electronics,Ltd.
2008/04/
4
6
GN DA
Compal Secret Data
C366
@ @
2
D13
GN DA
10P_0402_50V8J
Title
AMP,Audio speaker CONN

C ustom
R ev
0.1
KIWB1/B2_LA4601P
D ate: Monday, April 06, 2009
Sheet
1
23
of
42
LED
CMOS Camera CONN
R214
2
1
510_0402_5%
+5VALW
LED3
2
R213
SI2301BDS-T1-E3_SOT23-3
CMOS@
+5VS
S
3
CMOS@
2
+5V_CMOS
R216
2
1
300_0402_5%
+3VALW
2
R41
10K_0402_5%
CMOS@
CMOS1
0_0603_5%
Q23
2
1
510_0402_5%
+5VALW
R234
+5V_CMOS_R 1
CMOS@
C276
0.1U_0402_16V4Z
C277
CMOS@
0.01U_0402_25V7K
1
2
White
PWR_LED# <27>
HT-F196BP5_WHITE
LED2
2
1
White
HT-F196BP5_WHITE
LED5
2
1
Amber
CHARGE_LED0# <27>
CHARGE_LED1# <27>
HT-191UD-DT_AMBER_0603
1
R215
2
1
510_0402_5%
+5VS
LED4
2
White
WW_LED# <21>
HT-F196BP5_WHITE
1
JP2
2
@
D16
PSOT24C_SOT23-3
Q5
DTC124EKAT146_SC59-3
CMOS@
1
2
3
4
5
GND1
GND2
R4
2
1
510_0402_5%
+5VALW
LED1
2
ACES_88266-05001
ME@
IN
GND
<27> CMOS_OFF#
1
2
3
4
5
6
7
USB20_N2
USB20_P2
USB20_N2
USB20_P2
OUT
<19>
<19>
White
PWR_LED# <27>
HT-F196BP5_WHITE
2
+5VS
0.1U_0402_16V4Z
1
C23
1000P_0402_50V7K
10U_0805_10V4Z
1
C26
C22
C19
1U_0603_10V4Z
SATA HDD Conn.

JP10
3
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_DTX_IRX_N0
2 C380
3900P_0402_50V7K
SATA_DTX_IRX_P0
2
C383
3900P_0402_50V7K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3VS
+5VS
GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
GND
GND
24
23
SUYIN_127085FR022G211ZR
ME@
Issued Date
Compal Secret Data
2006/08/18
2007/8/18
Deciphered Date
A
Title
SSD,CMOS CONN\LED
Size
B
Document Number
R ev
0.2
LA-4421P
Date:

G
Sheet
24
H
of
42
1
R14
2
3.6K_0402_5%
+3V_LAN
LAN_DI
LAN_CS
1
R13
2
1K_0402_5%
Close to Pin10,13,30,36
Place Close to Chip
Close to Pin1,37,29
+LAN_VDD12
+3V_LAN
U1
0.1U_0402_16V4Z
C254 2
<19> PCIE_PTX_C_IRX_P3
C255 2
<19> PCIE_PTX_C_IRX_N3
1 0.1U_0402_10V7K
PCIE_PTX_IRX_P3
1 0.1U_0402_10V7K
PCIE_PTX_IRX_N3
20
21
HSOP
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
HSON
<19> PCIE_ITX_C_PRX_P3
15
<19> PCIE_ITX_C_PRX_N3
16
HSIN
<14> CLK_PCIE_LAN
<14> CLK_PCIE_LAN#
17
18
REFCLK_P
REFCLK_M
25
<14> CLKREQ_LAN#
27
<6,17,19,21> PLTRST#
R217 1
2 2.49K_0402_1%
<27> LAN_WAKE#
26
28
ISOLATEB
2
R9
+3V_LAN
1
10K_0402_5%
46
LAN_X1
LAN_X2
41
42
HSIP
LED0
RTL8103EL-GR
CLKREQB
PERSTB
MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
RSET
NC
LANWAKEB
ISOLATEB
CKXTAL1
CKXTAL2
1
2
R11
1K_0402_5%
ISOLATEB
23
24
NC
NC
7
14
31
47
GND
GND
GND
GND
22
GNDTX
R12
15K_0402_5%
38
LAN_ACTIVITY#
2
3
5
6
8
9
11
12
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
C6
C16
0.1U_0402_16V4Z
25MHZ_20P
30P_0402_50V8J
Close to Pin48
Close to Pin45
VDDTX
DVDD12
DVDD12
DVDD12
DVDD12
19
30
36
13
10
VCTRL12
VCTRL12
+LAN_VDD12
0.1U_0402_16V4Z
2
+EVDD12
+LAN_VDD12
C256
2
39
NC
VCTRL12D
44
45
VDD33
VDD33
29
37
AVDD33
NC
NC
1
40
43
+3V_LAN
Close to Pin19
+EVDD12
C259
C258
1U_0603_10V4Z
30P_0402_50V8J
C3
2 0.01U_0402_25V7K
C5
2 0.01U_0402_25V7K
LAN_MDI1+
LAN_MDI1LAN_CT0
1
2
3
4
5
6
7
8
JRJ1
LAN_CT1
LAN_MDI0+
LAN_MDI0-
RD+
RDCT
NC
NC
CT
TD+
TD-
RX+
RXCT
NC
NC
CT
TX+
TX-
16
15
14
13
12
11
10
9
RJ45_MIDI1+
RJ45_MIDI1RJ45_CT0
R1
1 300_0402_5%
12
1
R3
2
2
R2
RJ45_CT1
RJ45_MIDI0+
RJ45_MIDI0-
75_0402_5%
1
1
75_0402_5%
C1
@68P_0402_50V8K
C2
1000P_1206_2KV7K
11
+3V_LAN
For EMI.
C8
350uH_NS0013LF
@
2
RJ45_MIDI0+
RJ45_MIDI1+
1 470P_0402_50V7K
2
RJ45_MIDI0-
RJ45_MIDI1-
J1
2
@
1 JOPEN
LAN_SK_LAN_LINK#
C13
4.7U_0805_10V4Z
2
G
AO3414_SOT23-3
@
R10
33K_0402_5%
@
2
1
3
1 300_0402_5%
10
+3V_LAN
C7
68P_0402_50V8K
@
3 Q1
+3V_LAN
+3VALW
+3VALW
R5
16
SHLD3
15
PR4+
PR3-
SHLD4
PR4-
PR2-
Amber LED+
Layout Notice : Place as close

ch ip as possible.
Amber LED-
PR3+
PR2+
PR1SHLD2
PR1+
SHLD1
14
13
Green LEDGreen LED+

SUYIN_100073FR012S102ZR
ME@
C17
@
0.1U_0402_16V4Z
Compal Secret Data
Issued Date
2006/08/04
2006/10/06
Deciphered Date
A
C249
@ 10U_0805_10V4Z
3
LAN_ACTIVITY#
EN_WOL 2
Q3 G
2N7002_SOT23
@
+LAN_VDD12
T1
EN_WOL
1
C251
1
0.1U_0402_16V4Z
C252
<27>
C15
1
0.1U_0402_16V4Z
1U_0603_10V4Z
C4
0.1U_0402_16V4Z
LAN_X2
C253
C9
0.1U_0402_16V4Z
1
2
RTL8103EL-GR_LQFP48_7X7
C14
0.1U_0402_16V4Z
1
Y2
LAN_X1
C250
4
48
NC
LAN_DI
LAN_SK_LAN_LINK#
LAN_CS
VCTRL12A
+3VS
0.1U_0402_16V4Z
33
34
35
32
Title
RTL8103EL
Custom
Date:
R ev
0.2
Sheet
E
25
of
42
+V CC_3IN1
C3 75
+3VS
0.1U_0402_16V4Z
+3VS
0.1U_0402_16V4Z
+3VS
1
0.1U_0402_16V4Z
1
C 376
C 374
1
0.1U_0402_16V4Z
2
U18
1
C3 77
2
1
3
7
9
11
33
AV_PLL
NC1
NC
CARD_3V3
D3V3
D3V3
8
44
45
47
48
3V3_IN
RST#
MODE_SEL
XTLO
XTLI
4
5
14
DM
DP
GPIO0
C 373
VREG
MS_D4
NC
10
22
30
XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
MS_INS#_SP9
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI
43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18
XTAL_CTR
MS_D5
13
24
EEDO
EECS
EESK
SD_CMD
15
16
17
36
+3VS
100K_0402_5%
C3 65
C 372
2
R2 86
C 369
2
RS T#
MODE SEL
1
0_0402_5%
<14> CLK_48M_CR
2
<19>
<19>
USB20_N3
USB20_P3
CLK_48M_CR
USB20_N3
USB20_P3
CLK_48M_CR
EMI
1U_0603_10V4Z
RS T#
4.7U_0805_10V4Z
R2 85
0.1U_0402_16V4Z
R2 87
@
100K_0402_5%
C 370
@
2
R2 89
6.19K_0402_1%
RREF
12
32
DGND
DGND
6
46
AGND
AGND
2
1U_0603_10V4Z
C
SD_DATA 2_XD_RE#
SD_DATA 3_XD_WE#
R 275
X D_DATA1
SD_DA TA6_XD_DATA7_MS_DATA3
MS_INS#
X D_DATA3_MS_DATA1
XD_DATA5_MS_BS
XD_DA TA4_SD_DATA1
S D_C D#
S D _WP
1XD_DATA1_RR 273 1
0_0603_5%
R 274 1
2
22_0402_5%
2
22_0402_5%
MS _CLK
S D_CLK
+3VS
S D _CMD
3 in 1 Card Reader
0.1U_0402_16V4Z
RTS5159-GR_LQFP48_7X7
+V CC_3IN1
250mA
J P9
S D _WP
XD_DA TA4_SD_DATA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
XD_DATA5_MS_BS
S D_CLK
X D_DATA3_MS_DATA1
MS _CLK
R 272
@
100K_0402_5%
SD_DATA 3_XD_WE#
SD_DATA 2_XD_RE#
S D_C D#
R 276
@
100K_0402_5%
C 359
@
Issued Date
C3 58
Compal Secret Data

2006/08/04
Deciphered Date
2006/10/06
5
0.1U_0402_16V4Z
22
23
TAITW_R009-025-LR_NR
ME@
C 356
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
MS_INS#
S D _CMD
MS _CLK
S D_CLK
EMI
SD-WP
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
SD-DAT2 GND1
SD-CD
GND2
Title
C3 57
A
Size D ocument Number

Cus tom
Dat e:
Rev
0.1
Sheet
1
26
of
42
+3VALW
+EC_AVCC
2
47K_0402_5%
<19>
C141
0.1U_0402_16V4Z
EC_RST#
EC_SCI#
EC_SCI#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
+3VALW
KSO1
1
47K_0402_5%
KSO2
1
47K_0402_5%
2
R82
2
R81
KSO[0..15]
<29>
KSO[0..15]
<29>
KSI[0..7]
KSI[0..7]
+3VALW
1
10K_0402_5%
USER_DEFINE#
R108
<35>
<35>
<4>
<4>
R111
+3VS
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
<19> PM_SLP_S3#
<19> PM_SLP_S5#
<19> EC_SMI#
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
KILL_SW#
USER_DEFINE#
DETECTION
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
KILL_SW#
<28> USER_DEFINE#
<21> DETECTION
FAN_SPEED1
<4> FAN_SPEED1
EC_TX_P80_DATA
EC_RX_P80_CLK
<21> EC_TX_P80_DATA
<21> EC_RX_P80_CLK
<28>
ON/OFF#
<24> PWR_LED#
<28> NUM_LED#
XCLKI
XCLKO
AD
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
67
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
S M Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
G PO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
GPI
63
64
65
66
75
76
BATT_TEMP
BATT_OVP
INVT_PWM <15>
BEEP#
<22>
EN_WOL <25>
ACOFF
<36>
ACOFF
BRD_ID
68
70
71
72
EN_FAN1
IR EF
BATT_TEMP <35>
BATT_OVP <36>
ADP_I
<36>
EN_FAN1 <4>
IREF
<36>
CHGVADJ <36>
+3VALW
83
84
85
86
87
88
EC_MUTE# <22>
USB_ON <30>
USB_ON
TP_CLK
TP_DATA
R97
100K_0402_5%
BRD_ID
97
98
99
109
WL_OFF# <21>
LID_SW#
NOVO#
CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
SYSON
100
101
102
103
104
105
106
107
108
124
EC_LID_OUT#
EC_ON
ICH_POK
<28>
ID
FSTCHG <36>
CHARGE_LED0# <24>
CAPS_LED# <28>
CHARGE_LED1# <24>
SYSON
VR_ON
ACIN
<31,38>
<40>
<19,34>
20mil
22P_0402_50V8J
4
OUT
IN
NC
NC
3
EC_SMB_CK1
2
4.7K_0402_5%
EC_SMB_DA1
2
4.7K_0402_5%
1
R107
1
R109
22P_0402_50V8J
+5VALW
D7
ICH_POK
+3VALW
20mils
R116
C143 1
BATT_TEMP
C144 1
AC IN
C185 1
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
VGATE
<14,19,40>
U3
VCC
FSEL#SPICS# 2
R99
SPI_CLK
2
R165
FWR#SPI_SI 2
R88
VSS
W
HOLD
SPI_CS#
1
1
0_0402_5%
SPI_CLK_R
1
6
FBMA-11-100505-900T 0402
SPI_SI
1
5
0_0402_5%
S
C
D
C385
10P_0402_50V8J~D
32.768K_1TJS125BJ4A421P
BATT_OVP
SPI_SO
2
R96
1 FRD#SPI_SO
0_0402_5%
SST25LF080A_SO8-200mil
2
EC_SMB_CK2
2.2K_0402_5%
EC_SMB_DA2
2.2K_0402_5%
8M SPI ROM
8
0.1U_0402_16V4Z~D
2
JP11
SPI_CS#
SPI_SO
C147
R112
0V
0.25V
0.50V
3.3V
RB751V_SOD323
C152
2
4.7K_0402_5%
2
4.7K_0402_5%
+3VS
Vab
0
8.2K
18K
NC
C194
4.7U_0805_10V4Z
R165 change to Bead for EMI

1
R120
TP_DATA
1
R123
Rb
NC
100K
100K
100K
+5VS
TP_CLK
Ra
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
EC_RSMRST# <19>
EC_LID_OUT# <19>
EC_ON
<28>
CMOS_OFF# <24>
ICH_POK <6,19>
BKOFF# <15>
BT_OFF# <21>
WXMIT_OFF# <21>
PM_SLP_S4# <19>
GMCH_ENBKL <8>
EAPD
<22>
EC_THERM# <19>
SUSP#
<31,36,38,39>
PBTN_OUT# <19>
LAN_WAKE# <25>
EC_THERM#
SUSP#
PBTN_OUT#
BRD ID
0
1
2
3
C183
X1
Rb
BOARD ID Table
73
74
89
90
91
92
93
95
121
127
V18R
LID_SW# <28>
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#
119
120
126
128
110
112
114
115
116
117
118
R94 @
8.2K_0402_5%
7
C182
Ra
TP_CLK <29>
TP_DATA <29>
ECAGND
11
24
35
94
113
KB926QFC0_LQFP128
INVT_PWM
BEEP#
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
XCLK1
XCLK0
GND
GND
GND
GND
GND
122
123
21
23
26
27
PWM Output
DA Output
1
100K_0402_5%
<30>
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
12
13
37
20
38
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
<14> CLK_PCI_LPC
<17> PCI_RST#
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
1
10_0402_5%
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
<19>
SERIRQ
<18> LPC_FRAME#
<18>
LPC_AD3
<18>
LPC_AD2
<18>
LPC_AD1
<18>
LPC_AD0
2
R118@
@ 22P_0402_50V8J
1
+3VALW
R83
AGND
GATEA20
KB_RST#
C166
2
1
U6
AVCC
9
22
33
96
111
125
2 10K_0402_5%
<18>
<18>
69
R134 1
+3VS
C184
1000P_0402_50V7K
0.1U_0402_16V4Z
C181
1000P_0402_50V7K
ECAGND 1
2
FCM1608CF-121T03_2P
C177
0.1U_0402_16V4Z
+EC_AVCC
C154
C171
0.1U_0402_16V4Z
L3
C142
0.1U_0402_16V4Z
+3VALW
2
FCM1608CF-121T03_2P
C162
0.1U_0402_16V4Z
VCC
VCC
VCC
VCC
VCC
VCC
L2
R93
SPI_CLK_R
1
33_0402_5%
+3VALW
1
3
5
7
2
4
6
8
2
4
6
8
+3VALW
SPI_CLK_R
SPI_SI
E&T_2941-G08N-00E~D
ME@
22P_0402_50V8J
Compal Secret Data
Issued Date
1
3
5
7
2006/08/04
Deciphered Date
2006/10/06
Title
KB926/BIOS
Custom
Date:
R ev
0.2
LA-4421P
Sheet
27
of
42
+3VALW
R220
100K_0402_5%
<27>
NOVO#
<34>
51_ON#
D14
NOVO#
ONE_KEY_RECOVER#
51_ON#
3
SW2
BAV70W-7-F_SOT323-3
1
4
SMT1-05_4P
ON/OFFBTN#
6
5
+3VALW
ONE_KEY_RECOVER#
R8
ON/OFF# <27>
51_ON#
51_ON#
1
EC_ON
S 2N7002_SOT23
Q2
2
G
EC_ON
SMT1-05_4P
6
5
<27>
D1
BAV70W-7-F_SOT323-3
R15
FOR ESD
D15
<34>
PSOT24C_SOT23-3
3
SW1
ON /OFF#
ON/OFFBTN#
100K_0402_5%
10K_0402_5%
JP3
USER_SW
+5VS
<18> SATA_LED#
<27> CAPS_LED#
<27> NUM_LED#
INT_MIC_L
<22> INT_MIC_L
GNDA
LID Switch
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
GND
GND
ACES_85201-08051
ME@
+3VALW
VDD
R103
47K_0402_5%
OUTPUT
LID_SW# <27>
1
C150
U5
APX9132ATI-TRL SOT-23 3P
10P_0402_50V8J
GND
C155
0.1U_0402_16V4Z~D
D24
2
<27> USER_DEFINE#
<34>
51_ON#
51_ON#
USER_SW
1
3
BAV70W-7-F_SOT323-3
Issued Date
Compal Secret Data
2006/08/18
Deciphered Date
2007/8/18
Title
LID SW
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Sheet
28
of
42
KS O[0..15]
KSI[0..7]
<27>
To TP/B Conn.
INT_KBD Conn.
KSO[0..15] <27>
JP8
<27>
<27>
JP4
KSO4
C104 1
2 @ 100P_0402_50V8J
K SI1
C135 1
2 @ 100P_0402_50V8J
KSO5
C103 1
2 @ 100P_0402_50V8J
K SI2
C134 1
2 @ 100P_0402_50V8J
KSO6
C102 1
2 @ 100P_0402_50V8J
K SI3
C133 1
2 @ 100P_0402_50V8J
KSO7
C101 1
2 @ 100P_0402_50V8J
K SI4
C132 1
2 @ 100P_0402_50V8J
KSO8
C100 1
2 @ 100P_0402_50V8J
K SI5
C131 1
2 @ 100P_0402_50V8J
KSO9
C99
2 @ 100P_0402_50V8J
K SI6
C127 1
2 @ 100P_0402_50V8J
KSO10
C98
2 @ 100P_0402_50V8J
K SI7
C126 1
2 @ 100P_0402_50V8J
KSO11
C97
2 @ 100P_0402_50V8J
KSO0
C125 1
2 @ 100P_0402_50V8J
KSO12
C96
2 @ 100P_0402_50V8J
KSO1
C124 1
2 @ 100P_0402_50V8J
KSO13
C95
2 @ 100P_0402_50V8J
KSO2
C114 1
2 @ 100P_0402_50V8J
KSO14
C93
2 @ 100P_0402_50V8J
KSO3
C113 1
2 @ 100P_0402_50V8J
KSO15
C92
2 @ 100P_0402_50V8J
+5VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND2
GND1
SW /L
ACES_85201-06051
ME@
2
R101
2
R100
1 TP_CLK
10K_0402_5%
1 TP_DATA
10K_0402_5%
@
@
+5VS
C157
@
C156
@
0.1U_0402_16V4Z
TP_DATA
TP_CLK
2 @ 100P_0402_50V8J
1
2
3
4
5
6
GND
GND
C180
0.1U_0402_16V4Z
D3
@
PSOT24C_SOT23
C136 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0.1U_0402_16V4Z
K SI0
K SI0
K SI1
K SI2
KSO0
KSO1
KSO2
K SI3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
K SI4
KSO9
K SI5
K SI6
KSO10
KSO11
K SI7
KSO12
KSO13
KSO14
KSO15
1
2
3
4
5
6
7
8
TP_CLK
TP_DATA
SW /R
TP_CLK
TP_DATA
KSI[0..7]
26
25
E-T_6905-E24N-01R
6
5
ME@
SMT1-05_4P
SW /L
6
5
SW3
SMT1-05_4P
SW /R
SW4
Compal Secret Data
2006/08/18
Issued Date
Deciphered Date
2007/8/18
5
Title
KB/SW/TP/LPC Debug CONN

Size
B
D ate:
Document Number
R ev
0.2
LA-4421P
Sheet
1
29
of
42
+5VALW
+USB_VCCA
U7
C210
0.1U_0402_16V4Z
2
1
1
2
3
4
GND
IN
IN
EN
OUT
OUT
OUT
OC#
8
7
6
5
USB_OC#1 <19>
USB_OC#0 <19>
RT9715AGS SOP 8P
High active
USB_ON
JP6
1
USB_ON
1
<27>
+USB_VCCA
+USB_VCCA
<19> USB20_N0
<19> USB20_P0
C211
@ 1000P_0402_50V7K
R185
200K_0402_5%
@
<19> USB20_N1
<19> USB20_P1
<27> KILL_SW#
USB20_N0
USB20_P0
USB20_N1
USB20_P1
KILL_SW#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
GND
GND
ACES_85201-1005N
ME@
+5VALW
+USB_VCCC
U13
1
C317
0.1U_0402_16V4Z
1
2
3
4
GND
IN
IN
EN
OUT
OUT
OUT
OC#
8
7
6
5
USB CONN. 3
USB_OC#7 <19>
+USB_VCCC
RT9715AGS SOP 8P
High active
1
<27> USB_ON
W=40mils
+USB_VCCC
C320
@ 1000P_0402_50V7K
C315
150U_B_6.3VM_R40M
+
2
C316
470P_0402_50V7K
2
JP15
USB20_N7
USB20_P7
3
<19> USB20_N7
<19> USB20_P7
@
D21
PSOT24C_SOT23-3
1
2
3
4
5
6
7
8
1
2
3
4
GND
GND
GND
GND
SUYIN_020173MR004S558ZL
ME@
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
A
Title
USB PORTS
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Sheet
E
30
of
42
+5VALW TO +5VS
C219
R190
C191
10U_0805_10V4Z
2
2
1U_0603_10V4Z
10U_0805_10V4Z
2
2
10U_0805_10V4Z
C201
470_0603_5%
C170
C176
10U_0805_10V4Z
2
2
1U_0603_10V4Z
10U_0805_10V4Z
2
2
10U_0805_10V4Z
470_0603_5%
S
1
2
R139
100K_0402_5%
B+
C208
SUSP
2
Q13 G
2N7002_SOT23
0.01U_0402_25V7K
2 SUSP
G
Q12
2N7002_SOT23
SYSON#
C179
1
SUSP
2
Q17G
2N7002_SOT23
S
D
2
1
1
R187
20K_0402_5%
B+
2 SUSP
G
Q18
2N7002_SOT23
R141
100K_0402_5%
5VS_GATE
+5VALW
R114
2
C223
Q15
1
2
3
+3VS
SI4800BDY-T1-E3_SO8
8
7
6
5
4
C218
Q19
1
2
3
+3VALW
SI4800BDY-T1-E3_SO8
8
7
6
5
4
C221
+3VALW TO +3VS
+5VS
1 1
+5VALW
0.1U_0402_25V7K
Q14
<27,38>
SYSON
SYSON
DTC124EK_SC59
RTCVREF
+VCCP
+0.9VS
+1.8V
R16
470_0603_5%
R57
470_0603_5%
R70
470_0603_5%
<39>
SUSP
SUSP
R63
470_0603_5%
R51
470_0603_5%
R173
100K_0402_5%
1
+2.5VS
R172
100K_0402_5%
@
+1.5VS
+5VALW
2 SYSON#
G
Q8
2N7002_SOT23
DTC124EK_SC59
3
2 SUSP
G
Q9
2N7002_SOT23
<27,36,38,39> SUSP#
D
2 SUSP
G
Q7
2N7002_SOT23
2 SUSP
G
Q4
2N7002_SOT23
2 SUSP
G
Q6
2N7002_SOT23
Q16
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
A
Title
DC INTERFACE
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Sheet
E
31
of
42
H8
H
H_3P6X5P6N
FM4
H15
H
H10
H
@
H_2P8
H13
H
@
FM1
@
H3
H
@
FM3
H_3P2
1
H14
H
@
@
1
H7
H
@
1
FM2
H1
H
@
H9
H
@
FIDUCIAL_C40M80
H4
H
@
H5
H
@
H16
H
H2
H
@
H6
H
H11
H
H12
H
Issued Date
Compal Secret Data
2006/08/18
Deciphered Date
2007/8/18
Title
Screw
Size
B
Date:
Document Number
R ev
0.2
LA-4421P
Sheet
33
of
43
VIN
BATT ONLY
Precharge detector
Min.
typ.
Max.
High 7.196V 7.349V 7.505V
Low 6.138V 6.214V 6.359V
ACIN
Precharge detector
Min.
typ.
Max.
High 14.936V 15.381V 15.814V
Low 13.843V 14.247V 14.636V
PC60
100P_0402_50V8J
PC52
100P_0402_50V8J
PC59
1000P_0402_50V7K
APDIN1
J DC IN
@ ACES_85204-0400N
PL7
SMB3025500YA_2P
1
2
1
2
3
4
1
2
3
4
PF2
7A_24VDC_429007.WRML
1
2
PC63
1000P_0402_50V7K
PR29
@ 1K_1206_5%
1
2
PR30
@ 1K_1206_5%
1
2
Vin Detector
2
PR127
@ 10K_0402_1%
2
1
PD5
RLS4148_LL34-2
N1
<28> 51_ON#
OUT
GND
PC29
10U_0805_6.3V6M
1
2
RTC Battery
+RTCBATT
PD6
@ MAXEL_ML1220T10
N2
+CHGRTC
RB751V-40TE17_SOD323-2
4
SP093MX0000
PC27
1U_0805_25V4Z
Issued Date
Compal Secret Data
2007/09/20
Deciphered Date
2008/09/20
A
2
2
IN
JRTC
3.3V
PC30
0.1U_0603_25V7K
PR34
200_0603_5%
PU4
G920AT24U_SOT89-3
PR36
PR38
560_0603_5% 560_0603_5%
1
2
1
2
VS
RTCVREF
+CHGRTC
PQ19
@ DTC115EUA_SC70-3
PU10B
@ LM393DG_SO8
PC28
0.22U_0603_25V7K
PR37
22K_0402_1%
1
2
PR116
100K_0402_1%
PR33
68_1206_5%
2
PR35
200_0603_5%
1
2
+5VALWP
1
PR32
PQ15
68_1206_5%
TP0610K-T1-E3_SOT23-3
CHGRTCP
PACIN <36>
2
1
PD12
RLS4148_LL34-2
PQ22
PR120
@ 2N7002KW_SOT323-3 @ 47K_0402_1%
2
2
1
G
2
1
PR124
@ 66.5K_0402_1%
VIN
BATT+
RTCVREF
1
PR117
10K_0402_1%
2
3.3V
PC92
@0.01U_0402_25V7K
PU10A
@ LM393DG_SO8
<36>
RTCVREF
PD13
RLZ4.3B_LL34
PR128
10K_0402_1%
2
1
PU12A
LM393DG_SO8
PACIN
PC105
@ 0.1U_0402_10V7K
PACIN
2
1
PR121
@ 499K_0402_1%
1
2
1
PD15
@ RB715F_SOT323-3
2
1
3
ACON
2
1
PR135
@100K_0402_1%
1
PR123
10K_0805_5%
<35,37> MAINPWON
<19,27>
P
G
AC IN
<36>
O
PC96
0.1U_0402_16V7K
PR118
10K_0402_1%
1
2
PC91
0.01U_0402_25V7K
2
1
PR133
84.5K_0402_1%
1
PR136
22K_0402_1%
2
PC104
1000P_0603_50V7K
2
1
PR132
90.9K_0402_1%
1
2
1
PR119
@ 205K_0402_1%
VS
PRG++ 2
V IN
VS
V IN
2
1
PR142
@ 499K_0402_1%
PR138
@ 2.2M_0402_5%
2
1
VL
PR137
1M_0402_1%
1
2
B+
PR31
@ 1K_1206_5%
1
2
PC98
@0.01U_0402_25V7K
17.470
15.808
High 17.944 17.706

Low 16.242 16.027
2
1
PD4
@ RLS4148_LL34-2
PC95
@1000P_0402_50V7K
VIN
Title
DCIN & DETECTOR

Custom
Date:
R ev
0.1
Sheet
D
34
of
43
PH3 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 45 degree C
VL
VL
1
6
TM_REF1
O
-
D
PQ23
2N7002KW_SOT323-3
2
G
PU12B
LM393DG_SO8
2
1
1
2
VL
PR131
100K_0402_1%
PR134
100K_0402_1%
EC_SMB_CK1 <27>
PC99
1000P_0402_50V7K
1
2
PC12
0.22U_0402_6.3V6K
2
1
PR141
16.9K_0402_1%
1
PC51
0.01U_0402_25V7K
@ SUYIN_200082MR007G100ZR
PC45
1000P_0402_50V7K
1
PR1
100_0402_1%
PR2
100_0402_1%
MAINPW ON <34,37>
BATT+
EC_SMCA
EC_SMDA
TS
PR140
13.7K_0402_1%
1
2
PL4
SMB3025500YA_2P
1
2
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
GND
GND
VMB
PF1
7A_24VDC_429007.WRML
1
2
JBATT
VMB2
2
PR139
47K_0402_1%
1
PR129
47K_0402_1%
PH1
100K_0603_1%_TH11-4H104FT
EC_SMB_DA1 <27>
1
2
PR3
6.49K_0402_1%
1
2
PR4
10K_0402_1%
+3VALWP
BATT_TEMP <27>
A/D
3
Issued Date
Compal Secret Data
2007/6/22
Deciphered Date
2008/6/22
A
Title
BATTERY CONN / OTP

Size
Date:
Document Number
R ev
0.1
Sheet
D
35
of
43
B+
P3
P2
PQ16
FDS4435BZ_SO8
S
D 8
S
D 7
S
D 6
G
D 5
CHG_B+
1
PC5
2200P_0402_50V7K
CS IN
CSIP
1
2
3
4
1 1
UGATE
17
CHLIM
BOOT
16
10
ACLIM
VDDP
15
11
VADJ
LGATE
14
GND
PGND
13
DH_CHG
PR74
2.2_0402_5%
BST_CHG 1
2
PR80
31.6K_0402_1%
12
PC67
0.1U_0603_25V7K
BST_CHGA 2
1
4
PD11
RB751V-40TE17_SOD323-2
6251VDDP
DL_CHG
26251VDD
PR77
4.7_0402_5%
PC70
4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
Connect to EC A/D Pin.

<27> CHGVADJ
VMB2
1
PU9A
@ LM358DT_SO8
1 0
PR112
@ 105K_0402_1%
PR12
1
100K_0402_1%
1
PQ8
DTC115EUA_SC70-3
FSTCHG
SUSP#
PD2
RB715F_SOT323-3
FSTCHG <27>
SUSP# <27,31,38,39>
2007/6/22

2008/6/22
Deciphered Date
PU9B
@ LM358DT_SO8
7 0
Compal Secret Data
Issued Date
VS
6251DCIN
<27> BATT_OVP
PR14
100K_0402_1%
2
1
PR115
@ 10K_0402_1%
1
2
PR113
@ 499K_0402_1%
Per cell=3.5V
BATT-OVP=0.1112*VMB
3.2935V
PQ10 TP0610K-T1-E3_SOT23-3
3
PR114
@ 340K_0402_1%
PC87
@0.01U_0402_25V7K
4.35V
LI-3S :13.5V----BATT-OVP=1.5012V
IREF=0.468V~2.81V
1.882V
IREF=1.56*Icharge
0V
4.2V
4V
CC=0.3~1.8A
VS
CHGVADJ
Vcell
CHGVADJ=(Vcell-4)/0.10627
CP mode
Vaclim=2.39*(31.6K/(231.6K+13.7K))=1.6672V
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05)
where Vaclm=0.8199V, Iinput=1.7A
P3
BATT+
PR79
31.6K_0402_1%
2
1
PC85
@0.01U_0402_25V7K
Iada=0~2A(40W) CP = 85%*Iada ; CP = 1.7A
IREF=3.3V =>2.12A
PR78
15.4K_0402_1%
1
2
PL5
10UH_PCMB063T-100MS_4A_20%
PR63 0.05_1206_1%
C1HG
1
2
4
PC48
10U_1206_25V6M
2
1
5
VREF
PACIN
PQ9
2N7002KW_SOT323-3
PC47
10U_1206_25V6M
2
1
1
2
PC68
0.1U_0402_16V7K
PR81
13.7K_0402_1%
6251_VREF 1
2
18
ICM
2
G
S
PHASE
1
2
7
PR73
100_0402_1%
6251_VREF 8
V IN
PC46
10U_1206_25V6M
2
1
19
PC11
0.1U_0603_25V7K
2
1
CSIP
PR15
200K_0402_1%
1
2
VCOMP
20
PD3
RB715F_SOT323-3
PR10
@ 4.7_1206_5%
CSIN
ICOMP
CSOP
6.81K_0402_1%
2
ACOFF
3
1
PC8
@ 680P_0603_50V7K
21
PQ3
SIS412DN-T1-GE3 _PAK1212-8
CSOP
CSON
PC57
0.047U_0402_16V7K
1
2
PR69
20_0402_5%
2
1
PR70
PC62
20_0402_5%
0.1U_0402_16V7K
1
2
PR71
2.2_0402_5%
LX_CHG
PQ4
SI7716ADN-T1-GE3 _PAK1212-8
CELLS
22
3
2
1
CSON
EN
PR65
20_0402_5%
1
2
23
PQ7
DTC115EUA_SC70-3
3
2
1
1
PR76
100K_0402_1%
ACSET ACPRN
ADP_I
PR75
56K_0402_1%
2
1
6800P_0402_25V7K
2
1
2
PC64
@ 100P_0402_50V8J
PC69
0.01U_0402_25V7K
2
1
IREF
PR72
1
0.01U_0402_25V7K
<27>
ACOFF
24
PC65
1
2
ACON
ACOFF
DCIN
PC61
1
<27>
<27>
PR68
2
PQ2
D 2N7002KW_SOT323-3
2
G
PQ1
DTC115EUA_SC70-3
VDD
PR9
3K_0402_1%
PACIN 1
2
6251_EN
PC54
0.1U_0603_25V7K
6251DCIN 2
1
S
2
2
G
PU6
PR64
150K_0402_1%
PQ28
D 2N7002KW_SOT323-3
2
PC58
0.1U_0402_16V7K
100K_0402_1%
<27> FSTCHG
<34>
VIN
PR67
10K_0402_1%
2
1
PR13
10K_0402_1%
PC55
2.2U_0603_6.3V6K
2
1
1
PQ26
DTC115EUA_SC70-3
PACIN
8
7
6
5
D
D
D
D
PR16
47K_0402_1%
1
2
PD10
RB751V-40TE17_SOD323-2
6251VDD
1
2
<34>
S
S
S
G
PC2
4.7U_1206_25V6K
1
2
PQ17
FDS4435BZ_SO8
@ JUMP_43X118
PC3
4.7U_1206_25V6K
1
2
1
2
PC49
0.1U_0603_25V7K
2
1
PR61
200K_0402_1%
PQ27
PJ7
2
PC4
4.7U_1206_25V6K
1
2
PR58 0.05_1206_1%
4
1
PR143
47K_0402_5%
DTA144EUA_SC70-3
1
2
3
4
PC106
470P_0603_50V8J
PD9
B340A_SMA2
2
1
VIN
Title
Size
Date:
CHARGER
Document Number
R ev
0.1
Sheet
1
36
of
43
3V_B+
VL
30
OUT2
32
REFIN2
1
2 2VREF_ISL6237
PC32
0.22U_0603_25V7K
REF
LDOREFIN
PD7
RB751V-40TE17_SOD323-2
1
2
PGND
22
OUT1
10
FB1
11
BYP
SKIP
29
PR49
100K_0402_1%
1
2
PR43 @ 0_0402_5%
2
1
POK1
13
EN1
ILIM1
12
ILM1
ILIM2
31
IL IM2
GND
TON
NC
EN2
2
1
PR40
1
+5VALWP
Imax=5A
Ipeak=6.5A
Iocp(minimum)=7.6A
0_0402_5%
2
2
1
PR55
301K_0402_1%
2
PU5
SN0806081RHBR_QFN32_5X5
PR44
301K_0402_1%
PR41
0_0402_5%
PJ5
PR47
0_0402_5%
+3VALWP
2007/06/22
Issued Date
+3VALW
+5VALW
@ JUMP_43X118
Deciphered Date

2008/06/22
3
PJ6
+5VALWP
Compal Secret Data
@ JUMP_43X118
VL
2VREF_ISL6237
2
P C31
@ 0.047U_0402_16V7K
2
1
1
2
P C42
0.047U_0402_16V7K
0_0402_5%
21
5
P C37
1U_0603_10V6K
2
1
PR42
@ 47K_0402_5%
2VREF_ISL6237 1
806K_0603_1%
EN_LDO
VL
P R56
28
27
PR57
<34,35> MAINPW ON
14
POK2
2
1
P C88
2200P_0402_50V7K
PQ24
SIS412DN-T1-GE3_PAK1212-8
FB5
NC
4
PC35
0.22U_0603_25V7K
PD8
RB751V-40TE17_SOD323-2
1
2
P R50
200K_0402_1%
1
2
PD14
RLZ5.1B_LL34
1
2
PC97
680P_0603_50V8J
PR39 @ 0_0402_5%
2VREF_ISL6237
1
2
20
VS
PC40
0.1U_0603_25V7K
DL5
LGATE1
18
2VREF_ISL6237
+3VALWP
Imax=5A
Ipeak=6.5A
Iocp(minimum)=7.6A
5
LX5
PR126
4.7_1206_5%
P C38
150U_B2_6.3VM_R45M
LGATE2
3
2
1
PHASE1
16
P R53
@ 61.9K_0402_1%
1
2
PHASE2
4.7U_0805_6.3V6K
P C41
2
1
1U_0603_10V6K
BST5A2
PR52
0_0603_5%
+5VALWP
P R54
0_0402_5%
1
2
FB3
BOOT1
BOOT2
PL3
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1
23
D H5
17
DL3
15
3
2
1
24
PVCC
UGATE1
2
1 BST3A
PR48
0_0603_5%
PC33
0.1U_0603_25V7K
LX3
PC36
1U_0603_10V6K
1
2
19
UGATE2
VCC
26
LDO
6
VIN
TP
D H3
25
P C34
1
2
2
1
33
PQ25
SI7716DN-T1-E3_PAK1212-8
2
2
P R46
@ 10K_0402_1%
PQ21
SI7716DN-T1-E3_PAK1212-8
1
2
3
5
1
2
2
2
PC86
680P_0603_50V8J
PR111
4.7_1206_5%
P R45
0_0402_5%
PC39
0.1U_0603_25V7K
2
1
PC101
10U_1206_25V6M
PL2
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
+3VALWP
VL
@ JUMP_43X79
PQ20
1
2
3
5
2
1
P C93
2200P_0402_50V7K
2
1
P C89
10U_1206_25V6M
PR51
0_0402_5%
1
2
PJ12
P C26
150U_B2_6.3VM_R45M
3V_B+
B+
Title
3V/5V

C ustom
D ate:
R ev
0.1
Sheet
1
37
of
43
PJ2
DRVL
PC83
4.7U_0805_6.3V6K
PU3
TPS51117RGYR_QFN14_3.5x3.5
1
2
1
2
+
2
PR27
30.1K_0402_1%
1
2
3
2
1
LG_1.8V
PC74
10U_0805_6.3V6M
PR19
4.7_1206_5%
V5DRV
B+
+1.8VP
PC76
220U_B2_2.5VM_R25M
PGND
PGOOD
PC25
@ 47P_0402_50V8J
1
2
PC84
1U_0603_10V6K
GND
+5VALW
2
PR22
15.4K_0402_1%
PC18
680P_0603_50V7K
1.8V_TRIP
1
10
1.8V_SNB 2
VFB
SW _1.8V
11
12
PL9
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
1.8V_FB
LL
TRIP
PQ13
SI7716DN-T1-E3_PAK1212-8
V5FILT
UG_1.8V
5
VOUT
13
3
2
1
3
1.8V_V5FILT
DRVH
15
TP
1
TON
EN_PSV
2
PR110
422_0603_1%
1
2
PC20
0.1U_0603_25V7K
+5VALW
PC24
@0.1U_0402_16V7K
4
1
@ JUMP_43X79
2
1
PC16
10U_1206_25V6M
PR24
2.2_0603_5%
BST_1.8V 1
2BST_1.8V-1
1.8V_EN
PR25
0_0402_5%
1
2
14
SYSON
<27,31>
VBST
PC108
1000P_0603_50V7K
<BOM Structure>
PQ12
1.8V_TON
PC43
470P_0603_50V8J
<BOM Structure>
1.8V_IN 1.8V_IN
PR26
240K_0402_5%
1
2
PR28
21K_0402_1%
PJ1
VCCP_IN
LG_VCCP
PU1
TPS51117RGYR_QFN14_3.5x3.5
PC7
4.7U_0805_6.3V6K
PR59
8.87K_0402_1%
1
2
B+
+VCCPP
1
+
2
PC53
10U_0805_6.3V6M
+5VS
10
2
PR8
15.4K_0402_1%
V5DRV
DRVL
2
1
PC9
10U_1206_25V6M
1
VCCP_TRIP 1
PGND
8
GND
7
PC44
1U_0603_10V6K
3
2
1
15
14
SW _VCCP
11
@ JUMP_43X79
PC50
220U_B2_2.5VM_R25M
PGOOD
12
VCCP_SNB2
VFB
LL
TRIP
UG_VCCP
PL6
1
2
V5FILT
13
PQ6
SI7716DN-T1-E3_PAK1212-8
VOUT
VBST
DRVH
VCCP_FB
TP
1
VCCP_V5FILT
TON
PR62
422_0603_1%
1
2
PC6
0.1U_0603_25V7K
3
2
1
+5VS
EN_PSV
2
B
PC1
1U_0402_6.3V6K
4
2
PR11
4.7_1206_5%
PR7
0_0603_5%
BST_VCCP 1
2BST_VCCP-1 1
VCCP_EN
PR6
2.2K_0402_5%
1
2
1
<27,31,36,39> SUSP#
PC10
680P_0603_50V7K
VCCP_TON
PQ5
PR5
240K_0402_5%
1
2
PJ10
+1.8VP
+1.8V
@ JUMP_43X118
PR60
21K_0402_1%
PJ8
+VCCPP
+VCCP
@ JUMP_43X118
2007/6/22
Issued Date
Compal Secret Data
2008/6/22
Deciphered Date
Title
Size
Date:
1.8VP/VCCPP
Document Number
Sheet
1
R ev
0.1
38
of
43
+1.8V
+5VALW
PU11
APL5913-KAC-TRL_SO8
PR125
3K_0402_1%
1
2
+2.5VSP
PR66
@ 150_1206_5%
2
OUT
GND
IN
PC66
4.7U_0805_6.3V6K
1
2
2
PC56
1U_0603_10V6K
GND
PR130
2.7K_0402_1%
+3VS
PC90
0.68U_0603_10V6K
FB
PU7
APL5508-25DC-TRL_SOT89-3
+1.5VSP
EN
POK
3
4
PC102
22U_0805_6.3V6M
8
7
VOUT
VOUT
VCNTL
VIN
VIN
PC94
0.01U_0402_25V7K
6
5
9
2
1
PC100
1U_0603_10V6K
PR122
30K_0402_1%
1
2
<27,31,36,38> SUSP#
PJ11
@ JUMP_43X79
1
2
1
PC103
10U_0805_6.3V6M
PD16
RB751V-40TE17_SOD323-2
1
2
PJ14
@ JUMP_43X79
PJ4
@ JUMP_43X79
GND
NC
VREF
NC
VOUT
NC
TP
PC22
1U_0603_10V6K
+0.9VSP
1
3
PR21
1K_0402_1%
2
1
PC19
0.1U_0402_16V7K
PC21
@ 0.1U_0402_16V7K
2
G
PQ14
2N7002KW_SOT323-3
SUSP
<31>
PR23
0_0402_5%
1
2
+3VALW
PR20
1K_0402_1%
PC23
4.7U_0805_6.3V6K
PU2
APL5331KAC-TRL_SO8
VIN
VCNTL 6
+1.8V
PC17
10U_0805_6.3V6M
PJ13
+1.5VSP
+1.5VS
@ JUMP_43X79
PJ3
+0.9VSP
+0.9VS
@ JUMP_43X79
PJ9
+2.5VSP
+2.5VS
@ JUMP_43X39
2007/6/22
Issued Date
Compal Secret Data
2008/6/22
Deciphered Date
Title
Size
Date:
1.5V/0.9V/2.5V
Document Number
Sheet
1
39
R ev
0.1
of
43
PR105
124K_0402_1%
2
1
+5VS
CSP
25
V5IN
P U8
TPS51610RHB_QFN32_5X5
GNDSNS
DRVL
VGATE
21
<14,19,27>
4
20
LGATE_CPU
19
PHASE_CPU
18
BOOT_CPU
UGATE_CPU
P R86
0_0603_5%
VID0
DRVH
17
5
2
P C72
0.22U_0603_25V7K
4
3
2
1
16
VID1
15
VID3
VID2
14
13
2
PR104
56_0402_5%
VR_TT#
VID4
1
PR103
0_0402_5%
VBST
VID5
8
H_PROCHOT#
<4> H_PROCHOT#
THERM
12
11
2
20K_0603_1%
VID6
1
PH 3
10
2
1
PR106
10K_0402_1%
LL
DPRSTP#
+ CPU_CORE 1
2
P R18
100_0402_1%
VSNS
<5>
C PU_VID5
<5>
C PU_VID4
<5>
C PU_VID3
<5>
C PU_VID2
<5>
C PU_VID1
<5>
C PU_VID0
P R99
2 0_0402_5%
P R98
2 0_0402_5%
P R96
2 0_0402_5%
P R94
2 0_0402_5%
P R91
2 0_0402_5%
P R90
2 0_0402_5%
P R85
2 0_0402_5%
P R82
43.2K_0402_1%
1
2
P H2
150K +-5% ERTJ1VV154J 0603
PC71
680P_0603_50V8J
1
2
PR109
24.9K_0402_1%
+5VS
PC73
4.7U_0805_6.3V6K
P C82
6800P_0402_25V7K
C SN
C PU_VID6
2 0_0402_5%
+CPU_CORE
PR83
162K_0402_1%
P R84
6.8_1206_5%
C SP
<5>
PL8
1
2
<4,18> H_DPRSTP#
PR101
+ VCCP
1
0_0402_5%
B+
2
PR144
PC14
2200P_0402_50V7K
2
1
PM_DPRSLPVR <6,19>
22
PC13
10U_1206_25V6M
2
1
1
499_0402_1%
2
P R88
PC15
10U_1206_25V6M
2
1
VR_ON
27
26
PWRMON
28
TONSEL
TRIPSEL
29
OSRSEL
30
ISLEW
31
V5FILT
PGOOD
23
<5> V CCSENSE
DPRSLP
CSN
1
@ 0_0402_5%
3
2
1
<5> VSSSENSE
GND
2
P R87
24
PC78
100P_0402_50V8J
CLKEN#
2
470_0402_1%
PL1
FBMA-L11-201209-121LMA50T_0805
+CPU_B+
P R89
10K_0402_1%
C SP
1
PR108
PR17
100_0402_1%
1
2
33P_0402_50V8K
2
V R_ON <27>
PQ11
VREF
2
P R93
0_0402_5%
PQ18
SI7716DN-T1-E3_PAK1212-8
2
470_0402_1%
P C80
32
33
TP
1
C SN
1
PR107
DROOP
2
1
VR EF_CPU
P C79
33P_0402_50V8K
1
2
2
PR102
4.53K_0402_1%
PC107
470P_0603_50V8J
PM ON
1
1
PC81
0.22U_0603_25V7K
P R95
@ 0_0402_5%
P R97
0_0402_5%
2
PR100
0_0402_5%
2
1
P C77
27P_0402_50V8J
1
2
VR EF_CPU
PC75
1U_0603_10V6K
2007/09/20
Issued Date
Compal Secret Data
Deciphered Date
2008/09/20
Title
+CPU_CORE
Size
C
Date:
Document Number
R ev
0.1
KAV10 LA-4781P
Sheet
40
H
of
43
Version change list (P.I.R. List)

Item
Page 1 of 1
Fixed Issue
Rev.
PG#
LAN JRJ1
0.2
P25
Change NB,SB P/N
0.2
Customer request
0.2
Modify List
Change JRJ1 Pin define
0.2
0.2
P29
0.2
P28
0.2
P22
Customer request
6
7
Q26 3413 change to 2301

SW3,4 change to SN100000K00
change net name NOVO_BTN# to ONE_KEY_RECOVER#
Change C352,C353,C354,C355 to SE107225K80
0.2
P04
Change C312,C314 to SE000003H00
0.2
P13
Change C109,C110,C128,C129,C130,C112 to SE103225Z80
10
Modify LCD power squence
0.2
P15
Change R221 to 100K
11
Fix WLAN card leakage
0.2
P21
Delete WLAN port80 and cut WWAN port80
12
User define key support power on
0.2
P28
Add D24 for user define key power on and pull up change to +3valw
13
ESD request
0.2
P28
D15 change to SCA00000R00
14
Realtek recommend
0.2
P25
C258 change to 1uf
0.2
C71 and C81 change to 0603
16
For B Phase
0.2
P27
Add R97 100k and change R94 to 8.2K
17
EMI request
0.2
P27,15
Add R93,C385,C147,C10,C11 Change R165 to 33 ohm
18
ESD request
0.2
P4
Add C391~C397
19
For N280
0.2
P14
Unpop: R68,110,87 Pop:R69,119,84
20
Realtek recommend
0.2
P25
Delete C257
0.2
P10
C30 change to SE027474Z80
0.2
P30
U7,30 change to high active unpop R185
0.2
P22
Unpop C325
1.0
P27
Unpop R94
21
22
Customer request
23
SB to SA00000V1D0
TP 12pin change to 6pin
15
2
Change NB to SA00002KQ50
P29
24
EC code for MP
25
SSD pin change
POP C326
1.0
P21
JP13 32pin change to 47pin
26
1.0
P28
Change D14,D24 foorprint
27
1.0
28
1.0
29
1.0
30
1.0
P20
Unpop D12
1.0
P20
Add C257,C398,C399,C400
31
EMI request
32
Change BT connect
P16
Change D2 from SC1B491D000 to SCS00002000

Change C373, C297, C71, C73, C81, C82, C84 and C85 to SE052105Z80
3
1.0
P04
Unpop R58
33
SSD
1.0
P21
Unpop R117
34
EMI request
1.0
P27
R165 change to bead for EMI request
35
3G request
1.0
P14
Pop C390
36
1.0
P28
Change D1,14,24 P/N SC2N202U010 to SC6AV70W110
37
1.0
P27
Unpop D7

Title
A
HW PIR
Size
Document Number
R ev
LA-4421P
D ate:
Sheet
E
41
of
43

Item
1
Page 1 of 1 for PWR
Fixed Issue
Adjust charging current
PG#
Modify List
Adjust charging current
P36
Change PR75 from 88.7K to 56K.
2008.12.30
EVT
EMI requests to add soltion
P40
Add PC107
2009.02.13
PVT
Adjust charging voltage
P36
Change PR78 from 18.2K to 15.4K.
2009.02.13
PVT
Add PC106
2009.02.13
PVT
Add PC108 and PC43

Add PD16
Change PR122 from 10K to 30K.
Change PC90 from 0.47u to 0.68u.
2009.02.13
PVT
2009.02.13
PVT
Change PR141 from 21.5k to 16.9k.
2009.03.13
Pre-MP
Reason for change
Rev.
Date
Phase
EMI
2
3
Adjust charging voltage

EMI
4
5
6
7
EMI
Design change
Thermal
P36
P38
Adjust +1.5VSP turn on timing
P39
Adjust CPU OTP from 85 degree C to 90 degree C
P35
8
C
10
11
12
13
14
B
15
16
17
18
19
20
21
22
A
Issued Date
Compal Secret Data
2007/09/20
Deciphered Date
2008/09/20
Title
PIR (PWR)
Custom
Rev
0.1
<Doc>
Date:
Sheet
42
of
43

Item
Page 1 of 1
Fixed Issue
Rev.
PG#
0.2
P25
Change JRJ1 Pin define
P15
Change R221 to 100K
Customer request
0.2
P29
TP 12pin change to 6pin
Fix WLAN card leakage
0.2
P21
Delete WLAN port80 and cut WWAN port80
LAN JRJ1
Modify LCD power squence
3
4
Modify List
User define key support power on
0.2
Customer request
0.2
P28
Change net name NOVO_BTN# to ONE_KEY_RECOVER#
Add D24 for user define key power on and pull up change to +3valw
ESD request
0.2
P28
D15 change to SCA00000R00
Realtek recommend
0.2
P25
C258 change to 1uf
For B Phase
0.2
P27
Add R97 100k and change R94 to 8.2K
10
EMI request
0.2
P27,15
Add R93,C385,C147,C10,C11 Change R165 to 33 ohm
11
ESD request
0.2
P4
Add C391~C397
12
For N280
0.2
P14
Unpop: R68,110,87 Pop:R69,119,84
13
Customer request
0.2
P30
U7,30 change to high active unpop R185
14
EC code for MP
1.0
P27
Unpop R94
15
Mini SSD pin define change
1.0
P21
JP13 pin 32 change to 47
30 change to 45
16
2
17
18
19
22
22
0.2
23
0.2
24

Title
A
HW PIR
Size
Document Number
R ev
LA-4421P
D ate:
Sheet
E
43
of
43

Lenovo Ideapad s10-2 (Kiun0, La-5071p)

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Informasi Dokumen

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Lenovo Ideapad s10-2 (Kiun0, La-5071p)

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A

KIUN0 Schematics Document

Compal Electronics, Inc.

Compal Secret Data

Model Name : KIUN0

1.8V DDRII 400/533

AMP & INT

Compal Electronics, Inc.

Compal Secret Data

External PCI Devices

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

SLP_S3# SLP_S4# SLP_S5#

ICH7M SM Bus address

BOARD ID Table(Page 25)

Compal Electronics, Inc.

Compal Secret Data

This shall place near CPU

Close to CPU pin

Zo=27.4ohm +/-15%, make

CPU THERMAL SENSOR

H_THERMDA, H_THERMDC routing together.

Close to CPU pin

Close to CPU pin

Compal Electronics, Inc.

Compal Secret Data

Monday, April 06, 2009

Length match within 25 mils

PLACE IN CORRIDOR AND CLOSE TO CPU

Compal Electronics, Inc.

Compal Secret Data

Strap Pin Table

Compal Electronics, Inc.

Compal Secret Data

Monday, April 06, 2009

DDR2 SYSTEM MEMORY

Compal Electronics, Inc.

Compal Secret Data

Monday, April 06, 2009

Compal Electronics, Inc.

Compal Secret Data

Compal Electronics, Inc.

Compal Secret Data

Monday, April 06, 2009

Route +2.5VS from GMCH pinN33 to

Route VSSACRTDAC gnd from GMCH to

close pin C29/D29

close pin B31

Compal Electronics, Inc.

Compal Secret Data

PCI-E/MEM/PSB PLL decoupling

Monday, April 06, 2009