VLSI Physical Design Automation

VLSI Physical Design Automation

Objectives:

Obtain a general understanding of IC's.

Study the basic algorithms used in designing the
layout of a chip.
Study algorithms which convert a circuit description
into a geometric description.
Study the di erences in algorithms that perform the
same operations.

Algorithms for VLSI Physical Design Automation

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VLSI Physical Design Automation

VLSI Design Cylce

manual

System
Specifications

Chip

automation

Large number of devices

Optimization requirements for high performance
Time-to-market competition
Cost

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VLSI Design Cycle

1. System Speci cation
2. Functional Design
3. Logic Design
4. Circuit Design
~
5. Physical Design
6. Design Veri cation
7. Fabrication
8. Packaging, Testing, and Debugging

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VLSI Design Cycle

System Specification

Functional Design

Logic Design

x = (AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C)+AC+D+A(BC+D))

Circuit Design

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VLSI Design Cycle (cont.)

Physical Design

Fabrication

Packaging

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Physical Design

Physical design converts a circuit description into a

geometric description. This description is used to
manufacture a chip. The physical design cycle consists of
1. Partitioning
2. Floorplanning and Placement
~
3. Routing
4. Compaction

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Physical Design Cycle

Circuit
Design

Physical Design

cutline 2

(a)

(b)

Partitioning

cutline 1

Floorplanning
&

Placement

(c)

Routing

(d)

Compaction

Fabrication

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Complexities of Physical Design

More than 3 million transistors

Performance driven designs
Time-to-market
Design Styles

...

High performance, high cost

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Design Styles
Complexity of
VLSI curcuits

Performance

Size

Cost

Market time

Different design styles

Full custom

Gate array

Standard cell

FPGA

Cost, Flexibility, Cost

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Full Custom Design Style

Pad

Metal 1

Metal 2

Via

Data path
PLA

I/O

ROM/RAM

Random logic
A/D converter

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Standard Cell Design Style

Cell

VDD

Feedthrough

Metal 1

GND

Metal 2

Cell library
Cell A

Cell C

Cell B

Cell D

Feedthrough cell

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Gate Array Design Style

A
C
B

VDD

Metal 1

Metal 2

GND

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FPGA Design Style

P

D
F
B

(a)
P

(b)
VDD

GND

B
F

10

11

12

(c)

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Comparisons of Design Styles

style
full-custom standard cell gate array
FPGA
cell size
variable xed height
xed
xed
cell type
variable
variable
xed programmable
cell placement variable
in row
xed
xed
interconnections variable
variable
variable programmable
uneven height cells are also used.

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Comparisons of Design Styles

style
full-custom standard cell gate array
Area
compact
compact
moderate
to moderate
Performance
high
high
moderate
to moderate
Fabrication layers
All
All
routing layers

Algorithms for VLSI Physical Design Automation

FPGA
large

1.15

low
none

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Packaging Styles

Packaging

Printed Circuit Board

Multi-Chip Module

Wafer Scale Integration

PCB

MCM

WSI

Area
Performance, Cost

The increasing complexity and density of the

semiconductor devices are driving the development of
more advanced VLSI packaging and interconnection
approaches.
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VLSI Physical Design Automation

Printed Circuit Board Model

Package
Plated

IC

(a)

through
holes

x
y
x
y
(b)

Large number of layers (150 pitch)

Large area
Low performance
Low cost
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MCM Model

IC

(a)

x
y
x
y
(b)

Up to 36 layers (75 pitch)

Moderate to small area
Moderate to high performance
High cost
Heat dissipation problems
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Wafer Scale Integration

Small number of layers (VLSI technology - 6 pitch)

Smallest area
Signi cant yield problems
Very High performance
Signi cant heat dissipation problems

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Comparisons of Packaging styles

Technology
~

WSI
MCM
PCB

Figure of Merit
(inches/psec . density inches/sq in)
28.0
14.6
2.2

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History of VLSI CAD

Year
1950-1965

Manual design

Design Tools

1965-1975

Layout editors
Automatic routers (for PCB)
E cient partitioning algorithm

1975-1985

Automatic placement tools

Well de ned phases of design of circuits
Signi cant theoretical development in all phases

1985-present Performance driven placement and routing tools

Parallel algorithms for physical design
Signi cant development in underlying graph theory
Combinatorial optimization problems for layout
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VLSI CAD Conferences

ACM/IEEE Design Automation Conference (DAC)

International Conference on Computer Aided Design (ICCAD)
IEEE International Symposium on Circuits and Systems (ISCAS)
International Conference on Computer Design (ICCD)
IEEE Midwest Symposium on Circuits and Systems (MSCAS)
IEEE Great Lakes Symposium on VLSI (GLSVLSI)
European Design Automation Conference (EDAC)
International Conference on VLSI Design

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VLSI CAD Journals

IEEE Transactions on CAD of Circuits and Systems

Integration
Transactions on Circuits and Systems
Journal of Circuits, Systems and Computers
Algorithmica
SIAM journal of Discrete and Applied Mathematics
IEEE Transactions on Computers

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VLSI CAD Organizations

ACM SIGDA
Design Automation Technical Committee (DATC)

of IEEE Computer Society

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Summary
1. Physical design is one of the steps in the VLSI design cycle.
2. Physical design is further divided into partitioning, placement, routing
and compaction.
3. There are ve major design styles, e.g., full custom, standard cell,
gate array, sea of gates and FPGAs.
~ 4. There are three alternatives for packaging of chips, e.g., PCB,
MCM and WSI.
5. Automation reduces cost, increases chip density, reduces timeto-market, and improves performance.
6. CAD tools currently lag behind fabrication technology, which
is hindering the progress of IC technology.

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