Apple Macbook Pro A1286 (820-2850, K18) PDF

8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
ECN
<REV>
<ECN>
DESCRIPTION OF REVISION
CK
APPD
DATE
SCHEM,WHITE_ARROW,MLB,K18
<ECO_DESCRIPTION>
<ECODATE>
02/01/10
(.csa)
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
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48
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Date
Contents
Sync
Table of Contents
System Block Diagram
Power Block Diagram
Revision History
BOM Configuration
Functional / ICT Test
Power Aliases
Signal Aliases
CPU DMI/PEG/FDI/RSVD
CPU Clock/Misc/JTAG
CPU DDR3 Interfaces
CPU Power (1 of 2)
CPU Power (2 of 2)
CPU Grounds
CPU Non-GFX Decoupling (1 of 2)
PCH SATA/PCIE/CLK/LPC/SPI
PCH DMI/FDI/Graphics
PCH PCI/FlashCache/USB
PCH MISC
PCH Power
PCH Grounds
PCH Non-GFX Decoupling
CPU/PCH GFX Decoupling
eXtended Debug Port (XDP)
Clock (CK505)
Chipset Support
DDR3 SO-DIMM Connector A
DDR3 Byte/Bit Swaps
DDR3 SO-DIMM Connector B
CPU Memory S3 Support
FSB/DDR3/FRAMEBUF Vref Margining
X16/ALS/CAMERA CONNECTOR
SecureDigital Card Reader
USB HUB 1
USB HUB 2
Ethernet PHY (Caesar II/IV)
Ethernet Connector
FireWire LLC/PHY (FW643)
FireWire Port Power
FireWire Ports
SATA Connectors
External USB Connectors
Front Flex Support
SMC
MASTER
(.csa)
Page
MASTER
06/30/2009
K17_REF
06/30/2009
K17_REF
MASTER
MASTER
05/28/2009
K17_REF
MASTER
MASTER
MASTER
MASTER
06/11/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
08/24/2009
K17_REF
06/15/2009
K17_REF
10/07/2009
K18_MLB
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/23/2009
K17_MLB
06/15/2009
K17_REF
MASTER
MASTER
MASTER
MASTER
MASTER
MASTER
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K18_COMMS
08/26/2009
T27_REF
10/07/2009
K18_MLB
10/06/2009
K23F
08/20/2009
T27_REF
06/15/2009
K17_REF
05/29/2009
K19_MLB
05/29/2009
K19_MLB
05/29/2009
K19_MLB
10/01/2009
T27_REF
06/15/2009
K17_REF
05/29/2009
K19_MLB
06/15/2009
K17_REF
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49
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54
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57
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90
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82
84
85
86
87
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89
90
93
94
95
96
97
98
99
Date
Contents
Sync
SMC Support
LPC+SPI Debug Connector
K18 SMBus Connections
Current & Voltage Sensing
Current Sensing
Thermal Sensors
Fan Connectors
WELLSPRING 1
WELLSPRING 2
Sudden Motion Sensor (SMS)
DEBUG SENSORS AND ADC
SPI ROM
AUDIO: CODEC/REGULATOR
AUDIO: LINE INPUT FILTER
AUDIO: HEADPHONE FILTER
AUDIO: SPEAKER AMP
AUDIO: JACKS
AUDIO: JACK TRANSLATORS
DC-In & Battery Connectors
PBus Supply & Battery Charger
5V / 3.3V Power Supply
1.5V DDR3 Supply
CPU IMVP VCore Regulator
GFX IMVP VCore Regulator
CPUVTT (1.05V) Power Supply
Misc Power Supplies
Power FETs
Power Control
NV GT216 PCI-E
NV GT216 CORE/FB POWER
NV GT216 FRAME BUFFER I/F
GDDR3 Frame Buffer A (Top)
GDDR3 Frame Buffer B (Top)
NV GT216 GPIO/MIO/MISC
GT216 GPIOS & STRAPS
NV GT216 VIDEO INTERFACES
GPU (GT216) CORE SUPPLY
LVDS Display Connector
Muxed Graphics Support
DisplayPort Connector
1V8 / 1V55 FB Power Supply
Graphics MUX (GMUX)
LCD BACKLIGHT DRIVER
LCD Backlight Support
Misc Power Supplies
06/29/2009
K18_SENSORS
06/23/2009
K17_MLB
06/18/2009
K18_SENSORS
06/29/2009
K18_SENSORS
07/02/2009
K18_SENSORS
06/18/2009
K18_SENSORS
05/29/2009
K19_MLB
05/29/2009
K19_MLB
05/29/2009
K19_MLB
05/29/2009
K19_MLB
07/07/2009
K18_SENSORS
06/15/2009
K17_REF
09/21/2009
K18_AUDIO
07/29/2009
K18_AUDIO
07/29/2009
K18_AUDIO
07/29/2009
K18_AUDIO
07/29/2009
K18_AUDIO
07/29/2009
K18_AUDIO
06/30/2009
K18_POWER
06/30/2009
K18_POWER
07/13/2009
K18_POWER
07/14/2009
K18_POWER
06/29/2009
K18_POWER
07/08/2009
K18_POWER
07/14/2009
K18_POWER
06/29/2009
K18_POWER
06/10/2009
K18_POWER
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
07/14/2009
K18_POWER
05/29/2009
K19_MLB
06/15/2009
K17_REF
06/15/2009
K17_REF
06/26/2009
K18_POWER
06/15/2009
K17_REF
07/29/2009
K18_BKLT
05/29/2009
K19_MLB
06/10/2009
K18_POWER
(.csa)
Page
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132
CPU Constraints
Memory Constraints
PCH Constraints 1
PCH Constraints 2
Ethernet Constraints
FireWire Constraints
SMC Constraints
GPU (GT216) CONSTRAINTS
Project Specific Constraints
PCB Rule Definitions
BluRay Decrypter Card Connector
Date
Sync
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
06/15/2009
K17_REF
ALIASES RESOLVED
100
Contents
A
DRAWING TITLE
Schematic / PCB #s
PART NUMBER
DRAWING NUMBER
Apple Inc.
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
051-8504
SCH
CRITICAL
820-2850
PCBF,WHITE_ARROW,MLB,K18
PCB
CRITICAL
BOM OPTION
NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING
TITLE=MLB
ABBREV=DRAWING
LAST_MODIFIED=Mon Feb
1 10:13:48 2010
SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
1 OF 132
SHEET
1 OF 101
U2600
INTEL CPU
U8000
XDP CONN
PRAPHICS
2.X GHZ
NV GT216
ARRANDALE
PG 25
PG 9
PG 73
J2900
2 UDIMMs
DDR3-1067/1333MHZ
DIMM
J6950
PG 28,30
DC/BATT
POWER SUPPLY
PG 63
GPIO
PG 20
FDI
DMI
RTC
PG 18
PG 18
PG 17
U4900
TEMP SENSOR
CLOCK
CK505
U2700
Misc
CLK
PG 44
PG 20
U6100
BUFFER
P8 26
PG 17
J4500
SATA
Conn
HD
SPI
FAN CONN AND CONTROL
PG 56
1.05V/3GHZ.
PG 51
INTEL
SATA
U4900
ADC
B,0 BSB
IBEX PEAK-MPCH
SATA
SMC
LPC
PG 17
1.05V/3GHZ.
J5650,5660
PG 17
P8 40
J4501
POWER PGSENSE
44
SPI
Boot ROM
Fan Ser
Prt
J5100
PG 44
LPC Conn
Port80,serial
PG 46
Conn
ODD
PG 17
U1800
P8 40
J9000
PWR
DISPLAY PORT
CONN
CTRL
DP OUT
PG 84
RGB OUT
U9600
GMUX
XP2-5
LVDS OUT
PG 85
USB
PG 18
PG 19
TMDS OUT
PCI
PG 19
J9400
LVDS
CONN
(UP TO 14 DEVICES)
DVI OUT
PCI-E
0 1 2 3 4 5 6 7 8 9 10 11 12 13
J3401
HDMI OUT
J5713
Bluetooth
PG 33
J3401
TRACKPAD/
KEYBOARD
J3401
IR
PG 33
PG 52
J4600,J4610,4720
CAMERA
EXTERNAL
USB
Connectors
PG 33
PG 41
PG 19
SMB
JTAG
PG 71
SMB
CONN
PG 17
PG 17
HDA
PCI-E
PEG
PG 47
DIMMs
(UP TO 16 LINES)
PG 17
PG 17
PG 17
U6200
Audio
Codec
PG 57
U4100
U3900
U6500
J3500
GB
E-NET
FW643
BCM5764M
EXPRESSCARD
CONN
Line In
Amp
HEADPHONE
Amp
Speaker
Amps
PG 59
PG 60
PG 37
PG 35
U6610,6620,6630,6640,6650
Line Out
Amp
SYNC_MASTER=K17_REF
SYNC_DATE=06/30/2009
PAGE TITLE
System Block Diagram
PG 34
DRAWING NUMBER
J3400
J4310
Apple Inc.
J4000
R
Mini PCI-E
AirPort
E-NET
Conn
E-NET
Conn
PG 39
PG 36
J6780,6781,6782,6700,6750
Audio
Conns
PG 28

PG 61
SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
2 OF 132
SHEET
2 OF 101
K17 POWER SYSTEM ARCHITECTURE

PPDCIN_G3H_OR_PBUS_R
SMC PWRGD
NCP303LSN
U5000
(PAGE 45)
R6905
SMC_RESET_L
ENABLE
SMC AVREF SUPPLY
3.425V G3HOT
J6900
F7040
SMC_TPAD_RST_L
U7000
VIN
PPVBAT_G3H_CHGR_REG
VIN
VOUT
PP5V_S3_GPUVCORE
VDD
F7041
8A FUSE
ISL6259HRTZ
SMC_DCIN_ISENSE
PBUS SUPPLY/
BATTERY CHARGER
ISL6263C
U8900
PPVCORE_GPU
PP5V_S0_CPUVTTS0
VIN
U5410
PGOOD
EN
CPU VCORE
VOUT
VIN
ISL9522
SMC_CPU_FSB_ISENSE
CPUVTTS0_PGOOD
CPUVTTS0_EN
(PAGE 69)
GPUVCORE_PGOOD
SMC_CPU_HI_ISENSE
PPCPUVTT_S0
TPS51513
U7600
SMC_GPU_ISENSE
R5388
PPVBAT_G3H_CHGR_R
VOUT
1.05V
(PAGE 81)
Q7055
PPVBATT_G3H_CONN
U5001
R7640
SMC_GPU_VSENSE
PGOOD
GPUVCORE_EN
SMC_BATT_ISENSE
(PAGE 64)
J6950
GPU VCORE
R7050
VOUT
VR_ON
SMC_CPU_VSENSE
PPVCORE_S0_CPU
IBEX PEAK MPM_PWRBTN_L

PWRBTN#
SMC_CPU_ISENSE
U7400
SYS_RERST#
CPUIMVP_VR_ON
VR_ON
CHGR_BGATE
RSMRST#
CPUIMVP_GOOD
PGOOD
ACPRESENT
(PAGE 67)
PM_PCH_PWRGD
PLT_RERST_L
PS_PWRGD
PLTRST#
U1800
GMUX
U9600
XP2-5
PB16B
EG_RAIL1_EN
P1V1GPU_EN
PB17A
EG_RAIL2_EN
P3V3GPU_EN
PB17B
EG_RAIL3_EN
GPUVCORE_EN
PB18A
EG_RAIL4_EN
PP5V_S3_DDRREG
SMC_DDR_ISENSE
VIN
P1V1GPU_EN
EN1
PP1V1_S0GPU
VIN
DDRVTT_EN
VOUT1
R5413
1.103V(L/H)
P1V8FB_EN
U4900
RC
P60
(PAGE 44)
DELAY
SMC_PM_G2_EN
EN2
1.8V(R/H)
ISL6236
U9500
(PAGE 85)
P3V3S5_EN
VOUT2
VLDOIN
1.5V
S5
VOUT1
S3 0.75V
VOUT2
PPVTT_S0_DDR_LDO
CPU
PP1V8_S0GPU
TPS51116
DDRREG_PGOOD
U7300
PGOOD
(PAGE 66)
SMC_GPU_1V8_ISENSE
POK1
P1V1GPU_PGOOD
POK2
P1V8FB_PGOOD
PP1V5_S0
SLG5AP020
VOUT
P1V5DDR_EN
RESET*
(PAGE 9~14)
Q7850
PP1V2_GMUX_FET
P5VS0_EN
VIN
EN1
5V
EN2
3.3V
VOUT1
P3V3S5_EN
RC
RC
BKLT_PLT_RST_L
&&
LCD_BKLT_EN
DDRREG_EN
DELAY
U1800
P3V3S3_EN
U9700
BKLT_EN
VOUT
PP3V3_S5
VIN
P1V2ENET_EN
ISL8009B
EN
(R/H)
Q7870
U7760 VOUT
U7980
PP1V2_ENET
(PAGE 70)
RSMRST_PWRGD
P5VS3_PGOOD
PPVOUT_S0_LCDBKLT
P1V5_EXP_S0_EN
EN
P3V3GPU_EN
VIN
ISL8009B
U7710
Q7922
PP3V3_S0_PWRCTL
LTC1872
VIN
U7790
VIN
P1V8_S0_EN
EN
(PAGE 70)
P3V3S0_EN
SMC_ADAPTER_EN&&PM_SLP_S3_L
RC
DELAY
P1V2GMUX_EN
U7720
GFX_VR_ENVR_ON
RES*
PP1V8_S0
P1V8S0_PGOOD
U4900
(PAGE 44)
PP3V3_S0
PP1V5_S0
U7971
ADJ1
PP3V3_FW_FET
ISL88042IRTEZ
RST*
PP1V05_S0
PPVCORE_S0_GFX
ADJ2
FW_PWR_EN
(PAGE 72)
TPS51981
TRST = 200mS
U7500
SYNC_MASTER=K17_REF
Power Block Diagram
(PAGE 68)
CPUVTTS0_EN
PAGE TITLE
DRAWING NUMBER
P3V3S0_EN
GFX_DPRSLPVR
DPRSLPVR
SMC_RESET_L
PM_SLP_S3_L
VCC
Q4291
P5VS0_EN
PM_SLP_S4_L
SLP_S3_L(P93)
VOUT
(PAGE 70) PGOOD
R7540
GFXIMVP_ISENSE
VIN
VOUT
P1V8S0_EN
SLP_S5_L(P95)
Q3810
1.05V AUX
RC
DELAY
ISL8014
SMC_GFX_VSENSE
R7978
PM_SLP_S3_L_R
PM_PWRBTN_L
P17(BTN_OUT)
PM_SLP_S5_L
SLP_S4_L(P94)
S0PGOOD_PWROK
PP3V3_S0_FET
VOUT
P5VS3_PGOOD
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN
Q7830
SLP_S3#(P12)
IMVP_VR_ON
PM_SYSRST_L
PP3V3_ENET
P3V3S3_EN
(PAGE 17~22)
99ms DLY
IMVP_VR_ON(P16)
SYSRST(PA2)
PP3V3_S3
PFWBOOST
PM_RSMRST_L
RSMRST_OUT(P15)
(PAGE 70)
Q7810
Q4260
RSMRST_IN(P13)
PWR_BUTTON(P90)
OUT
P1V8S0_PGOOD
PM_SLP_S3_L
(P64)
SMC_ONOFF_L
PP1V5_EXP_S0
PGOOD
Apple Inc.
GFXIMVP_PGOOD

P1V5DDR_EN
SIZE
<SCH_NUM> D
REVISION
PBUSVSENS_EN
SMC_ADAPTER_EN
PWRGD(P12)
(PAGE 87)
PM_SLP_S4_L
SMC
ALL_SYS_PWRGD
PP3V3_S0_GPU
P3V3S5_PGOOD
VIN
APP001
ENA
SLP_S4#(H7)
PP3V3_S5
VOUT2
TPS51980
U7201
(PAGE 65)
PGOOD1
PGOOD2
P5VS3_EN
DELAY
P1V2GMUX_EN
PP5V_S3
PM_ALL_GPU_PGOOD
(L/H)
PM_SLP_S5_L
Q9806
SM_DRAMPWROK
U1000 VCCCPUPWRGD
Q7860
PP5V_S0_FET
P5VS3_EN
RC
DELAY
PP1V5_S3
U7801
SLP_S5#(E4)
RC
DELAY
(PAGE 17~22)
PPDDR_S3_REG
ON
IBEX_PEAK_M
U2850
SMC_CPU_DDR_VSENSE
R7350
DDRREG_EN
SMC
PM_MEM_PWRGD
P1V8_S0GPU_EN
(PAGE 86)
CPU_PWRGD
PROCPWRGD
DRAMPWROK
U5440
PM_ALL_GPU_PGOOD
PL32A
SMC_ONOFF_L
DCIN(16.5V)
IN
2S4P
VR5020 VOUT
(PAGE 45)
R7020
ADAPTER
(6 TO 8.4V)
VIN
PPBUS_G3H
F6905
6A FUSE
AC
Q5315
PP3V3_S5_AVREF_SMC
PP3V42_G3H
LT3470A
U6990
(PAGE 63)
SMC_PBUS_VSENSE
<E4LABEL>
BRANCH
<BRANCH>
PAGE
3 OF 132
SHEET
3 OF 101
PROTO:
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
Revision History
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
4 OF 132
SHEET
4 OF 101
BOM NAME
BOM OPTIONS
PART NUMBER
ALTERNATE FOR
PART NUMBER
138S0603
BOM OPTION
REF DES
COMMENTS:
138S0602
ALL
Murata alt to Samsung
157S0058
157S0055
ALL
Delta alt to TDK Magnetics
152S0896
152S0518
ALL
MAG LAYERS ALT TO CYNTEC
155S0457
155S0329
ALL
MAG LAYERS ALT TO MURATA
333S0506
333S0535
ALL
Hynix 900M alt to 1000M
516S0805
516S0806
ALL
Molex alt to Foxconn
152S1102
152S1088
ALL
Mag layer alt to Vishay
TABLE_BOMGROUP_ITEM
PCBA,2.0G,512SAM_VRAM,K18
TABLE_ALT_ITEM
K18_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,K18_PVT,EEEE_DCJ7
TABLE_BOMGROUP_ITEM
639-0953
PCBA,2.0G,512HYN_VRAM,K18
K18_COMMON,CPU_2_4GHZ,FB_256_HYNIX,K18_PVT,EEEE_DCJ8
639-0954
K18_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJ9
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
639-0955
TABLE_ALT_ITEM
K18_COMMON,CPU_2_53GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJC
TABLE_BOMGROUP_ITEM
639-0956
TABLE_ALT_ITEM
K18_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJD
TABLE_BOMGROUP_ITEM
639-0957
TABLE_ALT_ITEM
K18_COMMON,CPU_2_66GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJF
TABLE_BOMGROUP_ITEM
085-1404
TABLE_ALT_HEAD
TABLE_BOMGROUP_HEAD
639-0952
Alternate Parts
BOM Variants
BOM NUMBER
TABLE_ALT_ITEM
K18 DEVELOPMENT BOM
TABLE_ALT_ITEM
353S2805
353S2603
ALL
Fairchild wafer option
333S0542
333S0507
ALL
Samsung I die alt to H
128S0264
128S0257
ALL
Sanyo alt to Kemet
128S0303
128S0282
ALL
Panasonic alt to Sanyo
337S3808
337S3839
ALL
A02 alt to A03 GPU
128S0305
128S0294
ALL
6.3V alt to 11V Sanyo
TABLE_ALT_ITEM
TABLE_ALT_ITEM
K18 BOM GROUPS
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
TABLE_ALT_ITEM
BOM OPTIONS
TABLE_BOMGROUP_ITEM
K18_COMMON
TABLE_ALT_ITEM
ALTERNATE,COMMON,K18_COMMON1,K18_COMMON2,K18_PROGPARTS,USBHUB_2061,RDRV:8515A2,DCI
TABLE_BOMGROUP_ITEM
K18_COMMON1
BATT_3S,BCM5764M,GL137,CPUPOC_IMAX_40_50,CPUMEM_S0,SMC_EXCARD_NOT,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_3NONREM
K18_COMMON2
GMUXPLL_3V3,GPU_SS_INT,MIKEY,GPUVID_0P90V,DPMUX_EN_PLD,DP_CA_DET_EG_PLD,DP_ESD,VFRQ_SLPS3,SMC_OSC_YES,RAIL_MON
K18_PVT
BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM
K18_PROGPARTS
GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
FB_256_SAMSUNG
VRAM4,VRAM_256_SAMSUNG,FB1V55
FB_256_HYNIX
VRAM4,VRAM_256_HYNIX,FB1V55
FB_512_SAMSUNG
VRAM4,VRAM_512_SAMSUNG,FB1V35
FB_512_HYNIX
VRAM4,VRAM_512_HYNIX,FB1V35
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Bar Code Labels / EEE #s
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:DCJ7]
CRITICAL
EEEE_DCJ7
826-4393
[EEEE:DCJ8]
CRITICAL
EEEE_DCJ8
826-4393
[EEEE:DCJ9]
CRITICAL
EEEE_DCJ9
826-4393
[EEEE:DCJC]
CRITICAL
EEEE_DCJC
826-4393
[EEEE:DCJD]
CRITICAL
EEEE_DCJD
826-4393
[EEEE:DCJF]
CRITICAL
EEEE_DCJF
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
Module Parts
PART NUMBER
QTY
337S3848
ARD,SLBPE,PRQ,2.66G,35W,C2,3M,BGA
U1000
CRITICAL
CPU_2_66GHZ
337S3847
ARD,SLBPF,PRQ,2.53G,35W,C2,3M,BGA
U1000
CRITICAL
CPU_2_53GHZ
337S3846
ARD,SLBNA,PRQ,2.4G,35W,C2,4M,BGA
U1000
CRITICAL
CPU_2_4GHZ
337S3849
IC,PCH,IBEX PEAK-M,SLGZS,PRQ,B3,BGA
U1800
CRITICAL
337S3839
IC,GPU,NV GT216 LP++,969BGA,40NM,A03
U8000
CRITICAL
343S0493
IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN
U3900
CRITICAL
341S2731
IC,1MBIT,SPI FLASH,K17/K18
U3990
CRITICAL
338S0753
IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12
U4100
CRITICAL
338S0563
IC,SMC,HS8/2117,9MMX9MM,TLP
U4900
CRITICAL
341T0233
IC,SMC,K18
U4900
CRITICAL
SMC_PROG
335S0610
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U6100
CRITICAL
BOOTROM_BLANK
BOOTROM_PROG
341S2562
IC,EFI ROM,DEVELOPMENT,K18
U6100
CRITICAL
341S2384
IR,ENCORE II, CY7C63833-LFXC
U4800
CRITICAL
BCM5764M
SMC_BLANK
341S2616
IC,PSOC +W/USB,56PIN,MLF,K18
U5701
CRITICAL
TPAD_PROG
336S0025
IC,XP2-5,HF,CPLD,BLANK
U9600
CRITICAL
GMUX_5K_BLANK
341S2566
IC,CPLD,LATTICE,132CSBGA,K18
U9600
CRITICAL
GMUX_PROG
333S0507
CRITICAL
VRAM_256_SAMSUNG
333S0483
U8400,U8450,U8500,U8550
CRITICAL
VRAM_256_HYNIX
333S0533
IC,SGRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550
CRITICAL
VRAM_512_SAMSUNG
333S0535
IC,SDRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550
CRITICAL
VRAM_512_HYNIX
IC,SGRAM,GDDR3,16MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550
SYNC_MASTER=K17_REF
PAGE TITLE
IC,SDRAM,GDDR3,16MX32,900MHZ,136 FBGA
BOM Configuration
DRAWING NUMBER
Apple Inc.
R
Development BOM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
085-1404
K18 MLB DEVELOPMENT
DEVEL
CRITICAL
DEVEL_BOM

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
5 OF 132
SHEET
5 OF 101
Functional Test Points
USB PORTS
I1038 TRUE
J5650 (LEFT FAN CONN)

FUNC_TEST
70 72 86 88
PP5V_S0
TRUE
6 7 23 42 47
52 54 68 69
TRUE
TRUE
FAN_LT_PWM
FAN_LT_TACH
I1039 TRUE
3 TPs
per Fan
TRUE
I1103
I1102
43
I1104
43 99
I1105
43 99
I1107
I1106
52
I1108
I1042 TRUE
I1043 TRUE
I1044 TRUE
TRUE
52
J5660 (RIGHT FAN CONN)

TRUE
TRUE
TRUE
I1040 TRUE
PP5V_S3_RTUSB_A_F
USB2_LT1_N
USB2_LT1_P
GND
FAN_RT_PWM
FAN_RT_TACH
GND
52
PP5V_S3_RTUSB_B_F
USB_LT2_N
USB_LT2_P
GND
43
I1109
43 99
I1110
43 99
I1111
I1112
52
I1113
5 TPs
per Fan
I1114
I1115
I1117
J6780 (MIC CONN)
I1116
I1118
TRUE
TRUE
TRUE
I557
I558
I559
BI_MIC_N
BI_MIC_SHIELD
BI_MIC_P
62 63
I1119
J3401 & J3402 (AIRPORT/BT/CAMERA CONN) I1120

17 33 94
I1122
I1051 TRUE PCIE_AP_D2R_P
17 33 94
I1121
I1050 TRUE PCIE_AP_D2R_N
PCIE_AP_R2D_P
TRUE
33
94
I1123
I1053
33 94
I1124
I1052 TRUE PCIE_AP_R2D_N
I1125
I1054 TRUE PCIE_CLK100M_AP_CONN_P 33
99
33
PCIE_CLK100M_AP_CONN_N
I1127
I1056 TRUE
99
AP_CLKREQ_Q_L
33
TRUE
I1126
I1055
18 27 33
I1128
I1058 TRUE PCIE_WAKE_L
33
I1129
I1057 TRUE AP_RESET_CONN_L
PP3V3_WLAN
TRUE
33
I1130
I1059
I1061 TRUE PP5V_S3_ALSCAMERA_F 33
J6950 (BIL CABLE CONN)
I1060 TRUE SMBUS_SMC_A_S3_SDA 6 33 45 48 54 97
I1063 TRUE SMBUS_SMC_A_S3_SCL 6 33 45 48 54 97
USB_CAMERA_CONN_P
TRUE
33
93
I1062
I1150 TRUE PP5V_S3_IR_R
I1064 TRUE USB_CAMERA_CONN_N 33 93
I1149 TRUE SMC_LID_R
33 99
I1066 TRUE CONN_USB2_BT_P
I1151 TRUE IR_RX_OUT
33 99
I1065 TRUE CONN_USB2_BT_N
I1152 TRUE SYS_LED_ANODE
J3500 (SD CARD CONN)
GND
62 63
62 63
J6781 & J6782 (SPEAKERS CONN)

I989
I990
I992
I991
I994
I993
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
61 62 99
61 62 99
61 62 99
61 62 99
61 62 99
61 62 99
I1452
I1451
I996
I997
I998
I1000
I1001
I1002
I1004
I1003
I1005
I1007
I1006
I1009
I1008
I1010
I1011
I1012
I1014
I1013
I1015
I1016
I1017
I1018
I1019
I1020
I1022
I1021
PP3V3_SW_LCD
83
84 85 87 88 99
50 51 52 54 58 62 63 68 69 72
PP3V3_S0
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
PPVOUT_S0_LCDBKLT 73 80 83
2 TP needed
LVDS_DDC_CLK
83 84
LVDS_DDC_DATA
83 84
LVDS_CONN_A_DATA_P<0> 83 84 98
LVDS_CONN_A_DATA_N<0> 83 84 98
LVDS_CONN_A_CLK_F_P 83 98
LVDS_CONN_A_CLK_F_N 83 98
LVDS_CONN_B_DATA_P<0> 83 84 98
LVDS_CONN_B_DATA_N<0> 83 84 98
LVDS_CONN_B_CLK_F_P 83 98
LVDS_CONN_B_CLK_F_N 83 98
LED_RETURN_1
83 88
LED_RETURN_2
83 88
LED_RETURN_3
83 88
LED_RETURN_4
83 88
LED_RETURN_5
83 88
LED_RETURN_6
83 88
GND
4 TPs
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I1453
I1454
I1455
PP5V_SW_ODD
SMC_ODD_DETECT
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
GND
I1026 TRUE
I1025
I1028
I1027
I1029
TRUE
TRUE
TRUE
TRUE
TRUE
I1086 TRUE
I1273 TRUE
I1089 TRUE
I1088 TRUE
I1090 TRUE
I1464
I1098
I1097
I1095
I1096
I1094
3 TPs
I1099
42 56
I1100
42 45
I1101
42 93
42 93
I1031 TRUE
I1033 TRUE
I1035 TRUE
I1034 TRUE
42 93
42 93
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP18V5_S3
42
42 93
42 93
42 93
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
SPI_ALT_MISO
SPI_ALT_MOSI
SYS_LED_ANODE_R
TP_CPU_RSVD<65..62>
TP_CPU_RSVD<58..45>
TP_CPU_RSVD<43..32>
TP_CPU_RSVD<27..26>
TP_CPU_RSVD<24..15>
TP_CPU_RSVD<2..1>
17 45 47
18 45 47
18 27 45
45 47
TP_CPU_RSVD_NCTF<8..5>
45 47
18 6
45 46 47
18 6
45 46 47
18 6
45 48 54 97
45 48 54 97
64
TRUE
J5815 (KBD BACKLIGHT CONN)

KBDLED_ANODE
54
SMC_KDBLED_PRESENT_L 54
45 46 47
18 6
45 47
18 6
20 47 57
18 6
47
18 6
18 6
47
18 6
42
18 6
42
17 6
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
NC_CRT_IG_HSYNC
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_VSYNC
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_CLK
NC_LVDS_IG_CTRL_DATA
NC_PCH_LVDS_VBG
NC_LVDS_IG_CTRL_CLK
TRUE
MAKE_BASE=TRUE
TRUE NC_LVDS_IG_CTRL_DATA
MAKE_BASE=TRUE
NC_PCH_LVDS_VBG
TRUE
MAKE_BASE=TRUE
64
17 6
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
J6995 (BAT LED CONN)

PP3V42_G3H
TRUE SMBUS_SMC_BSA_SDA
TRUE SMBUS_SMC_BSA_SCL
TRUE SMC_BIL_BUTTON_L
I1142
GND
I1141
I1143
42 44
TRUE
GND
17 6
73
64 65 66
17 6
48 49 53
6 7 17 21 23 43
45 46 47
17 6
6 45 48 64 65 97
6 45 48 64 17 6
65 97
45 46 64
17 6
17 6
GND
17 6
TRUE
6 TPs
GND
17 6
17 6
17 6
19 6
19 6
TRUE PM_SLP_S3_L
18 31 45 73 85
TRUE PP0V75_S0_DDRVTT 7 28 30 31 67
6 54
TRUE PP18V5_S3
I603
TRUE PP1V05_S0
7 10 12 13 15 17 18 20 21 23 24
I604
25 26 40 70 73 86
PP1V05_S0GPU
TRUE
7 74 76 79 81 86
I605
PP1V05_S5
TRUE
7 17 71
I607
TRUE PP1V0_FW_FWPHY 7 39 40
I606
7 37 71 72
TRUE PP1V2_ENET
I610
TRUE PP1V2_S0
7 72 87
I612
TRUE PP1V5_S3
7 28 30 31 67 72
I611
PP1V5_S3RS0
TRUE
7 13 16 31 42 72 73 99
I613
PP1V8R1V55_S0GPU_ISNS
7 8 50 56 75 76 77 78
TRUE
I600
PP1V8R1V55_S0GPU_ISNS_R
7 50 86
TRUE
I625
TRUE PP1V8_GPUIFPX
7 72 81
I624
TRUE PP1V8_S0
7 12 16 21 23 24 58 71 72 87
I623
TRUE PP3V3_ENET
7 27 37 73
I620
TRUE PP3V3_FW_FWPHY
7 39 40 41
I621
83 84 85 87 88 99
50 51 52 54 58 62 63 68 69 72
TRUE PP3V3_S0
6 7 17 18 19 20 21 23 24 25 26
I618
27 28 30 34 37 40 42 46 47 48
73 80
PP3V3_S0GPU
TRUE
7 72 74 79 80 81 82 84
I617
TRUE PP3V3_S3
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
I615
55 72 73 87 101
TRUE PP3V3_S5
7 17 18 19 20 21 23 27 31 35 57
I616
66 71 72 73 83 85 99
TRUE PP3V3_S5_AVREF_SMC 45 46
I614
PP3V42_G3H
TRUE
6 7 17 21 23 43 45 46 47 48 49
I627
53 64 65 66 73
TRUE PP5V_S0
6 7 23 42 47 52 54 68 69 70 72
I626
86 88
TRUE PP5V_S3
7 31 33 42 43 44 46 54 56 58 61 66 67 72
I639
82 101
TRUE PP5V_S5
7 23 66 72
I638
PPBUS_G3H
TRUE
7 40 49 65 66 67 69 70 82 86 89
I637
TRUE PPDCIN_G3H
7 64 65
I636
TRUE PPVCORE_GPU
7 49 75 82
I709
PPVCORE_S0_CPU
7 12 15 49 68
I714 TRUE
PPVCORE_S0_GFX
TRUE
7 13 24 49 69
I1156
7 40 41
I1160 TRUE PPVP_FW
7 32 67
I1161 TRUE PPVTTDDR_S3
I640
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
NC_PCIE_PE7_D2RN
NC_PCIE_PE7_D2RP
NC_PCIE_PE7_R2D_CN
NC_PCIE_PE7_R2D_CP
NC_PCIE_PE8_D2RN
NC_PCIE_PE8_D2RP
NC_PCIE_PE8_R2D_CN
NC_PCIE_PE8_R2D_CP
18 6
18 6
6 18
18 6
6 18
18 6
6 18
6 18
19 6
19 6
19 6
19 6
TP_PCI_AD<31..0>
TP_PCI_C_BE_L<3..0>
NC_PCI_GNT3_L
NC_PCI_GNT2_L
NC_PCI_GNT1_L
NC_PCI_GNT0_L
NC_PCI_PAR
NC_PCI_RESET_L
NC_PCI_PME_L
NC_PCI_CLK33M_OUT3
NC_PCH_NV_RCOMP
TP_NV_DQ<15..0>
TP_NV_DQS<1..0>
TP_NV_CE_L<3..0>
19 6
19 6
19 6
17 6
17 6
17 6
17 6
20 6
20 6
20 6
20 6
53 6
17 6
17 6
17 6
17 6
17 6
17 6
17 6
17 6
17 6
17 6
NC_NV_ALE
NC_NV_CLE
NC_NV_RB_L
TP_NV_WR_RE_L<1..0>
TP_NV_WE_CK_L<1..0>
NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PSOC_P1_3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_SSD2_D2RN
NC_SATA_SSD2_D2RP
NC_SATA_SSD2_R2D_CN
NC_SATA_SSD2_R2D_CP
18 6
6 17
18 6
6 17
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
18 6
18 6
NC_PCI_AD<31..0> 19
NC_PCI_C_BE_L<3..0>
NC_PCI_GNT3_L
6 19
NC_PCI_GNT2_L
6 19
NC_PCI_GNT1_L
6 19
NC_PCI_GNT0_L
6 19
NC_PCI_PAR
6 19
NC_PCI_RESET_L 6 19
NC_PCI_PME_L
6 19
NC_PCI_CLK33M_OUT3 6
TRUE
18 6
MAKE_BASE=TRUE
19
TRUE
18 6
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
74 6
TRUE
80 79
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
80
TRUE
MAKE_BASE=TRUE
80 79
TRUE
80 79
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
19
TRUE
MAKE_BASE=TRUE
NC_PCH_NV_RCOMP
TRUE
6 19
MAKE_BASE=TRUE
6
NC_NV_DQ<15..0>
19
TRUE
MAKE_BASE=TRUE
93 18 8
NC_NV_DQS<1..0>
TRUE
19
MAKE_BASE=TRUE
93 18 8
NC_NV_CE_L<3..0>
TRUE
19 18 8
MAKE_BASE=TRUE
NC_NV_ALE
TRUE
6 19
MAKE_BASE=TRUE
NC_NV_CLE
TRUE
6 19
MAKE_BASE=TRUE
NC_NV_RB_L
TRUE
6 19 20
MAKE_BASE=TRUE
NC_NV_WR_RE_L<1..0> 19 20
TRUE
MAKE_BASE=TRUE
NC_NV_WE_CK_L<1..0> 19 20
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE4N 6 1720
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE4P 6 1720
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
20
NC_PSOC_P1_3
TRUE
6 53
MAKE_BASE=TRUE
20
NC_SATA_C_D2RN 6 17
TRUE
MAKE_BASE=TRUE
20
NC_SATA_C_D2RP 6 17
TRUE
MAKE_BASE=TRUE
20
NC_SATA_C_R2D_CN 6 17
TRUE
MAKE_BASE=TRUE
20
NC_SATA_C_R2D_CP 6 17
TRUE
MAKE_BASE=TRUE
20
NC_SATA_D_D2RN 6 17
TRUE
MAKE_BASE=TRUE
20
NC_SATA_D_D2RP 6 17
TRUE
MAKE_BASE=TRUE
20
NC_SATA_D_R2D_CN 6 17
TRUE
MAKE_BASE=TRUE
20
NC_SATA_D_R2D_CP 6 17
TRUE
20
MAKE_BASE=TRUE
NC_SATA_SSD2_D2RN 6 17
TRUE
20
MAKE_BASE=TRUE
NC_SATA_SSD2_D2RP 6 17
TRUE
20
MAKE_BASE=TRUE
NC_SATA_SSD2_R2D_CN 6 17
TRUE
20
MAKE_BASE=TRUE
NC_SATA_SSD2_R2D_CP 6 17
TRUE
MAKE_BASE=TRUE
20
TP_SMC_P41
NC_SMC_P41
TRUE
MAKE_BASE=TRUE
NC_PCIE_PE6_D2RN
NC_PCIE_PE6_D2RP
NC_PCIE_PE6_R2D_CN
NC_PCIE_PE6_R2D_CP
NC_PCIE_PE7_D2RN
NC_PCIE_PE7_D2RP
NC_PCIE_PE7_R2D_CN
NC_PCIE_PE7_R2D_CP
NC_PCIE_PE8_D2RN
NC_PCIE_PE8_D2RP
NC_PCIE_PE8_R2D_CN
NC_PCIE_PE8_R2D_CP
I767
I766
I769
I768
I770
I772
9
I771
I774
NC_DP_IG_D_HPD
NC_DP_IG_D_CTRL_CLK
NC_DP_IG_D_CTRL_DATA
TP_DP_IG_D_MLP<3..0>
TP_DP_IG_D_MLN<3..0>
NC_DP_IG_D_AUXP
NC_DP_IG_D_AUXN
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_STALLN
NC_SDVO_STALLP
NC_SDVO_INTN
NC_SDVO_INTP
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
I1442
6 18
18
6 18
6 18
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
6 18
6 18
NC_SDVO_STALLN
NC_SDVO_STALLP
6 18
6 18
NC_SDVO_INTN
NC_SDVO_INTP
6 18
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PCH_VSS_NCTF<1> 20 94
PCH_VSS_NCTF<7>
6 17
I1443
I1444
I1445
I1446
I1447
I1448
I1449
I1450
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
6 20
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>
20 94
20 94
6 20 94
6 20 94
20 94
20 94
20 94
20 94
6 17
SYNC_MASTER=MASTER
6 17
SYNC_DATE=MASTER
PAGE TITLE
6 17
Functional / ICT Test
6 17
DRAWING NUMBER
6 17
Apple Inc.
6 17
6 17
17 6
6 17
17 6
17 6
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
6 17
6 17
17 6
6 17
17 6
NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP
NC_CLINK_CLK 6 17
TRUE
MAKE_BASE=TRUE
NC_CLINK_DATA 6 17
TRUE
MAKE_BASE=TRUE
NC_CLINK_RESET_L 6
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
6 17

6 17
6 17

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
17
<BRANCH>
PAGE
7 OF 132
SHEET
6 OF 101
6 18
NC_PCH_SST
TRUE
MAKE_BASE=TRUE
NC_PCH_NC1
TRUE
MAKE_BASE=TRUE
NC_PCH_NC2
TRUE
MAKE_BASE=TRUE
NC_PCH_NC3
TRUE
MAKE_BASE=TRUE
NC_PCH_NC4
TRUE
MAKE_BASE=TRUE
NC_PCH_NC5
TRUE
MAKE_BASE=TRUE
NC_PCH_TP19
TRUE
MAKE_BASE=TRUE
NC_PCH_TP18
TRUE
MAKE_BASE=TRUE
NC_PCH_TP17
TRUE
MAKE_BASE=TRUE
NC_PCH_TP16
TRUE
MAKE_BASE=TRUE
NC_PCH_TP15
TRUE
MAKE_BASE=TRUE
NC_PCH_TP14
TRUE
MAKE_BASE=TRUE
NC_PCH_TP13
TRUE
MAKE_BASE=TRUE
NC_PCH_TP12
TRUE
MAKE_BASE=TRUE
NC_PCH_TP11
TRUE
MAKE_BASE=TRUE
NC_PCH_TP10
TRUE
MAKE_BASE=TRUE
NC_PCH_TP9
TRUE
MAKE_BASE=TRUE
NC_PCH_TP8
TRUE
MAKE_BASE=TRUE
NC_PCH_TP7
TRUE
MAKE_BASE=TRUE
NC_PCH_TP6
TRUE
MAKE_BASE=TRUE
NC_PCH_TP5
TRUE
MAKE_BASE=TRUE
NC_PCH_TP4
TRUE
MAKE_BASE=TRUE
NC_PCH_TP3
TRUE
MAKE_BASE=TRUE
NC_PCH_TP2
TRUE
MAKE_BASE=TRUE
NC_PCH_TP1
TRUE
MAKE_BASE=TRUE
I1441
6 18
18
NC_SMC_BS_ALRT_L
TRUE
MAKE_BASE=TRUE
6 17
6 18
NC_PCH_SST
NC_PCH_NC1
NC_PCH_NC2
NC_PCH_NC3
NC_PCH_NC4
NC_PCH_NC5
NC_PCH_TP19
NC_PCH_TP18
NC_PCH_TP17
NC_PCH_TP16
NC_PCH_TP15
NC_PCH_TP14
NC_PCH_TP13
NC_PCH_TP12
NC_PCH_TP11
NC_PCH_TP10
NC_PCH_TP9
NC_PCH_TP8
NC_PCH_TP7
NC_PCH_TP6
NC_PCH_TP5
NC_PCH_TP4
NC_PCH_TP3
NC_PCH_TP2
NC_PCH_TP1
6 17
6 18
NC_SMC_BS_ALRT_L
I1440
6 18
NC_LVDS_EG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKN
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
I1439
6 18
18
NC_LVDS_EG_BKL_PWM
TP_LVDS_IG_B_CLKN
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_BKL_PWM
6 17
6 18
18
NC_GPU_BUFRST_L 6 74
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE<0>
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE<1>
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_D<9..0>
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_DE
TRUE
MAKE_BASE=TRUE
I1437
6 18
NC_GPU_BUFRST_L
TP_GPU_GSTATE<0>
TP_GPU_GSTATE<1>
TP_GPU_MIOA_D<9..0>
TP_GPU_MIOA_DE
I1436
NC_FW643_AVREG 6 39
TRUE
MAKE_BASE=TRUE
NC_FW643_TDI
TRUE
6 39
MAKE_BASE=TRUE
NC_DP_IG_C_HPD
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLP<3..0>
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLN<3..0>
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXP
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXN
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_HPD
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLP<3..0>
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLN<3..0>
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXP
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXN
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_HPD
NC_DP_IG_C_CTRL_CLK
TP_DP_IG_C_MLP<3..0>
TP_DP_IG_C_MLN<3..0>
NC_DP_IG_C_AUXP
NC_DP_IG_C_AUXN
I1438
NC_PCIE_PE5_D2RN
NC_PCIE_PE5_D2RP
NC_PCIE_PE5_R2D_CN
NC_PCIE_PE5_R2D_CP
I765
6 17
18 6
NC NO_TESTs
NO_TEST
NC_PCIE_PE6_D2RN
NC_PCIE_PE6_D2RP
NC_PCIE_PE6_R2D_CN
NC_PCIE_PE6_R2D_CP
6 18
I764
6 18
NCNO_TEST
NO_TESTs
46 45
17 6
FUNC_TEST
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
64 65
17 6
18
42 46
17 6
GND
18 6
18 6
17 6
19 6
NC_PCIE_PE5_D2RN
NC_PCIE_PE5_D2RP
NC_PCIE_PE5_R2D_CN
NC_PCIE_PE5_R2D_CP
18 6
6 18
18 6
47
17 6
6 45 48 64 65 97
17 6
6
17 6
18 6
6 18
NC_CRT_IG_DDC_CLK 6
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_DDC_DATA
TRUE
MAKE_BASE=TRUE
47
64
6 45 48 64 65 97
6 18
NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA
43 45 46 47
GND
I1140 TRUE
I1146 TRUE
NC_CRT_IG_BLUE
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_GREEN
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_RED
TRUE
MAKE_BASE=TRUE
45 46 47
19 6
6 54
39 6
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
I763
NC_SMC_FAN_3_TACH 45 46
NC_SMC_FAN_3_CTL 45 46
NC_SMC_FAN_2_TACH 45 46
NC_SMC_FAN_2_CTL 45 46
NC_FW2_TPBP
39 41
NC_FW2_TPBN
39 41
NC_FW2_TPBIAS
39 41
NC_FW2_TPAP
39 41
NC_FW2_TPAN
39 41
NC_FW0_TPBP
39 41 96
NC_FW0_TPBN
39 41 96
NC_FW0_TPAP
39 41 96
NC_ESTARLDO_EN 45 46
NC_ALS_GAIN
45 46
NC_FW643_AVREG
NC_FW643_TDI
39 6
NO_TEST
43 45 46 47
POWER RAILS
2 TPs
NC_TP_CPU_RSVD<65..62>
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_TP_CPU_RSVD<43..32> 9
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_TP_CPU_RSVD_NCTF<8..5>
TRUE
MAKE_BASE=TRUE
NC NO_TESTs
45 46 53
45 46 47 65
FUNC_TEST
34 37
42 93
I1145 TRUE
SMC_TX_L
I762
NC NO_TESTs
NO_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I761
18 45 47
34
34 37
17 6
TRUE
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_TRST_L
I1297
NO_TEST
19 6
17 6
TRUE
LPC_PWRDWN_L
LPC_SERIRQ
PM_CLKRUN_L
PM_SYSRST_L
SMC_MD1
SMC_NMI
SMC_ONOFF_L
SMC_RESET_L
SMC_RX_L
34
Z2_CS_L
53 54
Z2_DEBUG3
53 54
Z2_MISO
53 54
Z2_BOOST_EN
54
Z2_SCLK
53 54
Z2_CLKIN
53 54
Z2_KEY_ACT_L
53 54
Z2_RESET
53 54
PSOC_F_CS_L
53 54
PICKB_L
53 54
PSOC_MISO
53 54
PSOC_MOSI
53 54
PSOC_SCLK
53 54
SMBUS_SMC_A_S3_SCL 6 33
SMBUS_SMC_A_S3_SDA 6 33
J6950 (MAIN BATT CONN)

I1134 TRUE PPVBAT_G3H_CONN
I1136 TRUE SMBUS_SMC_BSA_SCL
I1135 TRUE SMBUS_SMC_BSA_SDA
I1137 TRUE NC_SMC_BS_ALRT_L
GND
TRUE
TRUE
I732 TRUE
I731 TRUE
I734 TRUE
I733 TRUE
I735 TRUE
TRUE
I737 TRUE
I739 TRUE
I738 TRUE
I740 TRUE
I741 TRUE
I742 TRUE
I743 TRUE
I744 TRUE
I751 TRUE
I752 TRUE
TRUE
I760
I756 TRUE
I1292 TRUE
I1288 TRUE
I730
CPU NO_TESTs
34
GND
J6900 (DC POWER CONN)

I1131 TRUE ADAPTER_SENSE
I1132 TRUE PP18V5_DCIN_FUSE
J4501 (SATA HDD CONN)

PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
SD_D<7..0>
SD_CMD
SD_CLK
SD_CD_L
SD_WP
J5800 (IPD FLEX CONN)
5 TPs
I1032 TRUE
ICT Test Points
I602
I1093
J4500 (SATA ODD CONN)
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I1092
I1024 TRUE
4
FUNC_TEST
88
I720 TRUE BKLT_EN
I722 TRUE TP_ISSP_SCLK_P1_1 8 53
I724 TRUE TP_ISSP_SDATA_P1_0 8 53
87 88
I723 TRUE LCD_BKLT_PWM
20 47
I725 TRUE LPCPLUS_GPIO
I726 TRUE LPCPLUS_RESET_L 27 47 87 94
LPC_AD<0..3>
17 45 47 87 94
I727 TRUE
LPC_CLK33M_LPCPLUS 27 47 94
I729 TRUE
LPC_FRAME_L
17 45 47 87 94
I728 TRUE
TRUE
J9000 (LVDS CONN)

I995
J5713 (KEY BOARD CONN) 73 87 101

35 36 48 50
TRUE PP3V3_S3
6 7 8 17 20
31 32 33 34
53 54 55 72
TRUE PP3V42_G3H
6
7 17 21 23
43 45 46 47
5348 49 53 64
TRUE WS_KBD1
65 66 73
53
TRUE WS_KBD2
TRUE WS_KBD3
53
53
TRUE WS_KBD4
TRUE WS_KBD5
53
53
TRUE WS_KBD6
TRUE WS_KBD7
53
TRUE WS_KBD8
53
TRUE WS_KBD9
53
53
TRUE WS_KBD10
53
TRUE WS_KBD11
WS_KBD12
TRUE
53
53
TRUE WS_KBD13
53
TRUE WS_KBD14
53
TRUE WS_KBD15_CAP
53
TRUE WS_KBD16_NUM
TRUE WS_KBD17
53
TRUE WS_KBD18
53
WS_KBD19
TRUE
53
TRUE WS_KBD20
53
53
TRUE WS_KBD21
53
TRUE WS_KBD22
WS_KBD23
53
TRUE
TRUE WS_KBD_ONOFF_L
53
TRUE WS_LEFT_SHIFT_KBD 53
TRUE WS_LEFT_OPTION_KBD 53
TRUE WS_CONTROL_KBD
53
"G3Hot" (Always-Present) Rails

89 86 82
66 65 49 40 7 6
70 69 67
PPBUS_G3H
PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
D
68 49 7
PPBUS_CPU_IMVP_ISNS
PPDCIN_G3H
PPDCIN_G3H
PPDCIN_G3H
73
53 49 48
43 23 21 17 7 6
47 46 45
66 65 64
PP3V42_G3H
PP3V42_G3H
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM 53
VOLTAGE=3.42V
MAKE_BASE=TRUE
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V3_S5
6 7 40 49 65 66 67 69 70 82 86
89
6 7 40 49 65 66 67 69 70 82 86
89
7 49 68
7 49 68
6 7 64 65
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31
57 66 71 72 73 83 85 99
99
6 7 17 18 19 20 21 23 27 31
57 66 71 72 73 83
83 85 99
6 7 17 18 19 20 21 23
27 31 35 57 66 71 72 73
50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
PP3V3_S3
PP5V_S5
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
PP5V_S5
PP5V_S5
PP5V_S5
72 67 66 61 58
42 33 31 7 6
56 54 46 44 43
101 82
PP5V_S3
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 23 66 72
6 7 23 66 72
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
88 86 72
47 42 23 7 6
70 69 68 54 52
PP5V_S0
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33
72 82 101
6 7 31 33
72 82 101
6 7 31 33
72 82 101
6 7 31 33
72 82 101
42 43 44 46 54 56 58 61 66 67
42 43 44 46 54 56 58 61 66 67
42 43 44 46 54 56 58 61 66 67
42 43 44 46 54 56 58 61 66 67
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
PP5V_S0
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
6 7 23 42 47 52 54 68 69 70 72
86 88
PP1V0_FW_FWPHY
6 7 28 30 31 67 72
84 82 81 80 79 74 72 7 6
6 7 28 30 31 67 72
PP3V3_S0GPU
20
87
20
50
31 32
101
53
31 32
67 32
6 7 8 17 20 31 32
55 72 73 87 101
33 34 35 36 48 50 53 54
54 55 72 73 87 101
33 34
7 6
33 34 35 36 48 50 53 54
PPVTTDDR_S3
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
81 72 7 6
6 7 13 16 31 42 72 73 99
PP1V8_GPUIFPX
PP3V3_S0
PP0V75_S0_DDRVTT
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
6
27 28
7 17 18 19 20 21 23 24 25 26
30 34 37 40 42 46 47
48 50 51 52 54 58 62
63 68 69
87 72 7 6
72 73 80
83 84 85 87 88 99
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
6
27 28
7 17 18 19 20 21 23 24 25 26
8830 34 37 40 42 46 47 48 50
6351 52 54 58 62 63 68 69 72
4273 80 83 84 85 87 88 99
28
6 7 17 18 19 20 21 23
24 25 26 27 71 17 7 6
30 34 37 40
46 47 48 50 51 52 54 58 62 69
68 69 72 73 80 83 84 85 87
996 7 17 18 19 20 21 23 24 47
25
3026 27 28 30 34 37 40 42 46
1748 50 51 52 54 58 62 63 68
6 72 73 80 83 84 85 87 88 99
7
18 19 20 21 23 24 25 26 27 28
34 37 40 42 46 47 48 50 51
52 54 58 62 63 68 69 72 73
80 83 84 85 87 88 99
PP1V2_S0
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PPVTTDDR_S3
6 7 32 67
86 50 7 6
PP0V75_S0_DDRVTT
6 7 86 81 79 76 74 7 6
28 30 31 67
6 7 28 30 31 67
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
PP1V05_S0GPU
6 7 72 87
6 7 72 87
PP1V05_S5
6 7 17 71 82 75 49 7 6
6 7 8 50 56 75 76
77 78
6 7 8 50 56 75 76
77 78
6 7 8 50 56 75 76
77 78
6 7 8 50 56 75 76
77 78
6 7 50 86
6 7 50 86
PP1V05_S0GPU
6 7 74 76 79 81 86
PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PP1V2_S0
6 7 8 50 56 75 76
77 78
VOLTAGE=1.05V
MAKE_BASE=TRUE
6 7 28 30 31 67
PPVCORE_GPU
6 7 74 76 79 81 86
6 7 74 76 79 81 86
6 7 74 76 79 81 86
6 7 74 76 79 81 86
6 7 74 76 79 81 86
6 7 74 76 79 81 86
6 7 74 76 79 81 86
6 7 74 76 79 81 86
6 7 74 76 79 81 86
PPVCORE_GPU
6 7 49 75 82
VOLTAGE=1.0V
MAKE_BASE=TRUE
PPVCORE_GPU
6 7 17 71
6 7 49 75 82
PP1V05_S0
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
VOLTAGE=1.05V
MAKE_BASE=TRUE
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
6
27 28
197 17 18 19 20 21 23 24 25 26
1730 34 37 40 42 46 47 48 50
6 51 52 54 58 62 63 68 69 72
7 73 80 83 84 85 87 88 99
18
20 21 23 24 25 26 27 28 30
34 37 40 42 46 47 48 50 51
52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
6
27 28
197 17 18 19 20 21 23 24 25 26
1730 34 37 40 42 46 47 48 50
6 51 52 54 58 62 63 68 69 72
7 73 80 83 84 85 87 88 99
18
20 21 23 24 25 26 27 28 30
34 37 40 42 46 47 48 50 51
52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
27 28
6
197 17 18 19 20 21 23 24 25 26
1730 34 37 40 42 46 47 48 50
6 51 52 54 58 62 63 68 69 72
7 73 80 83 84 85 87 88 99
18
20 21 23 24 25 26 27 28 30
34 37 40 42 46 47 48 50 51
52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
73 37 27 7 6
50 51 52
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
54 58 62 63 68 69 72 73 80 83
84 85 87 88 99
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
58 62 63 68 69 72 73 80 83 84
28 30 34 37 40 42 46 47 48 50
6 7 17 18 19 20 21 23 24
25 26 27
72 71 37 7 6
51 52 54
85 87 88 99
26 40 70 73 86
6 7 10 12 13 15 17
18 20 21 23 24 25
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
Chipset "VCore" Rails
PPVCORE_S0_CPU
PPVCORE_S0_CPU
6 7 12 15 49
68
VOLTAGE=1.25V
MAKE_BASE=TRUE
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
PPVCORE_S0_CPU
PPVCORE_S0_GFX
6 7 12 15 49
68
PPVCORE_S0_GFX
69 49 24 13 7 6
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7 13 24 49
69
VOLTAGE=1.05V
MAKE_BASE=TRUE
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
PPVCORE_S0_GFX
6 7 10 12 13 15 17
18 20 21 16 12 7
23 24 25
266 40 70 73 86
7
1010 12 13 15 17 18 20 21 23
6 24 25 26 40 70 73 86
26 40
7
12 13 15 17 18 20 21 23 24 25
706 73 86
7
1010 12
6 13 15
16 12 7
7 17 18 20 21 23 24 25 26
1240 70 73 86
13
40 70 73 86
15 17 18 20 21 23 24 25 26
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
PPVCORE_S0_CPU_VCAP0
6 7 13 24 49
69
7 12 16
VOLTAGE=1.25V
MAKE_BASE=TRUE
VOLTAGE=1.25V
MAKE_BASE=TRUE
24 13 7
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
VOLTAGE=1.25V
MAKE_BASE=TRUE
7 12 16
7 13 24
ENET Rails
PP3V3_ENET
PP3V3_ENET
6 7 27 37 73
VOLTAGE=3.3V
MAKE_BASE=TRUE
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
PP3V3_ENET
6 7 27 37 73
PP1V2_ENET
6 7 37 71 72
Power Aliases
DRAWING NUMBER
PP1V2_ENET
6 7 28 30 31 67
PP1V05_S5
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
27 28
6
7 17 18 19 20 21 23 24 25 26
30 34 37 40 42 46 47 48 50
8051 52 54 58 62 63 68 69 72
5073 80 83 84 85 87 88 99
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
51 52 54 58 62 63 68 69 72 73
83 84 85 87 88 99
6 7 72 81
VOLTAGE=1.05V
MAKE_BASE=TRUE
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
6 7 72 81
VOLTAGE=1.8V
MAKE_BASE=TRUE
6 7 13 16 31 42 72 73 99
PP1V2_S0
PP1V05_S0
? mA
6 7 72 74 79 80 81 82 84
VOLTAGE=1.8V
MAKE_BASE=TRUE
VOLTAGE=1.2V
MAKE_BASE=TRUE
PP1V05_S5
6 7 72 74 79 80 81 82 84
PP1V8_GPUIFPX
6 7 13 16 31 42 72 73 99
78 77 76 75 56 50 8 7 6
6 7 13 16 31 42 72 73 99
PP0V75_S0_DDRVTT
PP0V75_S0_DDRVTT
PP0V75_S0_DDRVTT
73 80 83 84 85 87 88 99
50 51 52 54 58 62 63 68 69 72
27 28 30 34 37 40 42 46 47 48
6 7 17 18 19 20 21 23 24 25 26
6 7 72 74 79 80 81 82 84
6 7 72 74 79 80 81
82 84
PP1V8_GPUIFPX
MIN_LINE_WIDTH=2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
6 7 72 74 79 80 81 82 84
6 7 13 16 31 42 72 73 99
VOLTAGE=0.75V
MAKE_BASE=TRUE
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 72 74 79 80 81 82 84
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
6 7 28 30 31 67 72
VOLTAGE=1.2V
MAKE_BASE=TRUE
Apple Inc.
6 7 37 71 72
6 7 37 71 72

SIZE
<SCH_NUM> D
REVISION
PP1V2_ENET
PP1V2_ENET
PP3V3_S0GPU
6 7 28 30 31 67 72
PP1V5_S3RS0
6 7 39 40
"GPU" Rails
6 7 28 30 31 67 72
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
17
73
17
48
6 7 39 40
VOLTAGE=1.0V
MAKE_BASE=TRUE
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 8
55 72
6 7 8
35 36
6 7 39 40 41
PP1V0_FW_FWPHY
PP1V0_FW_FWPHY
6 7 28 30 31 67 72
PP1V5_S3RS0
PP1V5_S3RS0
PP1V5_S3RS0
PP1V5_S3RS0
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 39 40 41
6 7 12 16 21 23 24 58 71 72 87
VOLTAGE=1.5V
MAKE_BASE=TRUE
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 39 40 41
PP3V3_FW_FWPHY
PP3V3_FW_FWPHY
6 7 12 16 21 23 24 58 71 72 87
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
VOLTAGE=3.3V
MAKE_BASE=TRUE
6 7 23 66 72
VOLTAGE=5V
MAKE_BASE=TRUE
PP3V3_S0
6 7 12 16 21 23 24 58 71 72 87
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3RS0
6 7 40 41
VOLTAGE=3.3V
MAKE_BASE=TRUE
6 7 12 16 21 23 24 58 71 72 87
PP1V5_S3
99 73 72 42 31 16 13 7 6
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 40 41
PP3V3_FW_FWPHY
PP3V3_FW_FWPHY
VOLTAGE=1.5V
MAKE_BASE=TRUE
6 7 23 66 72
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
6 7 12 16 21 23 24 58
71 72 87 41 40 39 7 6
6 7 12 16 21 23 24 58 71 72 87
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
PPVP_FW
PPVP_FW
6 7 12 16 21 23 24 58 71 72 87
40 39 7 6
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 40 41
VOLTAGE=12.8V
MAKE_BASE=TRUE
35
85
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
MIN_LINE_WIDTH=0.50MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
PPVP_FW
PPVP_FW
6 7 12 16 21 23 24 58 71 72 87
35
PP1V5_S3
67 31 30 28 7 6
PP5V_S5
VOLTAGE=5V
MAKE_BASE=TRUE
35
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
PP3V3_S3
PP1V8_S0
VOLTAGE=1.8V
MAKE_BASE=TRUE
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 64 65
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
2
"FW" (FireWire) Rails
41 40 7 6
PP1V8_S0
2A max supply
87 72 71 58 24 23 21
73 83 85 99 16 12 7 6
6 7 17 18 19 20 21 23
27 31 35 57 66 71 72
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
6 7 40 49 65 66 67 69 70 82 86
89
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
5V Rails
72 66 23 7 6
1.8V/1.5V/1.2V/1.05V Rails
VOLTAGE=3.3V
MAKE_BASE=TRUE
6 7 40 49 65 66 67 69 70 82 86
89
PPBUS_CPU_IMVP_ISNS
VOLTAGE=18.5V
MAKE_BASE=TRUE
PP3V3_S5
6 7 40 49 65 66 67 69 70 82 86
89
6 7 40 49 65 66 67 69 70 82 86
89
PPBUS_CPU_IMVP_ISNS
65 64 7 6
99 85 83
20 19 18 17 7 6
73 72 71 66 57 35 31 27 23 21
6 7 40 49 65 66 67 69 70 82 86
89
6 7 40 49 65 66 67 69 70 82 86
89
6 7 40 49 65 66 67 69 70 82 86
89
VOLTAGE=12.8V
MAKE_BASE=TRUE
5
3.3V Rails
<E4LABEL>
BRANCH
<BRANCH>
PAGE
8 OF 132
SHEET
7 OF 101
ZT0984 Thermal Module Holes

ZT0981
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
1
Fan Holes
ZT0930
3
CPU signals
91 15 12
ZT0985
ZT0988
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
91 13
CPU_VID<0..6>
CPUIMVP_VID<0..6>
68
GFXIMVP_VID<0..6>
69
91 12 8
MAKE_BASE=TRUE
GFX_VID<0..6>
TP_CPU_VTT_SELECT
TP_CPU_VTT_SELECT
8 12 91
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEMVTT_EN
67 31 8
MEMVTT_EN
8 31 67
MAKE_BASE=TRUE
ZT0980
STDOFF-4.5OD.98H-1.1-3.48-TH
1
ZT0986
ZT0989
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
GPU signals
91 74 9
PEG_D2R_P<15..0>
91 74
PEG_D2R_N<15..0>
ZT0991
STDOFF-4.5OD.98H-1.1-3.48-TH
=PEG_D2R_N<0..15>
MAKE_BASE=TRUE
PEG_R2D_C_P<15..0>
91 74
PEG_R2D_C_N<15..0>
Frame Holes
ZT0915
=PEG_D2R_P<0..15>
MAKE_BASE=TRUE
91 74 9
=PEG_R2D_C_P<0..15>
MAKE_BASE=TRUE
=PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
** PEG LANES REVERSED. ARD STRAP REQD. **
3R2P5
1
GND
GMUX ALIASES
ZT0940
Left Speaker Holes
3R2P5
PM_ALL_GPU_PGOOD
87 86 82 73 8
ZT0934
STDOFF-4.0OD3.0H-TH
ZT0950
TH
87 8
8 73 82 86 87
91 25 9
CPU_CFG<3>
TP_LVDS_MUX_SEL_EG
ZT0935
ZT0960
STDOFF-4.0OD3.0H-TH
3R2P5
87 74 8
TP_LVDS_MUX_SEL_EG
EG_RESET_L
MAKE_BASE=TRUE
LVDS_IG_BKL_ON
87 18 8
LVDS_IG_BKL_ON
3.0K 2
8 87
8 74 87
TP_LVDS_IG_B_CLKN
18 8 6
LCD_BKLT_EN
LVDS_IG_PANEL_PWR
LCD_BKLT_EN
TP_LVDS_IG_B_CLKP
6 8 18 93
TP_LVDS_IG_B_CLKN
6 8 18 93
MAKE_BASE=TRUE
TP_LVDS_IG_BKL_PWM
TP_LVDS_IG_BKL_PWM
93 84
3R2P5
DP_IG_ML_P<3..0>
NC_GPU_XTALOUT
NC_GPU_XTALOUT
93 18 8
NC_LVDS_IG_A_DATAP<3>
93 18 8
NC_LVDS_IG_A_DATAN<3>
DP_IG_B_ML_P<3..0>
18
DP_IG_B_ML_N<3..0>
18
93 18 8
8 18 84
93
93 18 8
6 8 18
MAKE_BASE=TRUE
8 79
MAKE_BASE=TRUE NO_TEST=TRUE
8 18 87
8 87 89
MAKE_BASE=TRUE
ZT0990
93 18 8 6
8 18 87
MAKE_BASE=TRUE
89 87 8
TP_LVDS_IG_B_CLKP
79 8
LVDS_IG_PANEL_PWR
87 18 8
93 18 8 6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GND
EG_RESET_L
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
1
GND
SL-3.1X2.7-6CIR-NSP
R0902
PM_ALL_GPU_PGOOD
MAKE_BASE=TRUE
GND
8 18 93
8 18 93
NC_LVDS_IG_B_DATAP<3>
8 18 93
NC_LVDS_IG_B_DATAN<3>
8 18 93
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
GND
93 84
87 74 8
PEX_CLKREQ_L
PEX_CLKREQ_L
MAKE_BASE=TRUE
87 17 8
PEG_CLKREQ_L
PEG_CLKREQ_L
73 71 8
PM_ENET_EN
93 84 18 8
DP_IG_AUX_CH_N
MAKE_BASE=TRUE
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
8 18 84 93
DP_IG_DDC_CLK
8 18 80 84
MAKE_BASE=TRUE
PM_ENET_EN
MAKE_BASE=TRUE
8 71 73
84 80 18 8
84 80 18 8
84 18 8
DP_IG_DDC_CLK
MAKE_BASE=TRUE
DP_IG_DDC_DATA
SH0902
SM
ZT0953
SH0900
2.0DIA-TALL-EMI-MLB-M97-M98
40 20 8
FW_PLUG_DET_L
40 39 8
FW643_WAKE_L
8 18 80 84
DP_IG_HPD
8 18 84
MAKE_BASE=TRUE
DP_IG_HPD
SH0903
SM
SH0916
SM
NC_USB_HUB2_OCS3
17 8
NC_SATA_EXTA_D2R_N
17 8
NC_SATA_EXTA_D2R_P
17 8
NC_SATA_EXTA_R2D_C_N
17 8
NC_SATA_EXTA_R2D_C_P
17 8
NC_PCIE_EXCARD_D2R_N
17 8
NC_PCIE_EXCARD_D2R_P
17 8
NC_PCIE_EXCARD_R2D_C_N
17 8
NC_PCIE_EXCARD_R2D_C_P
94 17 8
94 17 8
Short (IO Row) EMI pogo pins

SH0911
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0910
SM
SM
1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
8 17
USB_SDCARD_P
NC_SATA_EXTA_D2R_P
8 17
NC_SATA_EXTA_R2D_C_N
8 17
NC_SATA_EXTA_R2D_C_P
8 17
8 17
8 17
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
USB_SDCARD_N
93 36 34 8
R09031
8 34 36 93
8 17
8 17
TP_ISSP_SCLK_P1_1
TP_ISSP_SDATA_P1_0
R0904
10K
5%
1/16W
MF-LF
2 402
USB_EXTC_N
USB_EXTC_P
35 93
35 93
R0900
8 17 94
78 77 76 75 56 50 7 6
PP1V8R1V55_S0GPU_ISNS1 10
TP_ISSP_SCLK_P1_1
6 8 53
TP_ISSP_SDATA_P1_0
6 8 53
GPU_FB_A_VREF_DIV
MAKE_BASE=TRUE
1%
1/16W
MF-LF
402
8 17 94
NO_TEST=TRUE
53 8 6
5%
1/16W
MF-LF
402 2
GPU_FB_A_VREF_DIV
8 32 77
8 32 77
R0901
MAKE_BASE=TRUE
10
1%
1/16W
MF-LF
402
MAKE_BASE=TRUE
GND
GND
GND
GND
USB_SDCARD_N
PP3V3_S3
NO_TEST=TRUE
53 8 6
8 34 36 93
MAKE_BASE=TRUE
10K
NC_PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_P
SM
SM
NC_SATA_EXTA_D2R_N
NC_PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARD_N
SH0913
8 45
MAKE_BASE=TRUE
SH0912
TP_SMC_EXCARD_PWR_EN
8 36
USB_SDCARD_P
MAKE_BASE=TRUE
93 36 34 8
54 53 50 48 36 35 34 33 32 31 20 17 7 6
101 87 73 72 55
SM
8 39 40
8 35
NC_USB_HUB2_OCS3
MAKE_BASE=TRUE
45 8
SH0904
8 20 40
FW643_WAKE_L
MAKE_BASE=TRUE
SM
1
FW_PLUG_DET_L
NC_USB_HUB1_OCS4
MAKE_BASE=TRUE
36 8
MAKE_BASE=TRUE
4.0OD1.85H-M1.6X0.35
NO_TEST=TRUE
NC_USB_HUB1_OCS4
35 8
DP_IG_DDC_DATA
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
4.0OD1.85H-M1.6X0.35
Tall EMI pogo pins
DP_IG_AUX_CH_P
MAKE_BASE=TRUE
8 17 87
Keyboard / IPD Conn Protect

ZT0952
DP_IG_ML_N<3..0>
MAKE_BASE=TRUE
8 74 87
93 84 18 8
MAKE_BASE=TRUE
ZT0987
STDOFF-4.5OD.98H-1.1-3.48-TH
GPU_FB_B_VREF_DIV
MAKE_BASE=TRUE
8 32 78
GPU_FB_B_VREF_DIV
8 32 78
GND
SH0917
SH0901
SM
SM
Digital Ground
SH0914
GND
VOLTAGE=0V
SM
1
GND_CHASSIS_AUDIO_JACK
62
SYNC_MASTER=K17_REF
PAGE TITLE
Signal Aliases
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
9 OF 132
SHEET
8 OF 101
OMIT
OMIT
U1000
U1000
IN
91 18
IN
91 18
IN
91 18
91 18
91 18
IN
IN
91 18
IN
91 18
IN
OUT
91 18
OUT
91 18
OUT
91 18
OUT
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
91 18
OUT
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
91 18
OUT
DMI_RX0*
DMI_RX1*
DMI_RX2*
DMI_RX3*
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
F9
J6
K9
J2
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
H17
K15
J13
F10
G17
M15
G13
J11
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
L2
N7
M4
P1
N10
R7
U7
W8
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
K1
N5
N2
R2
N9
R8
U6
W10
DMI_TX0*
DMI_TX1*
DMI_TX2*
DMI_TX3*
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI_TX0*
FDI_TX1*
FDI_TX2*
FDI_TX3*
FDI_TX4*
FDI_TX5*
FDI_TX6*
FDI_TX7*
FDI_TX0
FDI_TX1
FDI_TX2
FDI_TX3
FDI_TX4
FDI_TX5
FDI_TX6
FDI_TX7
91 18
IN
91 18
IN
FDI_FSYNC<0>
FDI_FSYNC<1>
AC7
AC9
91 18
IN
FDI_INT
AB5
FDI_INT
91 18
IN
FDI_LSYNC<0>
FDI_LSYNC<1>
AA1
AB2
FDI_LSYNC0
FDI_LSYNC1
91 18
IN
FDI_FSYNC0
FDI_FSYNC1
FLEXIBLE DISPLAY INTERFACE
91 18
OUT
F7
J8
K8
J4
BGA
(SYM 5 OF 11)
DMI
91 18
91 18
IN
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
BGA
(SYM 1 OF 11)
PCI EXPRESS -- GRAPHICS
91 18
ARRANDALE
ARRANDALE
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
B12
A13
D12
B11
PEG_RX0*
PEG_RX1*
PEG_RX2*
PEG_RX3*
PEG_RX4*
PEG_RX5*
PEG_RX6*
PEG_RX7*
PEG_RX8*
PEG_RX9*
PEG_RX10*
PEG_RX11*
PEG_RX12*
PEG_RX13*
PEG_RX14*
PEG_RX15*
G40
G38
H34
P34
G28
H25
H24
D29
B26
D26
B23
D22
A20
D19
A17
B14
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
F40
J38
G34
M34
J28
G25
K24
B28
A27
B25
A24
B21
B19
B18
B16
D15
91
CPU_PEG_COMP
91
CPU_PEG_RBIAS
=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>
PEG_D2R_P<15>
PEG_D2R_P<14>
PEG_D2R_P<13>
PEG_D2R_P<12>
PEG_D2R_P<11>
PEG_D2R_P<10>
PEG_D2R_P<9>
PEG_D2R_P<8>
PEG_D2R_P<7>
PEG_D2R_P<6>
PEG_D2R_P<5>
PEG_D2R_P<4>
PEG_D2R_P<3>
PEG_D2R_P<2>
PEG_D2R_P<1>
PEG_D2R_P<0>
PEG_TX0*
PEG_TX1*
PEG_TX2*
PEG_TX3*
PEG_TX4*
PEG_TX5*
PEG_TX6*
PEG_TX7*
PEG_TX8*
PEG_TX9*
PEG_TX10*
PEG_TX11*
PEG_TX12*
PEG_TX13*
PEG_TX14*
PEG_TX15*
N40
L38
M32
D40
A38
G32
B33
B35
L30
A31
B32
L28
N26
M24
G21
J20
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
L40
N38
N32
B39
B37
H32
A34
D36
J30
B30
D33
N28
M25
N24
F21
L20
PEG_R2D_C_P<15>
PEG_R2D_C_P<14>
PEG_R2D_C_P<13>
PEG_R2D_C_P<12>
PEG_R2D_C_P<11>
PEG_R2D_C_P<10>
PEG_R2D_C_P<9>
PEG_R2D_C_P<8>
PEG_R2D_C_P<7>
PEG_R2D_C_P<6>
PEG_R2D_C_P<5>
PEG_R2D_C_P<4>
PEG_R2D_C_P<3>
PEG_R2D_C_P<2>
PEG_R2D_C_P<1>
PEG_R2D_C_P<0>
R10121
R1010
IN
IN
IN
IN
IN
IN
IN
91 25
IN
IN
91 25
IN
IN
91 25
IN
IN
91 25 8
IN
IN
IN
IN
IN
IN
IN
IN
750
1%
1/16W
MF-LF
402 2
49.9
1%
1/16W
MF-LF
2 402
Embedded DisplayPort
(eDP) pins
(Auburndale only):
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
91 25
IN
eDP_AUX#
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
IN
8 74 91
NOTE: HPD must be inverted

and level-shifted for
Auburndale (1.05V).
6
6
eDP_HPD#
eDP_AUX
6
6
6
6
OUT
OUT
OUT
OUT
OUT
6
6
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
OUT
8 74 91
6
6
6
6
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>
AL4
AM2
AK1
AK2
AK4
AJ2
AT2
AG7
AF4
AG2
AH1
AC2
AC4
AE2
AD1
AF8
AF6
AB7
TP_CPU_RSVD_TP0
AU1
TP_CPU_RSVD<15>
TP_CPU_RSVD<16>
T4
T2
RSVD15
RSVD16
TP_CPU_RSVD<17>
TP_CPU_RSVD<18>
U1
V2
RSVD17
RSVD18
TP_CPU_RSVD<19>
TP_CPU_RSVD<20>
AV71
AW70
RSVD19
RSVD20
TP_CPU_RSVD<21>
TP_CPU_RSVD<22>
AY69
BB69
RSVD21
RSVD22
TP_CPU_RSVD<23>
TP_CPU_RSVD<24>
D8
B7
RSVD23
RSVD24
TP_CPU_RSVD<26>
TP_CPU_RSVD<27>
A10
B9
RSVD26
RSVD27
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
RSVD_TP0
NC_TP_CPU_RSVD_NCTF<7>
C5
A6
RSVD_NCTF7
RSVD_NCTF8
E3
F1
RSVD_NCTF6
RSVD_NCTF5
eDP_TX#<3>
eDP_TX#<2>
eDP_TX#<1>
eDP_TX#<0>
CFG0: PCIe Configuration Select

CFG3: PCIe Lane Reversal
CFG4: Display Port Presence
RESERVED
RSVD32 W66
RSVD33 W64
NC_TP_CPU_RSVD<32>
NC_TP_CPU_RSVD<33>
RSVD34 AC69
RSVD35 AC71
NC_TP_CPU_RSVD<34>
NC_TP_CPU_RSVD<35>
RSVD36 AA71
RSVD37 AA69
NC_TP_CPU_RSVD<36>
NC_TP_CPU_RSVD<37>
RSVD38 R66
RSVD39 R64
NC_TP_CPU_RSVD<38>
NC_TP_CPU_RSVD<39>
RSVD_NCTF3 BT5
RSVD_NCTF4 BR5
NC_TP_CPU_RSVD<40>
NC_TP_CPU_RSVD<41>
RSVD_NCTF2 BV6
RSVD_NCTF1 BV8
NC_TP_CPU_RSVD<42>
NC_TP_CPU_RSVD<43>
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
AV69
AK71
AN69
AP66
AH66
AK66
AR71
AM66
AK69
AU71
AT70
AR69
AU69
AT67
TP_CPU_RSVD<45>
TP_CPU_RSVD<46>
TP_CPU_RSVD<47>
TP_CPU_RSVD<48>
TP_CPU_RSVD<49>
TP_CPU_RSVD<50>
TP_CPU_RSVD<51>
TP_CPU_RSVD<52>
TP_CPU_RSVD<53>
TP_CPU_RSVD<54>
TP_CPU_RSVD<55>
TP_CPU_RSVD<56>
TP_CPU_RSVD<57>
TP_CPU_RSVD<58>
RSVD_TP2 AP2
RSVD_TP1 AN7
TP_CPU_RSVD<2>
TP_CPU_RSVD<1>
RSVD62 AV4
RSVD63 AU2
CPU_THERMD_P
CPU_THERMD_N
RSVD64 BE69
RSVD65 BE71
TP_CPU_RSVD<64>
TP_CPU_RSVD<65>
DC_TEST_BV71
DC_TEST_BV69
DC_TEST_BV68
DC_TEST_BV5
DC_TEST_BV3
DC_TEST_BV1
DC_TEST_BT71
DC_TEST_BT69
DC_TEST_BT3
DC_TEST_BT1
DC_TEST_BR71
DC_TEST_BR1
DC_TEST_E71
DC_TEST_E1
DC_TEST_C71
DC_TEST_C69
DC_TEST_C3
DC_TEST_A71
DC_TEST_A69
DC_TEST_A68
DC_TEST_A5
BV71
BV69
BV68
BV5
BV3
BV1
BT71
BT69
BT3
BT1
BR71
BR1
E71
E1
C71
C69
C3
A71
A69
A68
A5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
BI
51 99
BI
51 99
6
6
CPU_TEST_BV71_BV69
TP_CPU_TEST_BV68
TP_CPU_TEST_BV5
CPU_TEST_BV3_BT3
CPU_TEST_BV1_BT1
CPU_TEST_BT71_BT69
TP_CPU_TEST_BR71
TP_CPU_TEST_BR1
TP_CPU_TEST_E71
TP_CPU_TEST_E1
CPU_TEST_C71_A71
CPU_TEST_C69_A69
TP_CPU_TEST_C3
TP_CPU_TEST_A68
TP_CPU_TEST_A5
1 = Single PEG
1 = Normal Operation
1 = eDP Disabled
0 = Bifurcation Enabled
0 = Lanes Reversed
0 = Embedded Display Port Enabled
WF: RSVD nets with arrows have offpage marks on CRB schematic.
WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic.
eDP_TX<3>
eDP_TX<2>
eDP_TX<1>
eDP_TX<0>
SYNC_MASTER=K17_REF
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
10 OF 132
SHEET
9 OF 101
NO STUFF
R11011
R1100
49.9
68
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402 2
91
91
91
R11101
R11121
20
91
R1113
20
49.9
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
ARRANDALE
BGA
AD71
AC70
AD69
AE66
CPU_COMP3
CPU_COMP2
CPU_COMP1
CPU_COMP0
1%
1/16W
MF-LF
2 402
91 20
91 68 46
91 46 20
91 25
91 18
BI
M71
(SYM 2 OF 11)
COMP3
COMP2
COMP1
COMP0
PROC_DETECT
CPU_CATERR_L
N61
CATERR*
CPU_PECI
N19
PECI
BI
CPU_PROCHOT_L
N67
PROCHOT*
OUT
PM_THRMTRIP_L
N17
THERMTRIP*
OUT
BI
FSB_CPURST_L
N70
PM_SYNC
M17
PM_SYNC
PP1V05_S0
1
(IPD)
1K
91 31 18
91 25 20
IN
Y67
CPU_PWRGD
VCCPWRGOOD_0
(IPD)
AM5
PM_MEM_PWRGD
IN
SM_DRAMPWROK
(IPD)
91 70
IN
H15
CPUVTTS0_PGOOD
VTTPWRGOOD
(IPD)
91 25
OUT
Y70
XDP_CPUPWRGD
TAPPWRGOOD
R1125
27
IN
PLT_RST_BUF_L
1.5K 2
1%
1/16W
MF-LF
402
G3
PLT_RESET_LS1V1_L
R11261
RSTIN*
PWR MANAGEMENT
R1120
VCCPWRGOOD_1
JTAG & MBP
AM7
R1151
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
BCLK AK7
BCLK* AK8
FSB_CLK133M_CPU_P
FSB_CLK133M_CPU_N
IN
20 91
IN
20 91
BCLK_ITP K71
BCLK_ITP* J70
FSB_CLK133M_ITP_P
FSB_CLK133M_ITP_N
OUT
25 91
PEG_CLK L21
PEG_CLK* J21
DPLL_REF_SSCLK Y2
DPLL_REF_SSCLK* W4
OUT
25 91
PCIE_CLK100M_CPU_P
PCIE_CLK100M_CPU_N
IN
17 91
IN
17 91
GFX_CLK120M_DPLLSS_P
GFX_CLK120M_DPLLSS_N
IN
17 93
IN
17 93
CPU_MEM_RESET_L
SM_RCOMP0 BV33
SM_RCOMP1 BP39
SM_RCOMP2 BV40
91
91
91
PM_EXT_TS0* AV66
PM_EXT_TS1* AV64
RESET_OBS*
10K
SM_DRAMRST* BJ12
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
5%
1/16W
MF-LF
2 402
R11501
U1000
1K
THERMAL
R1111
R1103
(GND)
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
TP_CPU_SKTOCC_L
49.9
1%
1/16W
MF-LF
402 2
68
OMIT
1
MISC
91
R11021
CLOCKS
PP1V05_S0
DDR3
MISC
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
(IPU)
PRDY* U71
PREQ* U69
XDP_PRDY_L
XDP_PREQ_L
(IPU)
(IPU)
(IPU)
TCK T67
TMS N65
TRST* P69
XDP_TCK
XDP_TMS
XDP_TRST_L
(IPU)
TDI T69
TDO T71
JTAG_CPU_TDI
JTAG_GMCH_TDO
(IPU)
TDI_M P71
TDO_M T70
W71
DBR*
JTAG_GMCH_TDI
JTAG_CPU_TDO
XDP_DBRESET_L
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
BPM0*
BPM1*
BPM2*
BPM3*
BPM4*
BPM5*
BPM6*
BPM7*
J69
J67
J62
K65
K62
J64
K69
M69
750
OUT
31
CPU_SM_RCOMP0
CPU_SM_RCOMP1
CPU_SM_RCOMP2
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
IN
46 91
IN
46 91
OUT
25 91
IN
25 91
IN
25 91
IN
25 91
IN
25 91
IN
25
OUT
25
IN
25
OUT
25
OUT
25 27 91
OUT
25 91
OUT
25 91
OUT
25 91
OUT
25 91
OUT
25 91
OUT
25 91
OUT
25 91
OUT
25 91
R11601
R11621
130
100
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
R1161
24.9
1%
1/16W
MF-LF
2 402
R1170
1%
1/16W
MF-LF
402 2
51
5%
1/16W
MF-LF
402 2
SYNC_MASTER=K17_REF
PAGE TITLE
CPU Clock/Misc/JTAG
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
11 OF 132
SHEET
10 OF 101
OMIT
OMIT
U1000
U1000
ARRANDALE
ARRANDALE
BGA
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29 28
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 28
OUT
92 28
OUT
92 28
OUT
92 28
OUT
92 28
OUT
92 28
OUT
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
BT38
BH38
BF21
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
BK43
BL38
BF38
(SYM 4 OF 11)
SA_CK0 BM34
SA_CK0* BP35
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
SA_CKE0 BF20
MEM_A_CKE<0>
SA_CK1 BK36
SA_CK1* BH36
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
SA_CKE1 BK24
MEM_A_CKE<1>
SA_CS0* BH40
SA_CS1* BJ47
MEM_A_CS_L<0>
MEM_A_CS_L<1>
SA_ODT0 BF43
SA_ODT1 BL47
MEM_A_ODT<0>
MEM_A_ODT<1>
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
DDR SYSTEM MEMORY A
92 29
AT8
AT6
BB5
BB9
AV7
AV6
BE6
BE8
BF11
BE11
BK5
BH13
BF9
BF6
BK7
BN8
BN11
BN9
BG17
BK15
BK9
BG15
BH17
BK17
BN20
BN17
BK25
BH25
BJ20
BH21
BG24
BG25
BJ40
BM43
BF47
BF48
BN40
BH43
BN44
BN47
BN48
BN51
BH53
BJ55
BH48
BJ48
BM53
BN55
BF55
BN57
BN65
BJ61
BF57
BJ57
BK64
BK61
BJ63
BF64
BB64
BB66
BJ66
BF65
AY64
BC70
BGA
(SYM 3 OF 11)
BB10
BJ10
BM15
BN24
BG44
BG53
BN62
BH59
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
SA_DQS0*
SA_DQS1*
SA_DQS2*
SA_DQS3*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
AY5
BJ7
BN13
BL21
BH44
BK51
BP58
BE62
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
AY7
BJ5
BL13
BN21
BK44
BH51
BM60
BE64
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
BT36
BP33
BV36
BG34
BG32
BN32
BK32
BJ30
BN30
BF28
BH34
BH30
BJ28
BF40
BN28
BN25
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
92 29
BI
92 29
BI
92 29
BI
OUT
28 92
OUT
28 92
OUT
28 92
OUT
28 92
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
OUT
28 29 92
92 29
BI
OUT
29 92
92 29
BI
OUT
29 92
92 29
BI
OUT
29 92
92 29
BI
OUT
29 92
92 29
BI
OUT
29 92
92 29
BI
OUT
29 92
92 29
BI
OUT
29 92
92 29
BI
92 29
BI
BI
28 29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
92 29
BI
BI
28 29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 30 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
BI
29 92
92 29
BI
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
OUT
28 92
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
92 29
BI
SA_BS0
SA_BS1
SA_BS2
92 30
OUT
92 30
OUT
92 30
OUT
SA_CAS*
SA_RAS*
SA_WE*
92 30
OUT
92 30
OUT
92 30
OUT
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
BA2
AW2
BD1
BE4
AY1
BC2
BF2
BH2
BG4
BG1
BR6
BR8
BJ4
BK2
BU9
BV10
BR10
BT12
BT15
BV15
BV12
BP12
BV17
BU16
BP15
BU19
BV22
BT22
BP19
BV19
BV20
BT20
BT48
BV48
BV50
BP49
BT47
BV52
BV54
BT54
BP53
BU53
BT59
BT57
BP56
BT55
BU60
BV59
BV61
BP60
BR66
BR64
BR62
BT61
BN68
BL69
BJ71
BF70
BG71
BC67
BK70
BK67
BD71
BD69
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
BV43
BV41
BV24
SB_BS0
SB_BS1
SB_BS2
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L
BU46
BT40
BT41
SB_CAS*
SB_RAS*
SB_WE*
DDR SYSTEM MEMORY B
SB_CK0 BU33
SB_CK0* BV34
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
SB_CKE0 BT26
MEM_B_CKE<0>
SB_CK1 BV38
SB_CK1* BU39
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
SB_CKE1 BT24
MEM_B_CKE<1>
SB_CS0* BP46
SB_CS1* BT43
SB_ODT0 BV45
SB_ODT1 BU49
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
MEM_B_CS_L<0>
MEM_B_CS_L<1>
OUT
30 92
OUT
30 92
MEM_B_ODT<0>
MEM_B_ODT<1>
OUT
30 92
OUT
30 92
OUT
29 30 92
OUT
29 92
OUT
29 92
OUT
29 92
OUT
29 92
OUT
29 92
OUT
29 92
OUT
29 92
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
BB4
BL4
BT13
BP22
BV47
BV57
BU65
BF67
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
SB_DQS0*
SB_DQS1*
SB_DQS2*
SB_DQS3*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
BE2
BM3
BU12
BT19
BT52
BV55
BU63
BG69
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
BD4
BN4
BV13
BT17
BT50
BU56
BV62
BJ69
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
BT34
BP30
BV29
BU30
BV31
BT33
BT31
BP26
BV27
BT27
BU42
BU26
BT29
BT45
BV26
BU23
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
BI
29 30 92
BI
29 92
BI
29 92
BI
29 92
BI
29 92
BI
29 92
BI
29 92
BI
29 92
BI
29 30 92
BI
29 92
BI
29 92
BI
29 92
BI
29 92
BI
29 92
BI
29 92
BI
29 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
OUT
30 92
SYNC_MASTER=K17_REF
PAGE TITLE
CPU DDR3 Interfaces

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
12 OF 132
SHEET
11 OF 101
OMIT
U1000
ARRANDALE
ARRANDALE
BGA
POWER
CPU CORE SUPPLY
16 7
NOTE: VCAP1 is sourced by CPU

Do not connect to power supply,
but provide bypass caps on PCB.
BD44
BD41
BD37
BB44
BB41
BB37
AY46
AY42
AY39
AW46
AW42
AW39
AU44
AU41
AU37
AR44
AR41
AR37
AN46
AN42
AN39
AL46
AL42
AL39
AK46
AK42
AK39
VCAP1_1
VCAP1_2
VCAP1_3
VCAP1_4
VCAP1_5
VCAP1_6
VCAP1_7
VCAP1_8
VCAP1_9
VCAP1_10
VCAP1_11
VCAP1_12
VCAP1_13
VCAP1_14
VCAP1_15
VCAP1_16
VCAP1_17
VCAP1_18
VCAP1_19
VCAP1_20
VCAP1_21
VCAP1_22
VCAP1_23
VCAP1_24
VCAP1_25
VCAP1_26
VCAP1_27
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
AF57
AF55
AF53
AF51
AF50
AF48
AF46
AF44
AF42
AF41
AD55
AD51
AD48
AD44
AD41
AB55
AB51
AB48
AB44
AB41
AA55
AA51
AA48
AA44
AA41
W55
W51
W48
W44
W41
U55
U51
U48
U44
U41
R55
R51
R48
R44
R41
P60
N55
N51
N48
N44
N42
M60
M51
M44
L55
K60
K51
K44
J55
H60
H51
H44
G60
G55
G51
G44
F55
E60
E57
E53
E50
E46
E42
D59
D57
D55
D54
D52
D50
D48
D47
D45
D43
B60
B56
B53
B49
B46
B42
A57
A54
A50
A47
A43
(SYM 6 OF 11)
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
68 49 15 12 7 6
PP1V05_S0
PPVCORE_S0_CPU
CPU_PSI_L
F68
PSI*
OUT
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
A61
D61
D62
A62
B63
D64
D66
VID0
VID1
VID2
VID3
VID4
VID5
VID6
OUT
TP_CPU_VTT_SELECT
AN1
VTT_SELECT1
OUT
PM_DPRSLPVR
F66
PROC_DPRSLPVR
91 68 15
OUT
91 15 8
OUT
91 15 8
OUT
91 15 8
OUT
91 15 8
OUT
91 15 8
OUT
91 15 8
OUT
91 15 8
91 8
91 68 15
CPU VIDS
VCAP0_1
VCAP0_2
VCAP0_3
VCAP0_4
VCAP0_5
VCAP0_6
VCAP0_7
VCAP0_8
VCAP0_9
VCAP0_10
VCAP0_11
VCAP0_12
VCAP0_13
VCAP0_14
VCAP0_15
VCAP0_16
VCAP0_17
VCAP0_18
VCAP0_19
VCAP0_20
VCAP0_21
VCAP0_22
VCAP0_23
VCAP0_24
VCAP0_25
VCAP0_26
VCAP0_27
6 7 12 15 49 68
VTT_SELECT: 1 = 1.05V, 0 = 1.1V
R13001
100
PLACE_NEAR=U1000.F64:25.4MM
1%
1/16W
MF-LF
402 2
R1305
10
1%
1/16W
MF-LF
2 402
91 68 50
PLACE_NEAR=U1000.N13:25.4MM
91 68
OUT
91 68
OUT
91 70
OUT
91 70
OUT
R13011
100
1%
1/16W
MF-LF
402 2
IN
CPUIMVP_IMON
A41
ISENSE
CPU_VCCSENSE_P
CPU_VCCSENSE_N
F64
F63
VCC_SENSE
VSS_SENSE
CPU_VTTSENSE_P
CPU_VTTSENSE_N
N13
R12
VTT_SENSE
VSS_SENSE_VTT
W39
W37
U37
R39
R37
VCCPLL1
VCCPLL2
VCCPLL3
VCCPLL4
VCCPLL5
SENSE LINES
BD55
BD51
BD48
BB55
BB51
BB48
AY57
AY53
AY50
AW57
AW53
AW50
AU55
AU51
AU48
AR55
AR51
AR48
AN57
AN53
AN50
AL57
AL53
AL50
AK57
AK53
AK50
PPVCORE_S0_CPU
PLACE_NEAR=U1000.R12:25.4MM
1
R1306
10
1%
1/16W
MF-LF
2 402
87 72 71 58 24 23 21 16 7 6
16
PP1V8_S0
PP1V5_S3_CPU_VCCDDR_CLK
MIN_LINE_WIDTH=0.4mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=1.5V
BB14
BB12
VDDQ_CK1
VDDQ_CK2
POWER

BGA
(SYM 8 OF 11)
1.8V
16 7
OMIT
U1000
1.1V RAIL POWER
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
VTT0_45
VTT0_46
VTT0_47
VTT0_48
VTT0_49
VTT0_50
VTT0_51
VTT0_52
VTT0_53
VTT0_54
VTT0_55
VTT0_56
VTT0_57
VTT0_58
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT0_63
VTT0_64
VTT0_65
VTT0_66
VTT0_67
VTT0_68
VTT0_69
VTT0_70
VTT0_71
VTT0_72
VTT0_73
BF60
BF59
BD60
BD59
BB60
BB59
AY60
AW60
AW35
AW33
AW14
AW12
AU60
AU59
AU12
AR60
AR59
AR12
AN60
AN59
AN35
AN33
AN17
AN15
AN14
AN12
AM10
AL60
AL59
AL17
AL15
AL14
AL12
AK35
AK33
AF39
AF37
AF35
AF33
AF32
AF30
AD39
AD37
AD35
AD33
AD32
AD30
W35
W33
W32
W30
W28
W26
W24
W23
U35
U33
U32
U30
U28
U26
U24
U23
R35
R33
R32
R30
R28
R26
R24
R23
AY10
AN9
PP1V05_S0
6 7 10 12 13 15 17 18
24 25 26 40 70 73 86
Arrandale:
1.05V
Clarksfield: 1.1V
(Controlled by VTT_SELECT pin)
SYNC_MASTER=K17_REF
PAGE TITLE
CPU Power (1 of 2)
DRAWING NUMBER
Apple Inc.
SIZE
<SCH_NUM> D
REVISION
20 21 23
<E4LABEL>
BRANCH
<BRANCH>
PAGE
13 OF 132
SHEET
12 OF 101
OMIT
69 49 24 13 7 6
PPVCORE_S0_GFX
U1000
R14001
ARRANDALE
100
BGA
1%
1/16W
MF-LF
402 2
(SYM 7 OF 11)
B
24 7
VTT1_1
VTT1_2
VTT1_3
VTT1_4
VTT1_5
VTT1_6
VTT1_7
VTT1_8
VTT1_9
VTT1_10
VTT1_11
AK62
AK60
AK59
AH60
AH59
AF60
AF59
AD60
AD59
AB60
AB59
AA60
AA59
W60
W59
U60
U59
R60
R59

VCAP2_1
VCAP2_2
VCAP2_3
VCAP2_4
VCAP2_5
VCAP2_6
VCAP2_7
VCAP2_8
VCAP2_9
VCAP2_10
VCAP2_11
VCAP2_12
VCAP2_13
VCAP2_14
VCAP2_15
VCAP2_16
VCAP2_17
VCAP2_18
VCAP2_19
PLACE_NEAR=U1000.AF12:25.4MM
OUT
69 91
OUT
69 91
OUT
69 91
100
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6
AF71
AG67
AG70
AH71
AN71
AM67
AM70
GFX_VR_EN AH69
GFX_VID<0>
GFX_VID<1>
GFX_VID<2>
GFX_VID<3>
GFX_VID<4>
GFX_VID<5>
GFX_VID<6>
OUT
8 91
OUT
8 91
OUT
8 91
OUT
8 91
OUT
8 91
OUT
8 91
OUT
8 91
GFX_DPRSLPVR AL71
GFX_DPRSLPVR
OUT
69 91
GFX_IMON AL69
GFXIMVP_IMON
IN
69 91
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36
BU40
BU35
BU28
BN38
BM25
BL30
BJ38
BH32
BH28
BG43
BF16
BF15
BD35
BD33
BD32
BD30
BD28
BD26
BD24
BD23
BD21
BD19
BD17
BD15
BB35
BB33
BB32
BB30
BB28
BB26
BB24
BB23
BB21
BB19
BB17
BB15
VTT0_DDR
VTT0_DDR1
VTT0_DDR2
VTT0_DDR3
VTT0_DDR4
VTT0_DDR5
VTT0_DDR6
VTT0_DDR7
VTT0_DDR8
VTT0_DDR9
AW32
AW30
AW28
AW26
AW24
AW23
AW21
AW19
AW17
AW15
VTT1_12
VTT1_13
VTT1_14
VTT1_15
VTT1_16
VTT1_17
VTT1_18
VTT1_19
VTT1_20
VTT1_21
AD15
AD14
AD12
AB12
AA12
W17
W15
W14
W12
R15
1%
1/16W
MF-LF
402 2
GFX_VR_EN
PP1V5_S3RS0
PP1V05_S0
W21
W19
U21
U19
U17
U15
U14
U12
R21
R19
R17
GFX_VSENSE_P
GFX_VSENSE_N
R14011
POWER
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
VAXG_SENSE AF12
VSSAXG_SENSE AF10
DDR3 -1.5 V RAILS
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
GRAPHICS VIDS
AN32
AN30
AN28
AN26
AN24
AN23
AN21
AN19
AL32
AL30
AL28
AL26
AL24
AL23
AL21
AL19
AK14
AK12
AJ10
AH14
AH12
AF28
AF26
AF24
AF23
AF21
AF19
AF17
AF15
AF14
AD28
AD26
AD24
AD23
AD21
AD19
AD17
SENSE
LINES
PPVCORE_S0_GFX
GRAPHICS
69 49 24 13 7 6
PEG & DMI
R1405
4.7K
5%
1/16W
MF-LF
402 2
6 7 16 31 42 72 73 99
B
PP1V1R1V05_S0_CPU_VTT0_DDR
PP1V05_S0
15
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
SYNC_MASTER=K17_REF
PAGE TITLE
CPU Power (2 of 2)
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
14 OF 132
SHEET
13 OF 101
OMIT
U1000
OMIT
OMIT
U1000
U1000
BGA
(SYM 10 OF 11)
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
AY62
AY59
AY55
AY51
AY48
AY44
AY41
AY37
AY35
AY33
AY32
AY30
AY28
AY26
AY24
AY23
AY21
AY19
AY17
AY15
AY14
AY12
AY8
AY4
AW67
AW62
AW59
AW55
AW51
AW48
AW44
AW41
AW37
AV9
AV1
AU70
AU62
AU57
AU53
AU50
AU46
AU42
AU39
AU35
AU33
AU32
AU30
AU28
AU26
AU24
AU23
AU21
AU19
AU17
AU15
AU14
AU4
AT64
AT10
AR62
AR57
AR53
AR50
AR46
AR42
AR39
AR35
AR33
AR32
AR30
AR28
AR26
AR24
AR23
AR21
AR19
AR17
AR15
AR14
AR4
AR1
AP70
AP64
AN62
AN55
AN51
AN48
AN44
AN41
AN37
AN5
AN4
AM64
AM8
AL62
AL55
AL51
AL48
AL44
AL41
AL37
AL35
AL33
AL1
AK70
AK64
AK55
AK51
AK48
AK44
AK41
AK37
AK32
AK30
AK28
AK26
AK24
AK23
AK21
AK19
AK17
AK15
AJ70
AH62
AH57
AH55
AH53
BV66
AH51
BV64
AH50
BT68
AH48
BR69
BL71
AH46
BL1
AH37
BR68
R14
AH35
AH44
H71
AH33
BR3
F71
AH32
AH42
E69
AH30
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
ARRANDALE
BGA
BGA
(SYM 9 OF 11)
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
ARRANDALE
ARRANDALE
BU62
BU58
BU55
BU51
BU48
BU44
BU37
BU32
BU25
BU21
BU18
BU14
BU11
BU7
BP42
BN64
BN6
BM70
BM51
BM44
BM32
BM24
BM17
BL57
BL55
BL48
BL40
BL28
BL20
BK63
BK60
BK53
BK34
BK10
BJ64
BJ21
BJ9
BJ1
BH70
BH57
BH55
BH47
BH24
BH20
BH15
BG51
BG36
BF62
BF30
BF13
BF8
BE70
BE65
BE9
BE1
BD57
BD53
BD50
BD46
BD42
BD39
BD14
BB71
BB62
BB57
BB53
BB50
BB46
BB42
BB39
BB7
BB1
BA70
AY71
AY66
(SYM 11 OF 11)
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
BN71
E68
AH28
AH41
A66
AH26
BN1
A64
AH24
AH39
E5
AH23
C68
AH21
AH19
AH17
AH15
AH4
AG64
AG9
AG6
AF69
AF62
AF1
AE70
AE64
AD62
AD57
AD53
AD50
AD46
AD42
AD4
AC67
AC64
AC10
AC5
AC1
AB70
AB62
AB57
AB53
AB50
AB46
AB42
AB39
AB37
AB35
AB33
AB32
AB30
AB28
AB26
AB24
AB23
AB21
AB19
AB17
AB15
AB14
AB9
AA66
AA64
AA62
AA57
AA53
AA50
AA46
AA42
AA39
AA37
AA35
AA33
AA32
AA30
AA28
AA26
AA24
AA23
AA21
AA19
AA17
AA15
AA14
AA4
W69
W62
W57
W53
W50
W46
W42
W6
W1
V70
U64
U62
U57
U53
U50
U46
U42
U39
U9
U4
T1
R70
R62
R57
R53
R50
R46
R42
R5
P4
N63
N57
N53
N50
N46
N30
N21
N15
M53
M42
M36
M1
L70
L57
L48
L47
L13
K64
K53
K43
K36
K34
K32
K25
K17
K11
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
VSS361
VSS362
VSS363
VSS364
VSS365
VSS366
VSS367
VSS368
VSS369
VSS370
VSS371
VSS372
VSS373
VSS374
VSS375
VSS376
VSS377
VSS378
VSS379
VSS380
VSS381
VSS382
VSS383
VSS384
VSS385
VSS386
VSS387
VSS388
VSS389
VSS390
VSS391
VSS392
VSS393
VSS394
VSS395
VSS396
VSS397
VSS398
VSS399
VSS400
VSS401
VSS402
VSS403
VSS404
VSS405
VSS406
VSS407
VSS408
VSS409
VSS410
VSS411
VSS412
VSS413
VSS414
VSS415
VSS416
VSS417
VSS418
VSS419
VSS420
VSS421
VSS422
VSS423
VSS424
VSS425
VSS426
VSS427
VSS428
VSS429
VSS430
VSS431
VSS432
VSS433
K6
K4
J65
J57
J48
J47
J40
J9
H53
H43
H36
H1
G70
G57
G53
G48
G47
G43
G30
G24
G20
G15
F61
F48
F47
F28
F20
F4
E37
E33
E30
E16
E12
D41
D38
D34
D31
D27
D24
D20
D17
D13
D10
D6
B65
B62
B58
B55
B51
B48
B44
A59
A55
A52
A48
A45
A40
A36
A33
A29
A26
A22
A19
A15
A12
A8
B40
SYNC_MASTER=K17_REF
PAGE TITLE
CPU Grounds
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
15 OF 132
SHEET
14 OF 101
CPU VCore HF and Bulk Decoupling
CPU Power On Configuration (POC) Straps
4x 470uF 4.5mOhm, 3x 62uF B2, 10x 22uF 0603, 25x 1uF 0402
Intel recommends all option straps should be provided in layout
PLACEMENT_NOTE (C1600-C1624):
68 49 12 7 6
PPVCORE_S0_CPU
Place on bottom side of U1000..

1
C1600
1UF
C1601
1UF
10%
2 16V
X5R
402
C1602
1UF
10%
2 16V
X5R
402
PP1V05_S0
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
C1603
1UF
10%
2 16V
X5R
402
C1604
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C1605
1UF
C1606
1UF
10%
2 16V
X5R
402
C1607
1UF
10%
2 16V
X5R
402
C1608
1UF
C1609
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C1610
1UF
C1611
1UF
10%
2 16V
X5R
402
CPUPOC4U
C1612
R16001
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
R16021
1K
1K
5%
1/16W
MF-LF
402 2
R1601
1UF
C1614
1UF
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C1615
C1616
1UF
C1617
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C1618
1UF
C1619
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C1620
1UF
1UF
10%
2 16V
X5R
402
C1621
1UF
C1622
10%
2 16V
X5R
402
10%
2 16V
X5R
402
1UF
C1623
1UF
10%
2 16V
X5R
402
Place near U1000 on bottom side.
NO STUFF
1
NO STUFF
C1625
22UF
C1626
22UF
20%
2 6.3V
X5R-CERM
603
NO STUFF
C1627
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 6.3V
X5R-CERM
603
NO STUFF
C1628
22UF
NO STUFF
C1629
22UF
20%
2 6.3V
X5R-CERM
603
C1630
22UF
20%
2 6.3V
X5R-CERM
603
NO STUFF
C1631
22UF
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 6.3V
X5R-CERM
603
C1632
C1634
22UF
20%
2 6.3V
X5R-CERM
603
NO STUFF
1
C1691
22UF
C1692
NO STUFF
1
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 6.3V
X5R-CERM
603
C1693
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 6.3V
X5R-CERM
603
C1694
22UF
20%
2 6.3V
X5R-CERM
603
C1698
22UF
20%
2 6.3V
X5R-CERM
603
91 12 8
OUT
91 12 8
OUT
91 12 8
OUT
91 12 8
OUT
91 12 8
OUT
91 12 8
OUT
91 12 8
OUT
91 68 12
OUT
91 68 12
OUT
NO STUFF
C1635
22UF
22UF
20%
2 6.3V
X5R-CERM
603
C1636
C1637
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 6.3V
X5R-CERM
603
NO STUFF
1
C1638
22UF
NO STUFF
C1640
22UF
20%
2 6.3V
X5R-CERM
603
C1641
22UF
20%
2 6.3V
X5R-CERM
603
C1649
470UF-4MOHM
C1650
470UF-4MOHM
20%
2 2.0V
POLY-TANT
D2T-SM
20%
2 2.0V
POLY-TANT
D2T-SM
C1651
470UF-4MOHM
20%
3 2 2.0V
POLY-TANT
D2T-SM
C1652
470UF-4MOHM
62UF
20%
2 2.0V
POLY-TANT
D2T-SM
22UF
20%
6.3V
2 X5R-CERM
603
C16A1
62UF
20%
2 11V
ELEC
CASE-B2
C1643
NO STUFF
1
C1644
22UF
20%
2 6.3V
X5R-CERM
603
C1645
22UF
20%
2 6.3V
X5R-CERM
603
C1646
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 11V
ELEC
CASE-B2
C16A2
62UF
20%
2 11V
ELEC
CASE-B2
C16A3
62UF
20%
2 11V
ELEC
CASE-B2
R16161
R16181
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
1K
CPUPOC3D
1
R1611
C1648
R1613
1K
20%
2 6.3V
X5R-CERM
603
1K
5%
1/16W
MF-LF
2 402
1K
CPUPOC5D
NO STUFF
R1615
1K
5%
1/16W
MF-LF
2 402
R1617
1K
1K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
C
VID[2:0]
VID[5:3]
VID[6]
DPRSLPVR
PSI#
C16A4
62UF
20%
2 11V
ELEC
CASE-B2
5%
1/16W
MF-LF
2 402
R16141
22UF
20%
2 6.3V
X5R-CERM
603
1K
5%
1/16W
MF-LF
2 402
CPUPOC4D
1K
R1607
1K
5%
1/16W
MF-LF
402 2
NO STUFF
1
R1605
5%
1/16W
MF-LF
402 2
NO STUFF
1
C16A0
C1642
22UF
20%
6.3V
2 X5R-CERM
603
NO STUFF
1
NO STUFF
1
R16121
NO STUFF
NO STUFF
1
CPUPOC5U
1
NO STUFF
Place near inductors on bottom side.

1
5%
1/16W
MF-LF
402 2
R16101
NO STUFF
5%
1/16W
MF-LF
2 402
1K
5%
1/16W
MF-LF
402 2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
PM_DPRSLPVR
CPU_PSI_L
NO STUFF
1K
1K
5%
1/16W
MF-LF
2 402
1UF
10%
2 16V
X5R
402
R1603
1K
C1624
R16081
1K
5%
1/16W
MF-LF
402 2
CPUPOC3U
C1613
NO STUFF
R16061
1K
5%
1/16W
MF-LF
402 2
1
1
NO STUFF
R16041
=
=
=
=
=
Reserved (111)
GPU Gain Setting (See below)
Reserved (0)
1 - IMVP-6.5 compliant controller
Reserved (0)
TABLE_BOMGROUP_HEAD
BOM GROUP
IMAX @ 900mV
CPU Gain Setting
BOM OPTIONS
Equivalent Gain
TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_DIS
000
CPUPOC3D,CPUPOC4D,CPUPOC5D
TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_0_20
20A
001
CPUPOC3D,CPUPOC4D,CPUPOC5U
45
VTT (CPU Uncore) DECOUPLING
CPUPOC_IMAX_20_30
30A
010
CPUPOC3D,CPUPOC4U,CPUPOC5D
30
3x 330uF 6 mOhm, 4x 22uF 0805, 7x 10uF 0603, 24x 1uF 0402
CPUPOC_IMAX_30_40
40A
011
CPUPOC3D,CPUPOC4U,CPUPOC5U
22.5
CPUPOC_IMAX_40_50
50A
100
CPUPOC3U,CPUPOC4D,CPUPOC5D
18
CPUPOC_IMAX_50_60
60A
101
CPUPOC3U,CPUPOC4D,CPUPOC5U
15
CPUPOC_IMAX_60_70
70A
110
CPUPOC3U,CPUPOC4U,CPUPOC5D
12.857
CPUPOC_IMAX_70_90
90A
111
CPUPOC3U,CPUPOC4U,CPUPOC5U
10
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
86 73 70 40 26 25
15 13 12 10 7 6
24 23 21 20 18 17
PP1V05_S0
Place on bottom side of U1000.
TABLE_BOMGROUP_ITEM
C1653
22UF
C1654
22UF
20%
2 6.3V
X5R-CERM
603
C1655
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 6.3V
X5R-CERM
603
TABLE_BOMGROUP_ITEM
C1656
22UF
20%
2 6.3V
X5R-CERM
603
NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
Instead call out appropriate BOM GROUP defined in tables above.
Place on bottom side of U1000..

1
C1657
10UF
C1658
10UF
20%
2 6.3V
X5R
603
C1659
10UF
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
C1660
10UF
C1661
10UF
20%
2 6.3V
X5R
603
C1662
10UF
20%
2 6.3V
X5R
603
C1663
10UF
20%
2 6.3V
X5R
603
VTT0_DDR DECOUPLING
20%
2 6.3V
X5R
603
3x 1uF 0402
L1695
30-OHM-5A
2
0603
C1664
1UF
C1665
1UF
10%
10V
2 X5R
402
C1676
1UF
10%
10V
2 X5R
402
C1677
1UF
10%
2 10V
X5R
402
C1666
1UF
10%
10V
2 X5R
402
C1678
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1667
1UF
10%
10V
2 X5R
402
C1679
1UF
10%
2 10V
X5R
402
C1668
1UF
10%
10V
2 X5R
402
C1680
1UF
10%
2 10V
X5R
402
C1669
1UF
10%
10V
2 X5R
402
C1681
1UF
10%
2 10V
X5R
402
C1670
1UF
10%
10V
2 X5R
402
C1682
1UF
10%
2 10V
X5R
402
C1671
1UF
C1672
1UF
10%
10V
2 X5R
402
10%
10V
2 X5R
402
C1683
1UF
C1684
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1673
1UF
10%
10V
2 X5R
402
C1685
1UF
10%
2 10V
X5R
402
C1674
1UF
10%
10V
2 X5R
402
C1686
1UF
10%
2 10V
X5R
402
C1675
1UF
10%
10V
2 X5R
402
C1695
1UF
10%
10V
2 X5R
402
C1696
1UF
10%
10V
2 X5R
402
PP1V1R1V05_S0_CPU_VTT0_DDR
VOLTAGE=1.1V
13
C1697
1UF
10%
10V
2 X5R
402
C1687
1UF
10%
2 10V
X5R
402
SYNC_MASTER=K17_REF
PAGE TITLE

DRAWING NUMBER
1
C1688
330UF
20%
2 2.0V
POLY-TANT
D2T-SM2
C1689
330UF
20%
2 2.0V
POLY-TANT
D2T-SM2
C1690
Apple Inc.
330UF
20%
2 2.0V
POLY-TANT
D2T-SM2
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form Factor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
16 OF 132
SHEET
15 OF 101
VCAP0 (CPU BSC Package) DECOUPLING

12x 1uF 0402
12 7

1
C1700
1UF
C1701
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C1702
1UF
10%
2 16V
X5R
402
C1703
1UF
C1704
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C1705
1UF
10%
2 16V
X5R
402
C1706
1UF
10%
2 16V
X5R
402
C1707
1UF
C1708
1UF
10%
2 16V
X5R
402
C1709
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C1710
1UF
C1711
1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402

12x 1uF 0402
12 7

1
C1712
1UF
C1713
1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
C1714
1UF
10%
16V
2 X5R
402
C1715
1UF
C1716
1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
C1717
1UF
10%
16V
2 X5R
402
C1718
1UF
10%
16V
2 X5R
402
C1719
1UF
C1720
1UF
10%
16V
2 X5R
402
C1721
1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
C1722
1UF
C1723
1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
Memory (CPU VCCDDR) DECOUPLING

42 31 16 13 7 6
99 73 72
5x 1uF 0402
NOTE: 3x 330uF 6 mOhm caps to be shared between CPU and SO-DIMMs.
PP1V5_S3RS0
C1724
1UF
C1725
1UF
10%
2 10V
X5R
402
C1726
1UF
10%
2 10V
X5R
402
C1727
1UF
C1728
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
10%
2 10V
X5R
402
DG recommends 2x 22uF at SO_DIMM not provided. Decoupling caps at SO-DIMMs on CSA 29 and CSA 31.
NOTE: 19x 1uF 0402 caps per Apple SI for CMD and CNTRL lines.
1
C1735
1UF
C1736
1UF
10%
2 10V
X5R
402
10%
10V
2 X5R
402
C1737
1UF
10%
10V
2 X5R
402
C1738
1UF
C1739
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1740
1UF
10%
2 10V
X5R
402
C1741
1UF
10%
10V
2 X5R
402
C1742
1UF
C1743
1UF
10%
2 10V
X5R
402
10%
10V
2 X5R
402
C1744
1UF
10%
2 10V
X5R
402
C1745
1UF
C1746
1UF
10%
10V
2 X5R
402
10%
10V
2 X5R
402
C1747
1UF
10%
2 10V
X5R
402
C1748
1UF
10%
10V
2 X5R
402
C1749
1UF
10%
2 10V
X5R
402
C1750
1UF
10%
2 10V
X5R
402
C1751
1UF
10%
2 10V
X5R
402
C1752
1UF
C1753
1UF
10%
10V
2 X5R
402
10%
10V
2 X5R
402
C1729
330UF
20%
2 2.0V
POLY-TANT
D2T-SM2
PLL (CPU VCCSFR) DECOUPLING

1x 22uF 0805, 1x 4.7uF 0603
24 23 21 12 7 6
87 72 71 58
PP1V8_S0
C1732
22uF
C1733
4.7UF
20%
2 6.3V
CERM-X5R
805
10%
2 6.3V
X5R-CERM
603
DDR Clock (CPU VDDQ_CK) DECOUPLING

1x 1uF 0402
L1734
42 31 16 13 7 6
99 73 72
PP1V5_S3RS0
30-OHM-5A
PP1V5_S3_CPU_VCCDDR_CLK
12
2
0603
C1734
1UF
10%
2 10V
X5R
402
SYNC_MASTER=K17_REF
PAGE TITLE

DRAWING NUMBER
Apple Inc.
R

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F
actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
17 OF 132
SHEET
16 OF 101
R18901
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
37.4
IBEX_PEAK_M
D
D17 SRTCRST*
17
PCH_INTRUDER_L
A16 INTRUDER*
94 17
IN
6
6
6
P1 SPKR
(IPD)
HDA_RST_R_L
C30 HDA_RST* (IPD)
HDA_SDIN0
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
G30
F30
E32
F32
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
(IPD)
(IPD)
(IPD)
(IPD)
B29 HDA_SDO
IN
SPI_DESCRIPTOR_OVERRIDE_L
ENET_ENERGY_DET
(IPU/NO)
H32 HDA_DOCK_EN*/GPIO33
J30 HDA_DOCK_RST*/GPIO13
IN
JTAG_PCH_TCK
IN
(IPD)
M3 JTAG_TCK (IPU)
25 17
IN
JTAG_PCH_TMS
K3 JTAG_TMS (IPU)
25 17
IN
JTAG_PCH_TDI
K1 JTAG_TDI (IPU)
25 17
OUT
JTAG_PCH_TDO
JTAG
25 17
PCH_SPKR
J2 JTAG_TDO
TP_JTAG_PCH_TRST_L
J4 JTAG_RST* (IPU)
94 47
OUT
SPI_CLK_R
BA2 SPI_CLK
94 47
OUT
SPI_CS0_R_L
AV3 SPI_CS0*
TP_SPI_CS1_L
AY3 SPI_CS1*
94 47
OUT
SPI_MOSI_R
AY1 SPI_MOSI (IPD)
94 47
IN
SPI_MISO
AV1 SPI_MISO (IPU)
AK7 HDD
AK6
AK11
AK9
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AH6
AH5
AH9
AH8
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AD9
AD8
AD6
AD5
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AD3
AD1
AB3
AB1
94 37
IN
6 45 47 87 94
94 37
IN
BI
6 45 47 87 94
94 37
OUT
BI
6 45 47 87 94
94 37
OUT
6 45 47 87 94
94 33 6
94 33 6
BI
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
ODD
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
AF11 Unused
AF9
AF7
AF6
AH3
AH1
AF3
AF1
6 45 47 87 94
BI
OUT
LPC_SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
BI
TP_LPC_DREQ0_L
TP_LPC_DREQ1_L
SERIRQ AB9
D29 HDA_SYNC (IPD)
SPI
HDA_SYNC_R
LPC_FRAME_L
(IPU) LDRQ0* A34

LDRQ1*/GPIO23 F34
A30 HDA_BCLK (IPD)
HDA_SDOUT_R
94 17
37 17
HDA_BIT_CLK_R
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
D33
B33
C32
A32
FWH4/LFRAME* C34
Only ports 4 & 5

Not available on
support FIS-based
some IbexPeak SKUs
port multipliers
17
A14 INTVRMEN
IHDA
94 17
PCH_INTVRMEN_L
RTC
LPC
PCH_SRTCRST_L
94 17
45 17
C14 RTCRST*
17
17
94 58
RTC_RESET_L
SATA
17
FCBGA
(1 OF 10)
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
Unused NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
SSD
NC_SATA_SSD2_D2RN
NC_SATA_SSD2_D2RP
NC_SATA_SSD2_R2D_CN
NC_SATA_SSD2_R2D_CP
eSATA
SATAICOMPO AF16
SATAICOMPI AF15
94 33
OUT
94 39
IN
6 45 47
94 39
IN
42 93
94 39
OUT
IN
42 93
94 39
OUT
OUT
42 93
8
IN
IN
OUT
OUT
42 93
IN
42 93
IN
42 93
OUT
OUT
42 93
OUT
42 93
6
6
6
6
6
6
6
6
6
6
6
IN
IN
OUT
OUT
6
6
6
8
94 37
OUT
94 37
OUT
37 17
IN
PCH_SATAICOMP
(IPU) SATALED* T3
TP_PCH_SATALED_L
SATA0GP/GPIO21 Y9
SATA1GP/GPIO19 V1
SATARDRVR_A_EN
SATARDRVR_B_EN
PP3V42_G3H
71 7 6
R18021
20K
20K
5%
1/16W
MF-LF
402 2
R18001
330K
5%
1/16W
MF-LF
402 2
51
5%
1/16W
MF-LF
2 402
51
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
R1801
1M
5%
1/16W
MF-LF
2 402
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
C1802 1
1UF
R18281
51
5%
1/16W
MF-LF
402 2
17
C1803
1UF
OUT
17 25 42
OUT
17 25
R1810
94 17
HDA_BIT_CLK_R
33
5%
1/16W
MF-LF
402
94 17
HDA_BIT_CLK
HDA_RST_R_L
5%
1/16W
MF-LF
402
94 17
HDA_SDOUT_R
33
HDA_SYNC
OUT
58 94
5%
1/16W
MF-LF
402
R1812
94 17
58 94
R1811
HDA_SYNC_R
33
OUT
HDA_RST_L
OUT
58 94
R1813
1
33
HDA_SDOUT
OUT
58 94
5%
1/16W
MF-LF
402
PERN3
PERP3
PETN3
PETP3
BA32
BB32
BD32
BE32
PERN4
PERP4
PETN4
PETP4
NC_PCIE_PE5_D2RN
NC_PCIE_PE5_D2RP
NC_PCIE_PE5_R2D_CN
NC_PCIE_PE5_R2D_CP
BF33
BH33
BG32
BJ32
PERN5
PERP5
PETN5
PETP5
NC_PCIE_PE6_D2RN
NC_PCIE_PE6_D2RP
NC_PCIE_PE6_R2D_CN
NC_PCIE_PE6_R2D_CP
BA34
AW34
BC34
BD34
PERN6
PERP6
PETN6
PETP6
NC_PCIE_PE7_D2RN
NC_PCIE_PE7_D2RP
NC_PCIE_PE7_R2D_CN
NC_PCIE_PE7_R2D_CP
AT34
AU34
AU36
AV36
PERN7
PERP7
PETN7
PETP7
NC_PCIE_PE8_D2RN
NC_PCIE_PE8_D2RP
NC_PCIE_PE8_R2D_CN
NC_PCIE_PE8_R2D_CP
BG34
BJ34
BG36
BJ36
PERN8
PERP8
PETN8
PETP8
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
AK48 CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P
IN
AP_CLKREQ_L
33 25 17
94 39
OUT
94 39
OUT
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
IN
FW_CLKREQ_L
OMIT
FCBGA
(2 OF 10)
N4 PCIECLKRQ2*/GPIO20
NC_PCIE_CLK100M_EXCARD_N
NC_PCIE_CLK100M_EXCARD_P
IN
EXCARD_CLKREQ_L
R1827
51
5%
1/16W
MF-LF
2 402
17
6
6
AH42 CLKOUT_PCIE3N
AH41 CLKOUT_PCIE3P
M9 PCIECLKRQ4*/GPIO26
AJ50 CLKOUT_PCIE5N
AJ52 CLKOUT_PCIE5P
17 25
17 25
101 17
OUT
17 25
6
17 25
17
PP3V3_S5
PP3V3_S3
PP3V3_S0
BRCRYPT_PWR_EN
H6 PCIECLKRQ5*/GPIO44
AK53 CLKOUT_PEG_B_N
AK51 CLKOUT_PEG_B_P
PCH_PEB_CLKREQ_L
PCH_SML0ALERT_L
C6
G8
SML_PCH_0_CLK
SML_PCH_0_DATA
SML1ALERT*/GPIO74
M14
PCH_SML1ALERT_L
SML1CLK/GPIO58
SML1DATA/GPIO75
E10
G12
SML_PCH_1_CLK
SML_PCH_1_DATA
CL_CLK1
T13
NC_CLINK_CLK
(IPU) CL_DATA1
T11
NC_CLINK_DATA
T9
NC_CLINK_RESET_L
SML0CLK
SML0DATA
(IPU)
CL_RST1*
P13 PEG_B_CLKRQ*/GPIO56
CLKIN_BCLK_N AP3
CLKIN_BCLK_P AP1
CLKIN_DOT_96N F18
CLKIN_DOT_96P E18
CLKIN_SATA_N/CKSSCD_N AH13
CLKIN_SATA_P/CKSSCD_P AH12
REFCLK14IN P41
CLKIN_PCILOOPBACK J42
2
5%
1/16W
MF-LF
5%
1/16W MF-LF 402
2
2
2
2
2
2
2
2
2
5%
1/16W MF-LF 402
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
402
402
5%
1/16W MF-LF 402
5%
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
1/16W MF-LF 402
ENET_ENERGY_DET
17 37
ENET_CLKREQ_L
AP_CLKREQ_L
FW_CLKREQ_L
EXCARD_CLKREQ_L
PCH_PE4_CLKREQ_L
PCH_PEB_CLKREQ_L
SMC_WAKE_SCI_L
PCH_SML0ALERT_L
PCH_SML1ALERT_L
PEG_CLKREQ_L
2
2
2
2
2
17
17 45
BRCRYPT_PWR_EN
2
2
2
2
PCH_SPKR
SATARDRVR_A_EN
SATARDRVR_B_EN
5%
1/16W MF-LF 402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
94
25 26 28 30 32
42 47 48 63 88
25 26 28 30 32 42
47 48 63 88 94
17
OUT
BI
48 94
48 94
17
OUT
48 94
BI
48 94
IN
8 17 87
PEG_CLK100M_N
PEG_CLK100M_P
OUT
74 94
OUT
74 94
PCIE_CLK100M_CPU_N
PCIE_CLK100M_CPU_P
OUT
10 91
OUT
10 91
OUT
10 93
OUT
10 93
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
IN
26 93
IN
26 93
FSB_CLK133M_PCH_N
FSB_CLK133M_PCH_P
IN
26 93
IN
26 93
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
IN
26 93
IN
26 93
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
IN
26 93
IN
26 93
PCH_CLK14P3M_REFCLK
IN
26 93
PCH_CLK33M_PCIIN
IN
27 93
IN
27
OUT
27
PCH_CLK25M_XTALIN
PCH_CLK25M_XTALOUT
XCLK_RCOMP AF38
PCH_XCLK_RCOMP
BRCRYPT_RESET
17 101
Default: 0V
ARB_DETECT
17
Default: 24.576 MHz (unsupported)
MLB_RAM_SIZE
17
Default: 14.31818 MHz
MLB_RAM_VENDOR
17
Default: 48 MHz
CLKOUTFLEX0/GPIO64 T45
(IPD)
CLKOUTFLEX1/GPIO65 P43
(IPD)
CLKOUTFLEX2/GPIO66 T42
(IPD)
CLKOUTFLEX3/GPIO67 N50
(IPD)
17 25 42
17 25
17 37
17 25 33
17 25 40
17
17
17
SYNC_MASTER=K17_REF
17 101
PAGE TITLE
PCH SATA/PCIE/CLK/LPC/SPI
17 45
17
DRAWING NUMBER
17
Apple Inc.
8 17 87
17 101
<E4LABEL>
BRANCH
<BRANCH>
17

17
17
SIZE
<SCH_NUM> D
REVISION
BRCRYPT_RESET
ARB_DETECT
MLB_RAM_SIZE
MLB_RAM_VENDOR
17 45
All 4 CLKOUTFLEX outputs support

33.333 MHz and 14.31818 MHz,
CLKOUTFLEX3 also supports 48 MHz.
402
BI
XTAL25_IN AH51
XTAL25_OUT AH53
6 7 18 19 20 21 23 27 31 35 57
66 71 72 73 83 85 99
101
6 7 8 20 31 32 33 34 35 36 48 50 53 54 55
72 73 87
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
IN
OUT
PEG_CLKREQ_L
CLKOUT_PEG_A_N AD43
CLKOUT_PEG_A_P AD45
CLKIN_DMI_N AW24
CLKIN_DMI_P BA24
AM51 CLKOUT_PCIE4N
AM53 CLKOUT_PCIE4P
PCH_PE4_CLKREQ_L
J14
CLKOUT_DP_N/CLKOUT_BCLK1_N AT1
CLKOUT_DP_P/CLKOUT_BCLK1_P AT3
A8 PCIECLKRQ3*/GPIO25
SML0ALERT*/GPIO60
CLKOUT_DMI_N AN4
CLKOUT_DMI_P AN2
U4 PCIECLKRQ1*/GPIO18
OUT
SMBUS_PCH_CLK
SMBUS_PCH_DATA
PEG_A_CLKRQ*/GPIO47 H1
AM47 CLKOUT_PCIE2N
AM48 CLKOUT_PCIE2P
OUT
SMC_WAKE_SCI_L
H14
C8
IBEX_PEAK_M
P9 PCIECLKRQ0*/GPIO73
94 8
B9
SMBCLK
SMBDATA
SMBALERT*/GPIO11
U1800
AM43 CLKOUT_PCIE1N
AM45 CLKOUT_PCIE1P
94 8
R1899 2.2K 1
R1815 10K 1
R1816 10K 1
R1840 10K 1
R1841 10K 1
R1850 10K 1
R1851 10K 1
R1852 10K 1
R1853 10K 1
R1854 10K 1
R1855 10K 1
R1860 100K 1
R1870 10K 1
R1871 10K 1
R1872 10K 1
R1880 10K 1
R1895 10K 1
R1896 10K 1
R1897 10K 1
R1898 10K 1
10%
10V
2 X5R
402
10%
10V
X5R 2
402
AU30
AT30
AU32
AV32
ENET_CLKREQ_L
17
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
OUT
17
17
PERN2
PERP2
PETN2
PETP2
94 33
JTAG_PCH_TMS
JTAG_PCH_TDI
JTAG_PCH_TDO
JTAG_PCH_TCK
AW30
BA30
BC30
BD30
OUT
XDP_PCH
R18251 R18261
R1803
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
17
XDP_PCH
PERN1
PERP1
PETN1
PETP1
94 33
PP1V05_S5
XDP_PCH
BG30
BJ30
BF29
BH29
40 25 17
73 66 65
45 43 23 21 7 6
64 53 49 48 47 46
IN
OUT
IN
NC_SATA_EXTA_D2R_N
IN
NC_SATA_EXTA_D2R_P
IN
NC_SATA_EXTA_R2D_C_N OUT
NC_SATA_EXTA_R2D_C_P OUT
93
IN
94 33
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
SMBUS
OMIT
U1800
C-LINK
B13 RTCX1
D13 RTCX2
90.9
PEG
PCH_CLK32K_RTCX1
PCH_CLK32K_RTCX2
(IPU)
IN
PP1V05_S0
R18301
5%
1/16W
MF-LF
2 402
PCI-E*
10K
OUT
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
R1820
27
PP1V05_S0
PP3V3_S0
1
27
FROM CLK BUFFER
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
72 69 68 63 62 58 54 52 51
99 88 87 85 84 83 80 73
CLOCK
FLEX
PAGE
18 OF 132
SHEET
17 OF 101
PP3V3_S5
PP1V05_S0
6 7 10 12 13 15 17 20 21 23 24
25 26 40 70 73 86
R1900
49.9
1%
1/16W
MF-LF
2 402
IN
91 9
IN
91 9
IN
91 9
IN
91 9
IN
91 9
IN
91 9
IN
91 9
OUT
91 9
OUT
91 9
OUT
91 9
OUT
91 9
OUT
91 9
OUT
91 9
OUT
91 9
OUT
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
BC24
BJ22
AW20
BJ20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
BD24
BG22
BA20
BG20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
PCH_DMI_COMP
45 27 6
27
IN
IN
PM_SYSRST_L
PM_PCH_PWRGD
BE22
BF21
BD20
BE18
BD22
BH21
BC20
BD18
T6
M6
K5
PCH_LAN_RST_L
91 31 10
45 18
18
45 25
73 46 45
45 18
OUT
PM_MEM_PWRGD
IN
PM_RSMRST_L
IBEX_PEAK_M
FCBGA
(3 OF 10)
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
A10
D9
C16
SYS_RESET*
SYS_PWROK
PWROK
MEPWROK
LAN_RST*
DRAMPWROK
RSMRST*
PM_SUS_PWR_ACK
M1
SUS_PWR_ACK/GPIO30
IN
PM_PWRBTN_L
P5
PWRBTN* (IPU)
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
SMC_ADAPTER_EN
P7
ACPRESENT/GPIO31
IN
PM_BATLOW_L
A6
BATLOW*/GPIO72
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
FDI_INT
IN
9 91
87 8
OUT
IN
9 91
87 8
OUT
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
T48
T47
L_BKLTEN
L_VDD_EN
IN
9 91
8 6
OUT
TP_LVDS_IG_BKL_PWM
Y48
L_BKLTCTL
IN
9 91
IN
9 91
84
OUT
IN
9 91
84
BI
IN
9 91
IN
9 91
IN
9 91
IN
9 91
IN
9 91
IN
9 91
IN
9 91
IN
9 91
IN
9 91
IN
9 91
IN
BI
OUT
OUT
93 87
OUT
93 8
OUT
93 8 6
OUT
93 8 6
OUT
6 18 45 47
SLP_S5*/GPIO63 E4
PM_SLP_S5_L
OUT
45 46
SLP_S4* H7
PM_SLP_S4_L
OUT
31 43 45 46 72 73
6 31 45 73 85
TP_PM_SLP_M_L
93 87
OUT
93 87
OUT
93 87
OUT
93 8
OUT
93 87
OUT
93 87
OUT
93 87
OUT
93 8
OUT
PM_SYNC
BI
10 91
TP_SLP_LAN_L
SLP_LAN* F6
R1906
10K
5%
1/16W
MF-LF
2 402
6
6
72 69 68 63 62 58 54 52 51 50
26 25 24 23 21 20 19 17 7 6
48 47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73
LVD_VREFH
LVD_VREFL
AV53
AV51
LVDSA_CLK*
LVDSA_CLK
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_N<2>
BB47
BA52
AY48
AV47
LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2>
BB48
BA50
AY49
AV48
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
TP_LVDS_IG_B_CLKN
TP_LVDS_IG_B_CLKP
AP48
AP47
LVDSB_CLK*
LVDSB_CLK
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>
AY53
AT49
AU52
AT53
LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<2>
AY51
AT48
AU50
AT51
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
AA52
AB53
AD53
CRT_BLUE
CRT_GREEN
CRT_RED
TP_PM_SLP_DSW_L
TP23 N2
PMSYNCH BJ10
RI*
93 87
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_P
6 18 45 47
OUT
AT43
AT42
6 18 45 47
46 94
PM_SLP_S3_L
OUT
6 18 27 33
OUT
SLP_S3* P12
93 87
OUT
PM_CLK32K_SUSCLK
SUSCLK/GPIO62 F3
OUT
93 87
9 91
LPC_PWRDWN_L
93 87
OUT
OUT
MAKE_BASE=TRUE
1%
1/16W
MF-LF
2 402
93 8
9 91
SUS_STAT*/GPIO61 P8
2.37K
OUT
OUT
LVD_IBG
LVD_VBG
NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA
V51
V53
CRT_DDC_CLK
CRT_DDC_DATA
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
Y53
Y51
CRT_HSYNC
CRT_VSYNC
PP3V3_S0
PCH_DAC_IREF
R19201
10K
AD48
AB51
DAC_IREF
CRT_IRTN
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
BJ48
BG48
NC_SDVO_STALLN
NC_SDVO_STALLP
SDVO_INTN
SDVO_INTP
BF45
BH45
NC_SDVO_INTN
NC_SDVO_INTP
T51
T53
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
BG44
BJ44
AU38
DP_IG_AUX_CH_N
DP_IG_AUX_CH_P
DP_IG_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
DP_IG_B_ML_N<0>
DP_IG_B_ML_P<0>
DP_IG_B_ML_N<1>
DP_IG_B_ML_P<1>
DP_IG_B_ML_N<2>
DP_IG_B_ML_P<2>
DP_IG_B_ML_N<3>
DP_IG_B_ML_P<3>
(IPD) SDVO_CTRLCLK
(IPD) SDVO_CTRLDATA
(IPU)
DDPC_CTRLCLK
DDPC_CTRLDATA
(IPD)
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
Y49
AB49
NC_DP_IG_C_CTRL_CLK
BE44
BD44
AV40
NC_DP_IG_C_AUXN
NC_DP_IG_C_AUXP
NC_DP_IG_C_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
NC_DP_IG_C_MLN<0>
NC_DP_IG_C_MLP<0>
NC_DP_IG_C_MLN<1>
NC_DP_IG_C_MLP<1>
NC_DP_IG_C_MLN<2>
NC_DP_IG_C_MLP<2>
NC_DP_IG_C_MLN<3>
NC_DP_IG_C_MLP<3>
U50
U52
NC_DP_IG_D_CTRL_CLK
BC46
BD46
AT38
NC_DP_IG_D_AUXN
NC_DP_IG_D_AUXP
NC_DP_IG_D_HPD
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
NC_DP_IG_D_MLN<0>
NC_DP_IG_D_MLP<0>
NC_DP_IG_D_MLN<1>
NC_DP_IG_D_MLP<1>
NC_DP_IG_D_MLN<2>
NC_DP_IG_D_MLP<2>
NC_DP_IG_D_MLN<3>
NC_DP_IG_D_MLP<3>
(IPU)
DDPD_CTRLCLK
DDPD_CTRLDATA
(IPD)
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
6
6
6
6
6
6
OUT
BI
BI
BI
IN
8 80 84
8 80 84
8 84 93
8 84 93
8 84
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
R1921
R1951
10K
5%
1/16W
MF-LF
402 2
(IPD)
R1950
OUT
FDI_LSYNC<0>
FDI_LSYNC<1>
AP39
AP41
FCBGA
(4 OF 10)
93 87
FDI_LSYNC0 BJ12
FDI_LSYNC1 BG14
LPC_PWRDWN_L
PCH_LVDS_IBG
NC_PCH_LVDS_VBG
OUT
9 91
PM_CLKRUN_L
L_CTRL_CLK
L_CTRL_DATA
93 87
OUT
CLKRUN*/GPIO32 Y1
AB46
V48
93 87
OUT
PCIE_WAKE_L
NC_LVDS_IG_CTRL_CLK
NC_LVDS_IG_CTRL_DATA
9 91
9 91
WAKE* J12
L_DDC_CLK
L_DDC_DATA
BJ46
BG46
SDVO_TVCLKINN
SDVO_TVCLKINP
IBEX_PEAK_M
AB48
Y45
OUT
FDI_FSYNC<0>
FDI_FSYNC<1>
OMIT
U1800
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
FDI_FSYNC0 BF13
FDI_FSYNC1 BH13
SLP_M* K8
IN
F14
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
FDI_INT BJ14
OUT
PCH_RI_L
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BH25 DMI_ZCOMP
BF25 DMI_IRCOMP
B17
OMIT
U1800
LVDS
DIGITAL DISPLAY INTERFACE
IN
91 9
CRT
91 9
DMI
FDI
10K
1%
1/16W
MF-LF
402 2
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
SYSTEM POWER
MANAGEMENT
R19051
1K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
PM_SUS_PWR_ACK
PM_CLKRUN_L
6 18 45 47
PM_RSMRST_L
18 45
0.5% recommended, Intel okay

with 5% when CRTDAC not used.
18
R1925
10K
5%
1/16W
MF-LF
402 2
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
PP3V3_S5
R19301
10K
5%
1/16W
MF-LF
402 2
R1931
10K
5%
1/16W
MF-LF
2 402
PM_BATLOW_L
PCIE_WAKE_L
18 45
6 18 27 33
SYNC_MASTER=K17_REF
PAGE TITLE
PCH DMI/FDI/Graphics
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
19 OF 132
SHEET
18 OF 101
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
72 69 68 63 62 58 54 52 51 50
26 25 24 23 21 20 18 17 7 6
48 47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73
PP3V3_S0
R2010
R2011
R2012
R2013
R2014
10K
10K
10K
10K
1
1
1
1
2
2
2
2
10K
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
1/16W MF-LF 402

87 19
OUT
87 19
OUT
19
6
6
6
6
19
63 19
IN
19
IN
63 19
IN
6
R2020
R2021
R2022
10K
10K
1
1
2
2
10K
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
1/16W MF-LF 402

6
R2023
R2024
R2025
R2026
R2027
10K
10K
1
1
2
2
10K
10K
10K
1
1
2
2
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
6
40 31 27
OUT
94 27
OUT
27
OUT
27
6
27
OUT
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
NC_PCI_C_BE_L<0>
NC_PCI_C_BE_L<1>
NC_PCI_C_BE_L<2>
NC_PCI_C_BE_L<3>
J50
G42
H47
G34
C/BE0*
C/BE1*
C/BE2*
C/BE3*
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
G38
H51
B37
A44
PIRQA*
PIRQB*
PIRQC*
PIRQD*
PCI_REQ0_L
JTAG_GMUX_TMS
JTAG_GMUX_TDI
PCI_REQ3_L
F51
A46
B45
M53
REQ0*
REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54
NC_PCI_GNT0_L
NC_PCI_GNT1_L
NC_PCI_GNT2_L
NC_PCI_GNT3_L
F48
K45
F36
H53
GNT0*
(IPU)
GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55
PCH_GPIO2
AUD_IP_PERIPHERAL_DET
MIKEY_MIC_LOAD_DET
AUD_I2C_INT_L
B41
K53
A36
A48
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
NC_PCI_RESET_L
K6
PCI_SERR_L
PCI_PERR_L
E44
E50
SERR*
PERR*
PCI_IRDY_L
NC_PCI_PAR
PCI_DEVSEL_L
PCI_FRAME_L
A42
H44
F46
C46
IRDY*
PAR
DEVSEL*
FRAME*
PCI_PLOCK_L
D49
PLOCK*
PCI_STOP_L
PCI_TRDY_L
D41
C48
STOP*
TRDY*
NC_PCI_PME_L
M7
PME* (IPU)
PLT_RESET_L
D5
PLTRST*
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
LPC_CLK33M_GMUX_R
NC_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
N52
P53
P46
P51
P48
AY9
BD1
AP15
BD8
NC_NV_CE_L<0>
NC_NV_CE_L<1>
NC_NV_CE_L<2>
NC_NV_CE_L<3>
NV_DQS0
NV_DQS1
AV9
BG8
NC_NV_DQS<0>
NC_NV_DQS<1>
NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
NC_NV_DQ<0>
NC_NV_DQ<1>
NC_NV_DQ<2>
NC_NV_DQ<3>
NC_NV_DQ<4>
NC_NV_DQ<5>
NC_NV_DQ<6>
NC_NV_DQ<7>
NC_NV_DQ<8>
NC_NV_DQ<9>
NC_NV_DQ<10>
NC_NV_DQ<11>
NC_NV_DQ<12>
NC_NV_DQ<13>
NC_NV_DQ<14>
NC_NV_DQ<15>
NV_ALE
NV_CLE
BD3
AY6
NC_NV_ALE
NC_NV_CLE
NV_RCOMP
AU2
NC_PCH_NV_RCOMP
NV_RB*
AV7
NC_NV_RB_L
NV_WR0_RE*
NV_WR1_RE*
AY8
AY5
NC_NV_WR_RE_L<0>
NC_NV_WR_RE_L<1>
NV_WE_CK0*
NV_WE_CK1*
AV11
BF5
NC_NV_WE_CK_L<0>
NC_NV_WE_CK_L<1>
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
USB_HUB1_UP_N
USB_HUB1_UP_P
NC_USB_1N
NC_USB_1P
USB_BRCRYPT_N
USB_BRCRYPT_P
NC_USB_3N
NC_USB_3P
NC_USB_4N
NC_USB_4P
NC_USB_5N
NC_USB_5P
NC_USB_6N
NC_USB_6P
NC_USB_7N
NC_USB_7P
USB_HUB2_UP_N
USB_HUB2_UP_P
NC_USB_9N
NC_USB_9P
NC_USB_10N
NC_USB_10P
NC_USB_11N
NC_USB_11P
NC_USB_12N
NC_USB_12P
NC_USB_13N
NC_USB_13P
USBRBIAS*
USBRBIAS
B25
D25
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
N16
J16
F16
L16
E14
G16
F12
T15
IBEX_PEAK_M
PCIRST*
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
NV_CE0*
NV_CE1*
NV_CE2*
NV_CE3*
OMIT
U1800
FCBGA
(5 OF 10)
(IPD)
(IPD)
(IPU)
(DPD)
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
EHCI1
NC_PCI_AD<0>
NC_PCI_AD<1>
NC_PCI_AD<2>
NC_PCI_AD<3>
NC_PCI_AD<4>
NC_PCI_AD<5>
NC_PCI_AD<6>
NC_PCI_AD<7>
NC_PCI_AD<8>
NC_PCI_AD<9>
NC_PCI_AD<10>
NC_PCI_AD<11>
NC_PCI_AD<12>
NC_PCI_AD<13>
NC_PCI_AD<14>
NC_PCI_AD<15>
NC_PCI_AD<16>
NC_PCI_AD<17>
NC_PCI_AD<18>
NC_PCI_AD<19>
NC_PCI_AD<20>
NC_PCI_AD<21>
NC_PCI_AD<22>
NC_PCI_AD<23>
NC_PCI_AD<24>
NC_PCI_AD<25>
NC_PCI_AD<26>
NC_PCI_AD<27>
NC_PCI_AD<28>
NC_PCI_AD<29>
NC_PCI_AD<30>
NC_PCI_AD<31>
(DPD)
EHCI2
NVRAM
NOTE: Internal pull-downs on all USB pins
PCI
USB
93
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
BI
35 93
BI
35 93
BI
93 101
BI
93 101
BI
36 93
BI
36 93
External Hub 1
T57
External Hub 2
PP3V3_S5
R2061
PCH_USB_RBIAS
PCH_GPIO59
R2064
R2066
10K
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R20621
R20651
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
10K
10K
19 25
USB_HUB_SOFT_RESET_L
PCH_GPIO41
PCH_GPIO42
PCH_GPIO43
PCH_GPIO9
PCH_GPIO10
PM_LATRIGGER_L
IN
R20601
10K
IN
85 99
6 7 17 18 19 20 21 23 27
31 35 57 66 71 72 73 83
25 35
25
25
25
25
25 46
19 25
R20701
22.6
R2030
R2031
R2032
R2035
R2036
R2037
R2038
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
10K
10K
10K
1
1
1
2
2
2
10K
10K
10K
10K
1
1
1
1
2
2
2
2
5%
5%
5%
5%
5%
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
1/16W MF-LF 402
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
JTAG_GMUX_TMS
JTAG_GMUX_TDI
PCI_REQ3_L
PCH_GPIO2
MIKEY_MIC_LOAD_DET
AUD_I2C_INT_L
1%
1/16W
MF-LF
402 2
19 87
19 87
SYNC_MASTER=K18_MLB
19
PCH PCI/FlashCache/USB
DRAWING NUMBER
19 63
19
Apple Inc.
19 63
10K
10K
1
1
2
2
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
PCH_GPIO59
PM_LATRIGGER_L

19 25
19 25
SIZE
<SCH_NUM> D
REVISION
PP3V3_S5
R2080
R2081
PAGE TITLE
19
<E4LABEL>
BRANCH
<BRANCH>
PAGE
20 OF 132
SHEET
19 OF 101
PP3V3_S0
IPU* = Only on TACH function.

IN
SMC_IG_THROTTLE_L
40 20 8
IN
FW_PLUG_DET_L
IN
GMUX_INT
D37
TACH2/GPIO6 (IPU*)
45 20
IN
SMC_RUNTIME_SCI_L
J32
TACH3/GPIO7 (IPU*)
PCH_FCIM_EN_L
F10
GPIO8
37 20
OUT
63 25 20
47 20 6
42 20
20
20
OUT
IN
JTAG_GMUX_TDO
V3
H3
PCIECLKRQ6*/GPIO45
OUT
AP_PWR_EN
F1
PCIECLKRQ7*/GPIO46
40 20
OUT
FW_PWR_EN
AB6
SDATAOUT1/GPIO48
25 20
OUT
ME_TEMP_ALERT_L
AA4
SATA5GP/GPIO49
94 6
94 6
94
R2130 10K
R2131 10K
R2132 10K
R2133 10K
R2134 10K
R2135 10K
R2136 10K
R2137 10K
R2138 10K
R2139 100K
6 7 17 18 19 21 23 27 31 35 57
66 71 72 73 83 85 99
101
6 7 8 17 31 32 33 34 35 36 48 50 53 54 55
72 73 87
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
2
2
1
1
2
2
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
1/16W
5%
1/16W MF-LF 402
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
1/16W MF-LF 402
1
1
2
2
402
5%
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
1/16W MF-LF 402
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
AUD_IPHS_SWITCH_EN
LPCPLUS_GPIO
ODD_PWR_EN_L
PCH_GPIO24
PCH_VRM_EN
MXM_GOOD
SDCARD_RESET
JTAG_GMUX_TCK
JTAG_GMUX_TDO
PCH_GPIO39
PCH_VSS_NCTF<5>
TP_PCH_VSS_NCTF<7>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<22>
94 6
PCH_VSS_NCTF<25>
94 6
PCH_VSS_NCTF<27>
94 6
PCH_VSS_NCTF<29>
8 20 40
20 87
20 45
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
CPU_PECI
R2155
10K
OUT
10 91
OUT
10 91
T1
PCH_RCIN_L
PROCPWRGD
BE10
CPU_PWRGD
THRMTRIP*
BD10
PCH_THRMTRIP_L
RCIN*
GPIO57
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
VSS_NCTF20
VSS_NCTF21
VSS_NCTF22
VSS_NCTF23
VSS_NCTF24
VSS_NCTF25
VSS_NCTF26
VSS_NCTF27
VSS_NCTF28
VSS_NCTF29
VSS_NCTF30
VSS_NCTF31
(IPD)
5%
1/16W
MF-LF
2 402
PP1V05_S0
BI
10 91
R2160
56
OUT
10 25 91
R2161
1
56
5%
1/16W
MF-LF
2 402
PM_THRMTRIP_L
10 46 91
IN
5%
1/16W
MF-LF
402
BA22
NC_PCH_TP1
TP2
AW22
NC_PCH_TP2
TP3
BB22
NC_PCH_TP3
TP4
AY45
NC_PCH_TP4
(DPL_B_MON1_N)
TP5
AY46
NC_PCH_TP5
(DPL_B_MON1_P)
TP6
AV43
NC_PCH_TP6
(DPL_B_MON2_N)
TP7
AV45
NC_PCH_TP7
(DPL_B_MON2_P)
TP8
AF13
NC_PCH_TP8
(SATA_OB_ANA)
TP9
M18
NC_PCH_TP9
TP10
N18
NC_PCH_TP10
TP11
AJ24
NC_PCH_TP11
TP12
AK41
NC_PCH_TP12
(XCKPLL_MON1_N)
TP13
AK42
NC_PCH_TP13
(XCKPLL_MON1_P)
TP14
M32
NC_PCH_TP14
TP15
N32
NC_PCH_TP15
TP16
M30
NC_PCH_TP16
TP17
N30
NC_PCH_TP17
TP18
H12
NC_PCH_TP18
TP19
AA23
NC_PCH_TP19
NC_1
NC_2
NC_3
NC_4
NC_5
AB45
AB38
AB42
AB41
T39
NC_PCH_NC1
NC_PCH_NC2
NC_PCH_NC3
NC_PCH_NC4
NC_PCH_NC5
P6
TP_PCH_INIT3V3_L
C10
NC_PCH_SST
TP24
6 7 10 12 13 15 17 18 21 23 24
25 26 40 70 73 86
TP1
INIT3_3V*
10K
5%
1/16W
MF-LF
402 2
B
6
6
6
6
6
20
20 37
20
20 25 63
6 20 47
20 42
20
20
20
20 25 34
SYNC_MASTER=K17_REF
20 25 87
PAGE TITLE
PCH MISC
20 87
20
20 73
Apple Inc.
1/16W MF-LF 402
AP_PWR_EN
5%
20 25 45 46
PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
BG10
R21501
DRAWING NUMBER
WOL_EN
5%
MF-LF
SMC_RUNTIME_SCI_L
PCH_FCIM_EN_L
ENET_LOW_PWR
PCH_GPIO15
SDATAOUT0/GPIO39
WOL_EN
94 6
GMUX_INT
P3
OUT
94 6
1/16W MF-LF 402
PCH_GPIO39
F8
FSB_CLK133M_CPU_N
FSB_CLK133M_CPU_P
SLOAD/GPIO38
73 33 20
94 6
5%
SATACLKREQ*/GPIO35
SATA3GP/GPIO37
94 6
STP_PCI*/GPIO34
SATA2GP/GPIO36
94 6
M11
AB7
94
1/16W MF-LF 402

1/16W MF-LF 402
TP_PCH_STP_PCI_L
AB13
94 6
5%
5%
GPIO28 (IPU)
JTAG_GMUX_TCK
94 6
SMC_IG_THROTTLE_L
FW_PLUG_DET_L
V13
SPIROM_USE_MLB
AM3
AM1
GPIO27
SDCARD_RESET
BI
PCH_A20GATE
MEM_LED/GPIO24
ISOLATE_CPU_MEM_L
V6
U2
A20GATE
PECI
SCLOCK/GPIO22
OUT
94 6
2
2
AB12
CLKOUT_BCLK0_N/CLKOUT_PCIE8N
CLKOUT_BCLK0_P/CLKOUT_PCIE8P
TACH0/GPIO17 (IPU*)
OUT
57 47 20 6
1
1
PCH_VRM_EN
Y7
H10
AF48
AF47
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
SATA4GP/GPIO16
34 25 20
73 20
R2110 10K
R2111 10K
R2112 20K
R2113 10K
R2114 10K
R2115 2.2K
R2116 10K
R2120 10K
R2121 10K
R2122 10K
R2123 10K
R2124 10K
PCH_GPIO24
MXM_GOOD
OUT
20
PP3V3_S5
PP3V3_S3
PP3V3_S0
GPIO15 (IPD)
87 25 20
87 20
T7
ODD_PWR_EN_L
OUT
20
31 25
PCH_GPIO15
F38
CLKOUT_PCIE7N
CLKOUT_PCIE7P
MISC
(IPU)
LAN_PHY_PWR_CTRL/GPIO12
LPCPLUS_GPIO
BI
FCBGA
(6 OF 10)
K9
AA2
IBEX_PEAK_M
ENET_LOW_PWR
AUD_IPHS_SWITCH_EN
OUT
U1800
AH45
AH46
CPU
20
TACH1/GPIO1 (IPU*)
CLKOUT_PCIE6N
CLKOUT_PCIE6P
GPIO
20
C38
OMIT
BMBUSY*/GPIO0
RSVD
87 20
Y3
NCTF
46 45 25 20
20 33 73
<E4LABEL>
1/16W MF-LF 402
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
1/16W MF-LF 402
FW_PWR_EN
ME_TEMP_ALERT_L
SPIROM_USE_MLB
20 40

20 25
6 20 47 57
SIZE
<SCH_NUM> D
REVISION
BRANCH
<BRANCH>
PAGE
21 OF 132
SHEET
20 OF 101
OMIT
OMIT
U1800
U1800
IBEX_PEAK_M
20%
2 10V
CERM
402
VOLTAGE=1.05V
PP1V05_S0
1849 mA S0, 700 mA M-on
(VCCME[1-16] total)
AD38
AD39
AD41
AF43
AF41
AF42
V39
V41
V42
Y39
Y41
Y42
PLACE_NEAR=U1800.Y20:2.54MM
PCH output, for decoupling only

PPVOUT_G3_PCH_DCPRTC
1
C2210
20%
10V
2 CERM
402
PP1V05_S0_PCH_VCCADPLLA
68 mA
24
V9
VOLTAGE=X.XV
PP1V8_S0
164 mA (VCCVRM[1-4] total)
23 21 16 12 7 6
87 72 71 58 24
0.1UF
Y20
PLACE_NEAR=U1800.V9:2.54MM
PP1V05_S0_PCH_VCCADPLLB
69 mA
3062 mA (VCCIO[1-56] total)
26 25 24 23
PP1V05_S0
13 12 10 7 6
21 20 18 17 15
DCPSUSBYP
VCCME1
VCCME2
VCCME3
VCCME4
VCCME5
VCCME6
VCCME7
VCCME8
VCCME9
VCCME10
VCCME11
VCCME12
DCPRTC
AU24
VCCVRM3
BB51
BB53
VCCADPLLA1
VCCADPLLA2
BD51
BD53
VCCADPLLB1
VCCADPLLB2
AH23
AJ35
AH35
VCCIO21
VCCIO22
VCCIO23
24
R2225
1
0.2
PP1V05_S0_PCH_VCCIO_SSC_FLT
1%
1/6W
MF
402-HF
C2225 1
VOLTAGE=1.05V
20%
4V
X5R 2
402
115 mA
AF34
AH34
AF32

PPVOUT_S0_PCH_DCPSST
0.1UF
VOLTAGE=X.XV
1
VCCIO2
VCCIO3
VCCIO4
V12
DCPSST
Y22
DCPSUS
VOLTAGE=X.XV

PPVOUT_S5_PCH_DCPSUS
C2220
20%
10V
2 CERM
402
V23
PP1V05_S0
V5REF_SUS
F24
PP5V_S5_PCH_V5REFSUS
< 1 mA S0-S5
V5REF
K49
PP5V_S0_PCH_V5REF
< 1 mA
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
J38
L38
M36
N36
P36
U35
VCC3_3_14
AD13
4.7UF
VCCIO56
PCI/GPIO/LPC
86 73 70 40
C2230
0.1UF
20%
10V
402
PP3V3_S5
163 mA S0, 65 mA S3-S5
(VCCSUS3_3[1-32] total)
PP1V05_S0
AK24
PP1V05_S0_PCH_VCCAPLL_EXP
40 mA (if GPIO27 is low)
BJ24
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VCCIO41
VCCIO42
VCCIO43
VCCIO44
VCCIO45
VCCIO46
VCCIO47
VCCIO48
VCCIO49
VCCIO50
VCCIO51
VCCIO52
VCCIO53
AN30
AN31
VCCIO54
VCCIO55
PP3V3_S0
357 mA (VCC3_3[1-14] total)
AN35
VCC3_3_1
PP1V8_S0
AT22
VCCVRM1
PP1V05_S0_PCH_VCCAPLL_FDI
BJ18
VCCFDIPLL
PP1V05_S0
AM23
VCCIO1
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
23
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP1V05_S0
3062 mA
(VCCIO[1-56] total)
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
23
23
PP3V3_S0
357 mA
(VCC3_3[1-14] total)
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
48 50 51 52 54 58 62 63 68 69
PP3V3_S0
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47
357 mA (VCC3_3[1-14] total) 72 73 80 83 84 85 87 88 99
2 CERM
PLACE_NEAR=U1800.Y22:2.54MM
VCCSATAPLL1
VCCSATAPLL2
49 48 47 46 45 43 23 17 7 6
73 66 65 64 53
PP1V05_S0
< 1 mA
VCC3_3_5
VCC3_3_6
VCC3_3_7
AT18
AU18
PP3V42_G3H
2 mA S0-S5, ~6 uA G3
A12
V_CPU_IO1
V_CPU_IO2
VCCRTC
VCCIO9
SATA
V15
V16
Y16
PCI/GPIO/LPC
VCCSUS3_3_29
VCCSUS3_3_30
VCCSUS3_3_31
VCCSUS3_3_32
CPU
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP3V3_S0
357 mA
P18
U19
U20
U22
HDA
99
68 63 62 58 54 52 51 50 48 47
25 24 23 21 20 19 18 17 7 6
46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
PP3V3_S5
163 mA S0, 65 mA S3-S5
(VCCSUS3_3[1-32] total)
RTC
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
AK3
AK1
AH22
VCCVRM4
AT20
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
AH19
AD20
AF22
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
VCCME13
VCCME14
VCCME15
VCCME16
AA34
Y34
Y35
AA35
VCCSUSHDA
L30
PP1V05_S0_PCH_VCCAPLL_SATA
PP1V05_S0
23
99
68 63 62 58 54 52 51 50 48 47
25 24 23 21 20 19 18 17 7 6
46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
72 71 58 24 23 21 16 12 7 6
87
PP1V8_S0
6
VCC CORE
CRT
0.1UF
73 70 40 26 25 24
15 13 12 10 7 6
23 21 20 18 17
86
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
U23
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
LVDS
C2200
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS3_3_7
VCCSUS3_3_8
VCCSUS3_3_9
VCCSUS3_3_10
VCCSUS3_3_11
VCCSUS3_3_12
VCCSUS3_3_13
VCCSUS3_3_14
VCCSUS3_3_15
VCCSUS3_3_16
VCCSUS3_3_17
VCCSUS3_3_18
VCCSUS3_3_19
VCCSUS3_3_20
VCCSUS3_3_21
VCCSUS3_3_22
VCCSUS3_3_23
VCCSUS3_3_24
VCCSUS3_3_25
VCCSUS3_3_26
VCCSUS3_3_27
VCCSUS3_3_28
FCBGA
(7 OF 10)
VCCADAC1
VCCCORE1
VCCADAC2
VCCCORE2
VCCCORE3
VSSA_DAC1
VCCCORE4
VSSA_DAC2
VCCCORE5
VCCCORE6
VCCCORE7
VCCCORE8
VCCCORE9
VCCCORE10
VCCCORE11
VCCALVDS
VCCCORE12
VCCCORE13
VSSA_LVDS
VCCCORE14
VCCCORE15
VCCTX_LVDS1
VCCTX_LVDS2
VCCIO24
VCCTX_LVDS3
VCCTX_LVDS4
VCCAPLLEXP
PP1V05_S0
1432 mA
HVCMOS
1
VCCLAN1
VCCLAN2
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
7 12 16 21 23 24 58 71 72 87
23
GPIO27
HDA_SYNC
VccVRM
PLLs
1 (IPU)
1 (IPU)
0
0 (IPD)
1
X
1.8V
1.5V
1.05V
Float
Float
1.05V
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
AE50
AE52
PP3V3_S0_PCH_VCCA_DAC
69 mA
24
AF53
AF51
PP3V3_S0
< 1 mA
AH38
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
AH39
AP43
AP45
AT46
AT45
PP1V8_S0_PCH_VCCTX_LVDS
59 mA
PP3V3_S0
357 mA
VCC3_3_2
VCC3_3_3
VCC3_3_4
AB34
AB35
AD35
VCCVRM2
AT24
PP1V8_S0
VCCDMI1
VCCDMI2
AT16
AU16
PP1V05_S0
61 mA (1.1V)
58 mA (1.05V)
VCCPNAND1
VCCPNAND2
VCCPNAND3
VCCPNAND4
VCCPNAND5
VCCPNAND6
VCCPNAND7
VCCPNAND8
VCCPNAND9
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
VCCME3_3_1
VCCME3_3_2
VCCME3_3_3
VCCME3_3_4
AM8
AM9
AP11
AP9
PCI-E*
DMI

PPVOUT_S5_PCH_DCPSUSBYP
AF23
AF24
V24
V26
Y24
Y26
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
NAND / SPI
GND
320 mA S0, 67 mA M-on
IBEX_PEAK_M
PP1V05_S0
VCCIO5
VCCIO6
VCCIO7
VCCIO8
USB
AP51
AP53
FCBGA
(10 OF 10)
VCCACLK1
VCCACLK2
CLOCK AND MISCELLANEOUS
PP1V05_S0_PCH_VCCA_CLK
52 mA
23
FDI
24
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
6 7 12 16 21 23 24 58 71 72 87
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
PP1V8_S0
6 7 12 16 21 23 24 58 71
156 mA (1.8V)
NOTE: Connect to 3.3V if NAND not used.
72 87
B
PP3V3_S0
85 mA S0, 22 mA M-on
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
Note: 1.5V option consumes more current than 1.8V

PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL
PP1V05_S0
1849 mA S0, 700 mA M-on
(VCCME[1-16] total)
PP3V3_S0
6 mA S0, < 1 mA S3-S5
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
58 62 63 68 69 72 73 80 83 84
30 34
6 7 17
18 19 20 21 23 24 25 26 27 28
37 40 42 46 47 48 50 51 52 54
85 87 88 99
Verify S0 okay
SYNC_MASTER=K17_REF
PAGE TITLE
PCH Power
DRAWING NUMBER
Apple Inc.
R
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3).

Pre-Silicon Mobile Estimates.
SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
22 OF 132
SHEET
21 OF 101
6
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
OMIT
U1800
IBEX_PEAK_M
FCBGA
(9 OF 10)
VSS
VSS
2
AB16
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
OMIT
U1800
IBEX_PEAK_M
FCBGA
(8 OF 10)
VSS
VSS
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
SYNC_MASTER=K17_REF
PAGE TITLE
PCH Grounds
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
23 OF 132
SHEET
22 OF 101
8
85 83
57 35
20 19 18 17 7
72 71 6627 23
99
72 66 7
73
31
6
21
6
PCH V5REF_SUS Filter & Follower

(PCH Reference for 5V Tolerance on USB)
10
D2400
NC
1UF
10%
6.3V 2
CERM
402
PP5V_S5_PCH_V5REFSUS 21
1 mA S0-S5
C2400
87 72 71 58 24 21 16 12 7 6
C2420 1
SOT-363
VOLTAGE=5V
C2421
0.1UF
10%
16V
2 X5R
402
PLACE_NEAR=U1800.AK13:2.54MM
66
21
6
18
31
73
PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)
1
R24012
100
D2400
NC
BAT54DW-X-G
NC
5%
1/16W
MF-LF
402 1
SOT-363
163 mA S0 /
65 mA S3-S5
PP5V_S0_PCH_V5REF
C2401
VOLTAGE=5V
PLACE_NEAR=U1800.K49:2.54MM
21
1UF
10%
10V 2
X5R
402
PLACE_NEAR=U1800.AB24:2.54MM
1
0.1UF
10%
16V
2 X5R
402
C2470
10UF
20%
6.3V 2
X5R
603
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PLACE_NEAR=U1800.L30:2.54MM
C2445
0.1UF
PP1V05_S0
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
10%
2 6.3V
CERM
402
C2425
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
C2450 1
4.7UF
C2426
0.1UF
10%
2 16V
X5R
402
20%
6.3V 2
X5R
603
PLACE_NEAR=U1800.U23:2.54MM
1
C2427
0.1UF
C2476
1UF
10%
2 6.3V
CERM
402
C2477
1UF
10%
2 6.3V
CERM
402
PLACE_NEAR=U1800.AT18:2.54MM
1
C2451
0.1UF
10%
2 16V
X5R
402
C2452
0.1UF
PCH VCCIO BYPASS

(PCH USB 1.05V PWR)
10%
2 16V
X5R
402
PP1V05_S0
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
10%
2 16V
X5R
402
PLACE_NEAR=U1800.AH23:2.54MM
PLACE_NEAR=U1800.AH35:2.54MM
PP1V05_S0
PP3V3_S5
C2475
10%
2 6.3V
CERM
402
PCH V_CPU_IO BYPASS

(PCH 1.1V/1.05V CPU I/O PWR)
PLACE_NEAR=U1800.A26:2.54MM
1UF
PCH USB/VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)
1UF
D
1UF
C2471
10%
6.3V
2 CERM
402
PCH VCCIO BYPASS

(PCH CLK 1.05V PWR)
PP3V3_S0
PP3V3_S5
10%
2 16V
X5R
402
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
1 mA
C2440
PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)
PLACE_NEAR=U1800.P18:2.54MM
PP3V3_S0
PP5V_S0
1 mA
10%
2 16V
X5R
402
0.1UF
PCH VCCSUS3_3 BYPASS

(PCH SUSPEND PCI 3.3V PWR)
99
72 71
27 23
17 7
20 19
57 35
85 83
PP1V05_S0
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
C2422
(VCCSUS3_3 Total)
88 87 85
73 72 69
68 63 62
58 54 52
51 50 48
47 46 42
9940 37 34
8030 28 27
18 17 7 6
24 23 21
88
47 42 7 6
70 69 68
1
PCH VCCCORE BYPASS
(PCH 1.05V CORE PWR)
PP1V8_S0
1
1UF
10%
10V 2
X5R
402
PCH VCCPNAND BYPASS

(PCH NAND 1.8V/3.3V PWR)
PP3V42_G3H
2 mA S0-S5 /
6 uA G3
BAT54DW-X-G
NC
5%
1/16W
MF-LF
402 1
49 48 47 46 45 43 21 17 7 6
73 66 65 64 53
R2400
54 52
86 72
PCH VCCRTC BYPASS

(PCH RTC 3.3V PWR)
PP3V3_S5
PP5V_S5
1 mA S0-S5
2
84 83
20 19
26 25
C2480
1UF
10%
2 6.3V
CERM
402
PCH VCCIO BYPASS

(PCH DMI 1.05V PWR)
PCH VCCME3_3 BYPASS
(PCH ME 3.3V PWR)
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP1V05_S0
PP3V3_S0
PLACE_NEAR=U1800.AM8:2.54MM
10%
2 6.3V
CERM
402
C2430
0.1UF
PCH VCCIO BYPASS

(PCH SATA 1.05V PWR)
C2455
1UF
PP1V05_S0
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
10%
2 16V
X5R
402
1UF
PCH CORE/VCC3_3 BYPASS

(PCH MISC 3.3V PWR)
GND
NO STUFF
PP3V3_S0
10%
2 6.3V
CERM
402
C2435
0.1UF
10%
2 16V
X5R
402
21
99
88 87 85 84 83 80 73 72 69
68 63 62 58 54 52 51 50 48
47 46 42 40 37 34 30 28 27 26
25 24 23 21 20 19 18 17 7 6
PP1V05_S0_PCH_VCCAPLL_EXP
C2490 1
VOLTAGE=1.05V
PLACE_NEAR=U1800.BJ24:2.54MM
OMIT
1
PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)
WF: C2311 not in DG or CRB
C2413
PLACE_NEAR=U1800.J38:2.54MM
99
88 87 85 84 83 80 73 72 69
68 63 62 58 54 52 51 50 48
47 46 42 40 37 34 30 28 27 26
25 24 23 21 20 19 18 17 7 6
PP1V05_S0_PCH_VCCAPLL_FDI
OMIT
1
C2415
1UF
BB: C2417 removed from DG

NO STUFF
1
C2417
C2494
1UF
10%
2 6.3V
CERM
402
22UF
20%
6.3V
X5R-CERM 2
603
22UF
20%
6.3V
X5R-CERM 2
603
C2468
1UF
C2469
1UF
10%
2 6.3V
CERM
402
C2437
PP3V3_S0
PLACE_NEAR=U1800.AN35:2.54MM
C2438
0.1UF
10%
2 16V
X5R
402
PCH VCCACLK Filter

(PCH Misc PLL PWR)
PCH VCC3_3 BYPASS

(PCH CLK/HVCMOS 3.3V PWR)
85 84 83 80 73 72 69 68
42 40 37
18 17 7
30 28 27 26 25 24 23 21 20
62 58 54 52 51 50 48 47
99 88
PP1V05_S0_PCH_VCCA_CLK
BB: C2419 removed from DG

NO STUFF
1
C2419
63
34
6
19
46
87
SYNC_MASTER=K17_REF
PP3V3_S0
PAGE TITLE
1UF
PCH Non-GFX Decoupling
C2439
DRAWING NUMBER
0.1UF
10%
2 6.3V
CERM
402
10%
2 16V
X5R
402
Apple Inc.

SIZE
<SCH_NUM> D
REVISION
PCH VCC3_3 BYPASS

(PCH PCIe/DMI 3.3V PWR)
63
34
6
19
46
87
1UF
C2493
10%
2 6.3V
CERM
402
0.1UF
85 84 83 80 73 72 69 68
42 40 37
18 17 7
30 28 27 26 25 24 23 21 20
62 58 54 52 51 50 48 47
99 88
PP1V05_S0_PCH_VCCAPLL_SATA
VOLTAGE=1.05V
PLACE_NEAR=U1800.AP51:2.54MM
10%
2 16V
X5R
402
10%
2 6.3V
CERM
402
21
1UF
PP3V3_S0
PLACE_NEAR=U1800.AD13:2.54MM
PCH VCCSATAPLL Filter

(PCH SATA PLL PWR)
C2492
10%
2 6.3V
CERM
402
WF: C2413 not in DG or CRB
1UF
VOLTAGE=1.05V
PLACE_NEAR=U1800.AK1:2.54MM
PCH VCC3_3 BYPASS

(PCH SATA 3.3V PWR)
10%
2 6.3V
CERM
402
21
10%
2 6.3V
CERM
402
10%
2 16V
X5R
402
PCH VCCFDIPLL Filter

(PCH FDI PLL PWR)
VOLTAGE=1.05V
PLACE_NEAR=U1800.BJ18:2.54MM
20%
6.3V
X5R-CERM 2
603
22UF
10%
2 6.3V
CERM
402
1
C2436
C2491
1UF
20%
6.3V 2
X5R
603
PP1V05_S0
C2465 1 C2466 1 C2467 1

0.1UF
10%
2 6.3V
CERM
402
21
PP1V05_S0
10UF
1UF
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP3V3_S0
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PCH VCCME BYPASS

(PCH 1.05V ME Core PWR)
PCH VCCAPLLEXP Filter
(PCH PCIe PLL PWR)
PCH VCCIO BYPASS

(PCH PCIE 1.05V PWR)
C2460
1UF
C2485
10%
2 6.3V
CERM
402
PCH VCCLAN BYPASS

(PCH 1.05V LAN Core PWR)
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
<E4LABEL>
BRANCH
<BRANCH>
PAGE
24 OF 132
SHEET
23 OF 101
GFX (CPU VCCAXG) DECOUPLING

3x 330uF 6 mOhm (2 stuffed), 3x 22uF 0603, 16x 1uF 0402
PPVCORE_S0_GFX
69 49 13 7 6

1
C2500
22UF
C2501
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 6.3V
X5R-CERM
603
C2502
22UF
20%
2 6.3V
X5R-CERM
603
C2505
330UF
C2506
330UF
20%
3 2 2.0V
POLY-TANT
D2T-SM2
20%
3 2 2.0V
POLY-TANT
D2T-SM2
1
C2524
1UF
C2525
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C2526
1UF
C2527
1UF
10%
2 10V
X5R
402
C2528
1UF
10%
2 10V
X5R
402
C2529
1UF
10%
2 10V
X5R
402
C2530
1UF
10%
2 10V
X5R
402
C2531
1UF
10%
2 10V
X5R
402
C2532
1UF
10%
2 10V
X5R
402
C2533
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C2534
1UF
10%
2 10V
X5R
402
C2535
1UF
10%
2 10V
X5R
402
C2536
1UF
C2537
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C2538
1UF
10%
2 10V
X5R
402
C2539
1UF
10%
2 10V
X5R
402

5x 1uF 0402
13 7

1
C2510
1UF
10%
2 10V
X5R
402
C2511
1UF
10%
2 10V
X5R
402
C2512
1UF
10%
2 10V
X5R
402
C2513
1UF
C2514
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F
PLACE_NEAR=U1800.AE50:2.54MM
69 68 63 62 58 54 52 51 50 48
26 25 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73 72
L2550
R2550
PP3V3_S0
69 mA
5%
1/16W
MF-LF
402
PCH VCCADAC Filter

(PCH DAC PLL PWR)
180-OHM-1.5A
PP3V3_S0_PCH_VCCA_DAC_F
69 mA
VOLTAGE=3.3V
PP3V3_S0_PCH_VCCA_DAC
VOLTAGE=3.3V
2
0603
C2550 1
10UF
20%
6.3V 2
X5R
603
actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
C2551
0.1UF
10%
2 16V
X5R
402
C2552
21
69 mA
0.01UF
20%
2 16V
CERM
402
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 23
R2560
PP1V05_S0
137 mA
10UH-0.12A-0.36OHM
1
2
PP1V05_S0_PCH_VCCADPLLA_F
0603
68 mA
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
PCH VCCADPLLA Filter

(PCH DPLLA PWR)
L2560
C2560 1
220UF
20%
2.5V 2
POLY-TANT
CASE-B2-SM1
PP1V05_S0_PCH_VCCADPLLA
VOLTAGE=1.05V
21
68 mA
NO STUFF
C2561
PLACE_NEAR=U1800.BB51:2.54MM
1UF
10%
2 6.3V
CERM
402
PLACE_NEAR=U1800.BB51:2.54MM
R2565
1
5%
1/16W
MF-LF
402
PCH VCCADPLLB Filter

(PCH DPLLB PWR)
L2565
10UH-0.12A-0.36OHM
1
2
PP1V05_S0_PCH_VCCADPLLB_F
0603
69 mA
VOLTAGE=1.05V
C2565 1
220UF
20%
2.5V 2
POLY-TANT
CASE-B2-SM1
PP1V05_S0_PCH_VCCADPLLB
VOLTAGE=1.05V
21
69 mA
NO STUFF
C2566
PLACE_NEAR=U1800.BD51:2.54MM
1UF
10%
2 6.3V
CERM
402
PLACE_NEAR=U1800.BD51:2.54MM
L2570
87 72 71 58 23 21 16 12 7 6
PCH VCCTX_LVDS Filter

(PCH LVDS TX PWR)
0.1UH
PP1V8_S0
59 mA
PP1V8_S0_PCH_VCCTX_LVDS
VOLTAGE=1.8V
2
0805
C2570 1
22UF
20%
6.3V
X5R-CERM 2
603
C2571
0.01UF
20%
16V
2 CERM
402
C2572
21
59 mA
0.01UF
20%
16V
2 CERM
402
SYNC_MASTER=K17_REF
PAGE TITLE
CPU/PCH GFX Decoupling
DRAWING NUMBER
Apple Inc.
R
<E4LABEL>
Design recommendations from Calpella Design Guide Rev 1.5 (doc #398905) Section 3.25.3 tables 161 and 162.

SIZE
<SCH_NUM> D
REVISION
BRANCH
<BRANCH>
PAGE
25 OF 132
SHEET
24 OF 101
Calpella Processor mini XDP

21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 24 23
PP1V05_S0
XDP_CPU_BPM
CRITICAL
OMIT
RP2600
91 10
IN
91 10
IN
91 10
IN
91 10
IN
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
1
2
0
5%
1/16W
SM-LF
3
4
LTH-030-01-G-D-NOPEGS
F-ST-SM
5
91 10
XDP_CPU_CFG
91 10
RP2601
91 9
91 9
IN
IN
91 9
IN
91 9
IN
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
0
5%
1/16W
SM-LF
2
1
BI
IN
XDP_PREQ_L
XDP_PRDY_L
OBSDATA_A0
OBSDATA_A1
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
XDP_OBSDATA_A<2>
XDP_OBSDATA_A<3>
XDP
R2610
IN
OBSFN_A0
OBSFN_A1
XDP_OBSDATA_A<0>
XDP_OBSDATA_A<1>
OBSDATA_A2
OBSDATA_A3
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs.
91 20 10
CPU_PWRGD
1K
91 9
IN
91 9
IN
91 10
IN
91 10
IN
91 10
IN
91 10
IN
5%
1/16W
MF-LF
402
45 25 18
91 10
OUT
IN
63 48 47 42 32 30 28 26 25 17
94 88
BI
63 48 47 42 32 30 28 26 25 17
94 88
BI
91 10
OUT
CPU_CFG<17>
CPU_CFG<16>
OBSFN_B0
OBSFN_B1
XDP_BPM_L<4>
XDP_BPM_L<5>
OBSDATA_B0
OBSDATA_B1
XDP_BPM_L<6>
XDP_BPM_L<7>
OBSDATA_B2
OBSDATA_B3
XDP_PWRGD
PM_PWRBTN_L
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
XDP_CPUPWRGD
TP_XDP_HOOK3
SMBUS_PCH_DATA
SMBUS_PCH_CLK
SDA
SCL
TCK1
TCK0
XDP_TCK
XDP_NORMAL&XDP_CPU
10
OUT
JTAG_CPU_TDI
XDP_CPU
IN
JTAG_CPU_TDO
XDP_NORMAL
R2691
0
5%
1/16W
MF-LF
402 2
OUT
IN
OBSFN_C0
OBSFN_C1
CPU_CFG<8>
CPU_CFG<9>
IN
9 91
IN
9 91
OBSDATA_C0
OBSDATA_C1
CPU_CFG<0>
CPU_CFG<1>
IN
9 91
IN
9 91
OBSDATA_C2
OBSDATA_C3
CPU_CFG<2>
CPU_CFG<3>
IN
9 91
IN
8 9 91
OBSFN_D0
OBSFN_D1
CPU_CFG<10>
CPU_CFG<11>
IN
9 91
IN
9 91
OBSDATA_D0
OBSDATA_D1
CPU_CFG<4>
CPU_CFG<5>
30
29
32
31
IN
9 91
IN
34
33
9 91
OBSDATA_D2
OBSDATA_D3
CPU_CFG<6>
CPU_CFG<7>
36
35
38
37
IN
9 91
IN
40
39
9 91
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
FSB_CLK133M_ITP_P
ITPCLK/HOOK4
IN 10 91
FSB_CLK133M_ITP_N
ITPCLK#/HOOK5
IN 10 91
VCC_OBS_CD
91 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
OUT 10 25 27 91
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO
25 91
TDO
XDP_TRST_L
TRSTn
OUT 10 91
XDP_TDI
TDI
25 91
XDP_TMS
TMS
OUT 10 91
XDP_PRESENT#
XDP
516S0852
XDP
R2611
1
1K
5%
1/16W
MF-LF
402
FSB_CPURST_L
IN 10 91
PLACE_NEAR=U1000.N70:1.00MM
C2601
0.1uF
10%
2 16V
X5R
402
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
J2600
CRITICAL
XDP_CONN_CPU
TABLE_5_ITEM
516S0852
CONN,PLUG,B2B,60P,0.5MM,NOPEG
25 91
Calpella PCH mini XDP
R2696
JTAG_GMCH_TDI
XDP_NORMAL&XDP_GMCH
JTAG_GMCH_TDO
5%
1/16W
MF-LF
2 402
10%
16V 2
X5R
402
25 91
XDP_GMCH
R2692
10
51
5%
1/16W
MF-LF
402
10
XDP_TDI
XDP_TDO
NC
0.1uF
5%
1/16W
MF-LF
402
R2695
10
R2615
XDP
C2600
R2690
0
XDP
1
J2600
72 69 68 63 62 58 54 52 51 50
26 24 23 21 20 19 18 17 7 6
48 47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73
5%
1/16W
MF-LF
402
PP3V3_S0
CRITICAL
XDP_CONN_PCH
J2650
5%
1/16W
MF-LF
402
DF40C-60DS-0.4V
F-ST-SM-HF
TP_XDPPCH_OBSFN_A<0>
TP_XDPPCH_OBSFN_A<1>
PCH OC0#
PCH OC1#
PCH OC2#
PCH OC3#
19
IN
35 19
IN
19
IN
19
IN
PCH_GPIO59
OBSDATA_A0
OBSDATA_A1
PCH_GPIO41
PCH_GPIO42
OBSDATA_A2
OBSDATA_A3
TP_XDPPCH_OBSFN_B<0>
TP_XDPPCH_OBSFN_B<1>
PCH OC4#
PCH OC5#
PCH OC6#
PCH OC7#
19
IN
19
IN
46 19
IN
19
IN
87 73 45 27
IN
45 25 18
PCH_GPIO43
PCH_GPIO9
PCH_GPIO10
PM_LATRIGGER_L
ALL_SYS_PWRGD
PM_PWRBTN_L
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
63 48 47 42 32 30 28 26 25 17
94 88
63 48 47 42 32 30 28 26 25 17
94 88
17
OUT
OBSFN_A0
OBSFN_A1
SMBUS_PCH_DATA
SMBUS_PCH_CLK
JTAG_PCH_TCK
OBSFN_B0
OBSFN_B1
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
OBSFN_C0
OBSFN_C1
ISOLATE_CPU_MEM_L
SMC_IG_THROTTLE_L
IN
20 31
IN
20 45 46
OBSDATA_C0
OBSDATA_C1
FW_CLKREQ_L
AP_CLKREQ_L
IN
17 40
IN
17 33
OBSDATA_C2
OBSDATA_C3
SATARDRVR_A_EN
SATARDRVR_B_EN
IN
17 42
IN
17
OBSFN_D0
OBSFN_D1
TP_XDPPCH_OBSFN_D<0>
TP_XDPPCH_OBSFN_D<1>
OBSDATA_D0
OBSDATA_D1
SDCARD_RESET
JTAG_GMUX_TCK
IN
20 34
IN
20 87
OBSDATA_D2
OBSDATA_D3
AUD_IPHS_SWITCH_EN
ME_TEMP_ALERT_L
IN
20 63
IN
20
TP_XDPPCH_HOOK4
ITPCLK/HOOK4
TP_XDPPCH_HOOK5
ITPCLK#/HOOK5
VCC_OBS_CD
XDPPCH_PLTRST_L
RESET#/HOOK6
IN 27
XDP_DBRESET_L
10 25 27 91
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
JTAG_PCH_TDO
TDO
IN 17
TP_XDPPCH_TRST_L
TRSTn
JTAG_PCH_TDI
TDI
OUT 17
JTAG_PCH_TMS
TMS
OUT 17
XDP_PRESENT#
PCH GPIO28
PCH GPIO0
PCH GPIO20
PCH GPIO18
PCH GPIO21
PCH GPIO19
PCH GPIO36
PCH GPIO37
PCH GPIO16
PCH GPIO49
1K series R on PCH Support Page
SYNC_MASTER=K17_REF
PAGE TITLE
eXtended Debug Port (XDP)
518S0774
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
26 OF 132
SHEET
25 OF 101
L2700
72 69 68 63 62 58 54 52 51 50
25 24 23 21 20 19 18 17 7 6
48 47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73
PLACE_NEAR=L2700.2:2 mm:NO_VIA
PLACE_NEAR=U2700.1:2 mm
FERR-120-OHM-1.5A
1
2
PP3V3_S0_CK505_F
PP3V3_S0
VOLTAGE=3.3V
0402
C2700
10UF
L2710
21 20 18 17 15 13 12 10 7 6
86 73 70 40 25 24 23
10%
16V
2 X5R
402
VOLTAGE=1.05V
0402
C2710
C2706
0.1UF
10%
16V
2 X5R
402
C2707
0.1UF
10%
16V
2 X5R
402
C2708
0.1UF
10%
16V
2 X5R
402
C2709
0.1UF
10%
16V
2 X5R
402
PLACE_NEAR=L2710.2:2 mm:NO_VIA
FERR-120-OHM-1.5A
1
2
PP1V05_S0_CK505_F
PP1V05_S0
C2705
0.1UF
20%
6.3V
X5R 2
603
10UF
C2715
0.1UF
20%
6.3V 2
X5R
603
10%
2 16V
X5R
402
C2716
0.1UF
10%
2 16V
X5R
402
R2790
29
24
17
REF_FS 30
USB 8
XIN
XOUT
C2790 1
88 63 48 47 42 32 30 28 25 17
94
0.1UF
CPUIMVP_CLK_EN_L
5
1
74HC1G00GWDG
SC70-5
4
88 63 48 47 42 32 30 28 25 17
94
IN
SMBUS_PCH_CLK
32
SCLK
BI
SMBUS_PCH_DATA
31
SDATA
CK505_CKPWRGD
25
CK_PWRGD/PWRDWN*
CK505_27MHZ_EN_L
16
27MHZ_OE*
U2790
73
IN
VSS_SRC
VSS_27
VSS_DOT
VSS_REF
26
OUT
17 93
OUT
17 93
Unused 48MHz
TP_CK505_CPU1N
TP_CK505_CPU1P
SRC1* 14
SRC1 13
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
OUT
17 93
OUT
17 93
SRC0*/SATA* 11
SRC0/SATA 10
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
OUT
17 93
OUT
17 93
CK505_CLK27M
27M_SS 7
TP_CK505_CLK27M_SS
DOT96* 4
DOT96 3
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
PCH REFCLK 14.31818MHz
PCH BCLK 133MHz

Unused BCLK 133MHz
PCH DMI/PCIe 100MHz
PCH SATA 100MHz
27
GPU 27MHz Clocks (Single-Ended)

OUT
17 93
OUT
17 93
PCH USB Clock 96MHz
THRM
PAD
33
VSS_CPU
17 93
CPU1* 19
CPU1 20
27M_NSS 6
12
OUT
TP_CK505_USB
FSB_CLK133M_PCH_N
FSB_CLK133M_PCH_P
No internal pull.
Must be strapped appropriately
or connected to logic for
Muxed Graphics implementations.
21
PCH_CLK14P3M_REFCLK
CPU0* 22
CPU0 23
SL28776
QFN
28
27
BYPASS=U2790::5 mm
20%
10V
CERM 2
402
IN
(IPD)
CRITICAL
CK505_CLK14P3M_XIN
CK505_CLK14P3M_XOUT
10K
68
NOTE: REF/FS pin is input until first CK_PWRGD rising edge.

FS=0 => 133MHz BCLKs, FS=1 => 100MHz BCLKs
All other output frequencies are fixed.
U2700
5%
1/16W
MF-LF
402 2
VDD_CPU
VDD_SRC
18pF
C2731
5%
50V
2 CERM
402
VDD_REF
5X3.2-SM
1
5%
50V
CERM 2
402
18
PLACE_NEAR=Y2730.2:2 mm:NO_VIA
VDD_27
VDD_DOT
18pF
VDD_CPU_IO
C2730
14.31818
VDD_SRC_IO
Y2730
PLACE_NEAR=Y2730.1:2 mm:NO_VIA
15
CRITICAL
SYNC_MASTER=K17_MLB
PAGE TITLE
Clock (CK505)
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
27 OF 132
SHEET
26 OF 101
Platform Reset Connections
PCH RTC Crystal
Unbuffered
C2810
R2810
R28111
PCH_CLK32K_RTCX2_R
5%
1/16W
MF-LF
402
10M
CRITICAL
Y2810
5%
1/16W
MF-LF
402 2
17
OUT
32.768K
SM-2
NC
NC
40 31 27 19
IN
PLT_RESET_L
R2881
LPCPLUS_RESET_L
OUT
6 27 47 87 94
LPCPLUS_RESET_L
OUT
6 27 47 87 94
SMC_LRESET_L
OUT
45
ENET_RESET_L
OUT
37 95
AP_RESET_L
OUT
33
PCA9557D_RESET_L
OUT
32
XDPPCH_PLTRST_L
OUT
25
MAKE_BASE=TRUE
R2815
12pF
R2816
10M
Y2815
17
OUT
NC
NC
25.0000M
SM-3.2X2.5MM
XDP
R2889
GMUX_RESET_L
BCM5764_CLK25M_XTALO_R
5%
1/16W
MF-LF
402
R2821
10M
CRITICAL
Y2820
5%
1/16W
MF-LF
402 2
95 37
OUT
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
25.0000M
SM-3.2X2.5MM
NC
NC
PP3V3_S0
5
1
BKLT_PLT_RST_L
OUT
89
PLT_RESET_L
OUT
19 27 31 40
R2884
SC70-HF
PLT_RST_BUF_L
27 10
MAKE_BASE=TRUE
C2880 1
R2880
100K
5%
1/16W
MF-LF
2 402
0.1UF
5%
50V
CERM
402
20%
10V
CERM 2
402
SDCARD_PLT_RST_L
OUT
34
PLT_RST_BUF_L
OUT
10 27
5%
1/16W
MF-LF
402
27pF
1
MC74VHC1G08
U2880 4
2
C2821
BCM5764_CLK25M_XTALI
Buffered
5%
50V
CERM
402
2 4
BCM5764_CLK25M_XTALO
NO STUFF
IN
27 87
Series R is R4283
27pF
1
OUT
5%
1/16W
MF-LF
402
C2820
95 37
200
27 87
GMUX_RESET_L
R2893
Caesar II (ENET) 25MHz Crystal

R2820
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
5%
50V
CERM
402
1K
5%
1/16W
MF-LF
402
12pF
PCH_CLK25M_XTALIN
R2887
C2816
5%
1/16W
MF-LF
402
CRITICAL
5%
1/16W
MF-LF
402 2
5%
50V
CERM
402
PCH_CLK25M_XTALOUT_R
5%
1/16W
MF-LF
402
2 4
DCI
R2888
5%
1/16W
MF-LF
402
C2815
R2871
1
PCH_CLK25M_XTALOUT
33
5%
1/16W
MF-LF
402
PCH 25MHz Crystal

IN
R2883
5%
1/16W
MF-LF
402
5%
50V
CERM
402
17
MAKE_BASE=TRUE
R2882
12pF
1
C2811
PCH_CLK32K_RTCX1
33
5%
1/16W
MF-LF
402
5%
50V
CERM
402
2 4
PCH_CLK32K_RTCX2
IN
17
12pF
VTT voltage divider on CPU page
Ethernet WAKE# Isolation

PP3V3_ENET
6 7 37 73
R2825
R2830
Q2830
OUT
PCIE_WAKE_L
3
94 19
5%
1/16W
MF-LF
2 402
G
S
33 18 6
SOD-VESM-HF
10K
SSM3K15FV
PLACE_NEAR=U1800.N52
LPC_CLK33M_SMC_R
ENET_WAKE_L
MAKE_BASE=TRUE
IN
27 37
19
IN
19
IN
IN
LPC_CLK33M_GMUX_R 27
19
LPC_CLK33M_GMUX_R
PCH S0 PWRGD
1
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
C2850
87 73 45 25
68
IN
IN
CPUIMVP_PGOOD
R2851
1
CPUIMVP_PGOOD_R
5%
1/16W
MF-LF
402
IN
XDP_DBRESET_L
U2850
OUT
PM_SYSRST_L
18
BI
6 18 45
87
22
PCH_CLK33M_PCIIN
OUT
17 93
GPU_CLK27M
OUT
79 80 98
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
PAGE TITLE
Chipset Support
OMIT
DRAWING NUMBER
R2897
Apple Inc.
5%
1/16W
MF-LF
2 402
OUT
SYNC_MASTER=K17_REF

SIZE
<SCH_NUM> D
REVISION
SILK_PART=SYS RESET
LPC_CLK33M_GMUX
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
MC74VHC1G08
SC70-HF
4
PM_PCH_PWRGD
6 47 94
10K
XDP
91 25 10
5
1
OUT
R2829
R2824
0
LPC_CLK33M_LPCPLUS
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
22
R2895
R2896
ALL_SYS_PWRGD
CK505_CLK27M
MAKE_BASE=TRUE
20%
2 10V
CERM
402
27 26
45 94
R2826
PLACE_NEAR=U1800.P48
PCH_CLK33M_PCIOUT
CK505_CLK27M
22
OUT
PP3V3_S0
0.1UF
10K
5%
1/16W
MF-LF
402 2
IN
LPC_CLK33M_SMC
PCH Reset Button
PP3V3_S5
PP3V3_S0
R28501
R2827
MAKE_BASE=TRUE
PLACE_NEAR=U2700.6
27 26
57
6
48
6
26
72
22
LPC_CLK33M_LPCPLUS_R
27 19
99 85 83 73 72 71 66
35 31 23 21 20 19 18 17 7
69 68 63 62 58 54 52 51 50
25 24 23 21 20 19 18 17 7
47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73
5%
1/16W
MF-LF
402
ENET_WAKE_L
37 27
IN
<E4LABEL>
BRANCH
<BRANCH>
PAGE
28 OF 132
SHEET
27 OF 101
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes
72 67 31 30 7 6
PP1V5_S3
Power aliases required by this page:

- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
Signal aliases required by this page:
C2900
10UF
- =I2C_SODIMMA_SCL
20%
2 6.3V
X5R
603
- =I2C_SODIMMA_SDA
BOM options provided by this page:
C2911
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
C2912
0.1UF
20%
2 10V
CERM
402
C2913
0.1UF
20%
2 10V
CERM
402
C2914
0.1UF
20%
2 10V
CERM
402
C2915
0.1UF
20%
2 10V
CERM
402
C2916
0.1UF
C2917
0.1UF
20%
2 10V
CERM
402
C2918
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C2919
0.1UF
20%
2 10V
CERM
402
C2920
0.1UF
20%
2 10V
CERM
402
C2921
0.1UF
C2922
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C2923
0.1UF
20%
2 10V
CERM
402
C2901
10UF
20%
2 6.3V
X5R
603
32
PP0V75_S3_MEM_VREFDQ_A
(NONE)
C2930
C2931
2.2UF
2
0.1UF
20%
6.3V
CERM
402-LF
20%
10V
CERM
402
1
73
MEM_A_CKE<0>
NC
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
MEM_A_BA<2>
75
77
79
81
83
MEM_A_A<12>
MEM_A_A<9>
85
87
89
MEM_A_A<8>
MEM_A_A<5>
91
93
95
MEM_A_A<3>
MEM_A_A<1>
97
99
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
101
MEM_A_A<10>
MEM_A_BA<0>
107
MEM_A_WE_L
MEM_A_CAS_L
113
MEM_A_A<13>
MEM_A_CS_L<1>
119
121
103
105
109
111
115
117
123
NC
29
BI
29
BI
29
BI
29
BI
29
BI
29
BI
125
127
=MEM_A_DQ<32>
=MEM_A_DQ<33>
129
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
135
=MEM_A_DQ<34>
=MEM_A_DQ<35>
141
143
131
133
137
139
145
147
149
29
BI
29
BI
=MEM_A_DQ<40>
=MEM_A_DQ<41>
29
IN
=MEM_A_DM<5>
153
155
29
BI
157
29
BI
=MEM_A_DQ<42>
=MEM_A_DQ<43>
29
BI
29
BI
=MEM_A_DQ<48>
=MEM_A_DQ<49>
163
165
151
159
161
167
29
BI
29
BI
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
169
171
173
29
BI
29
BI
=MEM_A_DQ<50>
=MEM_A_DQ<51>
175
177
179
29
BI
29
BI
=MEM_A_DQ<56>
=MEM_A_DQ<57>
181
183
185
187
29
IN
=MEM_A_DM<7>
29
BI
29
BI
=MEM_A_DQ<58>
=MEM_A_DQ<59>
189
191
193
195
80 73 72 69 68
47 46 42 40 37
20 19 18 17 7 6
34 30 27 26 25 24 23 21
63 62 58 54 52 51 50 48
99 88 87 85 84 83
MEM_A_SA<0>
197
199
MEM_A_SA<1>
201
PP3V3_S0
203
1
1
C2940
10K
2.2UF
2
20%
6.3V
CERM
402-LF
R2940
CKE0
CKE1
VDD
VDD
NC
A15
BA2
A14
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DM4
DQS4*
DQS4
VSS
DQ38
VSS
DQ39
DQ34
DQ35
VSS
VSS
DQ44
DQ45
DQ40
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
VSS
DQS6
DQ54
VSS
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT
VTT
J2900
(SYMBOL 2 OF 2)
IN
DDR3-SODIMM-DUAL-K6
92 11
KEY
74
MEM_A_CKE<1>
76
78
IN
11 92
29
29
MEM_A_A<15>
MEM_A_A<14>
80
82
84
MEM_A_A<11>
MEM_A_A<7>
86
88
90
MEM_A_A<6>
MEM_A_A<4>
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
IN
11 92
IN
11 92
92 29 11
BI
BI
IN
IN
11 92
29
BI
IN
11 92
29
BI
IN
11 92
29
BI
IN
11 92
29
BI
MEM_A_A<2>
MEM_A_A<0>
IN
11 92
29
BI
IN
11 92
29
BI
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
IN
11 92
29
BI
IN
11 92
29
BI
MEM_A_BA<1>
MEM_A_RAS_L
IN
11 92
29
BI
IN
11 92
29
BI
MEM_A_CS_L<0>
MEM_A_ODT<0>
IN
11 92
29
BI
IN
11 92
29
BI
MEM_A_ODT<1>
IN
11 92
29
BI
29
BI
NC
3
5
=MEM_A_DQ<0>
=MEM_A_DQ<1>
7
9
11
MEM_A_DM<0>
13
15
=MEM_A_DQ<2>
=MEM_A_DQ<3>
17
19
21
=MEM_A_DQ<8>
=MEM_A_DQ<9>
23
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
33
=MEM_A_DQ<16>
=MEM_A_DQ<17>
39
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
45
=MEM_A_DQ<18>
=MEM_A_DQ<19>
51
53
136
138
140
=MEM_A_DQ<36>
MEM_A_DQ<37>
=MEM_A_DM<4>
29
BI
11 29 92
IN
29
BI
29
=MEM_A_DQ<44>
=MEM_A_DQ<45>
BI
29
BI
29
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
BI
29
BI
29
=MEM_A_DQ<46>
=MEM_A_DQ<47>
BI
29
BI
29
=MEM_A_DQ<52>
=MEM_A_DQ<53>
BI
29
BI
29
170
172
=MEM_A_DM<6>
IN
174
=MEM_A_DQ<54>
=MEM_A_DQ<55>
BI
29
BI
29
=MEM_A_DQ<60>
=MEM_A_DQ<61>
BI
29
BI
29
148
150
152
154
156
158
160
162
164
166
29
BI
29
BI
47
49
=MEM_A_DQ<24>
=MEM_A_DQ<25>
57
59
IN
=MEM_A_DM<3>
63
65
29
BI
67
29
BI
=MEM_A_DQ<26>
=MEM_A_DQ<27>
29
29
BI
146
41
43
61
BI
=MEM_A_DQ<38>
=MEM_A_DQ<39>
142
144
35
37
55
126
128
132
134
29
31
=MEM_A_DQ<10>
=MEM_A_DQ<11>
124
130
25
27
69
71
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
VSS
DQ1
VSS
DQS0*
DQS0
DM0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DQS1*
DM1
RESET*
DQS1
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
DQ28
VSS
DQ24
DQ29
VSS
DQ25
DQS3*
VSS
DQS3
DM3
VSS
VSS
DQ30
DQ26
DQ31
DQ27
VSS
VSS
J2900
(SYMBOL 1 OF 2)
DDR3-SODIMM-DUAL-K6
C2910
0.1UF
- =PP0V75_S0_MEM_VTT_A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
=MEM_A_DQ<4>
=MEM_A_DQ<5>
BI
29
BI
29
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
BI
11 29 92
BI
11 29 92
=MEM_A_DQ<6>
=MEM_A_DQ<7>
BI
29
BI
29
=MEM_A_DQ<12>
=MEM_A_DQ<13>
BI
29
=MEM_A_DM<1>
MEM_RESET_L
IN
29
IN
30 31
=MEM_A_DQ<14>
=MEM_A_DQ<15>
BI
29
BI
29
=MEM_A_DQ<20>
=MEM_A_DQ<21>
BI
29
BI
29
=MEM_A_DM<2>
IN
=MEM_A_DQ<22>
=MEM_A_DQ<23>
BI
29
BI
29
=MEM_A_DQ<28>
=MEM_A_DQ<29>
BI
29
BI
29
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
BI
29
BI
29
=MEM_A_DQ<30>
=MEM_A_DQ<31>
BI
29
BI
29
BI
29
29
KEY
516-0229
168
176
178
180
182
184
186
188
29
PP0V75_S3_MEM_VREFCA_A
C2935
2.2UF
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
BI
29
BI
29
=MEM_A_DQ<62>
=MEM_A_DQ<63>
BI
29
BI
29
20%
6.3V
CERM
402-LF
32
C2936
0.1UF
20%
10V
CERM
402
190
192
194
196
198
200
202
204
MEM_EVENT_A_L
SMBUS_PCH_DATA
SMBUS_PCH_CLK
OUT
30 45 46
BI
IN
"Factory" (top) slot
17 25 26 30 32 42 47 48 63 88
94
17 25 26 30 32 42 47 48 63 88
94
PP0V75_S0_DDRVTT
6 7 30 31 67
R2941
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
516-0229
SYNC_MASTER=MASTER
SPD ADDR=0xA0(WR)/0xA1(RD)
SYNC_DATE=MASTER
PAGE TITLE
DDR3 SO-DIMM Connector A

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
29 OF 132
SHEET
28 OF 101
CPU CHANNEL A DQS 0 -> DIMM A DQS 0

92 29 28 11
92 29 28 11
92 29 28 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DM<0>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DM<0>
=MEM_A_DQ<7>
=MEM_A_DQ<6>
=MEM_A_DQ<1>
=MEM_A_DQ<0>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<5>
=MEM_A_DQ<4>
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DM<1>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DM<1>
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<12>
11 28 29 92 92 30 29 11
11 28 29 92 92 30 29 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DM<2>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DM<2>
=MEM_A_DQ<23>
=MEM_A_DQ<19>
=MEM_A_DQ<20>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<18>
=MEM_A_DQ<17>
=MEM_A_DQ<16>
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DM<3>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
=MEM_A_DM<3>
=MEM_A_DQ<27>
=MEM_A_DQ<26>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQ<31>
=MEM_A_DQ<30>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
92 11
92 11
92 11
92 11
92 29 28 11
92 11
92 11
92 11
92 11
92 11
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DM<4>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DM<4>
=MEM_A_DQ<33>
=MEM_A_DQ<39>
MEM_A_DQ<37>
=MEM_A_DQ<38>
=MEM_A_DQ<35>
=MEM_A_DQ<34>
=MEM_A_DQ<32>
=MEM_A_DQ<36>
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DM<5>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DM<5>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
=MEM_A_DQ<45>
=MEM_A_DQ<44>
=MEM_A_DQ<47>
=MEM_A_DQ<46>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
28
92 11
28
92 11
28
92 11
28
92 11
11 28 29 92 92 30 29 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DM<6>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
=MEM_A_DM<6>
=MEM_A_DQ<49>
=MEM_A_DQ<50>
=MEM_A_DQ<54>
=MEM_A_DQ<53>
=MEM_A_DQ<55>
=MEM_A_DQ<51>
=MEM_A_DQ<48>
=MEM_A_DQ<52>
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
92 11
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DM<7>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DM<7>
=MEM_A_DQ<62>
=MEM_A_DQ<63>
=MEM_A_DQ<56>
=MEM_A_DQ<61>
=MEM_A_DQ<59>
=MEM_A_DQ<58>
=MEM_A_DQ<57>
=MEM_A_DQ<60>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DM<0>
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<2>
=MEM_B_DQ<4>
=MEM_B_DQ<3>
=MEM_B_DQ<1>
=MEM_B_DQ<5>
=MEM_B_DQ<0>
11 29 30 92
11 29 30 92
11 29 30 92
30
30
30
30
30
30
30
30
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DM<1>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DM<1>
=MEM_B_DQ<15>
=MEM_B_DQ<14>
=MEM_B_DQ<13>
=MEM_B_DQ<8>
=MEM_B_DQ<11>
=MEM_B_DQ<10>
=MEM_B_DQ<12>
=MEM_B_DQ<9>
30
30
30
30
30
30
30
30
30
30
30
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DM<2>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DM<2>
=MEM_B_DQ<23>
=MEM_B_DQ<18>
=MEM_B_DQ<20>
=MEM_B_DQ<17>
=MEM_B_DQ<19>
=MEM_B_DQ<22>
=MEM_B_DQ<21>
=MEM_B_DQ<16>
30
30
30
30
30
30
30
30
30
30
30
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DM<3>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DM<3>
=MEM_B_DQ<27>
=MEM_B_DQ<26>
=MEM_B_DQ<24>
=MEM_B_DQ<30>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQ<31>
=MEM_B_DQ<25>
30
30
30
30
30
30
30
30
30
30
30
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DM<4>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DM<4>
=MEM_B_DQ<35>
=MEM_B_DQ<38>
MEM_B_DQ<37>
=MEM_B_DQ<32>
=MEM_B_DQ<33>
=MEM_B_DQ<39>
=MEM_B_DQ<37>
=MEM_B_DQ<36>
30
30
30
30
30
11 29 30 92
30
30
30
30
30
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DM<5>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DM<5>
=MEM_B_DQ<47>
=MEM_B_DQ<43>
=MEM_B_DQ<45>
=MEM_B_DQ<41>
=MEM_B_DQ<46>
=MEM_B_DQ<42>
=MEM_B_DQ<44>
=MEM_B_DQ<40>
30
30
30
30
30
30
30
30
30
30
30
CPU CHANNEL B DQS 6 -> DIMM B DQS 6

28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11

92 11
92 11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

28

92 11
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DM<0>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

92 11

92 11

92 11

11 28 29 92 92 30 29 11

92 11
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DM<6>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DM<6>
=MEM_B_DQ<50>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
=MEM_B_DQ<53>
=MEM_B_DQ<49>
=MEM_B_DQ<51>
=MEM_B_DQ<48>
=MEM_B_DQ<52>
30
30
30
30
30
30
30
30
30
30
30

28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
28
92 11
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DM<7>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DM<7>
=MEM_B_DQ<63>
=MEM_B_DQ<62>
=MEM_B_DQ<57>
=MEM_B_DQ<56>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DQ<60>
=MEM_B_DQ<61>
30
30
SYNC_MASTER=MASTER
30
SYNC_DATE=MASTER
PAGE TITLE
30
DDR3 Byte/Bit Swaps
30
DRAWING NUMBER
30
30
Apple Inc.
30
R
<E4LABEL>
30
30

30
SIZE
<SCH_NUM> D
REVISION
BRANCH
<BRANCH>
PAGE
30 OF 132
SHEET
29 OF 101
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes
72 67 31 28 7 6
PP1V5_S3

- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
C3100
10UF
- =I2C_SODIMMB_SCL
20%
2 6.3V
X5R
603
- =I2C_SODIMMB_SDA
C3111
0.1UF
20%
2 10V
CERM
402
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
20%
2 10V
CERM
402
C3112
0.1UF
20%
2 10V
CERM
402
C3113
0.1UF
20%
2 10V
CERM
402
C3114
0.1UF
20%
2 10V
CERM
402
C3115
0.1UF
20%
2 10V
CERM
402
C3116
0.1UF
C3117
0.1UF
20%
2 10V
CERM
402
C3118
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C3119
0.1UF
20%
2 10V
CERM
402
C3120
0.1UF
20%
2 10V
CERM
402
C3121
0.1UF
20%
2 10V
CERM
402
C3122
0.1UF
20%
2 10V
CERM
402
C3123
0.1UF
20%
2 10V
CERM
402
C3101
10UF
20%
2 6.3V
X5R
603
32
PP0V75_S3_MEM_VREFDQ_B
(NONE)
C3130
C3131
2.2UF
2
0.1UF
20%
6.3V
CERM
402-LF
20%
10V
CERM
402
1
73
NC
92 11
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
IN
92 11
MEM_B_BA<2>
IN
203
205
207
MTG PIN
MTG PIN
MTG PIN
209
211
MTG PIN
MTG PIN
MTG PIN
79
81
83
MEM_B_A<12>
MEM_B_A<9>
85
87
89
MEM_B_A<8>
MEM_B_A<5>
91
93
95
MEM_B_A<3>
MEM_B_A<1>
IN
CKE0
CKE1
VDD
VDD
NC
A15
A14
BA2
VDD F-RT-BGA6 VDD
A11
A12/BC*
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
S0*
WE*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ37
DQ33
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
DQS7*
VSS
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
EVENT*
SA0
VDDSPD
SDA
SA1
SCL
VTT
VTT
75
77
97
99
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
101
MEM_B_A<10>
MEM_B_BA<0>
107
MEM_B_WE_L
MEM_B_CAS_L
113
MEM_B_A<13>
MEM_B_CS_L<1>
119
121
103
105
109
111
115
117
123
NC
29
BI
29
BI
29
BI
29
BI
92 29 11
BI
29
BI
125
127
=MEM_B_DQ<32>
=MEM_B_DQ<33>
129
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
135
MEM_B_DQ<37>
=MEM_B_DQ<35>
141
143
131
133
137
139
145
147
149
29
BI
29
BI
=MEM_B_DQ<40>
=MEM_B_DQ<41>
29
IN
=MEM_B_DM<5>
153
155
29
BI
157
29
BI
=MEM_B_DQ<42>
=MEM_B_DQ<43>
29
BI
29
BI
=MEM_B_DQ<48>
=MEM_B_DQ<49>
163
165
151
159
161
167
29
BI
29
BI
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
169
171
173
29
BI
29
BI
=MEM_B_DQ<50>
=MEM_B_DQ<51>
175
177
179
29
BI
29
BI
=MEM_B_DQ<56>
=MEM_B_DQ<57>
181
183
185
187
29
IN
=MEM_B_DM<7>
29
BI
29
BI
=MEM_B_DQ<58>
=MEM_B_DQ<59>
189
191
193
195
88 87 85 84 83 80
51 50 48 47 46 42
21 20 19 18 17 7 6
40 37 34 28 27 26 25 24 23
73 72 69 68 63 62 58 54 52
99
MEM_B_SA<0>
197
199
MEM_B_SA<1>
201
PP3V3_S0
1
1
C3140
2.2UF
20%
6.3V
CERM
402-LF
R3140
R3141
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
J3100
(2 OF 2)
MEM_B_CKE<0>
IN
DDR3-SODIMM
92 11
KEY
MTG PINS
MTG PIN
MTG PIN
74
MEM_B_CKE<1>
76
78
IN
29
11 92
29
MEM_B_A<15>
MEM_B_A<14>
80
82
84
MEM_B_A<11>
MEM_B_A<7>
86
88
90
MEM_B_A<6>
MEM_B_A<4>
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
IN
11 92
IN
11 92
92 29 11
BI
BI
IN
IN
11 92
29
BI
IN
11 92
29
BI
IN
11 92
29
BI
IN
11 92
29
BI
MEM_B_A<2>
MEM_B_A<0>
IN
11 92
29
BI
IN
11 92
29
BI
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
IN
11 92
29
BI
IN
11 92
29
BI
MEM_B_BA<1>
MEM_B_RAS_L
IN
11 92
29
BI
IN
11 92
29
BI
MEM_B_CS_L<0>
MEM_B_ODT<0>
IN
11 92
29
BI
IN
11 92
29
BI
MEM_B_ODT<1>
IN
11 92
29
BI
29
BI
NC
=MEM_B_DQ<0>
=MEM_B_DQ<1>
MEM_B_DM<0>
=MEM_B_DQ<2>
=MEM_B_DQ<3>
=MEM_B_DQ<8>
=MEM_B_DQ<9>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
136
138
140
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DM<4>
BI
29
BI
29
IN
BI
29
BI
29
=MEM_B_DQ<44>
=MEM_B_DQ<45>
BI
29
BI
29
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
BI
29
BI
29
=MEM_B_DQ<46>
=MEM_B_DQ<47>
BI
29
BI
29
=MEM_B_DQ<52>
=MEM_B_DQ<53>
BI
29
BI
29
170
172
=MEM_B_DM<6>
IN
174
=MEM_B_DQ<54>
=MEM_B_DQ<55>
BI
29
BI
29
=MEM_B_DQ<60>
=MEM_B_DQ<61>
BI
29
BI
29
146
148
150
152
154
156
158
160
162
164
166
13
15
17
19
21
23
25
27
29
31
33
=MEM_B_DQ<16>
=MEM_B_DQ<17>
39
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
45
=MEM_B_DQ<18>
=MEM_B_DQ<19>
51
53
35
37
41
43
47
49
29
BI
29
BI
=MEM_B_DQ<24>
=MEM_B_DQ<25>
57
59
61
IN
=MEM_B_DM<3>
63
65
29
BI
67
29
BI
=MEM_B_DQ<26>
=MEM_B_DQ<27>
29
29
=MEM_B_DQ<38>
=MEM_B_DQ<39>
142
144
11
55
126
128
132
134
7
9
=MEM_B_DQ<10>
=MEM_B_DQ<11>
124
130
3
5
69
71
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
DQ1
VSS
VSS
DQS0*
DM0
DQS0
F-RT-BGA6
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ14
DQ10
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
VSS
DQ28
DQ29
DQ24
VSS
DQ25
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
J3100
(1 OF 2)
DDR3-SODIMM
C3110
0.1UF
- =PP0V75_S0_MEM_VTT_B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
=MEM_B_DQ<4>
=MEM_B_DQ<5>
BI
29
BI
29
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
BI
11 29 92
BI
11 29 92
=MEM_B_DQ<6>
=MEM_B_DQ<7>
BI
29
BI
29
=MEM_B_DQ<12>
=MEM_B_DQ<13>
BI
29
=MEM_B_DM<1>
MEM_RESET_L
IN
29
IN
28 31
=MEM_B_DQ<14>
=MEM_B_DQ<15>
BI
29
BI
29
=MEM_B_DQ<20>
=MEM_B_DQ<21>
BI
29
BI
29
=MEM_B_DM<2>
IN
=MEM_B_DQ<22>
=MEM_B_DQ<23>
BI
29
BI
29
=MEM_B_DQ<28>
=MEM_B_DQ<29>
BI
29
BI
29
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
BI
29
BI
29
=MEM_B_DQ<30>
=MEM_B_DQ<31>
BI
29
BI
29
BI
29
29
KEY
516S0806
168
176
178
180
182
184
186
188
29
PP0V75_S3_MEM_VREFCA_B
C3135
2.2UF
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
BI
29
BI
29
=MEM_B_DQ<62>
=MEM_B_DQ<63>
BI
29
BI
29
20%
6.3V
CERM
402-LF
32
C3136
0.1UF
20%
10V
CERM
402
190
192
194
196
198
200
202
MEM_EVENT_A_L
SMBUS_PCH_DATA
SMBUS_PCH_CLK
OUT
28 45 46
BI
IN
204
17 25 26 28 32 42 47 48 63 88
94
"Expansion" (bottom) slot
17 25 26 28 32 42 47 48 63 88
94
PP0V75_S0_DDRVTT
6 7 28 31 67
206
208
210
212
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
DDR3 SO-DIMM Connector B

DRAWING NUMBER
516S0806
Apple Inc.
SPD ADDR=0xA4(WR)/0xA5(RD)
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
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31 OF 132
SHEET
30 OF 101
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPUs SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
1V5 S0 "PGOOD" for CPU
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

MEMVTT_EN
= (ISOLATE_CPU_MEM_L + PLT_RST_L)
* PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
73 72 46 45 43 18
PP3V3_S5
35 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57
PM_SLP_S4_L
IN
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CPUMEM_S0
1
R3205
99 73 72 42 16 13 7 6
PP1V5_S3RS0
PM_MEM_PWRGD
10K
P1V5CPU_EN
54 53 50 48 36 35 34 33 32 20 17 8 7 6
101 87 73 72 55
PP3V3_S3
Q3205
R32011
SSM6N15FEAPE
10K
OUT
5%
1/16W
MF-LF
2 402
R32201
72
5%
1/16W
MF-LF
402 2
D 6
P1V5_S0_DIV
S 1
Q3205
DMB53D0UV
0.001UF
1%
1/16W
MF-LF
402 2
SOT563
C3220 1
33.2K
SSM6N15FEAPE
S 4
CRITICAL
Q3220
4
NO STUFF
R32211
CPUMEM_S0
D 3
2 G
SOT-563
SOT563
Q3220
SOT-563
PM_MEM_PWRGD_L
3
SSM6N15FEAPE
IN
DMB53D0UV
1%
1/16W
MF-LF
402 2
P1V5CPU_EN_L
25 20
27.4K
CPUMEM_S0
CRITICAL
SOT563
100K
Q3200
10 18 91
R3222
CPUMEM_S0
CPUMEM_S0
OUT
5%
1/16W
MF-LF
2 402
20%
50V
CERM 2
402
G 5
ISOLATE_CPU_MEM_L
PM_SLP_S3_L
CPUMEM_S0
IN
6 18 45 73 85
R3210
10K
5%
1/16W
MF-LF
2 402
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
MEMVTT_EN
PP5V_S3
OUT
8 31 67
MEMVTT Clamp
CPUMEM_S0
CPUMEM_S0
Q3210
CPUMEM_S0
R3202
100K
100K
5%
1/16W
MF-LF
402 2
Ensures CKE signals are held low in S3
SSM6N15FEAPE
R3215
D 6
SOT563
5%
1/16W
MF-LF
402 2
S 1
67 30 28 7 6
MEMVTT_EN_L
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
G 2
S 1
G 5
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
IN
CPUMEM_S0
CPUMEM_S0
Q3250
R32511
SSM6N15FEAPE
19 27 40
PLT_RESET_L
PP5V_S3
100K
Q3215
5
MAKE_BASE=TRUE
CPU_MEM_RESET_L
R3216
CPUMEM_S0
Q3250
20K
5%
1/16W
MF-LF
2 402
D 3
SSM6N15FEAPE
MEM_RESET_L
OUT
S 1
5
67 31 8
IN
C3251 1
20%
50V
CERM 2
402
28 30
CPUMEM_S3
NO STUFF
0.001UF
SOT563
CPU_MEM_RESET_L
IN
SOT563
VTTCLAMP_EN
SSM6N15FEAPE
MEMRESET_ISOL_LS5V_L
6 7 28 30 67 72
D 6
SOT563
5%
1/16W
MF-LF
402 2
PP1V5_S3
CPUMEM_S0
CPUMEM_S0
31 10
75mA max load @ 0.75V

60mW max power
VTTCLAMP_L
G
D
6
5%
1/10W
MF-LF
603 2
Q3210
SSM6N15FEAPE
SOT563
10
CPUMEM_S0
D 6
Q3200
Q3215
SOT563
R32501
CPUMEM_S0
CPUMEM_S0
PP0V75_S0_DDRVTT
CPUMEM_S0
S 4
MEMVTT_EN
R3217
0
5%
1/16W
MF-LF
402
Step
S0
to
S3
to
S0
PM_SLP_S3_L
PM_SLP_S4_L
CPU_MEM_RESET_L
0
1
2
3
ISOLATE_CPU_MEM_L
1
0
0
0
PLT_RESET_L
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
X
CPU_MEM_RESET_L
1
1
1
MEM_RESET_L
MEMVTT_EN
1
1
0
0
P1V5CPU_EN
1
1
1
0
4
5
6
7
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
X
0 (*)
1
1
1
1
1
CPU_MEM_RESET_L
0
1
1
1
1
1
1
1
SYNC_MASTER=K17_REF
PAGE TITLE
CPU Memory S3 Support

DRAWING NUMBER
Apple Inc.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
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32 OF 132
SHEET
31 OF 101
50 48 36 35 34 33 31 20 17 8 7 6
101 87 73 72 55 54 53
NOTE: Must not enable more than two SO-DIMM margining

buffers at once or VRef source may be overloaded.
PP3V3_S3
VREFMRGN
OMIT
R3318
SHORT2
NONE
NONE
NONE
402
67 7 6
PP3V3_S3_VREFMRGN_DAC
MIN_NECK_WIDTH=0.2 mm VREFMRGN
VOLTAGE=3.3V
C3300 1
2.2UF
20%
6.3V 2
CERM
402-LF
C3301
VREFMRGN
0.1UF
63 48 47 42 32 30 28 26 25 17
94 88
0.1UF
20%
10V
CERM 2
402
U3300
IN
SMBUS_PCH_CLK
6 SCL
BI
SMBUS_PCH_DATA
7 SDA
10 A1
VOUTB 2
VREFMRGN_SODIMMB_DQ
VOUTC 4
VREFMRGN_SODIMMS_CA
B1
V+
UCSP
A1
VREFMRGN_DQ_SODIMMA_BUF
A4
V-
R3301
C3
PP3V3_S3_VREFMRGN_CTRL
B1
Addr=0x30(WR)/0x31(RD)
63 48 47 42 32 30 28 26 25 17
94 88
63 48 47 42 32 30 28 26 25 17
94 88
IN
BI
UCSP
C1
VREFMRGN_DQ_SODIMMB_BUF
SMBUS_PCH_CLK
SMBUS_PCH_DATA
V-
100K
NC
5%
1/16W
MF-LF
2 402
16
GND
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
VREFMRGN
VREFMRGN
C3304 1
0.1UF
20%
10V
CERM 2
402
A2
B1
V+
A3
UCSP
A1
VREFMRGN_CA_SODIMMA_BUF
B4
2
PLACE_NEAR=R3309.2:1mm
C2
B1
V+
C3
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
VREFMRGN_CA_SODIMMB_BUF
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R3303,R3305
CRITICAL
VREFMRGN_NOT
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R3309,R3311
CRITICAL
VREFMRGN_NOT
V-
30
2
VREFMRGN
R3308
VREFMRGN
C3305 1
5%
1/16W
MF-LF
2 402
VREFMRGN
0.1UF
20%
10V
CERM 2
402
C2
B1
V+
C3
VREFMRGN
U3304
MAX4253
UCSP
C1
R3314
VREFMRGN_MEMVREG_BUF
22.6K2
DDRREG_FB
1%
1/16W
MF-LF
402
C4
V-
B4
Page Notes
133
1%
1/16W
MF-LF
402
C4
PP0V75_S3_MEM_VREFCA_B
VOLTAGE=0.75V
100K
BOM OPTION
PLACE_NEAR=J3100.126:2.54mm
R3312
B4
PART NUMBER
VREFMRGN
U3303
MAX4253
UCSP
C1
200
1%
1/16W
MF-LF
402
VREFMRGN
5%
1/16W
MF-LF
2 402
PCA9557D_RESET_L
Required zero ohm resistors when no VREF margining circuit stuffed
OUT
67
OUT
8 77
OUT
8 78
VREFMRGN
VREFMRGN
R3316

- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
R3313
VREFMRGN
100K
5%
1/16W
MF-LF
2 402

- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
A2
B1
V+
A3
U3304
UCSP
A1
VREFMRGN_FRAMEBUF_BUF
A4
49.9 2
1%
1/16W
MF-LF
402
MAX4253
GPU_FB_A_VREF_DIV
VREFMRGN
R3317
V-
B4

VREFMRGN
- Stuffs VREF Margining
Circuitry.
VREFMRGN_NOT - Bypasses VREF Margining
Circuitry.
28
R3311
NOTE: Margining will be disabled across all

soft-resets and sleep/wake cycles.
A
1
133
PP0V75_S3_MEM_VREFCA_A
VOLTAGE=0.75V
VREFMRGN
RST* on platform reset so that system

watchdog will disable margining.
DAC Channel:
PCA9557D Pin:
Nominal value
Margined target:
DAC range:
VRef current:
DAC step size:
NC
100K
MEM A VREF DQ
1%
1/16W
MF-LF
402
A4
V-
R3307
200
R3310
VREFMRGN
IN
VREFMRGN
U3303
MAX4253
27
1%
1/16W
MF-LF
402
RESET* 15
PAD
30
R3309
R3302
QFN
(OD) P0 6
P1 7
P2 9
P3 10
P4 11
P5 12
P6 13
P7 14
17
THRM
133
PP0V75_S3_MEM_VREFDQ_B
VOLTAGE=0.75V
VREFMRGN
VREFMRGN
U3301
1 SCL
2 SDA
2 PLACE_NEAR=J3100.1:2.54mm
1%
1/16W
MF-LF
402
C4
PCA9557
3 A0
4 A1
5 A2
200
R3306
CRITICAL
VREFMRGN
VCC
20%
10V
CERM 2
402
VREFMRGN
U3302
MAX4253
B4
0.1UF
28
1%
1/16W
MF-LF
402
VREFMRGN
C2
OMIT
C3302 1
PP0V75_S3_MEM_VREFDQ_A
VOLTAGE=0.75V
R3305
VREFMRGN
V+
VREFMRGN
VREFMRGN
NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable
both at the same time!
R3319
NONE
NONE
NONE
402
133
1%
1/16W
MF-LF
402
B4
5%
1/16W
MF-LF
2 402
VOLTAGE=3.3V
R3304
100K
SHORT2
1
200
VREFMRGN
U3302
MAX4253
VREFMRGN_MEMVREG_FBVREF
VOUTD 5
GND
3
A2
A3
VREFMRGN_SODIMMA_DQ
1
MSOP VOUTA
9 A0
Addr=0x98(WR)/0x99(RD)
R3303
1%
1/16W
MF-LF
402
VREFMRGN
C3303 1
CRITICAL
VREFMRGN
20%
2 10V
CERM
402
DAC5574
63 48 47 42 32 30 28 26 25 17
94 88
PPVTTDDR_S3
10mA max load
VREFMRGN
8
VDD
49.9 2
1%
1/16W
MF-LF
402
VREFMRGN
GPU_FB_B_VREF_DIV
R3315
100K
5%
1/16W
MF-LF
2 402
MEM B VREF DQ
MEM A VREF CA
B
2
C
3
0.75V (DAC: 0x3A)
0.300V - 1.200V (+/- 450mV)
0.000V - 1.501V (0x00 - 0x74)
+3.4mA - -3.4mA (- = sourced)
7.69mV / step @ output
MEM B VREF CA
C
4
MEM VREG
GPU Frame Buffer (1.8V, 70% VRef)
D
5
1.5V (DAC: 0x3A)
1.998V - 1.002V (+/- 498mV)
0.000V - 1.501V (0x00 - 0x74)
+33uA - -33uA (- = sourced)
D
6
1.267V (DAC: 0x8B)
1.056V - 1.442V (+/- 180mV)
0.000V - 3.300V (0x00 - 0xFF)
+6.0mA - -5.0mA (- = sourced)
SYNC_MASTER=K17_REF
PAGE TITLE
FSB/DDR3/FRAMEBUF Vref Margining

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
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<BRANCH>
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33 OF 132
SHEET
32 OF 101
AP_PWR_EN
IN
20 73
3V S3 WLAN FET
D
25 17
OUT
AP_CLKREQ_L
6
MOSFET
TPCP8102
CHANNEL
P-TYPE
Q3401
20-30 MOHM @2.5V
RDS(ON)
SSM6N15FEAPE
SOT563
LOADING
1
0.727 A (EDP)
CRITICAL
AP_CLKREQ_Q_L
Q3450
TPCP8102
155S0367
10%
0.1uF
0.1uF
16V X5R 402
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
IN
17 94
IN
17 94
PP3V3_WLAN 1
MIN_LINE_WIDTH=1 mm
C3422
PLACEMENT_NOTE=Place close to J3401.
J3401
PCIE_AP_D2R_P OUT
PCIE_AP_D2R_N OUT
C3421
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
C3420
90-OHM-100MA
DLP11S
PP3V3_S3
1
C3451
10%
16V
X5R
402
C3450
0.1UF
PLACEMENT_NOTE=Place close to Q3450.
P3V3WLAN_SS
R3451
R3450
1
33K
5%
1/16W
MF-LF
402
PM_WLAN_EN_L
IN
33 73
5%
1/16W
MF-LF
402
10%
16V
X5R
402
PLACEMENT_NOTE=Place close to Q3450.
53 54 55 72 73 87
6 7 8 17 20 31 32
33 34 35 36 48 50
101
10K
0.033UF
20%
10V
X5R
805
AIRPORT
L3401
94
6
17
10UF
6 17 94
CRITICAL
F-ST-SM
32
31
PP3V3_WLAN_F
PP3V3_WLAN_R
0.1uF
CRITICAL
500913-0302
56 33
16V X5R 402
C3430
516S0582
2
0603
10%
1 2 3
MIN_LINE_WIDTH=1 mm
C3431
PCIE_AP_R2D_P
PCIE_AP_R2D_N
23V1K-SM
XW3452
SM
FERR-120-OHM-3A
5 6 7 8
94 6
94 6
L3404
727 MA PEAK
606 MA NOMINAL MAX
MIN_LINE_WIDTH=1 mm
4G
SYM_VER-1
2
4
6
8
10
12
NC
14
NC
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
34
33
99 6
99 6
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_P
IN
17 94
PCIE_CLK100M_AP_N
IN
17 94
L3403
90-OHM
BLUETOOTH
99 6
99 6
DLP0NS
CRITICAL
SYM_VER-1
PLACE_NEAR=J3401.21:2.54MM
USB_BT_P BI
36 93
USB_BT_N BI
36 93
CONN_USB2_BT_P
CONN_USB2_BT_N
PP3V3_S3_BT_F
L3406
1 C3432
0.01UF
10%
16V
CERM
402
PP3V3_S3
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
FERR-120-OHM-1.5A
0402-LF
PLACEMENT_NOTE=PLACE L3406 NEAR J3401.
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
PP3V3_WLAN_F
PP3V3_S3
PCIE_WAKE_L
OUT
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 18 27
33 56
R3453
110K
U3402
74LVC1G17 5
TC7SZ08AFEAPE 5
SOT665
6
AP_RESET_CONN_L
U3401
WLAN_SMIT_BUF
SOT353-1
4
518S0767
R3455
WLAN_SMIT_RC
NC
C3453
AP_RESET_L
CRITICAL
5%
1/16W
MF-LF
402
NC
IN
1UF
27
10%
6.3V
CERM
402
J3402
819Q-3506-K281
F-RT-SM
2
2
R3454
62K
5% NOSTUFF
5%
1/16W
MF-LF
402
WLAN_SMIT_DISCHRG
Q3401
SSM6N15FEAPE
SOT563
1/16W
MF-LF
402
G 5
PM_WLAN_EN_L
PP5V_S3_ALSCAMERA_F
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
93 6 USB_CAMERA_CONN_P
93 6 USB_CAMERA_CONN_N
33 73
5
4
3
RC (R3453 AND C3453)VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN
3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET
IN
BI
6 45 48 54 97
275 mA peak
206 mA nominal max
6 45 48 54 97
ALS
CAMERA
CRITICAL
L3407
90-OHM
DLP0NS
SYM_VER-1
USB_CAMERA_P
1
0402-LF
BI
PP5V_S3
SYNC_MASTER=K18_COMMS
6 7 31 42 43 44 46 54 56 58 61 66 67 72
82 101
C3452
35
PAGE TITLE
X16/ALS/CAMERA CONNECTOR
DRAWING NUMBER
0.1uF
PLACE_NEAR=J3402.6:2.54MM
3
PLACEMENT_NOTE=Place close to J3402
L3408
FERR-120-OHM-1.5A
Apple Inc.
20%
2 10V
CERM
402

1
USB_CAMERA_N
BI

35
PLACEMENT_NOTE=Place close to J3402
SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
34 OF 132
SHEET
33 OF 101
Caesar IV Support
37
37
GL137
D
50 48 36 35 33 32 31 20 17 8 7 6
101 87 73 72 55 54 53
PP3V3_S3
R3511
1
BYPASS=U3500.15:16:5 mm
BYPASS=U3500.26:27:5 mm
BYPASS=U3500.35:34:5 mm
PP3V3_S3_CARDREADER_DVDD
GL137
5%
1/16W
MF-LF
402
VOLTAGE=3.3V
GL137
C3500 1
10UF
603
L3500
0.1UF
20%
2 10V
CERM
402
20%
GL137
C3502
0.1UF
6.3V 2
X5R
GL137
GL137
C3501
37
37
C3503
0.1UF
20%
2 10V
CERM
402
37
20%
2 10V
CERM
402
37
SDCONN_DATA<0>
R3550
BI
SDCONN_DATA<1>
R3551
SDCONN_DATA<2>
R3552
BI
37
37 34 6
BYPASS=U3500.6:5:5 mm
BYPASS=U3500.11:12:5 mm
PP3V3_S3_CARDREADER_AVDD
GL137
VOLTAGE=3.3V
GL137
C3514 1
10UF
GL137
C3504
SDCONN_DATA<3>
BI
SDCONN_DATA<4..7>
0.1UF
603
VOLTAGE=1.8V
R3508
10K
10K
5%
1/16W
MF-LF
2 402
93 36 8
93 36 8
BI
BI
GL137_GPIO1
GL137_GPIO2
NO STUFF
R35091
10K
5%
1/16W
MF-LF
402 2
GL137
NC
R3510
GL137A
LQFP
48 GPIO1
47 GPIO2
46 GPIO3
CRITICAL
GL137
19
SK
NC
20 CS
NC
21 DO
NC
22 DI (IPD)
NC
10K
5%
1/16W
MF-LF
2 402
NO STUFF
R3503
1M
5%
1/16W
MF-LF
GL137
1
R3502
715
1%
1/16W
MF-LF
402 2
Y3500
12.000M-100PPM
1
GL137
R35061
402
GL137
CRITICAL
GL137_CLK12M_X1
GL137_CLK12M_X2
13 X1
14 X2
GL137_RREF
10 RREF
GL137_TESTMOD
17 TESTMOD
GL137_RESET_L
NO STUFF
18 EXTRSTZ* (IPU)
(IPD)
0.1UF
OUT
R3556
GL137
OUT
SD_WP
OUT
SD_CD_L
GL137
5%
5%
50V
50V
CERM
402
CERM
402
Q3500
34
33PF
1/16W MF-LF 402
SD_D<2>
6 34
5%
1/16W MF-LF 402
SD_D<3>
6 34
BCM57765
1
6 34
MAKE_BASE=TRUE
5%
SD_CLK
6 34
SD_CMD
6 34
1/16W MF-LF 402
1/16W MF-LF 402 MAKE_BASE=TRUE
SD_WP
SD_CD_L
MAKE_BASE=TRUE
6 34 37
6 34 37
R3555
PP3V3_S0
20%
6.3V
CERM1 2
603
PP3V3_SW_SD_PWR
R3505
39K
0.1UF
Max Current = 250 mA
5%
1/16W
MF-LF
2 402
20%
10V
2 CERM
402
CRITICAL
J3500
SD-CARD-K19-K24
F-RT-TH
3
6
34 6
34 6
34 6
34 6
34 6
34 6
34 6
34 6
34 6
SD_CLK
SD_CMD
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
5
2
7
8
9
1
10
11
12
13
14
SD_CLK_R
37 34 6
SD_WP
37 34 6
SD_CD_L
15
16
4
GL137_PDMOD
NO STUFF
NC
31
NC
42
NC
44
NC
45
NC
VOLTAGE=3.3V
MAKE_BASE=TRUE
C3505
5%
1/10W
MF-LF
603
40
43
37
29
28
30
32
38
(IPU) XD_CDZ
XD_CE
(IPD) XD_WEZ
(IPD) XD_RBZ
(IPD) XD_WPZ
16
27
33PF
6 34
MAKE_BASE=TRUE
34 6
D0
D1
D2
D3
D4
D5
D6
D7
3
41
2
23
GND
12
C3512
5
9
C3511
5%
5%
5%
1/16W
MF-LF
402 2
(IPU) MS_INS 24
(IPD) MS_BS 33
20%
10V
CERM 2
402
10K
(IPD) SD_WP
(IPD) SD_CMD
(IPU) PDMOD
(IPU) SD_CDZ
8X4.5X1.4-SM
GL137
R35121
CLK 39
C3513 1
5%
1/16W
MF-LF
2 402
36
25
15
26
35
U3500
7 DM
8 DP
USB_SDCARD_N
USB_SDCARD_P
2.2UF
GL137
PMOSO
VDD5V
NO STUFF
DVDD
4
VDD18O
402
5%
1/16W
MF-LF
402 2
C3507 1
NC
20%
R35071
1/16W MF-LF 402
BCM57765
R3554
72 69 68 63 62 58 54 52 51 50
25 24 23 21 20 19 18 17 7 6
48 47 46 42 40 37 30 28 27 26
99 88 87 85 84 83 80 73
10V
CERM 2
GL137
6 34
SD_D<1>
SD_D<4..7>
SDCONN_CMD
0.1UF
20%
2 10V
CERM
402
0.1UF
5%
SD_D<0>
1/16W MF-LF 402
BCM57765
6
AVDD 11
GL137
5%
BCM57765
SDCONN_CLK
Keep this net short!
C3506 1
BCM57765
IN
PP1V8_S3_CARDREADER
BYPASS=U3500.4:5:5 mm
BCM57765
C3508
20%
2 10V
CERM
402
20%
6.3V 2
X5R
37 34 6
R3553
BI
0.22UH
0805-1
BCM57765
BI
R3513
10K
5%
1/16W
MF-LF
402 2
18
GL137
R3504
1
19
20
5%
1/16W
MF-LF
402
CMD
DAT0
DAT1
DAT2
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
NO STUFF
1
C3515
10PF
5%
2 50V
CERM
402-1
NC
NC
17
VSS
VSS
CLK
516-0225
PDMOD: POWER DOWN MODES

NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
10K HIGH = REMOTE WAKE UP ENABLE
D 3
SSM6N15FEAPE
SOT563
5
25 20
IN
SDCARD_RESET
S 4
SDCARD_PLT_RST
GL137
Q3500
D 6
SSM6N15FEAPE
SOT563
2
27
IN
S 1
SDCARD_PLT_RST_L
SYNC_MASTER=T27_REF
PAGE TITLE
SecureDigital Card Reader

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
35 OF 132
SHEET
34 OF 101
PP3V3_S3
USB HUB-1
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
R3640
PP3V3_S5
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57
20K
5%
1/16W
MF-LF
402
R3641
10K
100K
5%
1/16W
MF-LF
402 2
L3658
FERR-120-OHM-1.5A
PP3V3_S3
101 87 73 72
33 32 31 20 17 8 7 6
55 54 53 50 48 36 35 34
10%
2 16V
CERM
402
C3618
10UF
2
1
5%
2 50V
CERM
402
1 C3639
C3638
10UF
0.1UF
VOLTAGE=3.3V
C3623
0.1UF
10%
2 16V
X7R-CERM
402
C3642
0.01UF
10%
2 16V
CERM
402
10%
2 16V
CERM
402
10%
2 16V
CERM
402
10%
6.3V
2 CERM-X5R
402
5%
2 50V
CERM
402
1 C3645
C3644
10UF
0.1UF
10%
2 16V
X7R-CERM
402
20%
2 6.3V
X5R
603
10%
2 16V
X7R-CERM
402
10%
2 16V
X7R-CERM
402
PPUSB_HUB1_VDD1V8PLL
VOLTAGE=1.8V
C3624
0.1UF
C3627
1UF
C3628
0.1UF
10%
2 16V
X7R-CERM
402
10%
2 16V
X5R
402
R3691
1M
1
5%
1/16W
MF-LF
402
USB_HUB_RESET_L
C3630
1UF
D3600
SOD-523
PP3V3_S3
HUB1_NONREM1_1
R36041
10K
C3634
0.1UF
10%
2 16V
X5R
402
5%
1/16W
MF-LF
4022
NOSTUFF
10K
5%
1/16W
MF-LF
4022
VCC
U3614
AT24C02B
SOT23-5
WP_HUB1
R36921
WP
TEST
26
RESET*
NOSTUFF
OMIT
XTAL1/CLKIN
XTAL2
28
SUSP_IND/LOCAL_PWR/NON_REM0
USB_HUB1_SMBDATA
22
SDA/SMBDATA/NON_REM1
USB_HUB1_SMBCLK
24
SCL/SMBCLK/CFG_SEL0
USB_HUB1_CFG_SEL1
25
HS_IND/CFG_SEL1
USBDN1_DM/PRT_DIS_M1
USBDN1_DP/PRT_DIS_P1
1
2
USB_CAMERA_N
USB_CAMERA_P
3
4
BI
33
BI
33
USB_IR_N
USB_IR_P
BI
44 93
BI
44 93
USBDN3_DM/PRT_DOS_M3
6
7
USB_EXTB_N
USB_EXTB_P
BI
43 93
BI
43 93
8
9
USB_EXTC_N
USB_EXTC_P
BI
8 93
BI
8 93
12
16
18
20
TP_USB_HUB1_PRTPWR1
NC_USB_HUB1_PRTPWR2
NC_USB_HUB1_PRTPWR3
NC_USB_HUB1_PRTPWR4
OCS1*
OCS2*
OCS3*
OCS4*
13
17
19
21
TP_USB_HUB1_OCS1
NC_USB_HUB1_OCS2
USB_EXTB_OC_L
NC_USB_HUB1_OCS4
RBIAS
35
VBUS_DET
27
USB_HUB1_VBUS_DET
USBUP_DM
USBUP_DP
30
31
USB_HUB1_UP_N
USB_HUB1_UP_P
R3694
10K
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
IPU
IPU
IPU
IPU
GND
2
HUB1_NONREM0_0
1
R3666
R3667
10K
10K
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
SEL0
DESCRIPTION
K17/K18 configuration: 0
Internal Default with Self powered Operation
SMBUS Slave Config
Internal Default with Bus powered Operation
EEPROM Supported
R3668
100
IR Receiver
External B
PP3V3_S3
R36821
10K
5%
1/16W
MF-LF
4022
IN
43
IN
USB_HUB1_RBIAS
BI
19 93
BI
19 93
THRML_PAD
5%
1/16W
MF-LF
2 402
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
External C
CRITICAL
R3600
12K
37
HUB1_NONREM1_0
SEL1
Camera
PRTPWR1
PRTPWR2
PRTPWR3
PRTPWR4
R3698
10K
SDA 3
SCL 1
R3665
10K
IN
BAT54XV2T1
USX2061
11
33
32
USB_HUB1_LOCAL_PWR
101
54 53 50 48
32 31 20 17 8 7 6
36 35 34 33
87 73 72 55
C3640
QFN
USB_HUB1_TEST
USB_HUB1_XTAL1
USB_HUB1_XTAL2
CRITICAL
SOT-363
U3600
C3620
18PF
36 35
VDD18 14
5%
1/16W
MF-LF
2 402
5%
2 50V
CERM
402
2N7002DW-X-G
VDD18PLL 34
CRITICAL
VDDA33
VDD33 23
5%
1/16W
MF-LF
4022
R3699
10K
VDD33CR 15
Y3600
5%
50V
CERM 2
402
HUB1_NONREM0_1
1
R3697
10K
24.000M-60PPM-16PF
VDD33PLL 36
5
29
10
NOSTUFF
C3619
18PF
Q3640
10%
2 16V
X5R
402
25 19
CRITICAL
1
VOLTAGE=1.8V
1 C3647
C3646
0.1UF
0.1UF
PP3V3_S3
5X3.2X1.4-SM
0.47UF
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
SOT-363
PPUSB_HUB1_VDD1V8
C3643
100PF
CRITICAL
2N7002DW-X-G
10%
2 16V
X7R-CERM
402
Q3640
6 7 8 17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87 101
C3625
C3626
C3629
0.1UF
0.01UF
0.01UF
10%
2 16V
X7R-CERM
402
USB_HUB_RESET_L
3
PPUSB_HUB1_VDDA3V3
0402
1
P3V3S3_EN_RC
PP3V3_S3
10%
2 16V
X7R-CERM
402
20%
2 6.3V
X5R
603
FERR-120-OHM-1.5A
1
USB_HUB_RESET
D
VOLTAGE=3.3V
C3637
100PF
2402
5%
2 50V
CERM
402
PPUSB_HUB1_VDDPLL3V3
L3629
20%
6.3V
2 X5R
603
C3641
100PF
6
0402
C3636
0.01UF
5%
1/16W
MF-LF
NOSTUFF
R3642
1%
1/16W
MF
2 402
BOM TABLE
TABLE_5_HEAD
CRITICAL
BOM OPTION
338S0720
PART#
QTY
DESCRIPTION
SMSC USB2514
U3600,U3700
CRITICAL
USBHUB_2514
338S0824
SMSC USB2514B
U3600,U3700
CRITICAL
USBHUB_2514B
U3600,U3700
CRITICAL
USBHUB_2061
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
338S0721
SMSC USX2061
SYNC_MASTER=K18_MLB SYNC_DATE=10/07/2009
PAGE TITLE
NON_REM1
0
0
1
1
NON_REM0
DESCRIPTION
0
All ports are removable
1
Port 1 is non removable
0
Port 1 and 2 are non removable
1
Port 1, 2, and 3 are non removable
USB HUB 1
DRAWING NUMBER
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
Apple Inc.
TABLE_BOMGROUP_ITEM
HUB1_ALLREM
HUB1_NONREM1_0,HUB1_NONREM0_0
HUB1_1NONREM
<E4LABEL>
TABLE_BOMGROUP_ITEM
BRANCH
<BRANCH>
TABLE_BOMGROUP_ITEM
HUB1_2NONREM
HUB1_3NONREM
TABLE_BOMGROUP_ITEM

SIZE
<SCH_NUM> D
REVISION
PAGE
36 OF 132
SHEET
35 OF 101
USB HUB-2
D
L3758
FERR-120-OHM-1.5A
1
PP3V3_S3
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
PPUSB_HUB2_VDDPLL3V3
VOLTAGE=3.3V
0402
C3736
0.01UF
10%
2 16V
CERM
402
C3718
10UF
C3737
100PF
5%
2 50V
CERM
402
FERR-120-OHM-1.5A
1
VOLTAGE=3.3V
PP3V3_S3
10%
2 16V
X7R-CERM
402
20%
2 6.3V
X5R
603
L3729
20%
2 6.3V
X5R
603
1 C3739
C3738
10UF
0.1UF
C3723
0.1UF
10%
2 16V
X7R-CERM
402
C3742
0.01UF
10%
2 16V
CERM
402
10%
2 16V
CERM
402
PPUSB_HUB2_VDD1V8
C3743
100PF
1 C3745
C3744
10UF
0.1UF
20%
2 6.3V
X5R
603
5%
2 50V
CERM
402
10%
2 16V
CERM
402
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
C3725
C3726
C3729
0.1UF
0.01UF
0.01UF
10%
2 16V
X7R-CERM
402
PPUSB_HUB2_VDDA3V3
0402
1
10%
2 16V
X7R-CERM
402
VOLTAGE=1.8V
1 C3747
C3746
0.1UF
0.1UF
10%
2 16V
X7R-CERM
402
10%
2 16V
X7R-CERM
402
PPUSB_HUB2_VDD1V8PLL
VOLTAGE=1.8V
C3724
0.1UF
10%
2 16V
X7R-CERM
402
C3727
1UF
10%
2 16V
X5R
402
C3728
0.1UF
C3730
1UF
10%
2 16V
X5R
402
10%
2 16V
X7R-CERM
402
PP3V3_S3
CRITICAL
5X3.2X1.4-SM
1
C3719
18PF
R3791
1M
5%
50V
CERM 2
402
5%
1/16W
MF-LF
402
QFN
USB_HUB2_TEST
IN
USB_HUB_RESET_L
USB_HUB2_LOCAL_PWR
USB_HUB2_SMBDATA
USB_HUB2_SMBCLK
USB_HUB2_CFG_SEL1
PP3V3_S3
HUB2_NONREM1_1
R37041
10K
5%
1/16W
MF-LF
4022
C3734
0.1UF
NOSTUFF
R37921
10K
5%
1/16W
MF-LF
4022
VCC
U3714
AT24C02B
SOT23-5
WP_HUB2
WP
10%
2 16V
X5R
402
NOSTUFF
10K
XTAL1/CLKIN
XTAL2
28
SUSP_IND/LOCAL_PWR/NON_REM0
22
SDA/SMBDATA/NON_REM1
24
25
SCL/SMBCLK/CFG_SEL0
1
2
USB_BT_N
USB_BT_P
3
4
USB_TPAD_N
USB_TPAD_P
USBDN3_DM/PRT_DOS_M3
6
7
8
9
HUB2_NONREM0_0
R3766
R3767
10K
10K
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
SEL0
DESCRIPTION
Internal Default with Self powered Operation
SMBUS Slave Config
Internal Default with Bus powered Operation
EEPROM Supported
NON_REM0
DESCRIPTION
All ports are removable
Port 1 is non removable
Port 1 and 2 are non removable
Port 1, 2, and 3 are non removable
R3768
100
5%
1/16W
MF-LF
2 402
33 93
BI
53 93
BI
53 93
BI
8 34 93
BI
8 34 93
BI
43 93
BI
43 93
OCS1*
OCS2*
OCS3*
OCS4*
13
17
19
21
RBIAS
35
VBUS_DET
27
USB_HUB2_VBUS_DET
USBUP_DM
USBUP_DP
30
31
USB_HUB2_UP_N
USB_HUB2_UP_P
GND
USB_EXTA_N
USB_EXTA_P
33 93
BI
12
16
18
20
IPU
IPU
IPU
IPU
USB_SDCARD_N
USB_SDCARD_P
BI
PRTPWR1
PRTPWR2
PRTPWR3
PRTPWR4
HS_IND/CFG_SEL1
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
0
1
0
1
OMIT
R3794
K17/K18 configuration: 0
NON_REM1
0
0
1
1
RESET*
SDA 3
SCL 1
R3765
10K
26
R3798
10K
HUB2_NONREM1_0
SEL1
TEST
Bluetooth
Trackpad/Keyboard
SD Card/Express Card
TP_USB_HUB2_OCS1
NC_USB_HUB2_OCS2
NC_USB_HUB2_OCS3
USB_EXTA_OC_L
PP3V3_S3
External A
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
R3782
TP_USB_HUB2_PRTPWR1
NC_USB_HUB2_PRTPWR2
NC_USB_HUB2_PRTPWR3
NC_USB_HUB2_PRTPWR4
10K
5%
1/16W
MF-LF
4022
IN
IN
43
USB_HUB2_RBIAS
THRML_PAD
BI
19 93
BI
19 93
CRITICAL
1
R3700
12K
37
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
USX2061
11
33
32
USB_HUB2_XTAL1
USB_HUB2_XTAL2
CRITICAL
U3700
C3720
18PF
35
VDD18 14
5%
1/16W
MF-LF
2 402
5%
2 50V
CERM
402
VDDA33
VDD18PLL 34
5%
1/16W
MF-LF
4022
CRITICAL
R3799
10K
VDD33 23
Y3700
24.000M-60PPM-16PF
1
HUB2_NONREM0_1
1
R3797
10K
VDD33CR 15
NOSTUFF
CRITICAL
VDD33PLL 36
5
29
10
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
1%
1/16W
MF
2 402
SYNC_MASTER=K23F
TABLE_BOMGROUP_HEAD
BOM GROUP
PAGE TITLE
BOM OPTIONS
USB HUB 2
TABLE_BOMGROUP_ITEM
HUB2_ALLREM
HUB2_1NONREM
DRAWING NUMBER
TABLE_BOMGROUP_ITEM
Apple Inc.
TABLE_BOMGROUP_ITEM
HUB2_2NONREM
HUB2_3NONREM
<E4LABEL>
TABLE_BOMGROUP_ITEM

SIZE
<SCH_NUM> D
REVISION
BRANCH
<BRANCH>
PAGE
37 OF 132
SHEET
36 OF 101
BCM57765 SR pins are internal 1.2V switching regulator.

If unused: Okay to float all 4 pins. (Broadcom not so sure now)
If used:
VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY
TP_BCM57765_SR_VDDP
BCM57765_SR_VDD
BCM57765
37
R3915
PP3V3_ENET
86mA (1000base-T, Caesar II)
73 37 27 7 6
CRITICAL
37
BCM57765
SM
CRITICAL
L3920
37
BCM57765_VDDO_PIN20
PP1V2_ENET_PHY_AVDDL
VOLTAGE=3.3V
R3900
FERR-600-OHM-0.5A
1
2 37 PP3V3_ENET_PHY_XTALVDDH
VOLTAGE=3.3V
37
FERR-600-OHM-0.5A
5%
1/16W
MF-LF
402
L3900
BCM57765_SR_LX
BCM57765_SR_VFB
5%
1/16W
MF-LF
402
C3900 1
0.1UF
37
C3921 1
VOLTAGE=1.2V
1
10%
16V
X7R-CERM 2
402
10%
2 6.3V
X5R-CERM
603
0.1UF
BCM57765_XTALVDDH
VOLTAGE=3.3V
L3905
C3926 1
1
0.1UF
C3905
10%
16V
X7R-CERM 2
402
10%
2 16V
X7R-CERM
402
CRITICAL
L3910
R3910
10%
2 16V
X7R-CERM
402
5%
1/16W
MF-LF
402 2
L3930
C3911
C3931
0.1UF
0.1UF
C3936 1
10%
16V
X7R-CERM 2
402
10%
2 6.3V
X5R
805
PCIE_ENET_D2R_P
C3951
2
94
10%
16V
X5R
402
C3955
94
94
0.1uF
94 17
94 17
IN
IN
PCIE_ENET_R2D_C_P
1
10%
16V
X5R
402
PCIE_ENET_R2D_C_N
C3956
0.1uF
1
R3943
OUT
94
BCM57765
37 27
ENET_WAKE_L
(See note)
2
10%
16V
X5R
402
(IPD)
PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P
27 PCIE_TXD_N
28 PCIE_TXD_P
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
33 PCIE_RXD_P
34 PCIE_RXD_N
IN
IN
ENET_RESET_L
11 PERST*
(IPD)
OUT
ENET_CLKREQ_L
12 CLKREQ*
(OD)
94 17
95 27
BCM57765_WAKE_L
ENET_LOW_PWR
IN
Must isolate from PCIe WAKE# if PHY

is powered-down in S3/S5. Standard
N-channel FET isolation suggested.
If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
37
37
37
37
37
95 27
IN
95 27
OUT
0.1UF
VDDC 35
VDDC 61
29
32
39
45
51
WAKE* 13
U3900
TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N
BCM5764M
QFN-8X8
VERSION 2
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
IN
20
58 SMB_DATA
31 PCIE_REFCLK_P
30 PCIE_REFCLK_N
94 17
17
5%
1/16W
MF-LF
402
WAKE#
BCM57765_VMAIN_PRSNT
37
0.1uF
1
VDDIO 16
CRITICAL
OMIT
GPHY_PLLVDDL 36
5%
1/16W
MF-LF
2 402
(IPD)
OUT
10%
16V
X5R
402
AVDDL
PCIE_PLLVDDL
1K
VDDC 14
AVDDH
REGCTL12 15
10%
2 16V
X7R-CERM
402
0.1UF
7
20
56
62
10%
6.3V
X5R-CERM 2
603
4.7UF
3 LINKLED* (OD)
4 LOW_PWR
6 VDDC
10 UART_MODE
BCM5764_SCLK
BCM5764_MISO
BCM5764_MOSI
BCM5764_CS_L
66
64
65
63
TP_BCM5764_SPD100LED_L
TP_BCM5764_TRAFFICLED_L
2 SPD100LED*
67 TRAFFICLED*
18 XTALI
19 XTALO
BCM5764_RDAC
38 RDAC
SCLK
SI
SO
CS*
NC
VOLTAGE=3.3V
BCM57765_MEDIA_SENSE
1.24K
BCM57765_CR_CMD
0.1UF
VCC
10%
2 16V
X7R-CERM
402
U3990
AT45DB011D
37
BCM5764_SCLK
BCM5764_CS_L
SCK
CS*
WP*
RESET*
OMIT
BCM5764_MOSI
SI 1
SO 8
BCM57765
1
R3990
GND
4.7K
5%
1/16W
MF-LF
2 402
37
BCM5764_MISO
BCM5764M
C3970 1
BI
38 95
4.7UF
BI
38 95
BI
38 95
BCM57765
R3972
10%
16V
2 X7R-CERM
402
BCM57765
0
ENET_ENERGY_DET
BCM57765
0
5%
1/16W MF-LF 402
SD_CD_L
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
OUT
17 37
IN
6 34
34
25
24
23
22
52
53
54
55
SDCONN_DATA<0>
SDCONN_DATA<1>
SDCONN_DATA<2>
SDCONN_DATA<3>
SDCONN_DATA<4>
SDCONN_DATA<5>
SDCONN_DATA<6>
SDCONN_DATA<7>
SMB_CLK
ENERGY_DET
DC5
SPD1000LED*
59
60
57
68
37
37
37
BCM57765_CR_DATA<4>
BCM57765_CR_DATA<5>
BCM57765_CR_DATA<6>
BCM57765_CR_DATA<7>
BCM57765_CE_L_MS_INS_L
BCM57765_CR_LED
R3975
R3976
R3977
R3978
0
0
0
0
1
1
1
1
2
2
2
2
BCM57765
37
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
BI
34
BI
34
BI
34
BI
34
BI
34
BI
34
BI
34
BI
34
All resistors above BOMOPTIONed BCM57765
37
SD_WP
IN 6 34
BCM57765 supports both active-levels for WP.
TP_BCM57765_XD_DET
BCM5764M Support
All parts below BOMOPTIONed BCM5764M
BCM5764M
R3980 0 1
2
13-WAKE*
37
BCM57765_SR_VFB
53-VMAIN_PRSNT
37
BCM57765_CR_DATA<5>
37
BCM57765_CE_L_MS_INS_L
BCM57765_VMAIN_PRSNT
BCM57765_CR_DATA<6>
BCM57765_SR_LX
37
BCM57765_VDDO_PIN20
37
37
37
37
37
37
37
BCM57765_CR_DATA<7>
BCM57765_XTALVDDH
BCM57765_SR_VDD
BCM57765_SMB_CLK
R3981
R3982
R3983
R3984
R3985
R3986
R3987
R3988
R3989
R3998
R3999
1K
4.7K
4.7K
1K
0
1
1
1
1
2
2
2
2
0
0
0
0
1
1
1
1
2
2
2
2
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
5%
1/16W MF-LF 402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
26-PCIE_VDDL
37
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
C3999 1
0.1UF
10%
16V
X7R-CERM 2
402
C3998
4.7UF
10%
2 6.3V
X5R-CERM
603
PLACE_NEAR=L3999.1:1 mm
17 37
27 37
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
PP3V3_ENET
6 7 27 37 73
PP3V3_ENET_PHY_XTALVDDH
37
PP1V2_ENET
6 7 37 71 72
402
402
402
402
SYNC_MASTER=T27_REF
PAGE TITLE
Ethernet PHY (Caesar II/IV)
FERR-600-OHM-0.5A
2
BCM57765_CR_CMD PLACE_NEAR=U3900.26:2 mm 1
SM CRITICAL
BCM5764M
BCM5764M
Keep net short,

with no stubs.
ENET_ENERGY_DET
ENET_WAKE_L (See note)
PP3V3_S0
L3999
C3972
0.1UF
10%
16V
2 X7R-CERM
402
DC4
DC3
DC2
DC1
NC
VMAIN_PRSNT
VAUX_PRSNT
VDDC
R3997
34
5%
1/16W
MF-LF
2 402
BCM57765
C3971
0.1UF
10%
6.3V
X5R-CERM 2
603
37
4.7K
BCM57765
1
IN
NOTE: Pull-down on SO plus internal pull-ups on

other 3 SPI pins configures BCM57765 for the
Atmel AT45DB011D (1Mbit) ROM. If a different
ROM is used then the straps must change.
NOTE: BCM5764M requires SI pull-down instead of SO.
38 95
OUT
55-VDDC
17-VDDC
14-VDDC
06-VDDC
37
38 95
BI
SDCONN_CMD
20-XTALVDDH
SOIC-8S1
BI
SDCONN_CLK
59-SMB_CLK
58-SMB_DATA
54-VAUX_PRSNT
16-VDDIO
C3990
38 95
PLACE_NEAR=L3999.1:1 mm
BCM5764M pin-function
BCM57765_CR_LED
60-ENERGY_DET
37
1%
1/16W
MF-LF
2 402
38 95
BI
21
37
69
R3965
ROM contains MAC address, PCIe config

info as well as code for Bonjour proxy.
Required for proper PHY operation.
(Required ROM size TBD)
PP3V3_ENET
73 37 27 7 6
38 95
BI
R3973
R3974
BCM57765_SD_DETECT
THRM_PAD
PHY Non-Volatile Memory
CR_BUS_PWR is not for SD Card power,

just decoupling for BCM57765 CR I/Os.
BI
DC0
PCIE_VDDL 26
(IPD-BCM5764M)
10UF
PP3V3R1V8_SW_SD_VIO
NC 1
(IPD)
BCM57765_SMB_CLK
BCM57765_SMB_DATA
C3935
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
40
41
44
43
46
47
50
49
GPIO_0/SERIAL_DO 5
GPIO_1/SERIAL_DI 8
GPIO_2 9
(IPU)
94 17
4.7UF
C3916
C3915 1
VDDC 17
5%
1/16W
MF-LF
2 402
VDDIO
XTALVDDH
VDDIO
VDDIO
4.7K
R3942
0.1uF
OUT
SM
C3930
10%
2 6.3V
X5R-CERM
603
BIASVDDH 37
R3941
5%
1/16W
MF-LF
402 2
C3950
VOLTAGE=1.2V
1
10%
16V
X7R-CERM 2
402
BCM57765
PCIE_ENET_D2R_N
10%
2 16V
X7R-CERM
402
94 17
4.7UF
10%
2 6.3V
X5R-CERM
603
CRITICAL
42
48
4.7K
SM
C3925
BCM57765
R39401
PP3V3_S0
C3910
0.1UF
4.7K
BCM57765
VOLTAGE=1.2V
1
FERR-600-OHM-0.5A
1
2
PP1V2_ENET_PHY_GPHYPLL
FERR-600-OHM-0.5A
1
2
PP3V3_ENET_PHY_AVDDH
VOLTAGE=3.3V
FERR-600-OHM-0.5A
1
2
PP1V2_ENET_PHY_PCIEPLL
0.1UF
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
4.7UF
L3925
VOLTAGE=3.3V
SM
PP1V2_ENET
6 7 37 71 72
396mA (1000base-T, Caesar II)
CRITICAL
FERR-600-OHM-0.5A
1
2
PP3V3_ENET_PHY_BIASVDDH
SM
2
SM
C3920
10%
16V
X7R-CERM 2
402
CRITICAL
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
39 OF 132
SHEET
37 OF 101
Page Notes
(NONE)
(NONE)
(NONE)
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1
1 C40021 C40041 C4006

C4000
0.1UF 0.1UF 0.1UF 0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
CRITICAL
95 37
BI
ENET_MDI_P<0>
95 37
BI
ENET_MDI_N<0>
T4000
SM
12
99
ENETCONN_P<0>
11
99
ENETCONN_N<0>
10
ENET_CTAP0
ENET_CTAP1
CRITICAL
J4000
RJ45-M97-3
TX
F-RT-TH
TLA-6T213HF
10
95 37
BI
ENET_MDI_N<1>
99
ENETCONN_N<1>
95 37
BI
ENET_MDI_P<1>
99
ENETCONN_P<1>
1
2
3
RX
4
5
CRITICAL
95 37
95 37
BI
ENET_MDI_N<2>
BI
ENET_MDI_P<2>
T4001
SM
6
7
12
99
ENETCONN_N<2>
11
99
ENETCONN_P<2>
11
12
10
ENET_CTAP2
ENET_CTAP3
TX
4
95 37
95 37
TLA-6T213HF
514-0636
BI
ENET_MDI_N<3>
99
ENETCONN_N<3>
BI
ENET_MDI_P<3>
99
ENETCONN_P<3>
RX
Transformers should be
1R40011
mirrored on opposite
R4000
75
75
sides of the board
5%
5%
1/16W
MF-LF
4022
1/16W
MF-LF
4022
1R4003
R4002
75
75
5%
1/16W
MF-LF
2402
CRITICAL
5%
1/16W
MF-LF
2402
ENET_BOB_SMITH_CAP
PLACE_NEAR=T4001.1:5mm
SLP2510P8
10%
2KV
CERM
1206
PLACE_NEAR=T4000.5:5mm
NC
IO
NC
IO
NC
IO
NC
IO
6 5 7 4 9 2 10 1
D4000
RCLAMP0524P
GND
D4001
RCLAMP0524P
GND
NC
IO
NC
IO
NC
IO
NC
IO
6 5 7 4 9 2 10 1
C4008
1000PF
SLP2510P8
CRITICAL
CRITICAL
SYNC_MASTER=K17_REF
PAGE TITLE
Ethernet Connector
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
40 OF 132
SHEET
38 OF 101
PP3V3_FW_FWPHY
7 mA I/O
C4120 1
C4121 1 C4122 1
1UF
1UF
10%
6.3V 2
CERM
402
C4123 1 C4124 1
1UF
10%
6.3V 2
CERM
402
6 7 39 40 41
138 mA
1UF
10%
6.3V 2
CERM
402
1UF
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
L4130
120-OHM-0.3A-EMI
1
2
PP3V3_FW_FWPHY_VDDA
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
114 mA FireWire PHY

TABLE_5_ITEM
114S0557
RES,0.475 ohm,1%,1/16W,0402
R4100
C4130 1 C4131 1
1UF
OMIT
1
0.2
VOLTAGE=1.0V
1%
1/16W
MF-LF
402
135 mA
10%
6.3V 2
CERM
402
L4135
120-OHM-0.3A-EMI
1
2
PP1V0_FW_FWPHY_AVDD
PP1V0_FW_R
25 mA PCIe SerDes
VOLTAGE=1.0V
0402-LF
C4110
1UF
10%
2 6.3V
CERM
402
C4100
1UF
10%
2 6.3V
CERM
402
120-OHM-0.3A-EMI
1
2
PP3V3_FW_FWPHY_VP25
17 mA PCIe SerDes
C4111
1UF
C4135 1
C4136 1
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
1UF
10%
2 6.3V
CERM
402
110 mA Digital Core

1
0402-LF
1UF
10%
6.3V 2
CERM
402
L4110
R4100
PP1V0_FW_FWPHY
C4132 1
1UF
10%
6.3V 2
CERM
402
40 7 6
VOLTAGE=3.3V
CRITICAL
VOLTAGE=3.3V
0402-LF
1UF
0 mA VReg PWR
C4101
1UF
10%
2 6.3V
CERM
402
C4102
1UF
10%
2 6.3V
CERM
402
C4103
1UF
10%
2 6.3V
CERM
402
C4104
1UF
C4105
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C4106
C4141 1
1UF
0.1UF
10%
2 6.3V
CERM
402
20%
10V
CERM 2
402
C4140
1UF
10%
2 6.3V
CERM
402
VDD10
41
IN
41
IN
96 41
BI
96 41 6
BI
96 41 40
BI
96 41 40
BI
41 6
BI
41 6
BI
96 41 6
BI
96 41 6
BI
96 41 40
BI
96 41 40
BI
PPVP_FW_CPS
R41601
IN
200K
1%
1/16W
MF-LF
402 2
41 6
BI
41 6
BI
41
BI
41 40
BI
41 6
BI
FWPHY_DS0
FWPHY_DS1
FWPHY_DS2
NC_FW0_TPBIAS
FW_P1_TPBIAS
NC_FW2_TPBIAS
PLACE_NEAR=U4100.B10:2mm
C4150
R4150
22PF
2
1
NC
22PF
Y4150
24.576MHZ
412
1%
1/16W
MF-LF
402
SM-3.2X2.5MM
R41611
2.94K
1%
1/16W
MF-LF
402 2
C4151 NC
2 4
5%
50V
CERM
402
FW_CLK24P576M_XO
CRITICAL
R4170
191
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402
R41621
470K
5%
1/16W
MF-LF
402 2
B8
A8
B5
A5
B3
A3
B9
A9
B6
A6
B4
A4
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
L6
L9
L5
L10
K12
94
94
94
94
0.1UF
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
C4175
1
0.1UF
C4176
1
BGA
REFCLKN N9
REFCLKP N10
PCI EXPRESS PHY
TP_FW643_TCK
NC_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
NT-2 (IPU) TRST* N1
FW643_TRST_L
NT-4 (IPU) TCK

NT-3 (IPU) TDI
(IPU) TDO
NT-1 (IPU) TMS
0.1UF
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
M4
N2
M1
M3
NT-10 (IPD)
FIXME!!! - TYPO IN SYMBOL REGCTL
POWER MANAGEMENT
NT-12 (IPD)
NT-13
IN
17 94
IN
17 94
IN
17 94
PCIE_FW_R2D_C_P
IN
17 94
2 16V
10%
X5R 402
10%
2 16V
X5R 402
PCIE_FW_D2R_N
OUT
17 94
PCIE_FW_D2R_P
OUT
17 94
PLACEMENT_NOTE=Place C4175 close to U4100

PP3V3_FW_FWPHY
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
C2
D13
E1
D2
L2
6 7 39 40 41
FW643_LDO
R41651
FW643_WAKE_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_PHY_L
OUT
8 40
OUT
40
5%
1/16W
MF-LF
402 2
R4166
10K
5%
1/16W
MF-LF
2 402
R4164
10K
K1
L8
F13
G13
NAND_TREE
REXT
XO
XI NT-9
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
NC_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
M13
N13
J2
L13
D12
D1
A10
H13
K13
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
NT-16 (IPD) SCIFCLK

NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
SCIF
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
G2
G1
H1
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
N12
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
5%
1/16W
MF-LF
2 402
MISCELLANEOUS
CHIP RESET
NT-5 PERST*
IN
40
R4163
10K
J12 OCR_CTL_V10
J13 OCR_CTL_V12 (Reserved)
VSS
10%
2 6.3V
CERM-X5R
402
N8
N7
N5
N6
PCIE_FW_R2D_C_N
10K
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
0.33UF
FW643
1394 PHY
B11 R0
B10 TPCPS
NC
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
TEST CONTROLLER
FW643_R0
FW643_TPCPS
C4162
0.1UF
C4171
1
VREG_PWR
U4100
B7 TPBIAS0
C3 TPBIAS1
A2 TPBIAS2
TP_FW643_OCR10_CTL
1
VP25
OMIT
CRITICAL
B13 ATBUSB
A13 ATBUSH
A11 ATBUSN
F12 DS0 (IPD) NT-19
E12 DS1 (IPD) NT-20
E13 DS2 (IPD) NT-21
NC_FW0_TPAN
NC_FW0_TPAP
FW_PORT1_TPA_N
FW_PORT1_TPA_P
NC_FW2_TPAN
NC_FW2_TPAP
NC_FW0_TPBN
NC_FW0_TPBP
FW_PORT1_TPB_N
FW_PORT1_TPB_P
NC_FW2_TPBN
NC_FW2_TPBP
VP
5%
1/16W
MF-LF
2 402
VREG_VSS
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
41
41
VDDH
VDD33
10%
2 16V
X5R 402
10%
2 16V
X5R 402
L12
NC
NC
NC
A12
D5
D6
D8
C1
C12
F1
G12
J1
L3
L11
M2
A1
B1
B12
C13
E2
E10
H2
H12
K2
L1
M12
N3
N11

C4170
1
SYNC_MASTER=K19_MLB
PAGE TITLE
FireWire LLC/PHY (FW643)

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
41 OF 132
SHEET
39 OF 101
Page Notes
3.3V FW FET

- =PPBUS_S5_FWPWRSW (system supply for bus power)
- =PP3V3_FW_LATEVG_ACTIVE
I(max)
= 1.7A (85C)
- =PPVP_FW_SUMNODE (power passthru summation node)

99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69

(NONE)
PP3V3_S0
U4201
1UF
10%
6.3V 2
CERM
402
TPS22924
C4201 1
40 20
FW_PWR_EN
IN
CSP
A2
B2
VIN
VOUT
PP3V3_FW_FWPHY 6
A1
B1
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
7 39 40 41
PP3V3_S0
1
R4281
CRITICAL
GND
40 39 7 6
PP1V0_FW_FWPHY
C1
PP3V3_FW_FWPHY
41 40 39 7 6
100K
R4280
C2 ON
10K
5%
1/16W
MF-LF
1%
1/16W
MF-LF
402
FW_PLUG_DET_L
1
OUT
8 20 40
R4277
R4276
10K
100K
5%
1/16W
MF-LF
402 2
FW_WAKE
1
1UF
10%
6.3V 2
CERM
402
DMB53D0UV
SOT-563
VIN
VOUT
PP1V0_FW_FWPHY 6
A1
B1
10%
6.3V
CERM 2
402
7 39 40
CRITICAL
GND
P1V0_RESET_GATE
C1
0.1UF
10%
16V
2 X5R
402
R4283
1
FW_CLKREQ_L
6
OUT
CRITICAL
Q4261
SOT-563
39 8
IN
FW643_WAKE_L
2 G
D 3
PLT_RESET_L
IN
19 27 31
Q4299
SOT-563
2 G
SOT563
DMB53D0UV
SSM6N15FEAPE
6
D
DMB53D0UV
10K
5%
1/16W
MF-LF
402
17 25
Q4276
SOT-563
C2 ON
C4276
CSP
A2
B2
DMB53D0UV
1UF
TPS22924
C4202 1
CRITICAL
Q4276
NOSTUFF
U4202
CRITICAL
Q4299
C4281 1
PP1V05_S0
40 26
10 7 6
25 24 23 21 20 18 17 15 13 12
86 73 70
5%
1/16W
MF-LF
2 402
CRITICAL
P1V0_FW_RC
1.05V FW FET
2 402
5 G
FW_RESET_L
S 4
OUT
39
PP1V05_FW PGOOD/FW_RESET_L
40 39
IN
40
39
FW_CLKREQ_PHY_L
FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
FireWire Port Power Switch

CRITICAL
CRITICAL
Q4260
NDS9407
86 82 70 69 67 66 65 49 7 6
89
PPBUS_G3H
1
R4260
470K
5%
1/16W
MF-LF
2 402
R4262
10K
5%
1/16W
MF-LF
402 2
C4260 1
PPBUS_FW_FWPWRSW_F
VOLTAGE=12.6V
MINISMDC110H24
PPBUS_FW_FWPWRSW_D
VOLTAGE=12.6V
PPVP_FW
6 7 41
CRS08-1.5A-30V
0.1UF
10%
25V 2
X5R
402
FWPWR_EN_L_DIV
4
B
FWPWR_EN_TRI
S
5
R42631
B
(SYM-VER2)
SOT-363
1
BSS8402DW
R4261
Q4262
21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP1V05_S0
330K
5%
1/16W
MF-LF
2 402
10
5%
1/16W
MF-LF
402 2
FWPWR_EN_TRI_R
R4275
Late-VG Protection
Q4261
Q4262
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
C4200
2 G
S 1
BI
BC847CDXV6TXG
SOT563
1
CRITICAL
Q4275
DMB53D0UV
1
C4270
0.1UF
10%
16V
2 X5R
402
FW_DET_EMIT
1
R4272
1K
1
BI
CRITICAL
Q4270
FW_P1_TPBIAS_R
CRITICAL
U4200
FW_PORT1_TPB_P
FW_PORT1_TPB_N
8 D1+
7 D1-
FW_PORT1_TPA_P
FW_PORT1_TPA_N
6 D2+
5 D2-
LLP
VCLMP 3
FWPWR_EN 4
6
D
TPD4S1394
5%
1/16W
MF-LF
2 402
Q4275
DMB53D0UV
TP_FW_LATEVG_VCLMP
FWPWR_EN
IN
FW_PWR_EN
GND
R4273
12K
5%
1/16W
MF-LF
2 402
PLACE_NEAR=C4360.1:2mm
SOT-563
40 20
2 G
CRITICAL
2
96 41 39
96 41 39
SYNC_MASTER=K19_MLB
1
R4201
100K
FireWire Port Power
5%
1/16W
MF-LF
PAGE TITLE
DRAWING NUMBER
2 402
Apple Inc.
41 39
IN
FW_P1_TPBIAS

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
8 20 40
PLACE_NEAR=J4310.1:2mm
BI
BC847CDXV6TXG
SOT563
VCC
BI
OUT
SOT-563
10%
2 16V
X5R
402
96 41 39
FW_PLUG_DET
Q4270
10%
25V 2
X5R
402
0.1UF
96 41 39
5%
1/16W
MF-LF
2 402
FW_DET_MIRROR
CRITICAL
0.1UF
SOT-363
(SYM-VER1)
FW_PLUG_DET_L
56K
5%
1/16W
MF-LF
2 402
NOSTUFF
C4261 1
SOT563
BSS8402DW
G
S
PLACE_NEAR=U4200.1:2mm
D 6
SSM6N15FEAPE
R4271
330K
5%
1/16W
MF-LF
2 402
FWPWR_EN_L
R4270
1K
FW_PWR_EN_L
D4260
SM
1.1A-24V
8
7
6
5
3
2
1
CRITICAL
F4260
SOI-HF
BRANCH
<BRANCH>
PAGE
42 OF 132
SHEET
40 OF 101
8
Page Notes

41 40 39 7 6
PP3V3_FW_FWPHY
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
R43821 R43801
10K
10K
1%
1/16W
MF-LF
402 2
- =GND_CHASSIS_FW_PORT1
- =GND_CHASSIS_FW_EMI_R
1%
1/16W
MF-LF
402 2
41 39
FireWire PHY Config Straps

(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
Configures PHY for:

41 39
- 1-port Portable Power Class (0)
FWPHY_DS2
39 41
FWPHY_DS1
FWPHY_DS1
39 41
39 41
R43811
- Port "1" Bilingual (1394B)
10K
1%
1/16W
MF-LF
402 2
41 39
41 39 6
96 41 39
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
96 41 39 6
41 39 6
41 39 6
96 41 39 6
96 41 39 6
Termination
41 39 6
SOT-363
(SYM-VER2)
C4360
0.33UF
NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
39 41
6 39 41
39 41 96
6 39 41 96
6 39 41
6 39 41
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
6 39 41 96
6 39 41 96
6 39 41
6 39 41
C
PPVP_FW_CPS MAKE_BASE=TRUE
VOLTAGE=12.6V
41 39
R43111
Cable Power
PPVP_FW
41 40 7 6
10%
2 6.3V
CERM-X5R
402
NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
NC_FW0_TPBIAS MAKE_BASE=TRUE
NC_FW2_TPBIAS MAKE_BASE=TRUE
NC_FW0_TPAN MAKE_BASE=TRUE
NC_FW0_TPAP MAKE_BASE=TRUE
NC_FW2_TPAN MAKE_BASE=TRUE
NC_FW2_TPAP MAKE_BASE=TRUE
Q4300
TI PHYs require 1uF even though

FW spec calls out 0.33uF
NC_FW0_TPBIAS
NC_FW2_TPBIAS
NC_FW0_TPAN
NC_FW0_TPAP
NC_FW2_TPAN
NC_FW2_TPAP
BSS8402DW
41 39 6
Place close to FireWire PHY
FWPHY_DS0
MAKE_BASE=TRUE
NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
FW_P1_TPBIAS
FWPHY_DS2
MAKE_BASE=TRUE

(NONE)
40 39
FWPHY_DS0
MAKE_BASE=TRUE
41 39
PPVP_FW_CPS
CRITICAL
39 41
L4310
41 40 7 6
FERR-250-OHM
PPVP_FW
1
5
470K
5%
1/16W
MF-LF
402 2
SM
1
56.2
1%
1/16W
MF-LF
PLACE_NEAR=U4100.A5:2mm 2 402
0.01UF
PORT 1
330K
R43611
5%
1/16W
MF-LF
402 2
56.2
1%
1/16W
MF-LF
402 2 PLACE_NEAR=U4100.B5:2mm
96 41 40 39
FW_PORT1_TPA_P
FW_PORT1_TPA_P
96 41 40 39
FW_PORT1_TPA_N
FW_PORT1_TPA_N
96 41 40 39
FW_PORT1_TPB_P
FW_PORT1_TPB_P
BILINGUAL
CPS_EN_L
39 40 41 96
CRITICAL
39 40 41 96
1394B-M97
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FW_PORT1_TPB_N
FW_PORT1_TPB_N
MAKE_BASE=TRUE
39 40 41 96
41 40 39 7 6
PP3V3_FW_FWPHY
R4362
56.2
1%
1/16W
MF-LF
2 402
R43631
F-RT-TH
BSS8402DW
G
S
39 40 41 96
96 41 40 39
SOT-363
FW_PORT1_TPB_N
1
9
2
8
NC 7
6
3
5
4
(FW_PORT1_BREF)
(SYM-VER1)
96 41 40 39
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U4100.B6:4mm 1 SIGNAL_MODEL=EMPTY
J4310
Q4300
MAKE_BASE=TRUE
96 41 40 39
PPVP_FW_PORT1_F
VOLTAGE=33V
R43121
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4360
C4314
Note: Trace PPVP_FW_PORT1 must handle up to 5A
10%
2 50V
X7R
402
CPS_EN_L_DIV
FW_PORT1_TPB_P
PLACE_NEAR=U4100.A6:4mm
56.2
1%
1/16W
MF-LF
402 2
(GND_FW_PORT1_VG)
96 41 40 39
FW_PORT1_TPA_N
96 41 40 39
FW_PORT1_TPA_P
FW_PORT1_AREF
TPB-
TPB(R)
TPBTPB<R>
OUTPUT
TPB+ TPB+
VP
VP
NCSC/NC
VG
TPA- TPAVG
TPA<R>
TPA+
INPUT
TPA(R)
TPA+
FW_PORT1_TPB_C
220pF
5%
2 25V
CERM
402
10
11
12
13
C4319 1
1
1 C4364 R4364
4.99K
0.1uF
10%
50V 2
X7R
603-1
1%
1/16W
MF-LF
402 2
CHASSIS
GND
R4319
1M
5%
1/16W
MF-LF
2 402
AREF needs to be isolated from all

local grounds per 1394b spec
514S0605
When a bilingual device is connected to a

beta-only device, there is no DC path
between them (to avoid ground offset issue)
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
BREF should be hard-connected to logic

ground for speed signaling and connection
SYNC_MASTER=K19_MLB
PAGE TITLE
FireWire Ports
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
43 OF 132
SHEET
41 OF 101
ODD Power Control
SATA ODD Connector

CRITICAL
CRITICAL
Q4590
TPCP8102
PP5V_S3
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
PP3V3_S0
ODD_PWR_EN_LS5V_L
Q4596
5%
1/16W
MF-LF
402
D 6
93 6
93 6
10
99
11
12
99
13
14
15
16
99
C4520 1
SATA_ODD_R2D_UF_N
7 8
IN
17 93
IN
17 93
10% 16V CERM 402
SATA_ODD_R2D_C_N
10% 16V CERM 402
0.01UF
SATA_ODD_R2D_P
SATA_ODD_R2D_N
CRITICAL
FL4525
90-OHM-100MA
SATA_ODD_D2R_UF_N
SATA_ODD_D2R_UF_P
DLP11S
3
93 6
C4526 1
SATA_ODD_D2R_C_N
516S0616
93 6
SATA_ODD_D2R_N
OUT
17 93
OUT
17 93
10% 16V CERM 402
C4525 1
SATA_ODD_D2R_C_P
SATA_ODD_D2R_P
10% 16V CERM 402
0.01UF
33K
S 1
5%
1/16W
MF-LF
402 2
ODD_PWR_EN
45 6
Q4596
SATA_ODD_R2D_C_P
0.01UF
R45901
2 G
C4521 1
SATA_ODD_R2D_UF_P
SYM_VER-1
PP3V3_S0
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
100K
5%
1/16W
MF-LF
402 2
SOT563
R4597
PP5V_SW_ODD
56 42 6
99
0.01UF
F-ST-SM
10%
16V
CERM
402
SSM6N15FEAPE
ODD_PWR_SS
J4500
0.01UF
100K 2
54722-0164
C4596
R4595
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
ensure the drive is unpowered in S3/S5.
CRITICAL
10%
10V
CERM 2
402
5%
1/16W
MF-LF
402 2
J4500 connection separated to

support debug sense resistor.
Alias together if no sense R.
0.068UF
100K
1 2
C4595 1
90-OHM-100MA
DLP11S
42
SYM_VER-1
23V1K-SM
R45961
FL4520
PP5V_SW_ODD_R
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
D 3
OUT
SMC_ODD_DETECT
Indicates disc presence
SSM6N15FEAPE
SOT563
5 G
20
IN
PS8511A / PS8515A Straps
S 4
ODD_PWR_EN_L
99 73 72 42 31 16 13 7 6
PP1V5_S3RS0
NO STUFF
PP5V_SW_ODD_R
42
PP5V_SW_ODD
VOLTAGE=5V
PS8511A:
6 42 56
VOLTAGE=5V
PIN
9
8
20
10
SATA HDD/IR/SIL Connector
NO STUFF
XW4599
SM
L4500
PLACE_NEAR=L4500.1:2mm
FERR-70-OHM-4A
1
VOLTAGE=5V
PP5V_S0_HDD_R
C4501
0.1UF
20%
10V
1 CERM
402
66 61 58 56
42 33 31 7 6
54 46 44 43
101 82 72 67
PP5V_S0
VOLTAGE=5V
2
0603
6 7 23 47 52 54 68 69 70 72 86
88
IN
SMBUS_PCH_CLK
IN
19
J4501
OUT
C4532
NC
0.1UF
10%
16V
2 X7R-CERM
402
10
11
12
13
14
15
16
17
18
19
20
21
22
SYS_LED_ANODE_R
C4531 1
0.001UF
NC
4.7
SYS_LED_ANODE
93 6
C4516 1
SATA_HDD_D2R_C_P
0.01UF
93 6
C4515 1
SATA_HDD_D2R_C_N
R4510
10% 16V
CERM 402
10K
5%
1/16W
MF-LF
1 402
10% 16V
CERM 402
93
93
FL4501
90-OHM-100MA
93
DLP11S
(C4514,
C4519 & R4510)
10%
16V
2 CERM
402
99
C4511 1
SATA_HDD_R2D_UF_N
0.01UF
1
99
C4510 1
SATA_HDD_R2D_UF_P
0.01UF
10% 16V
CERM 402
1
2
SATA_HDD_R2D_RDRV_OUT_N
SATA_HDD_R2D_RDRV_OUT_P
SATARDRVR_A_EN
IN
4
5
10% 16V
CERM 402
SATARDRVR_A_AUTOPWR_EN
42
42
42
7
17
SATARDRVR_A_I2C_EN
SATARDRVR_A_I2C_ADDR
10
8
SATARDRVR_A_I2C_SCL
SATARDRVR_A_I2C_SDA
19
18
C4580 1
0.01UF
C4581 1
0.01UF
C4585 1
0.01UF
C4586 1
0.01UF
42
42
42
NO STUFF
2
R4516
R4518
10K
10K
10K
5%
1/16W
MF-LF
402 1
5%
1/16W
MF-LF
1 402
5%
1/16W
MF-LF
1 402
A_EQ
(IPD)
SATARDRVR_A_I2C_SCL
42
18
B_EQ
(IPD)
SATARDRVR_A_I2C_SDA
42
93
TQFN
A_INP
A_INN
A_OUTP 15
A_OUTN 14
B_INN 12
B_INP 11
B_OUTN
B_OUTP
EN (IPU)
AUTOPW_EN
(IPD)
I2C_EN (IPD)
I2C_ADDR
(IPD)
SCL_CTL
SDA_CTL
REFERENCE DES
CRITICAL
SATA 3GB/S REDRIVER, LOW POWER
U4510
CRITICAL
RDRV:8511
338S0778
SATA 3GB/S REDRIVER, LOW POWER
U4510
CRITICAL
RDRV:8515A1
93
SATA_HDD_D2R_RDRV_OUT_P
C4518 1
SATA_HDD_D2R_RDRV_OUT_N
SATA_HDD_R2D_RDRV_IN_N
93
A_SD 20
B_SD 9
SATA_HDD_R2D_RDRV_IN_P
SATARDRVR_A_A_SD 42
SATARDRVR_A_B_SD 42
PS8515A:
x_SD pins are outputs
0.01UF
GND THRM
PAD
338S0848 (PS8515A2)
SATA_HDD_D2R_P
OUT
17 93
99
SATA_HDD_D2R_UF_N
SATA_HDD_D2R_N
OUT
17 93
SATA_HDD_R2D_C_N
IN
17 93
SATA_HDD_R2D_C_P
IN
17 93
10% 16V
CERM 402
(All 4 Rs, 2 Cs)

SIGNAL_MODEL=EMPTY
RDRV:NO
10PF
C4582 1
2 5%
CERM
R4580 1
50V
402
2
1%
1/16W
MF-LF 402
51.1
SYNC_MASTER=T27_REF
C4583 1
SATA_HDD_R2D_NORDRV_N
R4581 1
51.1
SATA_HDD_D2R_NORDRV_N
R4585 1
SATA_HDD_D2R_NORDRV_P
R4586 1
10% 16V
CERM 402
5%
50V
CERM
402
PAGE TITLE
SATA Connectors
10PF
SATA_HDD_R2D_NORDRV_P
SYM_VER-1
10% 16V
CERM 402
Addr: 0x94(Wr)/0x95(Rd)
Redriver Bypass Path
DLP11S
SATA_HDD_D2R_UF_P
10% 16V
CERM 402
C4513 1
C4512 1
99
10% 16V
CERM 402
C4517 1
10% 16V
CERM 402
2
0.01UF
93
BOM OPTION
FL4502
90-OHM-100MA
(All 4 Cs)
RDRV:8511&RDRV:8515A1&RDRV:8515A2
0.01UF
10% 16V
CERM 402
2
DESCRIPTION
0.01UF
10% 16V
CERM 402
2
QTY
BOMOPTIONs:
- RDRV:8511 stuffs PS8511A & associated parts (STRAPS TBD!!!)
- RDRV:8515A1&RDRV:8515A2 stuffs PS8515A & associated parts
- RDRV:NO stuffs bypass path (neither IC or associated parts stuffed)
CRITICAL
VDD
3
13
NOTE: Internal pulls are ~150K
(All 4 Cs)
SIGNAL_MODEL=EMPTY
RDRV:NO
6 7 13 16 31
42 72 73 99
CRITICAL
RDRV:8515A2
U4510
SATA_HDD_D2R_RDRV_IN_P
SATA_HDD_D2R_RDRV_IN_N
42
NO STUFF
42
338S0769
PS8515A-A2
25 17
SYM_VER-1
10%
6.3V
CERM-X5R 2
402
CRITICAL
SATA_HDD_R2D_N
SATA_HDD_R2D_P
PP1V5_S3RS0
(All 4 Cs)
1 C4519
C4514 1
1UF
0.01UF
93
93 6
6 46
10%
50V
CERM 2
402
516S0687
93 6
IN
5%
1/16W
MF-LF
402
0.01UF
SATA Redriver
6
16
NC
PART NUMBER
6 44
R4531
21
IR_RX_OUT
F-ST-SM
PP5V_S3_IR_R
SATARDRVR_A_B_SD
SATARDRVR_A_I2C_ADDR
SATARDRVR_A_A_SD
SATARDRVR_A_I2C_EN
R4514
SMBUS_PCH_DATA
CRITICAL
VOLTAGE=5V
NO STUFF
5%
1/16W
MF-LF
402
54722-0224
6
5%
1/16W
MF-LF
1 402
RDRV:8515A1&RDRV:8515A2
10
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
88 63 48 47 32 30 28 26 25 17
94
5%
1/16W
MF-LF
402 1
10K
R4513
88 63 48 47 32 30 28 26 25 17
94
0.1UF
PP5V_S3
R4532
10K
5%
1/16W
MF-LF
1 402
R45122
R4520
5%
1/16W
MF-LF
402 2
R4517
10K
(IPD)
(IPD)
(IPU)
(IPU)
10K
R4515
10K
5%
1/16W
MF-LF
402 1
C4502
20%
10V
1 CERM
402
NO STUFF
R45191
CRITICAL
PP5V_S0_HDD_FLT
NAME
A_PRE
B_PRE
A_BST#
B_BST#
R45112
XW4598
SM
DRAWING NUMBER
Apple Inc.
2
1%
1/16W
MF-LF 402

2
5%
1/16W
MF-LF 402
2
5%
1/16W
MF-LF 402

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
45 OF 132
SHEET
42 OF 101
Port Power Switch
Left USB Port A
CRITICAL
CRITICAL
L4605
Q4690
72 67 66 61 58 56 54 46 44 42 33 31 7 6
101 82
72 46 45 31 18
73
2 IN
PM_SLP_S4_L
36
R4690
35
OUT
OUT
USB_EXTB_OC_L
3 EN1
5 OC2*
10UF
20%
6.3V 2
X5R
603
0.47UF
10%
10V 2
X5R
402
J4600
20%
16V
CERM 2
402
10UF
20%
2 10V
CERM
402
F-RT-TH-M97-4
5
L4600
90-OHM-100MA
SYM_VER-1
CRITICAL
C4695 1
0.1UF
USB
CRITICAL
DLP11S
C4691
CRITICAL
0.01uF
VOLTAGE=5V
GND TPAD
1
VOLTAGE=5V
0603
C4605
PP5V_S3_RTUSB_B_ILIM
OUT2 6
EN2
USB_PWR_EN
C4690
C4692
OC1*
5%
1/16W
MF-LF
2 402
VOLTAGE=5V
MSOP
USB_EXTA_OC_L
5.1K
PP5V_S3_RTUSB_A_ILIM
7
OUT1
20%
6.3V 2
X5R
603
CRITICAL
C4696 C4617
10UF
100UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
20%
6.3V
X5R
603
USB2_EXTA_MUXED_N
99 6
USB2_LT1_N
99 6
USB2_LT1_P
1
2
C4616
100UF
99
20%
2 6.3V
POLY-TANT
CASE-B2-SM
99
USB2_EXTA_MUXED_P
3
4
2 5 3 4
6 VBUS
NC
IO
NC
IO
TPS2064DGN
PP5V_S3
FERR-220-OHM-2.5A
1
2 6 PP5V_S3_RTUSB_A_F
7
8
1 GND
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
Place L4600 and L4605 at connector pin
1
2 6 PP5V_S3_RTUSB_B_F
0603
C4615
VOLTAGE=5V
0.01uF
20%
2 16V
CERM
402
CRITICAL
J4610
USB/SMC Debug Mux
USB
F-RT-TH-M97-4
5
SMC_DEBUG_YES
73 66 65
45 23 21 17 7 6
64 53 49 48 47 46
CRITICAL
L4610
PP3V42_G3H
90-OHM-100MA
DLP11S
SYM_VER-1
R4650
0.1UF
47 46 45 6
IN
47 46 45 6
OUT
SMC_RX_L
SMC_TX_L
20%
10V
CERM 2
402
VCC
5 M+
4 M-
BI
USB_EXTB_N
10K
C4650 1
93 35
U4650
Y+ 1
Y- 2
99 6
5%
1/16W
MF-LF
2 402
93 35
BI
USB_EXTB_P
BI
93 36
BI
USB_EXTA_P
USB_EXTA_N
7 D+
6 D-
2
3
4
7
2 5 3 4
6 VBUS
TQFN
CRITICAL
1 GND
SEL 10
8 OE*
USB_LT2_N
USB_LT2_P
PI3USB102ZLE
93 36
99 6
NC
IO
NC
IO
SMC_DEBUG_YES
GND
USB_DEBUGPRT_EN_L
SEL=0 Choose SMC
SEL=1 Choose USB
IN
45
D4610
RCLAMP0502N
SLP1210N6
CRITICAL
SMC_DEBUG_NO
SYNC_MASTER=K17_REF
R4651
1
5%
1/16W
MF-LF
402
Left USB Port B
External USB Connectors
SMC_DEBUG_NO
DRAWING NUMBER
R4652
0
Apple Inc.

SIZE
<SCH_NUM> D
REVISION
5%
1/16W
MF-LF
402
PAGE TITLE
<E4LABEL>
BRANCH
<BRANCH>
PAGE
46 OF 132
SHEET
43 OF 101
IR SUPPORT
D
PP5V_S3
72 67 66 61 58 56 54 46 43 42 33 31 7 6
101 82
C4801
0.1UF
14
10%
2 16V
X7R-CERM
402
VCC
U4800
CY7C63803-LQXC
93 35
BI
93 35
BI
QFN
12 P1.0/D+
P0.0
13 P1.1/DP0.1
15
IR_VREF_FILTER
P1.2/VREG
INT0/P0.2
16 P1.3/SSEL
INT1/P0.3
17 P1.4/SCLK
INT2/P0.4
1
18 P1.5/SMOSI
TIO0/P0.5
1UF
10%
19 P1.6/SMISO
TIO1/P0.6
2 10V
X5R
402-1
8
CRITICAL
OMIT
9
10
P/N 338S0633
20
21 NC
USB_IR_P
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_N
DIFFERENTIAL_PAIR=USB2_IR
C4803
R4800
IR_RX_OUT_RC
100
IR_RX_OUT
IN
6 42
5%
1/16W
MF-LF
402
1
C4804
0.001UF
10%
2 50V
CERM
402
C
25
THRML
PAD
VSS
11
22
23
24
7
6
5
4
3
2
1
SYNC_MASTER=K19_MLB
PAGE TITLE
Front Flex Support

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
48 OF 132
SHEET
44 OF 101
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
46 6
49 48 47 46 43 23 21 17 7 6
73 66 65 64 53
22UF
20%
6.3V 2
CERM
805
C4903
0.1UF
20%
2 10V
CERM
402
C4905
0.1UF
20%
2 10V
CERM
402
C4906
0.1UF
20%
2 10V
CERM
402
SMC_VCL
OUT
OUT
87 73 27 25
IN
73
IN
68
OUT
25 18
OUT
PM_RSMRST_L
CPUIMVP_VR_ON
PM_PWRBTN_L
46 6
OUT
NC_ESTARLDO_EN
18
U4900
TP_SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
OUT
46
49 46
TP_SMC_P24
SMC_BMON_MUX_SEL
NC
NC
NC
NC
NC
NC
94 87 47 17 6
BI
94 87 47 17 6
BI
94 87 47 17 6
BI
94 87 47 17 6
BI
94 87 47 17 6
IN
27
IN
94 27
47 17 6
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
IN
BI
TP_SMC_P41
SMBUS_SMC_MGMT_SDA
SMS_PWRDN
55
BI
OUT
80
OUT
54
OUT
47 46 45 43 6
OUT
47 46 45 43 6
97 81 51 48
IN
BI
(DEBUG_SW_1)
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
P10
P11
P12
P13
P14
P15
P16
P17
D13
E11
D12
F11
E13
E12
F13
E10
P20
P21
P22
P23
P24
P25
P26
P27
A9
D9
C8
B7
A8
D8
D7
D6
NC
46 6
97 56 48
B12
A13
A12
B13
D11
C13
C12
D10
(OC)
NC
NC
SMC_TX_L
SMC_RX_L
SMBUS_SMC_0_S0_SCL
(OC)
SMC_PA0
PM_SYSRST_L
USB_DEBUGPRT_EN_L
MEM_EVENT_A_L
MEM_EVENT_B_L
SYS_ONEWIRE
PM_BATLOW_L
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
OUT
27 18 6
OUT
43
OUT
46 30 28
BI
46
BI
64 46
BI
18
OUT
20
OUT
P40
P41
P42
P43
P44
P45
P46
P47
G2
F3
E4
P50
P51
P52
IN
46 25
46
IN
46
IN
80
IN
52
OUT
52
OUT
46 6
OUT
46 6
OUT
52
IN
52
IN
46 6
IN
46 6
IN
55
IN
55
IN
55
IN
50 46
IN
50 46
IN
50 46
IN
49 46
IN
49 46
IN
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_IG_THROTTLE_L (See below)
20
SMC_EXCARD_CP
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
OMIT
SMC_PM_G2_EN
P60
P61
P62
P63
P64
P65
P66
P67
L13
K12
K11
J12
K13
J10
J11
H12
P70
P71
P72
P73
P74
P75
P76
P77
N10
M11
L10
N11
N12
M13
N13
L12
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_GFX_ISENSE
P80
P81
P82
P83
P84
P85
P86
A7
B6
C7
D5
A6
B5
C6
SMC_WAKE_SCI_L
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
(OC) SMBUS_SMC_MGMT_SCL
P90
P91
P92
P93
P94
P95
P96
P97
J4
G3
H2
G1
H4
G4
F4
F1
SMC_ONOFF_L
SMC_BC_ACOK
SMC_P92
46
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_CLK32K
(OC) SMBUS_SMC_0_S0_SDA
NC
NC
NC
NC
NC
N3
N1
M3
M2
N2
L1
K3
L2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
B8
C9
B9
A10
C10
B10
C11
A11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
SMC_FAN_0_CTL
SMC_FAN_1_CTL
NC_SMC_FAN_2_CTL
NC_SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
NC_SMC_FAN_2_TACH
NC_SMC_FAN_3_TACH
G11
G13
F12
H13
G10
G12
H11
J13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_GPU_1V8_ISENSE
SMC_CPUVTT_ISENSE
SMC_P1V5S3_ISENSE
SMC_GFX_VSENSE
SMC_CPU_HI_ISENSE
M10
N9
K10
L8
M9
N8
K9
L7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
H8S2117
LGA-HF
(2 OF 3)
OMIT
OUT
66 73
AVCC
VCC
VCL AVREF
10%
6.3V
CERM-X5R 2
402
R49091
U4900
NC
E5
MD1
MD2
D1
H1
NMI
E3
ETRST
H3
AVSS
L9
H8S2117
10K
NC
5%
1/16W
MF-LF
402 2
LGA-HF
(3 OF 3)
SMC_ADAPTER_EN
OUT
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
18 46 73
IN
46
IN
6 46 64
IN
50
IN
49
IN
50
IN
49
IN
49
IN
49
IN
49
IN
46 50
OMIT
65 47 46 6
IN
46
OUT
17
OUT
6 18 47
46
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
A2
XTAL
EXTAL
K1
J3
K2
J1
K4
K5
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
G3_POWERON_L
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
M6
L5
M5
N4
L4
M4
SMC_SYS_LED
SMC_LID
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
N7
K8
K7
K6
N6
M7
L6
PH0
PH1
PH2
PH3
PH4
PH5
E2
F2
J2
A4
B3
C4
TP_SMC_PF5
IN
6 43 45 46 47
IN
6 43 45 46 47
BI
6 46 53
IN
46 64 65
IN
6 18 31 73 85
IN
18 31 43 46 72 73
IN
18 46
IN
46
5%
1/16W
MF-LF
2 402
SMC_MD1
IN
6 47
SMC_NMI
IN
6 47
IN
6 47
SMC_TRST_L
NO STUFF
1
R4902
R4998
10K
10K
5%
1/16W
MF-LF
2 402
XW4900
SM
5%
1/16W
MF-LF
2 402
R4903
0
5%
1/16W
MF-LF
2 402
GND_SMC_AVSS
46 49 50
NOTE: P94 and P95 are shorted, P95 could be spare.
48 51 81 97
IN
46
IN
6 46 47
IN
6 46 47
OUT
10K
48 56 97
IN
BI
R4901
PLACE_NEAR=U4900.L3:4mm
6 18 47
OUT
SMC_KBC_MDE
VSS
PE0
PE1
PE2
PE3
PE4
PF0
NC
NC
0.47UF
0.1UF
20%
10V
CERM 2
402
PLACE_NEAR=U4900.E1:3mm
C4907 1
L11
C4920 1
E1
VOLTAGE=3.3V
NC
U4900
NC
42 6
LGA-HF
(1 OF 3)
P30
P31
P32
P33
P34
P35
P36
P37
D4
A5
B4
A1
C2
B2
C1
C3
46
17
H8S2117
PP3V3_S5_SMC_AVCC
D2
L3
F10
B11
C5
B1
M1
H10
4.7
5%
1/16W
MF-LF
402
C4904
M12
0.1UF
20%
2 10V
CERM
402
R4999 PLACE_NEAR=U4900.M12:3mm
PLACE_NEAR=U4900.M12:3mm
46
PP3V3_S5_AVREF_SMC
PP3V42_G3H
C4902 1
6 46 47
IN
6 46 47
IN
46
OUT
46
IN
46 53 64
IN
46
46
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMS_INT_L
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL
SMC_PROCHOT
SMC_THRMTRIP
NC
NC_ALS_GAIN
BI
6 48 64 65 97
BI
6 48 64 65 97
BI
6 33 48 54 97
BI
6 33 48 54 97
BI
48 51 97
BI
OUT
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
48 51 97
46
OUT
46
OUT
6 46
NC
NC
SYNC_MASTER=K17_REF
PAGE TITLE
SMC
DRAWING NUMBER
Apple Inc.
SMC_PB3:
R
SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
49 OF 132
SHEET
45 OF 101
NC_SMC_FAN_2_CTL
SMC Reset "Button" / Brownout Detect
NC_SMC_FAN_2_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_TACH
6 45 46
MAKE_BASE=TRUE
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
46 45 6
PP3V42_G3H
NC_SMC_FAN_3_CTL
NC_SMC_FAN_3_CTL
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
6 45 46
MAKE_BASE=TRUE
46 45 6
NC_SMC_FAN_3_TACH
NC_SMC_FAN_3_TACH
PP3V3_S0
6 45 46
MAKE_BASE=TRUE
C5000 1
0.1uF
SMC_MANUAL_RST_L
OMIT
R5001
5
4
NC
CD
NC
GND
OUT
IN
46 45 6
SMC_RESET_L
1
2
46 45
NC_ESTARLDO_EN
NC_ESTARLDO_EN
NC_ALS_GAIN
NC_ALS_GAIN
6 45 46
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
49 46 45
10%
16V
CERM 2
402
Q5032
45 46
MAKE_BASE=TRUE
SMC_BC_ACOK
SMC_BC_ACOK
45 46 64 65
SMC_BMON_MUX_SEL
45 46 49
MAKE_BASE=TRUE
SMC_BMON_MUX_SEL
MAKE_BASE=TRUE
53 46 45 6
IN
SMC_ONOFF_L
SOT553-5
4
SMC_TPAD_RST
46 45
45
IN
45
IN
45
SMC_IG_THROTTLE_L
SMC_IG_THROTTLE_L
5 G
SSM6N15FEAPE
20 25 45 46
SMS_INT_L
TO CPU
45 46
91 68 10
49 46 45
SMC_GFX_VSENSE
49 46 45
SMC_CPU_HI_ISENSE
50 46 45
SMC_CPUVTT_ISENSE
50 46 45
SMC_P1V5S3_ISENSE
50 46 45
SMC_GFX_ISENSE
50 46 45
SMC_GPU_1V8_ISENSE
SOT563
S 4
SMS_INT_L
S 1
NC
NC
02
46 45
SMC_GFX_VSENSE
R5062
CPU_PROCHOT_L
BI
SMC_CPU_HI_ISENSE
6 D
45 46 49
MAKE_BASE=TRUE
2 G
3.3K 2 CPU_PROCHOT_L_R
Q5060
DMB53D0UV
5%
1/16W
MF-LF
402
45 46 49
MAKE_BASE=TRUE
SOT-563
4
Q5059
SSM6N15FEAPE
SMC_CPUVTT_ISENSE
SOT563
45 46 50
MAKE_BASE=TRUE
SMC_P1V5S3_ISENSE
45 46 50
MAKE_BASE=TRUE
SMC_GFX_ISENSE
1 S
45 46 50
MAKE_BASE=TRUE
G 2
SMC_PROCHOT
SMC_GPU_1V8_ISENSE
45 46 50
MAKE_BASE=TRUE
TP_SMC_P24
Q5060
SOT-563
MAKE_BASE=TRUE
U5001
SN74LVC1G02
OUT
DMB53D0UV
D 6
Q5032
SOT563
SMC_TPAD_RST_L
D 3
SSM6N15FEAPE
PP3V42_G3H
TO SMC
SMC_PROCHOT_3_3_L
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
IN
5%
1/16W
MF-LF
2 402
CPU_PROCHOT_BUF
46 45 25 20
53
10K
6
65 64 46 45
NC
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
R5060
5%
1/16W
MF-LF
2 402
6 45 46
MAKE_BASE=TRUE
6 45 47 65
OUT
0.01UF
5%
1/10W
MF-LF
2 603
46 45 6
5%
1/16W
MF-LF
2 402
SOT23-5-HF
C5001 1
SILK_PART=SMC_RST
1K
NCP303LSN
R5061
100K
R5000
U5000
20%
10V
CERM 2
402
CRITICAL
SMC FSB to 3.3V Level Shifting
6 45 46
MAKE_BASE=TRUE
46 45 6
91 20 10
TP_SMC_P24
45 46
OUT
PM_THRMTRIP_L
MAKE_BASE=TRUE
46 45 6
TP_SMC_P41
46 45
TP_SMC_PF5
TP_SMC_P41
TP_SMC_PF5
REF3333
PP3V42_G3H
IN
OUT
SMC_EXCARD_OC_L
C5026
4 S
PCH_GPIO10
IN
SMC_THRMTRIP
REF DES
COMMENTS:
ALL
Intersil ISL60002-33
SMC_OSC_YES
VOLTAGE=0V
L5010
45 49 50
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
FERR-120-OHM-0.2A
1
2
PP3V42_G3H_SMC_CLK_F
PP3V42_G3H
0603
VOLTAGE=3.425V
SMC_OSC_YES
SMC_OSC_YES
C5002 1
4.7UF
SMC_XTAL
5%
1/16W
MF-LF
402
CRITICAL
Y5010 1
20.00MHZ
5X3.2-SM
2
45
12
VDD
15pF
NO STUFF
U5010
R5011
32.768KHZ-9-3.6V
SG-3040LC-SM
5%
50V
CERM
402
VIO
C5011
2
3
NC
NC
NC
NC
15pF
SMC_EXTAL
20%
2 10V
CERM
402
CRITICAL
C5010
SMC_XTAL_R
C5003
0.1UF
20%
6.3V 2
CERM
603
SMC Crystal Circuit

R5010
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
To support timed wake-up events in G3Hot
TABLE_ALT_ITEM
45
G 5
19 25
SMC G3Hot 32kHz Oscillator
20%
6.3V 2
X5R
603
GND_SMC_AVSS
353S1381 353S1912
5%
1/16W
MF-LF
402
10uF
TABLE_ALT_HEAD
BOM OPTION
OUT
10%
2 16V
CERM
402
C5020 C5025 1
0.47UF
ALTERNATE FOR
PART NUMBER
46 45
0.01UF
10%
6.3V
2 CERM-X5R
402
PART NUMBER
6 45
VOLTAGE=3.3V
GND
R5095
PP3V3_S5_AVREF_SMC
SOT23-3
SOT563
SMC_EXCARD
VR5020
47 46 45 43 23 21 17 7 6
73 66 65 64 53 49 48
Q5059
SSM6N15FEAPE
45 46
MAKE_BASE=TRUE
CRITICAL
3 D
6 45 46
MAKE_BASE=TRUE
SMC AVREF Supply
5%
50V
CERM
402
OUT
NC0
NC4
NC1
NC2
NC5
NC6
8
9
NC3
OMIT
NC7
10
11
GND
SMC_CLK32K_R
22
SMC_CLK32K
OUT
10K
10K
100K
10K
100K
2.0K
10K
10K
10K
10K
10K
470K
10K
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
SMC_P92
SMC_PA0
R5076
R5091
100K
100K
1
1
2
2
SMC_EXCARD_OC_L
R5092
SMC_EXCARD_NOT
100K 1
2
SMC_ADAPTER_EN
SMC_CASE_OPEN
R5085
R5086
10K
10K
1
1
2
2
SMC_EXCARD_CP
PM_SLP_S5_L
PM_SLP_S4_L
R5088
R5090
R5094
10K
100K
100K
1
1
1
2
2
2
MEM_EVENT_B_L
R5089
45
45
5%
1/16W
MF-LF
402
NC
NC
NC
NC
45
46 45
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
73 45 18
CRITICAL
BOM OPTION
CRITICAL
SMC_OSC_YES
45
TABLE_5_ITEM
197S0350
U5010
OSC,XTAL,32.768KHZ,LF,HF
R5012
System (Sleep) LED Circuit

82
58 56 54 44
7 6
43 42 33 31
72 67 66 61
101
94 18
IN
PM_CLK32K_SUSCLK
45
45 18
73 72 45 43 31 18
5%
1/16W
MF-LF
402
PP5V_S3
R50311
CPU PM_EXTTS_L / MEM_EVENT_L Level Shifting
R5030
523
1%
1/16W
MF-LF
2 402
45
1
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
SYS_LED_L_VDIV
R5042
10K
R5032
1%
1/16W
MF-LF
402 2
CRITICAL
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
Q5030
R5040
10K
SYS_LED_L
Q2
Q1
MEM_EVENT
SOT-563
FROM DIMMS
MEM_EVENT_A_L
28
IN
46 45 30
46 45 30 28
BI
MEM_EVENT_A_L
MAKE_BASE=TRUE
OUT
10 91
PM_EXT_TS_L<0>
OUT
10 91
SYS_LED_ANODE
OUT
402
402
402
402
402
402
402
402
402
402
402
402
402
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
1/16W MF-LF 402
PP3V3_S0
2
1/16W MF-LF 402
2N7002DW-X-G
SOT-363
Debug Power "Buttons"
Q5040
OMIT
2N7002DW-X-G
R5016
SOT-363
SYNC_MASTER=K18_SENSORS
5%
1/10W
MF-LF
603 2
SILK_PART=PWR_BTN
SMC_ONOFF_L
OMIT
OUT
6 42
SMC Support
DRAWING NUMBER
6 45 46 53
Apple Inc.
R5015
5%
1/10W
MF-LF
2 603
SILK_PART=PWR_BTN

SIZE
<SCH_NUM> D
REVISION
PAGE TITLE
5%
1/16W
MF-LF
402 2
Q5040
PLACEMENT_NOTE=Place R5015 on top side

PLACEMENT_NOTE=Place R5016 on bottom side
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
TO CPU
TO/FROM SMC
SMC_SYS_LED
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
5%
PM_EXT_TS_L<1>
5%
1/16W
MF-LF
2 402
PP3V3_S0
DMB54D0UV
IN
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/16W
MF-LF
402
PP3V3_S0
1.47K
10K
R5044
SYS_LED_ILIM
45
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
20
1%
1/16W
MF-LF
402 2
PP3V42_G3H
R5070
SMC_ONOFF_L
53 46 45 6
R5072
G3_POWERON_L
45
R5071
SMC_LID
64 53 45
R5073
SMC_TX_L
47 45 43 6
R5074
SMC_RX_L
47 45 43 6
SYS_ONEWIRE NO STUFF R5075
64 45
R5077
SMC_TMS
47 45 6
R5078
SMC_TDO
47 45 6
R5079
SMC_TDI
47 45 6
R5080
SMC_TCK
47 45 6
R5081
SMC_BIL_BUTTON_L
64 45 6
R5087
SMC_BC_ACOK
65 64 46 45
R5093
SMS_INT_L
46 45
<E4LABEL>
BRANCH
<BRANCH>
PAGE
50 OF 132
SHEET
46 OF 101
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
49 48 46 45 43 23 21 17 7 6
73 66 65 64 53
72 70 69 68 54 52 42 23 7 6
88 86
94 87 45 17 6
LPC_AD<0>
LPC_AD<1>
BI
94 87 45 17 6
BI
47 6
IN
47 6
OUT
94 87 45 17 6
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
IN
45 18 6
OUT
46 45 6
OUT
94 87 27 6
IN
46 45 6
OUT
45 6
IN
45 6
OUT
46 45 43 6
M-ST-SM
31
32
PP3V42_G3H
PP5V_S0
IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
IN
6 27 94
BI
6 17 45 87 94
BI
6 17 45 87 94
OUT
6 20 57
IN
6 47
IN
6 47
6 17 45
BI
IN
6 18 45
OUT
6 45 46
OUT
6 45 46
OUT
6 45 46 65
OUT
6 45
OUT
6 43 45 46
OUT
6 20
516S0573
SPI Bus Series Termination

SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
LPCPLUS
1
R5128
0
PLACE_NEAR=U1800.BA2:5mm
94 17
SPI_CLK_R
IN
PLACE_NEAR=U1800.AY1:5mm
94 17
SPI_MOSI_R
IN
15
15
SPI_CS0_L
OUT
SPI_CLK
SPI_MOSI
R5123
SPI_MISO
PP3V3_S0
15
47
47
47
SPI_MLB_CS_L
OUT
57
5%
1/16W
MF-LF
402
SPI_MLB_CLK
OUT
57
SPI_MLB_MOSI
OUT
57
SPI_MLB_MISO
IN
57
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
EFI_DEBUG
1
EFI_DEBUG EFI_DEBUG
1
20%
10V
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
DEBUGROM_E2
DEBUGROM_E1
EFI_DEBUG
402
VCC
3 E2
2 E1
M24M01-R
SO8N
R5102 1R5104
SDA 5
CRITICAL SCL
7 WC*
EFI Debug ROM
2 CERM
U5101
NO STUFF NO STUFF
1
C5101
0.1UF
R5101 R5103
5%
1/16W
MF-LF
402
R5122
94
69 68 63 62 58 54 52 51 50
25 24 23 21 20 19 18 17 7 6
48 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
R5125
5%
1/16W
MF-LF
402
94 17
6 47
LPCPLUS
5%
1/16W
MF-LF
2 402
R5121
94
6 47
47
5%
1/16W
MF-LF
2 402
6 47
R5120
94
5%
1/16W
MF-LF
402
R5112
1
15
R5126
47
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
R5111
1
LPCPLUS
1
R5110
PLACE_NEAR=U1800.AV3:5mm
SPI_CS0_R_L
IN
R5127
47
5%
1/16W
MF-LF
2 402
94 17
LPCPLUS
1
6 47
E0/NC0 1
SMBUS_PCH_DATA
BI
SMBUS_PCH_CLK
IN
17 25 26 28 30 32 42 48 63 88
94
17 25 26 28 30 32 42 48 63 88
94
SYNC_MASTER=K17_MLB
NC
PAGE TITLE
LPC+SPI Debug Connector
VSS
4
DRAWING NUMBER
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
Apple Inc.
Write: 0xAC 0xAE

Read: 0xAD 0xAF

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
51 OF 132
SHEET
47 OF 101
PCH SMBus "0" Connections

99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
R52001
1K
5%
1/16W
MF-LF
402 2
U1800
(MASTER)
94 88 63 48
28 26 25 17
47 42 32 30
SMBUS_PCH_CLK
94 88 63 48
28 26 25 17
47 42 32 30
SMBUS_PCH_DATA
R5201
1K
5%
1/16W
MF-LF
2 402
SO-DIMM "A"
SMBUS_PCH_CLK
48
26
32
94
48
26
32
94
47
25
30
88
47
25
30
88
42
17
28
63
42
17
28
63
42
17
28
63
42
17
28
63
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
47
25
30
88
47
25
30
88
48
26
32
94
48
26
32
94
SMBUS_PCH_CLK
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_DATA
42
17
28
63
42
17
28
63
47
25
30
88
47
25
30
88
U4900
(MASTER)
SMBUS_SMC_0_S0_SCL
81 51 48 45
97
97
81
51 48
45
5%
1/16W
MF-LF
402 2
U2700
(Write: 0xD2 Read: 0xD3)
SMBUS_PCH_CLK
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_DATA
42
17
28
63
42
17
28
63
47
25
30
88
47
25
30
88
48
26
32
94
48
26
32
94
EFI Debug Serial
LED BACKLIGHT
U5101
U9701
(WRITE: 0x58 READ: 0x59)
(Write: 0xAC/AE Read: 0xAD/AF)

48
26
32
94
48
26
32
94
47
25
30
88
47
25
30
88
42
17
28
63
42
17
28
63
R5251
GPU Temp (Ext)
4.7K
5%
1/16W
MF-LF
2 402
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
SMBUS_PCH_CLK
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_DATA
PP3V42_G3H
R52801
SMC
EMC1414-A: U5550
(Write: 0x98 Read: 0x99)
MAKE_BASE=TRUE
97 81
51 48
45
SMBUS_SMC_0_S0_SDA
81 51 48 45
97
64 48 45 6
97 65
45 48 51
81 97
64 48 45 6
97 65
R5281
1K
SMBUS_SMC_BSA_SCL
Battery Charger
1K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
45 48 51
81 97
5%
1/16W
MF-LF
2 402
ISL6258 - U7000
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
42
17
28
63
42
17
28
63
47
25
30
88
47
25
30
88
48
26
32
94
48
26
32
94
97
51
45
48
81
51
45
48
81
97
Battery Manager - (Write: 0x16 Read: 0x17)

Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
6
54 48 45 33
97
48 45 33 6
97 54
SMBUS_SMC_A_S3_SCL
R5271
Trackpad
1K
5%
1/16W
MF-LF
2 402
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
PP3V3_S3
R52901
SMC
J5800
R5291
U4900
(MASTER)
SMBUS_SMC_A_S3_SCL
97 56 48 45
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_A_S3_SDA
97
6 33
45 48 54
97 56 48 45
SMBUS_SMC_MGMT_SDA
97
56 48
45
Sensor ADC A
4.7K
5%
1/16W
MF-LF
402 2
97
56 48
45
MAKE_BASE=TRUE
4.7K
97
6 33
45 48 54
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
6 45 48
64 65 97
The bus formerly known as "Battery B"
PP3V3_S3
1K
6 45 48
64 65 97
SMC "Management" SMBus Connections
SMC "A" SMBus Connections
R52701
6 45 48
64 65 97
J6955
(See Table)
Battery
NOTE: SMC RMT bus remains powered and may be active in S3 state
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
6 45 48
64 65 97
Battery
GT216: U8000
(Write: 0x9E Read: 0x9F)
SMC
48
26
32
94
48
26
32
94
CK505 (Clock)
42
17
28
63
42
17
28
63
4.7K
GPU Temp (Int)
U2901
47
25
30
88
47
25
30
88
R52501
SO-DIMM "B"
Margin Control
48
26
32
94
48
26
32
94
49 47 46 45 43 23 21 17 7 6
73 66 65 64 53
J3100
(Write: 0xA4 Read: 0xA5)
U2900
SMC "Battery A" SMBus Connections
PP3V3_S0
SMC
J2900
(Write: 0xA0 Read: 0xA1)
VRef DACs
SMC "0" SMBus Connections

99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
PP3V3_S0
Ibex Peak-M
5%
1/16W
MF-LF
2 402
U5930
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
45 48 56
97
45 48 56
97
ALS
J3401
XDP Connectors
Mikey
J2600 & J2650

(MASTER)
U6800
94 88 63 48
28 26 25 17
47 42 32 30
SMBUS_PCH_CLK
SMBUS_PCH_CLK
94 88 63 48
28 26 25 17
47 42 32 30
SMBUS_PCH_DATA
SMBUS_PCH_DATA
42
17
28
63
42
17
28
63
47
25
30
88
47
25
30
88
48
26
32
94
48
26
32
94
U4510
SMBUS_PCH_CLK
SMBUS_PCH_DATA
47
25
30
88
47
25
30
88
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
48
26
32
94
48
26
32
94
R52601
SMC
51 48 45
97
PCH "SMLink 0" Connections

99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
4.7K
5%
1/16W
MF-LF
402 2
R52101
8.2K
5%
1/16W
MF-LF
402 2
U1800
(MASTER)
SML_PCH_0_CLK
94 17
SML_PCH_0_DATA
97 51 48 45
SMBUS_SMC_B_S0_SCL
97
51 48
45
SMBUS_SMC_B_S0_SDA
97
51 48
45
R5261
CPU Temp
4.7K
5%
1/16W
MF-LF
2 402
EMC1414-A: U5570
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
45 48 51
97
45 48 51
97
PP3V3_S0
Ibex Peak-M
94 17
97
6 33
45 48 54
PP3V3_S0
U4900
(MASTER)
97
6 33
45 48 54
SMC "B" SMBus Connections
HDD Redriver Control A
42
17
28
63
42
17
28
63
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
R5211
8.2K
5%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCH "SMLink 1" Connections

99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
PP3V3_S0
NO STUFF
Ibex Peak-M
U1800
94 17
SML_PCH_1_CLK
94 17
SML_PCH_1_DATA
R52201
8.2K
5%
1/16W
MF-LF
402 2
NO STUFF
1
R5221
8.2K
5%
1/16W
MF-LF
2 402
R5223
0
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
K18 SMBus Connections
DRAWING NUMBER
R5222
Apple Inc.
0
5%

SIZE
<SCH_NUM> D
REVISION
1/16W
MF-LF
402
SMLink 1 is slave port to

access PCH & CPU via PECI.
PAGE TITLE
2
MAKE_BASE=TRUE
<E4LABEL>
BRANCH
<BRANCH>
PAGE
52 OF 132
SHEET
48 OF 101
CPU Voltage Sense / Filter

68 15 12 7 6
XW5309
PPVCORE_S0_CPU
PBUS Voltage Sense & Filter
R5309
SM
CPUVSENSE_IN
4.53K
SMC_CPU_VSENSE
1%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place near U1000
Q5315
45
OUT
FDG6332CG
1
SC70-6
C5309
0.22UF
82 70 69 67 66 65 49 40 7 6
89 86
20%
6.3V
X5R
402
P-CHN
PPBUS_G3H
R5315
45 46 49 50
GPU Voltage Sense / Filter

PLACE_NEAR=U4900.N11:5mm
82 75 7 6
XW5359
PPVCORE_GPU
4.53K
GPUVSENSE_IN
SMC_GPU_VSENSE
2
1%
1/16W
MF-LF
402
R5385 1
27.4K
1%
1/16W
MF-LF
402
D
Rthevenin = 4504 ohms
PBUSVSENS_EN_DIV
R5359
SM
1
PPBUS_G3H_VSENSE
VOLTAGE=6V
100K
5%
1/16W
MF-LF
402
GND_SMC_AVSS
SMC_PBUS_VSENSE
45
R5316
C5359
0.22UF
OUT
R5386
100K
5.49K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
20%
6.3V
X5R
402
45
C5385
0.22UF
2
2
PBUSVSENS_EN_L
GND_SMC_AVSS
OUT
20%
6.3V
X5R
402
GND_SMC_AVSS
45 46 49 50
45 46 49 50
69 24 13 7 6
PPVCORE_S0_GFX
PLACE_NEAR=U4900.K9:5mm
XW5399
SM
2
1%
1/16W
MF-LF
402
PM_SLP_S3_L_R
SMC_GFX_VSENSE
1
C5399
0.22UF
OUT
Q5315
FDG6332CG
SC70-6
Enables PBUS VSense divider when high.
4.53K2
1
GFXVSENSE_IN
1
73 72
R5399
N-CHN
GFX Voltage Sense / Filter
45 46
20%
6.3V
2 X5R
402
GND_SMC_AVSS
45 46 49 50
CPU VCore High Side Current Sensor
C
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
PP3V42_G3H
1
C5388
0.1UF
2
68 7
PPBUS_CPU_IMVP_ISNS
OUT
V+
PART#
QTY
DESCRIPTION
CRITICAL
R5388
BOM OPTION
102S0858
RES,0.010 OHM,1%,1/2W,1206
R5388
1 3
99
ISNS_CPU_N
0.001
1%
1W
MF
1206
TABLE_5_ITEM
CRITICAL
U5388
OMIT
TABLE_5_HEAD
20%
10V
CERM
402
99
ISNS_CPU_P
5 IN-
R5335
INA213
SC70
4 IN+
4.53K
2
OUT 6 CPUVCORE_HISIDE_IOUT 1
REF 1
2 4
SMC_CPU_HI_ISENSE OUT
1%
1/16W
MF-LF
402
GAIN: 500X
0.22UF
GND
IN
PPBUS_G3H
82 70 69 67 66 65 49 40 7 6
89 86
45 46
C5335
20%
6.3V
X5R
402
GND_SMC_AVSS
45 46 49 50
EDP for PPVIN_S5_CPU_IMVP_ISNS_R = 5.867 amps for K18.
BMON Current Sense - Entire circuit must be near SMC (U4900)
B
DCIN Current Sense Filter
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
PP3V42_G3H
BMON_ENG
BMON_ENG
U5313
BMON_ENG
1 C5318
REGULATOR SIDE:
0.1uF
20%
2 10V
CERM
402
BMON_INA_OUT
99 65
OUT
IN
CHGR_CSO_R_P
5 IN-
GND
VCC
OUT 6
65
IN
CHGR_BMON 3
4
B0
4 IN+
BMON_PROD
R5330
2
Monitors battery discharge

current from battery to PBUS
IN
45 46
R5391
45.3K2
1%
BMON_ENG 1/16W
R5371
REF 1
GND
LOAD SIDE:
BMON_AMUX_OUT
VER 1
CHGR_CSO_R_N
SMC_BMON_MUX_SEL
IN
CHGR_AMON
4.53K
1
SMC_DCIN_ISENSE
2
1%
1/16W
MF-LF
402
100K
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
402
MF-LF
402
OUT
1
20%
6.3V
X5R
402
45
GND_SMC_AVSS
45
OUT
C5380
0.22UF
SMC_BATT_ISENSE
45 46 49 50
C5390
0.022UF
10%
16V
2 CERM-X5R
402
GAIN: 50X
GND_SMC_AVSS
65
INA213
SC70
R5380
20%
2 10V
CERM
402
V+
U5323
99 65
0.1uF
NC7SB3157P6XG
SC70 SEL
B1
BMON_ENG
1 C5369
45 46 49 50
U5303 only senses current up to 6.6A
PAGE TITLE
Current & Voltage Sensing

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
53 OF 132
SHEET
49 OF 101
GPU VCore Current Sense
CPU VCore Load Side Current Sense / Filter
CRITICAL
U5410
R5409
82
CRITICAL
U5450
R5459
91 68 12
IN
CPUIMVP_IMON
2.87K
CPUISENS_P
V+
10K
CPUVCORE_IOUT
4.53K
99
GPUISENS_P
OUT
45
V+
1%
1/16W
MF-LF
402
R5452
20.0K
4.53K
GPUVCORE_IOUT
SMC_GPU_ISENSE
2
1%
1/16W
MF-LF
402
0.22UF
45
20%
6.3V
X5R
402
Gain: 1.4x
2
1%
1/16W
MF-LF
402
C5453
OUT
C5408
GPUISENS_N
GND_SMC_AVSS
45 46 49 50
R5412
0.22UF
VTHRM
99
R5411
DFN
10K
OPA2333
R5410
SMC_CPU_ISENSE
1%
1/16W
MF-LF
402
CPUISENS_N
2.87K
1%
1/16W
MF-LF
402
R5450
1
VTHRM
GFXIMVP6_IMON
R5453
DFN
1%
1/16W
MF-LF
402
IN
OPA2333
20%
6.3V
X5R
402
4.02K
1%
1/16W
MF-LF
402
C5407
Gain: 3X
470PF
1%
1/16W
MF-LF
402
10%
50V
CERM
402
C5457
NOSTUFF
470PF
1
10%
50V
CERM
402
1.8V FB Current Sense

NOSTUFF
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
1
C5410
0.1UF
20%
10V
CERM
402
86 7 6
IN
R5415
CRITICAL
R5413 1
GFX VCore Current Sense
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
1%
1W
MF-1
0612
PP3V3_S0
C5444
CRITICAL
U5430
R5484
7.15K2
GFXIMVP_CS_R_P
IN
GFX_ISNS_R_P
99 69
GFXIMVP_CS_R_N
IN
7.15K2
V+
R5481
78 77 76 75 56 8 7 6
OUT
SMC_GFX_ISENSE
1%
1/16W
MF-LF
402
GAIN: 140X
4.53K
2.32K
2.32K
ISNS_P1V8GPU_R_N
45 46
C5482
1M
R5482
470PF
1%
1/16W
MF-LF
402
1M
10%
50V
CERM 2
402
1%
1/16W
MF-LF
2 402
SMC_GPU_1V8_ISENSE
1
0.22UF
2
45 46
OUT
C5411
20%
6.3V
X5R
402
GND_SMC_AVSS
45 46 49 50
R5416
R5417
1M
1%
1/16W
MF-LF
2 402
10%
50V
CERM 2
402
1M
20%
6.3V
X5R
402
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
C5412
470PF
1
10%
50V
CERM
402
R5483
NOSTUFF
2
1%
1/16W
MF-LF
402
Gain: 431x
470PF
C5479
4.53K
1
0.22UF
R5418
P1V8_S0GPU_IOUT
1%
1/16W
MF-LF
402
NOSTUFF
C5409 1
OUT
VTHRM
99
DFN
V+
R5414
2 4
OPA2333
ISNS_P1V8GPU_R_P3
1%
1/16W
MF-LF
402
R5479
GFXIMVP_ISNS_IOUT
GFX_ISNS_R_N
1%
1/16W
MF-LF
402
VTHRM
99
20%
10V
CERM
402
DFN
1%
1/16W
MF-LF
402
OPA2333
8
99
ISNS_P1V8GPU_P
ISNS_P1V8GPU_N
99
0.1UF
99 69
0.001
CRITICAL
U5410
SIGNAL_MODEL=EMPTY
NOSTUFF
SIGNAL_MODEL=EMPTY
NOSTUFF
CPU & MEM 1.5V S3 (DDR) Current Sense
C5443
470PF
1
10%
50V
CERM
402
SIGNAL_MODEL=EMPTY
54 53 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55
PP3V3_S3
1
C5454
0.1UF
CRITICAL
U5450
R5444
99 67
4.12K2
ISNS_1V5_S3_P
IN
R5443
CPUVTT 1.05V Current Sense
99 67
ISNS_1V5_S3_N
IN
4.12K2
99
470PF
10%
50V
CERM 2
402
CRITICAL
U5430
99 70
IN
7.15K2
CPUVTTS0_CS_P
IN
CPUVTTS0_CS_N
V+
7.15K2
1%
1/16W
MF-LF
402
99
CPUVTT_IOUT
Gain: 140x
1%
1/16W
MF-LF
402
4.53K
1%
1/16W
MF-LF
402
C5472 1
470PF
10%
50V
CERM 2
402
R5472
1M
1%
1/16W
MF-LF
2 402
1M
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
2 402
Gain: 243x
R5441
1
1M
1%
1/16W
MF-LF
402
OUT
45 46
0.22UF
20%
6.3V
X5R
402
45 46 49 50
470PF
2
SIGNAL_MODEL=EMPTY
NOSTUFF
0.22UF
20%
6.3V
X5R
402
45 46 49 50
PAGE TITLE
Current Sensing
DRAWING NUMBER
Apple Inc.
SIZE
<SCH_NUM> D
REVISION
SIGNAL_MODEL=EMPTY
45 46
C5441
C5471
470PF
OUT
C5490
SIGNAL_MODEL=EMPTY
10%
50V
CERM
402
10%
50V
CERM
402
SMC_P1V5S3_ISENSE
2
1%
1/16W
MF-LF
402
NOSTUFF
THRM
R5471
1
4.53K
1
C5480
GND_SMC_AVSS
1
CPUDDR_IOUT
V-
SMC_CPUVTT_ISENSE
NOSTUFF
1M
R5487
CPUVTTISNS_R_N
R5442
VTHRM
GND_SMC_AVSS
1
OPA2333
DFN
R5473
99 70
CPUVTTISNS_R_P
V+
DDRISNS_R_N
R5440
DFN
C5442 1
99
DDRISNS_R_P
1%
1/16W
MF-LF
402
NOSTUFF
R5474
99
OPA2333
1%
1/16W
MF-LF
402
20%
10V
CERM
402
<E4LABEL>
BRANCH
<BRANCH>
PAGE
54 OF 132
SHEET
50 OF 101
GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack

R5550
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
PP3V3_S0_GPUTHMSNS_R
5%
1/16W
MF-LF
402
99 80 79
47
GPU_TDIODE_P
BI
Detect GPU Die Temperature
VOLTAGE=3.3V
20%
2 10V
CERM
402
99 80 79
Q5501
99
BC846BMXXH
Placement note:
GPUTHMSNS_D_P
SOT732-3
SIGNAL_MODEL=EMPTY
Q5503
C5552
THERM*/ADDR
GPUTHMSNS_THM_L
3 DN1
ALERT*
GPUTHMSNS_ALERT_L
CRITICAL
4 DP2/DN3
SMDATA
SMBUS_SMC_0_S0_SDA
BI
45 48 81 97
5 DN2/DP3
10
SMBUS_SMC_0_S0_SCL
BI
45 48 81 97
SMCLK
GND
6
10%
50V
CERM 2
402
SOT732-3
2
99
5%
1/16W
MF-LF
2 402
2 DP1
0.0022uF
BC846BMXXH
Place Q5501 on bottom side

close to the right fin stack
10K
MSOP
GPU_TDIODE_N
BI
R5552
EMC1414-A
10%
50V
CERM 2
402
Detect Right Fin Stack Temperature
5%
1/16W
MF-LF
402 2
U5550
0.0022uF
10K
1
VDD
SIGNAL_MODEL=EMPTY
C5551
C5550
0.1uF
R55511
Placement note:
GPUTHMSNS_D_N
Place U5550 on bottom side under GPU

Detect Left Heat Pipe Temperature
Placement note:
Write Address: 0x98
Read Address: 0x99
Place Q5503 on top side under left heat pipe near GPU
CPU Proximity/CPU Die/PCH Proximity/Battery Charger Proximity

R5570
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
47
5%
1/16W
MF-LF
402
PP3V3_S0_CPUTHMSNS_R
VOLTAGE=3.3V
1
1
VDD
U5570
99 9
BI
CPU_THERMD_P
SIGNAL_MODEL=EMPTY
C5571
Detect CPU Die Temperature
0.0022uF
10%
50V
CERM 2
402
99 9
BI
CPU_THERMD_N
C5570
0.1uF R55711
20%
2 10V
CERM
402
EMC1414-A
MSOP
10K
5%
1/16W
MF-LF
402 2
R5572
10K
5%
1/16W
MF-LF
2 402
2 DP1
THERM*/ADDR
CPUTHMSNS_THM_L
3 DN1
ALERT*
CPUTHMSNS_ALERT_L
CRITICAL
4 DP2/DN3
SMDATA
SMBUS_SMC_B_S0_SDA
BI
45 48 97
5 DN2/DP3
10
SMBUS_SMC_B_S0_SCL
BI
45 48 97
SMCLK
GND
6
Detect Battery Charger Proximity Temperature

99
Q5502
BC846BMXXH
CPUTHMSNS_D2_P
SIGNAL_MODEL=EMPTY
Place Q5502 on bottom side

close to battery charger circuit
Q5504
0.0022uF
10%
50V
CERM 2
402
BC846BMXXH
Placement note:
SOT732-3
Place U5570 under CPU
C5590 1
SOT732-3
1
Note: EMC1414 can perform Beta

Compensation for External Diode 1 only
Placement note:
99
Detect PCH Proximity Temperature
CPUTHMSNS_D2_N
Write Address: 0x98

Read Address: 0x99
Placement note:
Place Q5504 under PCH
PAGE TITLE
Thermal Sensors
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
55 OF 132
SHEET
51 OF 101
Left Fan
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
PP5V_S0
PP3V3_S0
CRITICAL
1
R5650
47K
5%
1/16W
MF-LF
402 2
R5655
45
OUT
SMC_FAN_0_TACH
47K
FAN_LT_TACH
5%
1/16W
MF-LF
402
R56511
5%
1/16W
MF-LF
402 2
45
IN
SMC_FAN_0_CTL
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
PP5V_S0
PP3V3_S0
R5660
78171-0004
M-RT-SM
5
47K
2N7002DW-X-G
D
SOT-363
3
6 FAN_LT_PWM
5%
1/16W
MF-LF
402 2
R5665
1
2
3
4
45
OUT
SMC_FAN_1_TACH
47K
FAN_RT_TACH
5%
1/16W
MF-LF
402
R56611
5%
1/16W
MF-LF
402 2
518S0369
45
IN
SMC_FAN_1_CTL
J5660
78171-0004
M-RT-SM
5
1
2
3
4
6
100K
Q5660
4 S
CRITICAL
J5650
100K
Right Fan
Q5660
2N7002DW-X-G
SOT-363
1 S
D 6
518S0369
FAN_RT_PWM
SYNC_MASTER=K19_MLB
PAGE TITLE
Fan Connectors
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
56 OF 132
SHEET
52 OF 101
KEYBOARD CONNECTOR
PSOC USB CONTROLLER
IC
PIN NAME
TMP102
V+
CURRENT
R_SNS
V_SNS
POWER
10UA
2.55 KOHM
0.0255 V
0.255E-6 W
0.204 V
16.32E-6 W
80UA
3V3 LDO
USB INTERFACES TO MLB

SPI HOST TO Z2
TRACKPAD PICK BUTTONS

KEYBOARD SCANNER
VDD
60MA MAX
10 OHM
VOUT
60MA MAX
0.2 OHM
0.012 V
1.5 OHM
0.012 V
96E-6 W
0.021 V
294E-6 W
PSOC
VDD
18V BOOSTER
VIN
8MA (TYP)
0.6 V
14MA (MAX)
54 6
53
54
53
NC
IN
4.7 OHM
4MA (MAX)
0.0188 V
75.2E-6 W
54 6
54 6
54 6
54 6
54 6
54 6
54 6
54 6
54 6
54
54 6
WS_CONTROL_KEY
Z2_KEY_ACT_L
TP_BOOT_CFG1
TP_P4_5
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1
CRITICAL
U5701
CY8C24794
MLF
(SYM-VER2)
APN 337S2983
OMIT
15 P1_7
16 P1_5
17 P1_3
18 P1_1
19 VSS
20 D+
21 D22 VDD
23 P7_7
24 P7_0
25 P1_0
26 P1_2
27 P1_4
28 P1_6
53
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
53
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
36E-3 W
R5714
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WS_KBD17 6 53
WS_KBD16N 53
WS_KBD15_C 53
WS_KBD14 6 53
WS_KBD13 6 53
WS_KBD12 6 53
WS_KBD11 6 53
WS_KBD10 6 53
WS_KBD9 6 53
WS_KBD8 6 53
WS_KBD7 6 53
WS_KBD1 6 53
WS_KBD2 6 53
WS_KBD3 6 53
53
470
1%
1/16W
MF-LF
402
R5715
53
WS_KBD16N
10K
1%
1/16W
MF-LF
402
46 45 6
OUT
SMC_ONOFF_L
C5710
0.1UF
20%
2 10V
CERM
402
WS_KBD4 6
WS_KBD5 6
WS_KBD6 6
WS_KBD1
53 6 WS_KBD2
53 6 WS_KBD3
53 6 WS_KBD4
53 6 WS_KBD5
53 6 WS_KBD6
53 6 WS_KBD7
53 6 WS_KBD8
53 6 WS_KBD9
53 6 WS_KBD10
53 6 WS_KBD11
53 6 WS_KBD12
53 6 WS_KBD13
53 6 WS_KBD14
6 WS_KBD15_CAP
6 WS_KBD16_NUM
53 6 WS_KBD17
53 6 WS_KBD18
53 6 WS_KBD19
53 6 WS_KBD20
53 6 WS_KBD21
53 6 WS_KBD22
R5710
53 6 WS_KBD23
1K
1
2
6 WS_KBD_ONOFF_L
5%
6 PP3V42_G3H
1/16W47 4673456643652364215317497 48
MF-LF
53 6 WS_LEFT_SHIFT_KBD
402
53 6 WS_LEFT_OPTION_KBD
53 6 WS_CONTROL_KBD
53
49 48 47 46 45 43 23 21 17 7 6
73 66 65 64 53
PP3V3_S3
6 54
53 6
WS_LEFT_SHIFT_KBD
20%
CRITICAL
10V
5 TC7SZ08AFEAPE
CERM
SOT665
402
4
31
F-RT-SM
U5725Y
SMC_MANUAL_RESET LOGIC
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
WS_LEFT_SHIFT_KEY 53
PP3V42_G3H
1
C5758
0.1UF
10%
16V
2 X7R-CERM
402
TP_P7_7
TP_ISSP_SCLK_P1_1
8 6
0.1UF
101 87 73
34 33 32 31 20 17 8 7 6
72 55 54 53 50 48 36 35
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FF14-30A-R11B-B-3H
C5725
PP3V42_G3H
53
TP_ISSP_SDATA_P1_0
Z2_CLKIN
NC
PLACEMENT_NOTE=NEAR J5713
ISOLATION CIRCUIT
ISSP SDATA/I2C SDA
NC_PSOC_P1_3
PP3V3_S3
53
WS_KBD15_C
57
TP_PSOC_SCL
TP_PSOC_SDA
32
0.72E-3 W
53 6
53
WS_KBD23 6 53
WS_KBD22 6 53
WS_KBD21 6 53
WS_KBD20 6 53
WS_KBD19 6 53
WS_KBD18 6 53
PP3V3_S3_PSOC
J5713
APN 518S0637
ISSP SCLK/I2C SCL

48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
PP3V42_G3H
APN 311S0406
CRITICAL
DIFFERENTIAL_PAIR=USB2_TPAD
USB_TPAD_P
93 36
R5701
24
PP3V3_S3_PSOC
5%
1/16W
MF-LF
402
TO MLB CONNECTOR
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_85D
53
53 6
PP3V3_S3
WS_LEFT_OPTION_KBD
U5726Y
WS_LEFT_OPTION_KEY 53
53 6
53 6
53 6
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
1
3
6
CRITICAL
SN74LVC1G10
SC70
4
B
Y
U5703
46
SMC_TPAD_RST_L
R5702
USB_TPAD_N
93 36
36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54 53 50 48
USB_TPAD_R_P
5 TC7SZ08AFEAPE
SOT665
4
24
USB_TPAD_R_N
5%
1/16W
MF-LF
402
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_85D
R5769
PP3V42_G3H
33K
5%
1/16W
MF-LF
2 402
49 48 47 46 45 43 23 21 17 7 6
73 66 65 64 53
CRITICAL
48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54 53 50
53 6
PP3V3_S3
WS_CONTROL_KBD
5 TC7SZ08AFEAPE
SOT665
4
U5727Y
R5770
33K
5%
1/16W
MF-LF
2 402
R5771
33K
5%
1/16W
MF-LF
2 402
WS_CONTROL_KEY 53
3
U5701 CHIP DECOUPLING
PLACE C5701, C5702 & C5703
PLACE C5704, C5705 & C5706
CLOSE TO U5701
CLOSE TO U5701
VDD PIN 22
VDD PIN 49
TPAD BUTTONS DISABLE

R5704
53
PP3V3_S3_PSOC
1
C5701
4.7UF
20%
2 6.3V
X5R
603
1.5
1
1
VOLTAGE=3.3V
1
C5702
100PF
5%
2 50V
CERM
402
C5703
0.1UF
10%
2 16V
X7R-CERM
402
C5704
100PF
5%
2 50V
CERM
402
C5705
0.1UF
10%
2 16V
X7R-CERM
402
PP3V3_S3
53
BUTTON_DISABLE
6 7 8 17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87 101
5%
1/16W
MF-LF
402
PLACE THESE COMPONENTS CLOSE TO J5800

THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB
C5706
4.7UF
Q5701
20%
2 6.3V
X5R
603
SSM3K15FV
D 3
SOD-VESM-HF
SYNC_MASTER=K19_MLB
1 G
SMC_LID
64 46 45
IN
S 2
PAGE TITLE
THE TPAD BUTTONS WILL BE DISABLE

WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
WELLSPRING 1
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
57 OF 132
SHEET
53 OF 101
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
D
APN 152S0504
PP5V_S3
D
IPD FLEX CONNECTOR
CRITICAL
72 67 66 61 58 56 46 44 43 42 33 31 7 6
101 82
INPUT_SW
D5802
SOD-323
BOOST_SW
R5806
PP18V5_S3_SW
MIN_NECK_WIDTH=0.20MMB0520WSXG
VLF3010AT-SM-HF
0.50MM
0.20MM
SWITCH_NODE=TRUE
VOLTAGE=18.5V
1
PP5V_S3_BOOSTER
39PF
5%
2 50V
CERM
402
APN 353S1401
2
VOLTAGE=5V
C5818
5%
1/16W
MF-LF
402
APN 371S0313
5%
1/16W
MF-LF
402
R5805
L5801
3.3UH-870MA
PP18V5_S3
APN 516S0689
VOLTAGE=18.5V
CRITICAL
R5812
J5800
1M
55560-0228
1%
1/16W
MF-LF
2 402
M-ST-SM
2
4
6
8
10
12
14
16
18
20
22
Z2_CS_L
53 6 Z2_DEBUG3
53 Z2_MOSI
53 6 Z2_MISO
53 6 Z2_SCLK
54 6 Z2_BOOST_EN
53 Z2_HOST_INTN
53 6
VIN
U5805
1 L
1
FB
BOOST_FB
Z2_BOOST_EN
1UF
10%
2 25V
X5R
603-1
TPS61045
3
QFN
DO
CTRL
6 54
0.1UF
10%
2 16V
X7R-CERM
402
C5817
PAD
2.2UF
R5813
SW
71.5K
6 GND
C5816
7 PGND
CRITICAL
THRML
C5819
1%
1/16W
MF-LF
2 402
R5811
100K
53 6
Z2_CLKIN
PP3V3_S3
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55
1%
1/16W
MF-LF
2 402
10%
2 16V
X5R
603
1
3
5
7
9
11
13
15
17
19
21
Z2_KEY_ACT_L 6 53
Z2_RESET 6 53
PSOC_F_CS_L 6 53
PICKB_L 6 53
PSOC_MISO 6 53
PSOC_MOSI 6 53
PSOC_SCLK 6 53
SMBUS_SMC_A_S3_SDA 6 33 45 48
SMBUS_SMC_A_S3_SCL 69733 45 48
97
PP18V5_S3 6 54
Keyboard LED Driver

69 68 63 62 58 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
72 70 69 68 52 47 42 23 7 6
88 86
PP5V_S0
CRITICAL
L5850
10UH-0.58A-0.35OHM
1
2
KBDLED_SW
R5853
To detect Keyboard backlight, SMC will
470K
LOW = keyboard backlight present

HIGH= keyboard backlight not present
45
1098AS-SM
1UF
VIN
10%
10V 2
X5R
402-1
54 6
LED 5
KBDLED_ANODE
CRITICAL
R58541
R5853 ALWAYS PRESENT
4.7K
5%
1/16W
MF-LF
402 2
NO STUFF
U5850
R58521
LT3491
10K
5%
1/16W
MF-LF
402 2
R5855
APN 518S0612
10
SYNC_MASTER=K19_MLB
1%
1/16W
MF-LF
2 402
DFN
CAP 4
PAD
THRML
GND
DRAWING NUMBER
1
Apple Inc.
C5855
1UF

SIZE
<SCH_NUM> D
REVISION
SMC_KDBLED_PRESENT_L
WELLSPRING 2
KBDLED_CAP
54 6
PAGE TITLE
KBD BACKLIGHT CONNECTOR
10%
2 35V
X5R
603
F-RT-SM
1
2
3
4
BOM OPTION: KBDLED_YES
SMC_KDBLED_PRESENT_L
SW 3
6 CTRL
J5815 pin 1 is grounded

on keyboard backlight flex
FF18-4A-R11AD-B-3H
SWITCH_NODE=TRUE
C5850 1
SMC_SYS_KBDLED
J5815
5%
1/16W
MF-LF
402 2
tristate SMC_SYS_KBDLED:
CRITICAL
<E4LABEL>
BRANCH
<BRANCH>
PAGE
58 OF 132
SHEET
54 OF 101
Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
Desired orientation when
PP3V3_S3
placed on board top-side:

14
R59211
IN
SMS_PWRDN
MAKE_BASE=TRUE
C5926
10UF
20%
2 4V
X5R
603
+Y
AP344ALH
SMS_SELFTEST
NO STUFF
1 FS
5 PD
2 ST
SMS_X_AXIS
OUT
45
VOUTY 10
SMS_Y_AXIS
OUT
45
VOUTZ 8
SMS_Z_AXIS
OUT
45
VOUTX 12
CRITICAL
15 RES
4 RES
NC
10K
3 NC
6 NC
9 NC
NC 11 NC
NC 13 NC
1
NC 16 NC
C5923
0.1UF
GND
10%
16V
2 X5R
402
5%
1/16W
MF-LF
2 402
NC
NC
NC
+Z (up)
Circle indicates pin 1 location when placed

in correct orientation
R5922
Front of system
+X
LGA
SMS_PWRDN
55 45
10%
2 16V
X5R
402
U5920
5%
1/16W
MF-LF
402 2
55 45
0.1UF
NO STUFF
VDD
10K
C5922
C5924
0.1UF
10%
16V
2 X5R
402
C5925
0.1UF
10%
16V
402
2 X5R
PLACE CAPS ON SMS OUTPUT SIGNALS CLOSE TO SMC
R5940
0
5%
1/16W
MF-LF
2 402
Alternate location Analog SMS

55 54
35 34
17 8 7
32 31
50 48
87 73
101
53
33
6
20
36
72
R5941
0
5%
1/16W
MF-LF
2 402
R5942
0
5%
1/16W
MF-LF
2 402
Desired orientation when
PP3V3_S3
NO STUFF
14
C5932
0.1UF
10%
2 16V
X5R
402
VDD
U5930
placed on board top-side:
NO STUFF
1
C5936
10UF
20%
2 4V
X5R
603
+Y
AP344ALH
+X
LGA
SMS_ALT_SELFTEST
1 FS
5 PD
2 ST
VOUTX 12
CRITICAL
SMS_ALT_X_AXIS
VOUTY 10
SMS_ALT_Y_AXIS
VOUTZ 8
SMS_ALT_Z_AXIS
15 RES
4 RES
NC
Circle indicates pin 1 location when placed

in correct orientation
R5932
NC
NC
NC
10K
5%
1/16W
MF-LF
2 402
3 NC
6 NC
9 NC
Front of system
+Z (up)
NC 11 NC
NC 13 NC
NC 16 NC
GND
SYNC_MASTER=K19_MLB
PAGE TITLE
Sudden Motion Sensor (SMS)

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
59 OF 132
SHEET
55 OF 101
3
R6003
PP5V_S3
XW6010
SM
1
PP3V3_WLAN_F
XW6020
SM
P3V3_WLAN_F_XW
42 6
PP5V_SW_ODD
DEBUG_ADC
DEBUG_ADC
5%
1/16W
MF-LF
402
R6010
1%
1/16W
MF-LF
2 402
P3V3_WLAN_F_DIV
DEBUG_ADC
1
R6011
1M
ADC_CH0
1%
1/16W
MF-LF
402
20%
2 10V
X5R
603
10UF
2 10V
CERM
402
R6021
681K
2.2UF
ADC_CH1
1%
1/16W
MF-LF
402
20%
10V
CERM 2
402
20%
10V 2
X5R
603
56
C6022
56
2.2UF
56
10%
2 6.3V
X5R
402
56
56
56
56
22
23
24
1
2
3
4
5
ADC_CH0
ADC_CH1
ADC_CH2
ADC_CH3
ADC_CH4
ADC_CH5
ADC_CH6
ADC_CH7
DVDD
I2C ADDRESS: 0X10 / 0X11

ADC RANGE: 0V TO 4.096V
LSB: 0.001V
R6001
AD0 14
AD1 15
QFN
DEBUG_ADC
SDA 17
SCL 16
THRM
PAD
R6002
SMBUS_SMC_MGMT_SCL
R6030
TP_ISNS_AIRPORT_P
243
99
DEBUG_ADC
ISNS_AIRPORT_R_P
C6004
C6005
10UF
20%
2 10V
CERM
402
45 48 97
20%
2 6.3V
X5R
603
DEBUG_ADC
1
C6006
2.2UF
20%
2 6.3V
CERM
402-LF
DEBUG_ADC
1
DEBUG_ADC
243
V+
VTHRM
99
ISNS_AIRPORT_R_N
TP_ISNS_ODD_P
GAIN: 1239X
ADC_CH2
1%
1/16W
MF-LF
402
56
C6032 1
470PF
NOSTUFF 10%
50V
DEBUG_ADC
1
CERM 2
402
R6032
IN
TP_ISNS_ODD_N
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
V+
THRM
DEBUG_ADC
1
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
470PF
2
10%
50V
CERM
402
IN
TP_ISNS_HDD_P
DEBUG_ADC
412
99
ISNS_HDD_R_P
U6040
1%
1/16W
MF-LF
402
R6044
ADC_CH3
56
DEBUG_ADC
C6044
IN
TP_ISNS_HDD_N
10%
2 6.3V
X5R
402
412
V+
ISNS_HDD_R_N
470PF
10%
50V
NOSTUFF CERM
DEBUG_ADC
1
PPVOUT_S0_LCDBKLT
88 83 6
5 IN-
TP_ISNS_LCDBKLT_P
4 IN+
C6064
1%
1/16W
MF-LF
2 402
348K 2
1
1%
1/16W
MF-LF
402
C6063
470PF
2
10% NOSTUFF
50V
CERM
402
PVOUT_S0_LCDBKLT_XW
1
R6080
1M
DEBUG_ADC
U6050
R6074
INA210
ISNS_LCDBKLT_IOUT 1 226K 2
OUT 6
DEBUG_ADC
REF 1
1%
1/16W
MF-LF
2 402
GAIN: 200X
ADC_CH6
1%
1/16W
MF-LF
402
PVOUT_S0_LCDBKLT_DIV
DEBUG_ADC
56
DEBUG_ADC
1
R6081
C6074
52.3K
2.2UF
DEBUG_ADC
R6082
1
226K 2
1%
1/16W
MF-LF
402
ADC_CH7
56
DEBUG_ADC
1
C6082
2.2UF
1%
1/16W
MF-LF
2 402
10%
2 6.3V
X5R
402
GND
10%
2 6.3V
X5R
402
PAGE TITLE
DEBUG SENSORS AND ADC
DRAWING NUMBER
Apple Inc.
DIVIDER: ~ 1/20

SIZE
<SCH_NUM> D
REVISION
DEBUG_ADC
V+
SC70
56
DEBUG_ADC
XW6080
SM
TP_ISNS_LCDBKLT_N
GAIN: 845X
ADC_CH5
R6063
348K
PLACE_NEAR=D9701.2:3mm
20%
2 10V
CERM
402
1%
1/16W
MF-LF
402
2.2UF
0.1UF
226K 2
DEBUG_ADC
R6062
402
C6050
10%
2 6.3V
X5R
402
C6062 1
DEBUG_ADC
ISNS_HDD_IOUT
1%
1/16W
MF-LF
402
VTHRM
99
R6064
DFN
R6061
DEBUG_ADC
OPA2333
DEBUG_ADC
2.2UF
NOSTUFF
R6060
FB Voltage Sense / Filter
PP5V_S3
C6054
10%
2 6.3V
X5R
402
C6053
DEBUG_ADC
DEBUG_ADC
1
280K 2
56
2.2UF
NOSTUFF
1%
1/16W
MF-LF
402
ADC_CH4
R6053
280K
FBVSENSE_IN
PLACEMENT_NOTE=Place near R5413
1%
1/16W
MF-LF
402
DEBUG_ADC
R6052
470PF
226K 2
402
226K 2
1
GAIN: 561X
1%
1/16W
MF-LF
402
470PF
10%
50V
NOSTUFF CERM
XW6040
SM
ISNS_ODD_IOUT
V-
ISNS_ODD_R_N
C6052 1
10%
50V
CERM
402
R6054
DFN
99
DEBUG_ADC
OPA2333
C6033
U6040
3
301K 2
1
78 77 76 75 50 8 7 6
499
DEBUG_ADC
ISNS_ODD_R_P
R6033
301K
99
R6051
C6034
2.2UF
DEBUG_ADC
DEBUG_ADC
1
DEBUG_ADC
10%
2 6.3V
X5R
402
1%
1/16W
MF-LF
402
499
1%
1/16W
MF-LF
402
ISNS_AIRPORT_IOUT 1 226K 2
IN
R6034
DFN
R6031
TP_ISNS_AIRPORT_N
0.1UF
R6050
DEBUG_ADC
OPA2333
8
3
C6040
20%
2 10V
CERM
402
DEBUG_ADC
U6030
1%
1/16W
MF-LF
402
IN
5%
1/16W
MF-LF
402
0.1UF
C6030
20%
2 10V
CERM
402
DEBUG_ADC
IN
45 48 97
BI
DEBUG_ADC
ADC_REFCOMP
DEBUG_ADC
DEBUG_ADC
0.1UF
IN
SMBUS_SMC_MGMT_SDA
ADC_VREF
REFCOMP 8
PLACE_NEAR=U4900.F1:3mm
5%
1/16W
MF-LF
402
ADC_SDA
ADC_SCL
VREF 7
GND
DEBUG_ADC
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
DEBUG_ADC
PP5V_S3
1
IN
82 101
61 66
46 54
6 7 31 33 42
43 44
56 58
67 72
PP5V_S3
DEBUG_ADC
LTC2309
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
6 COM
DIVIDER: ~ 2/5
DIVIDER: ~ 2/3
IN
10UF
U6000
56
DEBUG_ADC
1%
1/16W
MF-LF
2 402
10%
2 6.3V
X5R
402
C6003 1
10
5%
1/16W
MF-LF
402
DEBUG_ADC
C6002 1
0.1UF
AVDD
226K 2
56
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
20%
DEBUG_ADC
C6001
R6022
C6012
DEBUG_ADC
P5V_SW_ODD_DIV
DEBUG_ADC
56
DEBUG_ADC
1%
1/16W
MF-LF
2 402
0.1UF
1%
1/16W
MF-LF
2 402
R6012
226K 2
1
DEBUG_ADC
C6000
1M
DEBUG_ADC
R6004
VOLTAGE=5V
DEBUG_ADC
R6020
649K
PP5V_S3_DEBUG_ADC_DVDD_R
DEBUG_ADC
1
PP5V_S3_DEBUG_ADC_AVDD_R
VOLTAGE=5V
P5V_SW_ODD_XW
10
12
13
33
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
21
25
9
10
11
18
19
20
<E4LABEL>
BRANCH
<BRANCH>
PAGE
60 OF 132
SHEET
56 OF 101
C
PP3V3_S5
R6101
3.3K
5%
1/16W
MF-LF
2 402
47
IN
47
IN
47 20 6
IN
C6100 1
20%
10V
CERM 2
402
SPI_MLB_CLK
SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB
NOTE: If HOLD* is asserted

ROM will ignore SPI cycles.
CRITICAL
VCC
0.1UF
U6100
32MBIT
SOP
SI/SIO0 5
MX25L3205DM2I-12G
6 SCLK
1 CE*
SPI_MLB_MOSI
IN
47
SPI_MLB_MISO
OUT
47
OMIT
SO/SIO1 2
3 WP*/ACC
7 HOLD*
GND
4
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 35
SYNC_MASTER=K17_REF
PAGE TITLE
SPI ROM
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
61 OF 132
SHEET
57 OF 101
AUDIO CODEC
APPLE P/N 353S2592
CRITICAL
L6201
FERR-220-OHM
87 72 71 24 23 21 16 12 7 6
PP1V8_S0
IN
PP5V_S3
2
0402
PP1V8_S0_AUDIO_DIG
VOLTAGE=1.8V
CRITICAL
C6210
4.7UF
20%
4V
X5R
402
C6211
10%
2 16V
X5R
402
C6216
10UF
R6210
10UF
20%
6.3V
X5R
603
2.67K
1%
1/16W
MF-LF
2 402
C6220
20%
6.3V
X5R
603
VBIAS_DAC
CS4206_FP
CS4206_FN
29
44
41
NC TP_AUD_GPIO_0
NC TP_AUD_GPIO_1
NC TP_AUD_GPIO_2
61
OUT
AUD_GPIO_3
2
12
14
15
63
IN
AUD_SENSE_A
13
CS4206_FLYP
CS4206_FLYC
CRITICAL
CRITICAL
C6222
C6223
2.2UF
20%
6.3V
CERM
402-LF
45
43
42
2.2UF
2
20%
6.3V
CERM
402-LF
HDA_BIT_CLK
IN
HDA_SYNC
94 17
OUT
HDA_SDIN0
R6211
94 17
IN
94 17
IN
62
IN
HDA_SDOUT
HDA_RST_L
AUD_SPDIF_IN
39
GPIO0/DMIC_SDA1
GPIO1/DMIC_SDA2
/SPDIF_OUT2
GPIO2
GPIO3
LINEOUT_L1+
LINEOUT_L1LINEOUT_R1+
LINEOUT_R1-
35
34
36
37
SENSE_A
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
31
30
32
33
MICBIAS
16
VL_IF
BITCLK
AUD_SDI_R
62
AUD_SPDIF_OUT
OUT
39
QFN
VCOM
28
LINEIN_L+
LINEIN_CLINEIN_R+
21
22
23
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
17
19
20
VREF+_ADC
27
RESET*
47
48
AUD_SPDIF_OUT_CHIP
SPDIF_IN
SPDIF_OUT
DMIC_SCL
5%
1/16W
MF-LF
402
AUD_HP_PORT_L
AUD_HP_PORT_R
AUD_HP_PORT_REF
58 60 62
58 59 63
OUT
AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R
AUD_CODEC_MICBIAS
60
OUT
60
IN
62
TP_AUD_LO1_P_L NC
TP_AUD_LO1_N_L NC
AUD_LO1_P_R OUT
AUD_LO1_N_R OUT
OUT
61
61
61
OUT
61
OUT
61
OUT
61
OUT
63
IN
59
CS4206_VCOM
AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
CS4206_VREF_ADC
IN
59
IN
59
IN
63
IN
63
IN
63
IN
63
NC
TP_AUD_DMIC_CLK
NC
DGND THRM_PAD AGND
CRITICAL
CRITICAL
C6224 1
1UF
C6225
10UF
10%
20V
TANT 2
CASE-P3-HF
63 59 58
20%
2 6.3V
X5R
603
CS4206ACNZC
SDI
SDO
11
R6212
58
SYNC
8
5
5%
1/16W
MF-LF
402
VOLTAGE=4.5V
GND_AUDIO_HP_AMP
GND_AUDIO_CODEC
VL_HD
C6213
10UF
10%
16V 2
X5R
402
0.1UF
39
FLYP
FLYC
FLYN
10
94
10%
16V 2
X5R
402
26
IN
94 17
49
94 17
C6217
38
40
CRITICAL
10%
1CRITICAL10V
X5R
402-1
10UF
20%
2 16V
TANT-POLY
2012-LLP
CRITICAL
C6215 1 C6214 1
0.1UF
VD VA_REF VA_HP VA
VBIAS_DAC
HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTHPREF
U6201
CS4206_FLYN
10%
16V 2
X5R
402
25
CRITICAL
C6221
46
CRITICAL
1
0.1UF
24
IN
C6218 1
20%
16V
TANT-POLY 2
2012-LLP
9
58
GND_AUDIO_HP_AMP
PP4V5_AUDIO_ANALOG
1UF
10UF
62 60 58
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
PP4V5_AUDIO_ANALOG IN
CRITICAL
CRITICAL
C6219
PP3V3_S0
0.1UF
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
20%
2 16V
POLY-TANT
CASE-B2-SM
R6213
100K
5%
1/16W
MF-LF
2 402
VOLTAGE=0V
GND_AUDIO_CODEC
B
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2234
CRITICAL
L6200
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
IN
99 88
63 62 58 54 52 51 50 48 47
25 24 23 21 20 19 18 17 7 6
46 42 40 37 34 30 28 27 26
87 85 84 83 80 73 72 69 68
IN
PP5V_S3
CRITICAL
U6200
FERR-220-OHM MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V
1
2
4V5_REG_IN
VOLTAGE=4.5V
NOTES ON CODEC I/O
MAX8840-4.5V
1 IN
UDFN
PP4V5_AUDIO_ANALOG
OUT 6
OUT
DIFF FSINPUT= 2.45VRMS

SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
58
0402
R6200
4V5_REG_EN
2.21K2
1%
1/16W
MF-LF
402
BP 4 4V5_NR
3 SHDN*
GND
C6200
CRITICAL
1UF
10%
10V
2 X5R
402-1
NC 5
PP3V3_S0
10%
2 10V
X5R
402-1
C6203
1UF
10%
2 10V
X5R
402-1
10%
16V
X7R-CERM
402
1UF
XW6200
SM
0.1UF
1
C6201
CRITICAL
C6202
GND_AUDIO_CODEC
58 59 63
VOLTAGE=0V
NOSTUFF
R6201
SYNC_MASTER=K18_AUDIO
5%
1/16W
MF-LF
402
AUDIO: CODEC/REGULATOR
XW6201
SM
1
PAGE TITLE
DRAWING NUMBER
VOLTAGE=0V
GND_AUDIO_HP_AMP 58
Apple Inc.
60 62
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
62 OF 132
SHEET
58 OF 101
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS
NET RIN = 18K OHMS
FC = 8 HZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6301
R6301
62
AUD_LI_L
IN
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
7.87K2
1%
1/16W
MF-LF
402
3.3UF
1
AUD_LI_L_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
10%
10V
CERM-X5R
805-1
AUD_LI_P_L
58
OUT
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
R6302
21.5K
1%
1/16W
MF-LF
2 402
CRITICAL
C6302
3.3UF
1
10%
10V
CERM-X5R
805-1
62
IN
AUD_LI_REF
AUD_LI_GND
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
58
R6300
10
CRITICAL
1%
1/16W
MF-LF
2 402
C6312
3.3UF
1
63 58
IN
10%
10V
CERM-X5R
805-1
GND_AUDIO_CODEC
R6312
21.5K
1%
1/16W
MF-LF
2 402
CRITICAL
C6311
R6311
62
IN
AUD_LI_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
3.3UF
7.87K2
AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1%
1/16W
MF-LF
402
10%
10V
CERM-X5R
805-1
AUD_LI_P_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
58
PAGE TITLE
AUDIO: LINE INPUT FILTER

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
63 OF 132
SHEET
59 OF 101
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

R6501
58
IN
AUD_HP_PORT_L
C6500 1
0.1UF
NC
AUD_HP_L OUT
62
5%
1/10W
MF-LF
603
CRITICAL
10%
16V
X7R-CERM 2
402
R6502
3.32K
1%
1/16W
MF-LF
2 402
AUD_HP_ZOBEL_L
1
R6500
39
5%
1/16W
MF-LF
402 2
62 58
IN
GND_AUDIO_HP_AMP
R65101
39
5%
1/16W
MF-LF
402 2
NC
R6512
AUD_HP_ZOBEL_R
3.32K
1%
1/16W
MF-LF
2 402
CRITICAL
C6510
0.1UF
10%
16V
X7R-CERM 2
402
58
IN
AUD_HP_PORT_R
R6511
1
AUD_HP_R
OUT
62
5%
1/10W
MF-LF
603
PAGE TITLE
AUDIO: HEADPHONE FILTER

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
65 OF 132
SHEET
60 OF 101
3X MONO SPEAKER AMPLIFIERS (SSM2315)

APN: 353S2500
GAIN = 6DB
1ST ORDER FC (L&R) = 120 HZ +/- 30%
1ST ORDER FC (SUB) = 58HZ +/- 30%
PLACE C6610 CLOSE TO VDD PIN

67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
PP5V_S3
CRITICAL
CRITICAL
VDD
16V
X5R
402
CRITICAL
61
CRITICAL
SSM2315L_N
SSM2315L_P
IN
OUT
6 62 99
CRITICAL
C2 SD*
SPKRCONN_L_OUT_N
GND
A2
B3
5%
1/16W
MF-LF
402 2
FERR-1000-OHM
1
6 62 99
100K
L6601
AUD_GPIO_3
OUT
R66011
CRITICAL
58
WLCSP OUT+ C3
OUT_ A3
C1 INA1 IN+
16V
X5R
402
AUD_SPKRAMP_SHUTDOWN_L
SPKRCONN_L_OUT_P
U6610
C6610
FERR-1000-OHM
0.033UF
1
2 AUD_SPKRAMP_LIN_P
1
2
0402
NO_TEST=TRUE
10%
AUD_LO2_P_L
IN
PVDD
SSM2315
L6610
58
B2
AUD_LO2_N_L
IN
10%
2 16V
X5R
402
20%
6.3V
TANT-POLY 2
CASE-A4
C6611
FERR-1000-OHM
0.033UF
1
2 AUD_SPKRAMP_LIN_N
1
2
0402
NO_TEST=TRUE
10%
C6613
0.1UF
47UF
L6611
58
C6612 1
CRITICAL
B1
CRITICAL
2
0402
C
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
PP5V_S3
CRITICAL
C6622 1
AUD_LO2_N_R
IN
AUD_SPKRAMP_RIN_N
NO_TEST=TRUE
0402
CRITICAL
L6620
IN
AUD_LO2_P_R
2
0402
61
0.1UF
SPKRCONN_R_OUT_P
OUT
6 62 99
OUT
6 62 99
SSM2315
SSM2315R_N
SSM2315R_P
C1 INA1 IN+
WLCSP OUT+ C3
OUT_ A3
C2 SD* CRITICAL
C6620
1
C6623
10%
2 16V
X5R
402
U6620
10%
16V
X5R
402
0.033UF
AUD_SPKRAMP_RIN_P
NO_TEST=TRUE
PVDD
VDD
CRITICAL
FERR-1000-OHM
58
B2
0.033UF
SPKRCONN_R_OUT_N
GND
A2
B3
58
20%
6.3V
TANT-POLY 2
CASE-A4
C6621
FERR-1000-OHM
CRITICAL
47UF
CRITICAL
L6621
B1
CRITICAL
10%
16V
X5R
402

67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
PP5V_S3
CRITICAL
58
IN
FERR-1000-OHM
0.068UF
1
2 AUD_SPKRAMP_SUBIN_N
1
2
AUD_LO1_N_R
0402
NO_TEST=TRUE
10%
10V
CERM
402
58
IN
61
100UF
20%
6.3V 2
TANT
CASE-AL1
VDD
PVDD
C6633
0.1UF
10%
2 16V
X5R
402
SPKRCONN_S_OUT_P
U6630
OUT
6 62 99
OUT
6 62 99
SSM2315
CRITICAL
CRITICAL
L6630
C6630
FERR-1000-OHM
0.068UF
1
2 AUD_SPKRAMP_SUBIN_P
1
2
AUD_LO1_P_R
0402
NO_TEST=TRUE
10%
10V
CERM
402
CRITICAL
C6632 1
B2
C6631
B1
L6631
CRITICAL
SSM2315S_N
SSM2315S_P
C1 INA1 IN+
WLCSP OUT+ C3
OUT_ A3
CRITICAL
C2 SD*
SPKRCONN_S_OUT_N
GND
A2
B3
CRITICAL
PAGE TITLE
AUDIO: SPEAKER AMP

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
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<BRANCH>
PAGE
66 OF 132
SHEET
61 OF 101
AUDIO JACK 1 LO/HP JACK, SPDIF TX

AUD_SPDIF_OUT
MIC CONNECTOR
58
IN
L6703
FERR-1000-OHM CRITICAL
1
CRITICAL
HS_MIC_P
J6780
63
OUT
99 88 87
73 72 69 68
51 50 48 47
30 28 27 26
19 18 17 7 6
25 24 23 21 20
46 42 40 37 34
63 62 58 54 52
85 84 83 80
78171-0003
APN: 518S0520
0402
L6702
M-RT-SM
4
PP3V3_S0
HS_MIC_N
0402
APN: 514-0671
CRITICAL
FERR-220-OHM
1
J6700
AUD_HP_PORT_REF
63 6
OUT
63 6
OUT
63 6
OUT
BI_MIC_N
BI_MIC_SHIELD
BI_MIC_P
1
2
3
58
BI
0402
CRITICAL
SPDIF-TXRX-K24
L6701
F-RT-TH
FERR-220-OHM-2.5A
1
AUD_CONNJ1_SLEEVE2
AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING
AUD_CONNJ1_SLEEVE
6
5
MIC
DETECT
SWITCH
LEFT
RIGHT
GND
2
1
3
4
2
0603
GND_AUDIO_HP_AMP
OUT
AUD_HP_R
BI
58 60
CRITICAL
L6704
FERR-220-OHM
1
60
0402
CRITICAL
AUDIO
L6706
7
8
A - VIN
B - VCC
C - GND
FERR-220-OHM
1
AUD_HP_L
BI
60
0402
R6700
OPERATING VOLTAGE 3.3
63
OUT
L6707
POF
10K
1
10
11
12
SHELL
SHIELD
PINS
CRITICAL
1
13
C6700
0.1UF
10%
2 16V
X5R
402
C6701
CRITICAL
2.2UF
DZ6703
20%
2 6.3V
CERM
402-LF
DZ6704
CRITICAL
6.8V-100PF
402
402
2
DZ6706
OUT
63
C
SPEAKER CONNECTOR
CRITICAL
J6781
DZ6701
6.8V-100PF
6.8V-100PF
402
402
63
0402
CRITICAL
CRITICAL
1
2
AUD_J1_TIPDET_R
6.8V-100PF
402
OUT
L6705
DZ6700
6.8V-100PF
AUD_J1_SLEEVEDET_R
5%
1/16W
MF-LF
402
APN: 518S0519
C6705
100PF
5%
2 50V
CERM
402
78171-0002
VOLTAGE=0V
8 62
99 61 6
IN
99 61 6
IN
M-RT-SM
3
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
1
2
4
XW6701
SM
1
J6782
78171-0004
XW6702
SM
GND PATCH
73 72 69 68 63
46 42 40 37 34
20 19 18 17 7 6
30 28 27 26 25 24 23 21
62 58 54 52 51 50 48 47
99 88 87 85 84 83 80
CRITICAL
R6701
PP3V3_S0
62 8
AUD_J2_OPT_OUT
J6750
LEFT
RIGHT
GROUND
5
2
1
3
4
4.7
AUD_SPDIF_IN
OUT
99 61 6
IN
99 61 6
IN
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
1
2
3
4
C6781 1
AUD_LI_R
BI
59
AUD_LI_L
BI
59
NOSTUFF
CRITICAL
1
C6784
33PF
5%
2 50V
CERM
402
C6782
33PF
5%
50V
CERM 2
402
FERR-1000-OHM
1
33PF
L6754
AUD_CONNJ2_RING
33PF
5%
50V
NOSTUFF CERM
CRITICAL 402
NOSTUFF
CRITICAL
58
CRITICAL
AUD_CONNJ2_TIPDET
5%
50V
2 CERM
402
0402
CRITICAL
L6756
FERR-1000-OHM
6
7
8
AUD_CONNJ2_TIP
2
0402
CRITICAL
L6758
600-OHM-300MA
POF
SHIELD
PINS
IN
C6783
OPERATING VOLTAGE 3.3
SHELL
IN
99 61 6
R6749
AUDIO
A - VDD
B - GND
C - VOUT
99 61 6
NOSTUFF
CRITICAL
5%
1/16W
MF-LF
402
F-RT-TH5
SWITCH
5%
1/16W
MF-LF
402
AUDIO-RCVR-M97
DETECT FOR PLUG TYPE
APN: 514-0635
M-RT-SM
5
APN: 518S0521
9
10
11
12
AUD_CONNJ2_SLEEVE
AUD_LI_GND
59
0402
CRITICAL
1
C6750
CRITICAL
1UF
DZ6758
10%
2 10V
X5R
402-1
DZ6754
DZ6757
402
SOD882
L6752
FERR-1000-OHM
6.8V-100PF
ESDALC5-1BM2
CRITICAL
CRITICAL
2
2
1
AUD_J2_TIPDET_R
OUT
63
0402
CRITICAL
DZ6756
6.8V-100PF
402
ESDALC5-1BM2
SOD882
C6756
AUDIO: JACKS
5%
50V
2 CERM
402
PAGE TITLE
100PF
DRAWING NUMBER
Apple Inc.
8 62
R
AUDIO JACK 2 LINE IN JACK, SPDIF RX

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
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<BRANCH>
PAGE
67 OF 132
SHEET
62 OF 101
CODEC OUTPUT SIGNAL PATHS

CONVERTER
0X02 (2)
0X04 (4)
0X03 (03)
0X08 (8)
PIN COMPLEX
0X09 (9,A)
0X0B (11)
0X0A (10)
0X10 (16)
MUTE CONTROL
N/A
GPIO_3
GPIO_3
N/A
PORT B LEFT(HEADSET MIC)

CRITICAL HP=80HZ, LP=8.82KHZ
MIKEY
L6880
FERR-1000-OHMVOLTAGE=3.3V
1
2 PP3V3_S0_HS_RX
DRC MIKEY
0402
DET ASSIGNMENT
0X09 (A)
N/A
N/A
0X0C (B)
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
CODEC INPUT SIGNAL PATHS

FUNCTION
LINE IN
SPDIF IN
BUILT-IN MIC
HEADSET MIC
CONVERTER
0X05 (5)
0X07 (7)
0X06 (6)
0X06 (6)
PIN COMPLEX
0X0C (12,C)
0X0F (15)
0X0D (13,B,RIGHT)
0X0D (13,V22,B,LEFT)
VREF
N/A
N/A
MIC_BIAS (80%)
MIKEY
INT
6.3V 20% 2
603 X5R
AVDD
DRC
88 48 47 42 32 30 28 26 25 17
94
IN
SMBUS_PCH_CLK
88 48 47 42 32 30 28 26 25 17
94
BI
SMBUS_PCH_DATA
19
SCL
MICBIAS
HS_MIC_BIAS
SDA
DETECT
HS_SW_DET
OUT
AUD_I2C_INT_L
INT*
IN
AUD_IPHS_SWITCH_EN
ENABLE
GND
BYPASS
10
MIKEY
CRITICAL
1
HS_RX_BP
C6882
2.2UF
20%
2 6.3V
TANT
402
THM
4
9
25 20
MIKEY
U6880
CD3275
PULLUPS ON MCP PAGE
GPIO
SATA4GP/GPIO 16
GPIO 5
GPIO 3
PIRQ H
PIRQ F
C6880
10UF
SYSTEM INT AND GPIO LINES

FUNCTION
MIKEY ENABLE
MIKEY INTERRUPT
PERIPHERAL DETECT
APN:353S2256
CRITICAL
MIKEY 1
DET ASSIGNMENT
0X0C (12,C)
N/A
N/A
MIKEY
VOLUME
0X02 (2)
0X04 (4)
0X03 (3)
N/A
11
FUNCTION
HP/LINE OUT
SATELLITES
SUB
SPDIF OUT
MIKEY 1
GND_AUDIO_CODEC
C6881
0.01UF
16V
MIKEY
10%
402 CERM 2
63 59 58
MIKEY
C6883
63 58
OUT
63
MIKEY
CRITICAL
C6886
0.1UF
58
PP3V3_S0_AUDIO_F
R6801
220K
5%
1/16W
MF-LF
2 402
Q6801
SOT563
47K
63 59 58
D 3
SSM6N15FEAPE
Q6801
5 G
C6801
S 4
2 G
220K 2
1
PP3V3_S0_AUDIO_F
R6850
58
IN
AUD_CODEC_MICBIAS
220K
5%
1/16W
MF-LF
2 402
63 59 58
D 6
Q6800
63 62
GND_AUDIO_CODEC
AUD_J1_SLEEVEDET_R
C6802
2 G
OUT
AUD_MIC_INP_R
C6851
0.1UF
10%
2 16V
CERM
402
58
OUT
AUD_MIC_INN_R
GND_AUDIO_CODEC
2
10%
25V
X5R
402
25V
X5R
402
MF
402-1
2.2UF
L6850
FERR-1000-OHM
1
BI_MIC_HI_F
CRITICAL
BI_MIC_P
IN
6 62
R6852
100K
2.4K 2
5%
1/16W
MF-LF
2 402
C6853
0.001UF
50V
10%
402 CERM 2
BI_MIC_LO_F
IN
6 62
IN
6 62
CRITICAL
C6854
27PF
50V
2 5%
CERM 402
L6851
FERR-1000-OHM
1
BI_MIC_N
0402
1%
1/16W
MF
402-1
BI_MIC_SHIELD
HP=80HZ
FERR-1000-OHM
IN
PP3V3_S0
PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
0402
C6861
63
0.1UF
PORT C DETECT (LINE-IN)
10V 20% 2
402 CERM
63 59 58
R6865
GND_AUDIO_CODEC
100K 2
R6861
AUD_PERPH_DET_R
5%
1/16W
MF-LF
402
R6864
100
63 58
OUT
AUD_SENSE_A
OUT
19
5%
1/16W
MF-LF
402
220K 2 AUD_J1_TIPDET_INV
63
R68131
PP3V3_S0_AUDIO_F
10K
1%
1/16W
MF-LF
402 2
R6811
5%
1/16W
MF-LF
402
AUD_INJACK_INSERT_L
270K
Q6803
SSM6N15FEAPE
D 6
SOT563
Q6803
5%
1/16W
MF-LF
2 402
D 3
SSM6N15FEAPE
AUD_J1_TIPDET_R1
15K
SOT563
5%
1/16W
MF-LF
402
SSM3K15FV
2 G
S 1
5 G
S 4
62
IN
AUD_J2_TIPDET_R
47K
5%
1/16W
MF-LF
402
C6860
0.1UF
10V
2 20%
CERM 402
63 59 58
D 3
SOD-VESM-HF
R6812
TIPDET_FILT
1
NC
Q6802
R6860
63 62
C6852
R6853
1
XW6851
SM
1
0402
CRITICAL 10%
S 1
L6862
88
58
30
7 6
23
47
73
R6851
CRITICAL
99
62
34
17
24
48
80
HS_MIC_N
0.1UF
EXTRACTION NOTIFICATION
63
37
18
25
50
83
CRITICAL
CRITICAL
C6850
63 59 58
68
40
19
26
51
84
27PF
50V
2 5%
CERM 402
2 10%
X7R 402
CRITICAL
SOT563
69
42
20
27
52
85
62
C6885
0.0082UF
25V
20%
2 6.3V
TANT
402
SSM6N15FEAPE
0.01UF
72
46
21
28
54
87
IN
1 MIKEY
MIKEY
C6884
MIC_BIAS_FILT 1 2.4K 2
1%
CRITICAL
1/16W
AUD_J1_SLEEVEDET_INV
58
GND_AUDIO_CODEC
100
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R6804
63 59 58
XW6880
SM
62
PORT B RIGHT(BUILT-IN MIC)
S 1
0.1UF
10V
5%
1/16W
MF-LF
2 402
IN
SOT563
S 4
GND_AUDIO_CODEC
AUD_J1_SLEEVEDET_R
R6883
HS_MIC_P
5%
1/16W
MF-LF
402
MIKEY
1
2.2K 2
SSM6N15FEAPE
SOT563
5 G
IN
AUD_PORTB_DET_L NC
R6803
63 62
5%
1/16W
MF-LF
2 402
D 6
2 20%
CERM 402
63
10%
25V
X5R
402
2.2K
AUD_J1_DET_RC
5%
1/16W
MF-LF
402
63 59 58
HS_MIC_HI_RC
100K
GND_AUDIO_CODEC
R6882
D 3
SSM6N15FEAPE
R6802
AUD_J1_TIPDET_R
1%
1/16W
MF-LF
2 402
2
10%
25V
X5R
402
20.0K
1%
1/16W
MF-LF
2 402
AUD_PORTA_DET_L NC
Q6800
AUD_MIC_INN_L
R6805
39.2K
APN:376S0613
AUD_OUTJACK_INSERT_L
OUT
R6806
IN
OUT
AUD_SENSE_A
63 62
PORT B DETECT(SPDIF DELEGATE)
AUD_MIC_INP_L
1%
1/16W
MF-LF
402 2
R6884
0.1UF
PORT A DETECT (HEADPHONES)
R6881
1K
MIKEY
CRITICAL
58
GND_AUDIO_CODEC
58 59 63
MIKEY
APN:376S0612
AUD_J2_DET_RC
1
C6811
AUDIO: JACK TRANSLATORS
S 2
DRAWING NUMBER
0.1UF
10V
2 20%
CERM 402
GND_AUDIO_CODEC
63 59 58
PAGE TITLE
1 G
Apple Inc.
GND_AUDIO_CODEC

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
68 OF 132
SHEET
63 OF 101
MagSafe DC Power Jack

CRITICAL
CRITICAL
F6905
J6900
6
M-RT-SM
PWR
PWR
GND
GND
SIG
PPDCIN_G3H
6AMP-24V
78048-0573
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V
1
2
3
4
5
C6905
1206-2
PP3V42_G3H
0.01UF
20%
2 50V
CERM
603
C6908
0.1UF
R6929
2.0K
VCC
5%
1/16W
MF-LF
2 402
BI
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
SMC_BC_ACOK_VCC
1
46 45
6 7 65
U6900
SC70-5
4 INT
EXT 5
GND
NC
SMC_BC_ACOK
U6901
IN
45 46 65
CRITICAL
402
TC7SZ08AFEAPE
SOT665
A
MAX9940
SYS_ONEWIRE
20% PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

2 10V
CERM
NC
BIL CONNECTOR
PP3V42_G3H
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
C6951
1-Wire OverVoltage Protection

6
516S0523
CRITICAL
0.1UF
10%
25V
X5R
402
ADAPTER_SENSE
J6955
CPB6312-0101F
F-ST-SM
14
The chassis ground will otherwise float and can

send transients onto ADAPTER_SENSE when AC is
connected.
R6961
53 46 45
SMC_LID
OUT
100
402
10
12
11
16
15
NC
SMC_LID_R
SMBUS_SMC_BSA_SDA
BI
SMBUS_SMC_BSA_SCL
BI
6
1/16W
97
48 45 6
65 64
5%
MF-LF
48 45 6
65 64
97
C6955
C6953
10%
50V
CERM
402
C6952
47PF
0.001UF
5%
50V
CERM
402
5%
50V
CERM
402
NC
TO SMC
SMC_BIL_BUTTON_L
C6954
47PF
2
13
OUT
6 45 46
0.001UF
10%
50V
CERM
402
3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator
R6990
1
VOLTAGE=18.5V
PPDCIN_G3H_OR_PBUS_R
VOLTAGE=18.5V
5%
1/16W
MF-LF
402
C6990 1
1UF
P3V42G3H_BOOST
10%
25V
X5R 2
603-1
PPDCIN_G3H_OR_PBUS
65
VIN
C6994 1
BOOST
0.1UF
LT3970
CRITICAL
J6950
CRITICAL
353s2730
9 PG
NC
10 RT
GND
P3V42_RT
4
6 65
SW
BD
FB
L6995
33UH
P3V42G3H_SW
SWITCH_NODE=TRUE
DIDT=TRUE
P3V42_BD_R
1/16W
MF-LF
402
5%
PAD
R6991
SMBUS_SMC_BSA_SCL
SYS_DETECT_L
SMBUS_SMC_BSA_SDA
150K
6 45 48 64 65 97
6
45 48 64 65 97
CRITICAL
2
RCLAMP2402B
SC-75
D6950
1%
1/16W
MF-LF
2 402
R6950 1
C6950
10%
25V
X5R
402
5%
1/16W
MF-LF
402 2
10
11
C6995 1
47PF
5%
50V
CERM 2
402
<Ra>
1
(Switcher limit)
R6995
1.00M
1%
1/8W
MF-LF
2 805
C6999
22UF
P3V42G3H_FB
20%
2 6.3V
X5R-CERM
603
<Rb>
1
R6996
549K
1%
1/16W
MF-LF
2 402
0.1UF
10K
250mA max output
R6992
THRM
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
Vout = 3.425
CDPH4D19FHF-SM
PP3V42_G3H
2
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
PPVBAT_G3H_CONN
1
2
6
7
P3V42_EN_R
1/16W
MF-LF
402
5%
M-RT-TH
4
5
DFN
2 EN/UVL0
R6993
BATTERY CONNECTOR
BAT-K19
P1
P2
P3
P4
P5
P6
P7
P8
P9
11
518-0358
CRITICAL
10%
16V 2
X5R
402
U6990
12
GND
Vout = 1.25V * (1 + Ra / Rb)
13
SYNC_MASTER=K18_POWER
PAGE TITLE
DC-In & Battery Connectors

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
69 OF 132
SHEET
64 OF 101
Reverse-Current Protection
CRITICAL
Q7080
SOI
PPDCIN_G3H
D2
D1
S1
R7080
100K
GATE
CHGR_SGATE_DIV
D3
D2
D1
S1
PPDCIN_G3H_INRUSH
VOLTAGE=18.5V
7
6
CHGR_AGATE_DIV
1
1
R7081
R7086
62K
332K
5%
1/16W
MF-LF
2 402
CRITICAL
D7005
BAT30CWFILM
1%
1/16W
MF-LF
402 2
(CHGR_SGATE)
SOT-323
1
(CHGR_AGATE)
R7005
3
CHGR_DCIN_D_R
20
R7021
(CHGR_DCIN)
Divider sets ACIN threshold at 13.55V
R7002
VDD
30.1K
5% 48
1/16W97
MF-LF48
402 97
1%
1/16W
MF-LF
2 402
CHGR_RST_L
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
CHGR_VFRQ
CHGR_CELL
2
45 6
64
IN
45 6
64
73
BI
IN
Float CELL for 1S
CHGR_ACIN
R7011
9.31K
1%
1/16W
MF-LF
2 402
R7015
97
220K
97
5%
1/16W
MF-LF
2 402
BATT_2S
R70131
CHGR_VCOMP_R
1K
1%
1/16W
MF-LF
402 2
C7015 1
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
C7050
1UF
10%
16V
2 X5R
402
0.020
0.5%
1W
MF-LF
CHGR_CSI_R_N
3 1 0612
PPDCIN_G3H_CHGR
0.1UF
VOLTAGE=18.5V
C7021
10%
2 25V
X5R
402
U7000
CHGR_DCIN
26
1
28
27
CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
97
97
25
24
23
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
21
CHGR_LGATE
CRITICAL
D
1
C7025
RJK0332DPB-01
LFPAK-SM
0.22UF
C7036
1UF
10%
25V
2 X5R
603-1
20%
2 25V
POLY-TANT
CASE-D2-SM
C7037
0.001UF
10%
2 50V
X7R
402
10%
25V
2 X5R
603-1
CHGR_BGATE
CHGR_AMON
CHGR_BMON
SMC_BC_ACOK
DIDT=TRUE
8AMP-24V
1
49
NO STUFF
OUT
49
OUT
45 46 64
180
5%
1/10W
MF-LF
603 2
PPVBAT_G3H_CHGR_REG
VOLTAGE=12.6V
CHGR_PHASE_RC
CRITICAL
XW7000
SM
CRITICAL
1
RJK0305DPB
NO STUFF
1
C7039
BATT_2S
10%
2 50V
CERM
402
1 2 3
Q7055
SI7137DP
SO-8
1%
1W
MF
0612
1
3
2
4
PPVBAT_G3H_CHGR_R
VOLTAGE=12.6V
C7055 1
C7056 1
C7057 1
10%
25V
X5R 2
603-1
10%
16V 2
X5R
402
10%
16V
CERM 2
402
1UF
CHGR_VNEG_R
R7051
R7052
(CHGR_CSO_N)
2.2
99 49
99 49
CRITICAL
0.005
(GND)
(CHGR_CSO_P)
10%
2 50V
X7R
402
R7050
470PF
C7045
0.001UF
20%
2 25V
POLY-TANT
CASE-D2-SM
DIDT=TRUE
Q7035
C7040
22UF
470PF
C7016
6 7 40 49 66 67 69 70 82
86 89
1206
R70391
OUT
353S2392
10%
2 50V
CERM
402
PPBUS_G3H
FDA1254F-SM
TO SYSTEM
F7040
4.7UH-10.2A
2
SWITCH_NODE=TRUE
LFPAK-HF
CRITICAL
L7030
GATE_NODE=TRUE DIDT=TRUE
16
9
36V/V BMON 15
(OD) ACOK 14
1 2 3
DIDT=TRUE
C7035
1UF
22UF
CRITICAL
1%
1/16W
MF-LF
402 2
C7031
Max Current = 8A
(L7030 limit)
f = 400 kHz
Q7030
10%
10V
2 CERM
402
10%
50V
CERM 2
402
3.01K
CRITICAL
1
5
2
470PF
R70161
C7030
20%
2 25V
POLY-TANT
CASE-D2-SM
0.1UF
10%
25V 2
X5R
402
CRITICAL
1
22UF
VDDP
VHST CRITICAL DCIN

SMB_RST_N
SGATE
SCL
AGATE
TQFN
SDA
CSIP
VFRQ
CSIN
CELL
BOOT
3 ACIN
UGATE
5 ICOMP
PHASE
7 VCOMP
LGATE
8 VNEG
18 CSOP
BGATE
17 CSON
20V/V AMON
ISL6259HRTZ
SMC_RESET_L
IN
12
13
11
10
4
6
PGND
65
5%
1/16W
MF-LF
2 402
R7020
20
100K
GND_CHGR_AGND
C7022 1
10%
10V 2
X5R
402
(AGND)
THRM_PAD
R7010
C7001 1
1UF
R7000
0
VOLTAGE=5.1V
5%
1/16W
MF-LF
402
22
1%
1/16W
MF-LF
402 2
99
10
4 2
CHGR_CSI_R_P
5%
1/16W
MF-LF
402
PP5V1_CHGR_VDDP
10%
10V 2
X5R
402
1K
4.7
NO STUFF
1UF
R70121
19
C7002
BATT_3S
VOLTAGE=5.1V
PP3V42_G3H
29
R7022
1
R7001
PP5V1_CHGR_VDD
48 47 46 45 43 23 21 17 7 6
73 66 64 53 49
CRITICAL
99
C7020
10%
10V
2 CERM
402
30mA max load
5%
1/16W
MF-LF
402
0.047UF
Input impedance of ~40K meets

sparkitecture requirements
10
5%
1/16W
MF-LF
402
ACIN pin threshold is 3.2V, +/- 50mV
GATE
1%
1/16W
MF-LF
402
2 X5R
2 402
470K
10%
25V
402
5%
1/16W
MF-LF
C70851 R7085
0.1UF
D4
S3
S2
TO/FROM BATTERY
0.1UF
PPVBAT_G3H_CONN
5
Inrush Limiter
VOLTAGE=18.5V
S3
S2
D3
This node is powered

through body diodes:
* DCIN through Q7080.
* PBUS through Q7085,
Charger TOP FETs and CRITICAL
Q7055.
Q7085
HAT1128R01
PPDCIN_G3H_OR_PBUS 64
SOI
D4
0.01uF
VOLTAGE=12.6V
6 64
64 7 6
HAT1128R01
2 3
FROM ADAPTER
CHGR_CSO_R_P
5% 1/16W MF-LF 402
CHGR_CSO_R_N
5% 1/16W MF-LF 402
(PPVBAT_G3H_CHGR_R)
(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
C7042
C7011 1
0.033UF
0.01UF
10%
2 16V
X5R
402
10%
16V
CERM 2
402
C7000
1UF
10%
2 10V
X5R
402-1
C7005 1
C7026 1
0.22UF
0.001UF
20%
25V 2
X5R
603
65
10%
50V
CERM 2
402
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
R7050
CRITICAL
BATT_3S
GND_CHGR_AGND
TABLE_5_ITEM
VOLTAGE=0V
107S0139
RES,0.010,0.5%,1W,0612-1
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER
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SIZE
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<BRANCH>
PAGE
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73 45
SMC_PM_G2_EN
R7273
100K
5%
1/16W
MF-LF
2 402
PPBUS_G3H
86 82 70 69 67 65 49 40 7 6
89
CRITICAL
72 23 7 6
C7241
SIS424DN
PP5V_S3
PWRPK-1212-8-SM
4 TONSEL
Vout = 5.0V
CRITICAL
9.1A MAX OUTPUT
L7220
(Q7220 limit)
3 2 1
2
4.7UH-13A-15MOHM
CRITICAL
VIN
14 SKIPSEL
PCMB104E4R7-SM
C7252 1
C7250 1
20%
6.3V
POLY-TANT 2
CASE-D3L-SM1
20%
10V 2
X5R
805
NO STUFF1
R7222
10UF
330UF
10
5%
1/16W
MF-LF
402 2
C7251
0.001UF
10%
2 50V
CERM
402
NO STUFF
5
CRITICAL MIN_NECK_WIDTH=0.2 mm
D
P5VS3_RC
QFN
20 LL1
P5VS3_LL
19 DRVL1
P5VS3_DRVL
GATE_NODE=TRUE
DRVL2 12
(P5VS5_VO1)
P5VS3_VFB
2 VFB1
P5VS3_ENTRIP
1 ENTRIP1
DIDT=TRUE
ENTRIP2 6
P3V3S5_ENTRIP
1%
1/16W
MF-LF
2 402
2.2UH-10A-14MOHM
G2
C7208
220PF
5%
2 25V
CERM
402
P5V_S3_V01_XW
R7220
15.0K
1%
1/16W
MF-LF
2 402
GND_P5VP3V3_SGND
VOLTAGE=0V
CRITICAL
R7262
10
5%
1/16W
MF-LF
402 2
C7292
150UF-.025-OHM
C7290 1
P3V3S5_RC
XW7261
SM
5%
50V
CERM 2
402
20%
6.3V 2
X5R
603
C7291
0.001UF
10%
50V
2 CERM
402
20%
2 6.3V
TANT
CASE-B2-SM
10UF
2
XW7260
SM
R7206
88.7K
1%
1/16W
MF-LF
2 402
P3V3_S5_V02_XW
P3V3_S5_REG_XW
1
R7260
XW7200
SM
(L7260 limit)
2
FDVE0830-SM
NO STUFF
1
NO STUFF
NO STUFF
1
7.2A MAX OUTPUT
L7260
S1/D2
Vout = 3.3V
CRITICAL
WPAK
G1
100PF
EN0 13
5V3V3_REG_EN
GND THRM_PAD
88.7K
C7262 1
NC
PGOOD 23
R7200
mm
mm
mm
mm
mm
mm
mm
mm
S2
P3V3S5_VFB
P5V_S3_REG_XW
DIDT=TRUE
(P3V3S5_V02)
VFB2 5
SM
DIDT=TRUE
P3V3S5_DRVL
GATE_NODE=TRUE
VO2 7
152S1115
RJK0384DPA
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
99
31 35 57 71
6 7 17 18 19
20 21 23 27
72 73 83 85
PP3V3_S5
Q7260
D1
P3V3S5_LL
DIDT=TRUE
f=460KHz
CRITICAL
P3V3S5_DRVH
SWITCH_NODE=TRUE
24 VO1
10%
50V 2
X7R
603-1
10%
10V
CERM
402
LL2 11
402
10%
2 25V
X5R
603-1
0.1UF
P3V3S5_VBST
VCLK 18
1
1UF
C7264 1
0.22UF
DRVH2 10
CRITICAL
DIDT=TRUE
10UF
C7201
VBST2 9
10%
50V
C7281CERM
C7205
20%
10V
2 X5R
603
10%
25V
X5R 2
603-1
GATE_NODE=TRUE
S
3 2
VREG5 17
DIDT=TRUE
C7222 1
100PF
XW7220
5%
2
50V
CERM
402
XW7221
SM
2
P5VS3_DRVH
TPS51125
21 DRVH1
SWITCH_NODE=TRUE
U7201
22 VBST1
GATE_NODE=TRUE
PWRPK-12128
VREG3 8
P5VS3_VBST
Q7225
SIS426DN
VREF
15
72 67 61 58 56 54 46 44 43 42 33 31 7 6
101 82
10%
25V 2
X5R
603-1
10%
2 50V
X7R
603-1
1UF
Q7220
C7203
1UF
C7224
0.1UF
C7200
5%
1/16W
MF-LF
402
CRITICAL
5
1
20%
16V
POLY-TANT 2
CASE-D2E-SM
P5VP3V3_VREF
R7224
2
0.001UF
68UF
P3V3S5_VBST_R
5%
1/16W
MF-LF
402
P5VP3V3_VREG3
P5VS3_VBST_R
10%
2 25V
X5R
603-1
20%
16V
POLY-TANT 2
CASE-D2E-SM
f=365KHz
PP5V_S5
1UF
68UF
25
10%
50V
CERM 2
402
C7240 1
0.001UF
16
C7243
CRITICAL
C7282 1
C7280 1
R7264
6.49K
1%
1/16W
MF-LF
2 402
R7261
R7221
10K
One master PGOOD for both 5V and 3V3
10K
1%
1/16W
MF-LF
2 402
73
1%
1/16W
MF-LF
2 402
P5V3V3_PGOOD
OUT
D 6
Q7210
SSM6N15FEAPE
SOT563
B
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
PP3V42_G3H
2 G
S 1
Q7211
R7210
SOT563
5%
1/16W
MF-LF
2 402
5 G
P5VS3_EN_L
Q7210
D 3
46 45 43 23 21 17 7 6
73 66 65 64 53 49 48 47
SSM6N15FEAPE
SOT563
D 3
SSM6N15FEAPE
10K
S 4
PP3V42_G3H
1
R7211
10K
5 G
73
5%
1/16W
MF-LF
S 4
2 402
P5VS3_EN
P3V3S5_EN_L
Q7211
D 6
SSM6N15FEAPE
SOT563
2
73
S 1
P3V3S5_EN
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER
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<E4LABEL>

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<SCH_NUM> D
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BRANCH
<BRANCH>
PAGE
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66 OF 101
72 67 31 30 28 7 6
PP1V5_S3
C7355
89 86 82
49 40 7 6
70 69 66 65
PPBUS_G3H
10UF
20%
2 6.3V
X5R
603
72 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82
CRITICAL
4.7
68UF
20%
20%
16V
16V
POLY-TANT 2
POLY-TANT 2
CASE-D2E-SM
CASE-D2E-SM
PP5V_S3_DDRREG_V5FILT
C7331 1
68UF
R7305
PP5V_S3
CRITICAL
C7330 1
C7332
1UF
C7333
0.001UF
10%
2 25V
X5R
603-1
10%
2 50V
X7R
402
VOLTAGE=5V
5%
1/16W
MF-LF
402
CRITICAL
10%
10V 2
X5R
402-1
V5IN
V5FILT
32 7 6
31 30 28 7 6
VBST 22
U7300
TPS51116
PPVTTDDR_S3
10mA max load
PP0V75_S0_DDRVTT
CRITICAL
C7360
CRITICAL
22UF
20%
6.3V
X5R-CERM 2
603
QFN
5 VTTREF
LL 20
24 VTT
= VTTREF
GATE_NODE=TRUE
DDRREG_LL
SWITCH_NODE=TRUE
DDRREG_DRVL
DRVL 19
C7325
R7325
1
5%
1/16W
MF-LF
402
CRITICAL
1 2 3
2 VTTSNS
NC
NC
1
2
DDRREG_VBST_R
MIN_NECK_WIDTH=0.17 mm 10%
50V
X7R
603-1
20%
2 6.3V
X5R-CERM
603
VDDQSET 9
VTTGND
THRM_PAD GND
(DDRREG_LL)
(DDRREG_DRVL)
Q7335
CSD58857Q5
R7350
C7345 1 C7346
C7341 1
20%
2V 2
TANT
CASE-B4-SM
20%
2 6.3V
X5R
603
10UF
DDRREG_FB_XW
PLACEMENT_NOTE=Place next to Q7335
(DDRREG_CSGND)
XW7335
SM
1
1
R7320
15.0K
1%
1/16W
MF-LF
2 402
<Ra>
(DDRREG_FB)
XW7300
SM
XW7301
SM
0.001UF
(DDRREG_VDDQSNS)
10%
16V 2
X5R
402
10%
50V
2 X7R
402
to memory
C7350 1
Vout = 1.5V
13A max output
(Q7335 limit)
f = 400 kHz
CRITICAL
CRITICAL
1 2 3
DDRREG_CSGND
0.033UF
0.001
20%
2 2V
TANT
CASE-B4-SM
270UF
DDRREG_FB
PP1V5_S3
6 7 28 30 31 67 72
C7340
C7360, C7361 close
50 99
MF-1
1W
1%
270UF
CRITICAL
PGND CS_GND
OUT
2 0612
CRITICAL
1
S
32
ISNS_1V5_S3_N
C
4
PPDDR_S3_REG_R
2
FDU1040D-SM
DDRREG_CS
CS 16
7 NC0
12 NC1
50 99
VOLTAGE=1.5V
L7330
1.0UH-21A
0.1UF
MLP5X6-LFPAK-Q5
22UF
DDRREG_DRVH
DIDT=TRUE
DDRREG_VTTSNS
C7361
DDRREG_VBST
OUT
DIDT=TRUE
SYM (2 OF 2)
Vout = VDDQSNS/2
Vout
XW7360
SM
DRVH 21
18
IN
OUT
1%
1/16W
MF-LF
402 2
ISNS_1V5_S3_P
MLP5X6-LFPAK-Q5A
5.23K
MODE 4
10 S3
VTT Enable
11 S5
VDDQ/VTTREF Enable
13 PGOOD VDDQ PGOOD
73
73
MEMVTT_EN
DDRREG_EN
DDRREG_PGOOD
25
IN
31 8
CSD58856Q5A
R73101
VDDQSNS 8
CRITICAL
VLDOIN
6 COMP
(DDRREG_DRVH)
23
1UF
17
C7305
20%
10V 2
X5R
603
14
10UF
Q7330
1
15
C7300
Vout = 0.75V * (1 + Ra / Rb)
R7321
15.0K
1%
1/16W
MF-LF
2 402
<Rb>
GND_DDRREG_SGND
VOLTAGE=0V
PAGE TITLE
1.5V DDR3 Supply

DRAWING NUMBER
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<SCH_NUM> D
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5
PLACE_NEAR=Q7410.1:8mm
PPBUS_CPU_IMVP_ISNS
49 7
CRITICAL
CRITICAL
CRITICAL
C7410 1
C7413 1
C7415 1
20%
16V 2
POLY-TANT
CASE-D2E-SM
20%
16V 2
POLY-TANT
CASE-D2E-SM
20%
16V 2
POLY-TANT
CASE-D2E-SM
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
CRITICAL
C7405 1
68UF
68UF
C7411
10UF
68UF
10%
25V
2 X5R
805
C7412
0.001UF
C7421
10UF
10%
2 50V
X7R
402
10%
25V
2 X5R
805
C7422
0.001UF
10%
2 50V
X7R
402
CRITICAL
L7415
0.36UH-20%-40A-0.00075OHM
1
99 88 87 85 84 83
51 50 48 47 46 42 40
21 20 19 18 17 7 6
37 34 30 28 27 26 25 24 23
80 73 72 69 63 62 58 54 52
54 52 47 42 23 7 6
88 86 72 70 69
PP3V3_S0
PP5V_S0
4
CRITICAL
Q7410
RJK0365DPA-02
WPAK
VOLTAGE=5V
C7401
20%
10V
X5R-CERM 2
402
XW7417
SM
1 PLACE_NEAR=L7415.1:4mm
1PLACE_NEAR=L7415.2:4mm
22.1K
1%
1/16W
MF-LF
2 402
IN
IN
CPU_VCCSENSE_P
CPU_VCCSENSE_N
40
C7402
0.22UF
10%
2 10V
CERM
402
R74001
249K
1%
1/16W
MF-LF
402 2
68
68
68
IN
IN
IN
IN
IN
IN
IN
CPUIMVP_VID<0>
CPUIMVP_VID<1>
CPUIMVP_VID<2>
CPUIMVP_VID<3>
CPUIMVP_VID<4>
CPUIMVP_VID<5>
CPUIMVP_VID<6>
20
19
18
17
16
15
14
CPUIMVP_SLEW
37
CPUIMVP_ISEN1P
CPUIMVP_ISEN1N
6
5
CSP1
CSN1
CPUIMVP_ISEN2P
CPUIMVP_ISEN2N
3
4
CSP2
CSN2
OMIT
C7440
NOSTUFF
OMIT
1
NONE
NONE 2
NONE
402
C7441
NOSTUFF
OMIT
1
NONE
NONE 2
NONE
402
C7442
150KOHM-5%
NOSTUFF
NONE
NONE
2 NONE
402
22
21
23
24
CPUIMVP_BOOT1
CPUIMVP_UGATE1
CPUIMVP_PHASE1
CPUIMVP_LGATE1
29
30
28
27
CPUIMVP_BOOT2
CPUIMVP_UGATE2
CPUIMVP_PHASE2
CPUIMVP_LGATE2
C7443
NOSTUFF
NONE
NONE
2 NONE
402
R7414 2
5%
CPUIMVP_BOOT1_RC
1/16W
33
34
35
12
13
1
CPUIMVP_PGOOD
CPUIMVP_CLK_EN_L
CPUIMVP_VR_ON
PM_DPRSLPVR
CPU_PSI_L
C7414
MF-LF 402
10% 25V
C7420
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
R7424 2
CPUIMVP_BOOT2_RC
1/16W
C7424
MF-LF 402
10%
25V
X5R
603-2
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
OUT
26
IN
45
IN
12 15 91
IN
12 15 91
RJK0365DPA-02
CPUIMVP_ISEN1P
WPAK
68
L7425
(CPUIMVP_PHASE2)
2
PIMA104E-SM
R7440
5% 1/16W
CPU_PROCHOT_L
MF-LF
16.9K
1%
1/16W
MF-LF
2 402
402
OUT
10 46 91
OUT
12 50 91
CRITICAL
Q7425
C7450
XW7427
SM
1 PLACE_NEAR=L7425.2:4mm
CPUIMVP_PHASE2X
RJK0208DPA
CPUIMVP_ISEN2N_R
WPAK
0.0033UF
10%
50V
2 CERM
402
XW7426
SM
5
1
R7426
22.1K
1%
1/16W
MF-LF
2 402
1 2 3
IMON output range: 1.1V
R7427
1
100K
41.2K2
1
294K 2
R7428
1%
1/16W
MF-LF
402
R7429
5%
1/16W
MF-LF
402 2
XW7400
SM
2
CPUIMVP_ISEN1N
68
0.36UH-20%-40A-0.00075OHM
R7450
CPU_VCCSENSE_N
CRITICAL
1 2 3
91 68 12
CPUIMVP_NTC
CPUIMVP_VR_TT_L
CPUIMVP_IMON
6 7 12 15 49
R74221
5%
1/16W
MF-LF
402 2
27
OUT
PPVCORE_S0_CPU
5%
1/16W
MF-LF
402 2
CRITICAL
Q7420
48A max current
2
10%
10V
X5R
402
R74211
1UF
X5R 603-2
5%
CPUIMVP_ISEN1P_R
R74451
1%
1/16W
MF-LF
402
27.0NF
1UF
THRM
GND PGND PAD
OMIT
1
R7419
CPUIMVP_ISEN1_NTC 141.2K2
1 2 3
THERM 9
VR_TT* 10
IMON 11
TRIPSEL 31
OSRSEL 32
68
41
91 12
91 68 12
8
7
CPUIMVP_VREF
QFN
VBST1
DRVH1
DROOP
353S2942 LL1
DRVL1
VSNS
GNDSNS
VBST2
DRVH2
VREF
CRITICAL LL2
VID0
DRVL2
VID1
VID2
PGOOD
VID3
CLK_EN*
VID4
VR_ON
VID5
DPRSLPVR
VID6
PSI*
MODE
SLEW
39
CPUIMVP_DROOP
1%
1/16W
MF-LF
402
TPS51621
36 TONSEL
5%
50V
CERM
402
3.92K2
1
U7400
25
R7403
1%
1/16W
MF-LF
402
0402
WPAK
V5FILT V5IN
33PF
294K 2
R7418
RJK0208DPA
26
38
C7403
R7417
CRITICAL
Q7415
4
CPUIMVP_ISEN1N_R
R7416
5
D
XW7416
SM
(CPUIMVP_PHASE1)
10%
10V
2 X5R
805
1 2 3
C7400
4.7UF
2.2UF
CPUIMVP_PHASE1X
PP5V_S0_CPUIMVP_V5FILT
2
PIMA104E-SM
0402
CPUIMVP_ISEN2_NTC
1%
1/16W
MF-LF
402
C7430
150KOHM-5%
27.0NF
CPUIMVP_AGND
CPUIMVP_ISEN2P_R
VOLTAGE=0V
2
10%
10V
X5R
402
R7430
0
R74311
0
5%
1/16W
MF-LF
402 2
Loadline = DCR * K * 5.95 / (R7403 * 2uA/mV)

Loadline = 1.83 mohm
5%
1/16W
MF-LF
402 2
CPUIMVP_ISEN2P
68
68
CPUIMVP_ISEN2N
VIMON = Io * DCR * 2uA/mV * R7450

50 A = 1.00 V
K = (R7417 || (R7418 + R7419)) / (R7417 || (R7418 + R7419) + R7416) = 0.66
PAGE TITLE
CPU IMVP VCore Regulator

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
74 OF 132
SHEET
68 OF 101
GFX IMVP VCORE
86 82 70 67 66 65 49 40 7 6
89
PPBUS_G3H
PP5V_S0
70 69 68 54 52 47 42 23 7 6
88 86 72
NO STUFF
R7514 1
C7511
1%
1/16W
MF-LF
402 2
R7511
IN
91 13
IN
5%
50V
CERM 2
402
C7512
0.22UF
R7513
46.4K
1%
1/10W
MF-LF
2 603
IN
IN
IN
IN
IN
IN
IN
VSNS
GNDSNS
GFXIMVP_VREF
32
VREF
GFXIMVP_VID<0>
GFXIMVP_VID<1>
GFXIMVP_VID<2>
GFXIMVP_VID<3>
GFXIMVP_VID<4>
GFXIMVP_VID<5>
GFXIMVP_VID<6>
16
15
14
13
12
11
10
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GFXIMVP_ISLEW
29
ISLEW
99
2
3
GFXIMVP_CS_N
353S2664
IMONC
TRIPSEL
IMON
VR_TT*
THERM
GFXIMVP_CS_P
99
GND_GFXIMVP_AGND
VBST
DRVH
LL
DRVL
PGOOD
CLK_EN*
VR_ON
DPRSLPVR
MODE
CSP
CSN
30
18
17
19
20
4
GATE_NODE=TRUE
28
26
8
7
6
MLP5X6-LFPAK-Q5A
88 99
50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87
PP3V3_S0
CRITICAL
R7540
CRITICAL
0.001
L7530
1 2 3
0.68UH-27A-1.7MOHM
1
2 PPVCORE_S0_GFX_REG_R
SWITCH_NODE=TRUE
FDU1040D-SM
VOLTAGE=1.05V
2
4
1%
1W
MF-1
0612
Vout = VID controlled

22A max output
f = 350KHz
PPVCORE_S0_GFX
1
3
6 7 13 24 49
DIDT=TRUE
GFXIMVP_PGOOD
OUT
73
R7517
GFX_VR_EN
GFX_DPRSLPVR
IN
13 91
IN
13 91
23 42 47 52 54 68 69 70 72 86
6
7
88
GFXIMVP_IMONC
GFXIMVP_VREF_R
GFXIMVP_IMON
200K
1%
1/16W
MF-LF
2 402
GFXIMVP_LGATE
OUT
CRITICAL
C7556
10UF
Q7535
CSD58857Q5
GATE_NODE=TRUE
MLP5X6-LFPAK-Q5
20%
6.3V
X5R
603
C7557
1000PF
5%
25V
2 NP0-C0G
402
DIDT=TRUE
13 91
NC
GFXIMVP_THERM
1 2 3
SIGNAL_MODEL=EMPTY
C7515
150K
5%
2 25V
NP0-C0G
402
CSD58856Q5A
GFXIMVP_PHASE
R7516 1
1%
1/16W
MF-LF
402
XW7500
SM
C7524
Q7530
GFXIMVP_V5FILT
23
24
NC
25
9
22
PP5V_S0
1000PF
10%
2 25V
X5R
603-1
CRITICAL
GFXIMVP_UGATE
GFXIMVP_VBST
C7523
1UF
DIDT=TRUE
V5FILT
CRITICAL
GND
10%
10V
CERM 2
402
5
4
QFN
DROOP
TONSEL
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
5
2
10%
16V 2
X5R
402
TPS51981
31
27
1UF
U7500
1%
1/16W
MF-LF
2 402
GFX_VSENSE_P
GFX_VSENSE_N
69
C7514
V5IN
1.69K
33PF
GFXIMVP_VBST_R
GFXIMVP_TONSEL
91 13
10%
16V 2
X5R
603
C7521 1
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
SOT-323
1
CRITICAL
C7520 1
BAT30CWFILM
5%
1/16W
MF-LF
402
2.2UF
10%
16V 2
X5R
603
PGND
1K
C7513
2.2UF
33
R7512
C7510
GFXIMVP_DROOP
21
PP3V3_S0
CRITICAL
D7514
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
0.0033UF
10%
50V
CERM 2
402
SIGNAL_MODEL=EMPTY
1
R7515
22.6K
1%
1/16W
MF-LF
2 402
NO STUFF
R7518
100K
1%
1/16W
MF-LF
2 402
C7517
0.022UF
10%
2 16V
CERM-X5R
402
R7509
5%
1/16W
MF-LF
402
R7510
0
2
5%
1/16W
MF-LF
402
GFXIMVP_VREF
(GND_GFXIMVP_AGND)
(GFX_VSENSE_N)
VOLTAGE=0V
69
R7542
1
99 50
GFXIMVP_CS_R_N
99 50
GFXIMVP_CS_R_P
5%
1/16W
MF-LF
402
R7541
1
C7549 1
10PF
5%
50V
CERM 2
402
OMIT
C7542
OMIT
C7541
NOSTUFF
NONE
NONE 2
NONE
402
5%
1/16W
MF-LF
402
NOSTUFF
NONE
NONE 2
NONE
402
(GND_GFXIMVP_AGND)
Imon= Io xR7540 x2uA/mV x R7515

Imon= Io x45.2mV/A
22A => 1V
PAGE TITLE
GFX IMVP VCore Regulator

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
75 OF 132
SHEET
69 OF 101
CPU VTT (1.05V S0) Regulator

D
PPBUS_G3H
86 82 69 67 66 65 49 40 7 6
89
PP5V_S0
72 69 68 54 52 47 42 23 7 6
88 86
CRITICAL
R76011
VCC
CPUVTTS0_BOOT_RC
CPUVTTS0_SREF
91 10
OUT
CPUVTTS0_PGOOD
IN
CPU_VTTSENSE_P
CPUVTTS0_VO
CPUVTTS0_OCSET
91 12
R7604
91 12
IN
3.01K2
CPU_VTTSENSE_N
CPUVTTS0_RTN
1%
1/16W
MF-LF
402
CPUVTTS0_FSEL
1
2
EN
BOOT 12
FB
UGATE 11
SREF
PHASE 10
VO
LGATE 15
OCSET
PGOOD
RTN
C7602 1
CPUVTTS0_DRVH
10%
16V
X5R 2
603
C7604
0.001UF
10%
50V 2
X7R
402
C7605
CRITICAL
Q7630
CSD58856Q5A
GATE_NODE=TRUE
MLP5X6-LFPAK-Q5A
CRITICAL
1 2 3
CPUVTTS0_LL
SWITCH_NODE=TRUE
FSEL
GND
PGND
CRITICAL
CRITICAL
0.001
0.68UH-27A-1.7MOHM
1
2
PPCPUVTT_S0_REG_R
VOLTAGE=1.05V
CRITICAL
Q7635
99 50
10%
402
2
4
PP1V05_S0
1
3
CPUVTTS0_CS_P
99 50
CPUVTTS0_CS_N
1
C7647
20%
6.3V
603
2 X5R
5%
1/16W
MF-LF
2 402
R7641
1 2 3
3.48K
1%
1/16W
MF-LF
402 2
C7640
C7603
1000PF
2
CPUVTTS0_AGND
5%
25V
NP0-C0G
402
XW7600
SM
R7642
3.48K
1%
1/16W
MF-LF
2 402
(CPUVTTS0_OCSET)
SIGNAL_MODEL=EMPTY
NO STUFF
C7641 1
(CPUVTTS0_VO)
0.0022UF
10%
50V
CERM 2
402
CPUVTTS0_FB_RC
SIGNAL_MODEL=EMPTY
NO STUFF
10UF
VOLTAGE=0V
6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 73 86
Vout = 1.05V
27A max output
f = 300 kHz
MLP5X6-LFPAK-Q5
10%
2 10V
CERM
402
2 50V
X7R
1%
1W
MF-1
0612
CSD58857Q5
0.047UF
0.001UF
R7640
L7630
FDU1040D-SM
CPUVTTS0_DRVL
152S1085
DIDT=TRUE
R7603
1%
1/16W
MF-LF
402 2
2.2UF
0.001UF
10%
2 50V
X7R
402
CPUVTTS0_VBST
2.74K
C7622
1UF
10%
2 16V
X5R
402
DIDT=TRUE
R7605
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
C7630
GATE_NODE=TRUE
1
20%
16V 2
POLY-TANT
CASE-D2E-SM
DIDT=TRUE
16
CPUVTTS0_FB
UTQFN
CPUVTTS0_EN
0
5%
1/16W
MF-LF
402
ISL95870
IN
C7623 1
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
R7630
PVCC
U7600
73
CRITICAL
C7621 1
14
13
VOLTAGE=5V
CRITICAL
C7620 1
68UF
20%
2 10V
X5R
603
5%
1/10W
MF-LF
603 2
PP5V_S0_CPUVTTS0_VCC
C7601
10UF
2.2
R7644
3.01K
1%
1/16W
MF-LF
1 402
R76432
<Ra>
100
1%
1/16W
MF-LF
402 1
Vout = 0.5V * (1 + Ra / Rb)
(CPUVTTS0_FB)
<Rb>
1
R7645
2.74K
1%
1/16W
MF-LF
2 402
(CPUVTTS0_AGND)
PAGE TITLE
CPUVTT (1.05V) Power Supply

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
76 OF 132
SHEET
70 OF 101
1.2V S3 Regulator
D
D
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
PP3V3_S5
C7760
22UF
20%
6.3V
CERM
805
1.05V S5 LDO
CRITICAL
152S0771
CRITICAL
U7760
2.2UH-1.2A
SC194A
PCAA031B-SM
Ibex Peak-M requires JTAG pull-ups to be powered at 1.05V in S5.

Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
L7760
MLP10
1 VIN
73 8
4 EN
PM_ENET_EN
IN
LX 10
353S2719
VOUT 5
P1V2ENET_SW
PP1V2_ENET
SWITCH_NODE=TRUE
DIDT=TRUE
3 SYNC/PWM
XW7761
SM
6 VID0
P1V2ENET_FB
7 VID1
PLACE_NEAR=L7760.2:1MM
2 MODE
3 EN
11
C7740 1
NC 2
GND
5
1UF
10%
6.3V 2
CERM
402
THRM
PAD
7
6 7 17
Vout = 1.05V
Max Current = 0.35A
OUT 1
XDP_PCH
PP1V05_S5
4 BIAS
6 IN
PAD
TPS720105
SON
PP3V3_S5
20%
6.3V
CERM
805
THRM
PGND
U7740
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
22UF
2
2
GND
C7761
CRITICAL
XDP_PCH
6 7 37 72
Vout = 1.2V
MAX CURRENT = 0.7A
FREQ = 1MHZ
NC
XDP_PCH
1
C7741
2.2UF
10%
2 6.3V
X5R
402
1.8V S0 Regulator
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
PP3V3_S5
22UF
5%
25V
NP0-C0G 2
402
20%
6.3V
CERM 2
805
152S1088
VDD
1
VIN 2
C7720 1
1000PF
CRITICAL
C7724
L7720
1.0UH-6.5A
U7720
IHLP2020CZ
PP1V8_S0
ISL8014
73
IN
P1V8S0_EN
5 EN
QFN
CRITICAL
73
OUT
P1V8S0_PGOOD
LX 14
LX 15
P1V8S0_SW
SWITCH_NODE=TRUE
DIDT=TRUE
CRITICAL
XW7700
SM
7 PG
P1V8S0_FB
R7722
17
11
12 PGND
9
10 SGND
4 SYNCH
THRM_PAD
VFB 8
P1V8S0_SYNCH
NC
16
6
13
P1V8S0_FB_XW
2
PLACE_NEAR=L7720.2:1MM
NC
NC
NC
R77201
CRITICAL
1
C7723
47PF
5%
50V
2 CERM
402
22UF
113K
1%
1/16W
MF-LF
402 2
<Ra>
CRITICAL
C7722
90.9K
5%
1/16W
MF-LF
2 402
C7721
20%
6.3V
2 CERM
805
R77211
10K
6 7 12 16 21 23 24 58 72 87
Vout = 1.794V
Max Current = 2.7A
Freq = ???
22UF
1%
1/16W
MF-LF
402 2
20%
6.3V
CERM 2
805
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
PAGE TITLE
Misc Power Supplies

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
77 OF 132
SHEET
71 OF 101
3.3V S0 FET
CRITICAL
CRITICAL
SIA417DJ
SIA417DJ
SC70-6L
2 G
73 46
31 18
45 43
P3V3S3_EN_L
S 1
47K
PM_SLP_S4_L
IN
3.3V S3 FET
Q7812
7
5%
1/16W
MF-LF
402
SSM6N15FEAPE
SOT563
C7810
0.01UF
1
P3V3S3_SS
5%
1/16W
MF-LF
402
MOSFET
SiA417
CHANNEL
P-TYPE 8V/5V
RDS(ON)
10%
16V
CERM
402
23 mOhm @4.5V
LOADING
0.033UF
10%
16V
X5R
402
2
73 72 49
IN
5 G
S 4
P3V3S0_SS
P-TYPE 8V/5V
23 mOhm @4.5V
LOADING
5%
1/16W
MF-LF
402
1.568 A (EDP)
SiA417
CHANNEL
RDS(ON)
0.01UF
47K
1
MOSFET
C7830
R7830
P3V3S0_EN_L
PM_SLP_S3_L_R
D
G
R7810
1
3.3V S0 FET
C7831
100K
D 3
10%
16V
X5R
402
SOT563
50 51 52 54 58 62 63 68 69 73
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
80 83 84 85 87 88 99
PP3V3_S0
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 73 87 101
R7832
0.033UF
10K
5%
1/16W
MF-LF
402
SSM6N15FEAPE
PP3V3_S3
PP3V3_S5
Q7812
R7812
D 6
C7811
PP3V3_S5
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
SC70-6L
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
Q7830
Q7810
3.3V S3 FET
2.3 A (EDP)
10%
16V
CERM
402
1.5V S3/S0 FET

PP1V5_S3
67 31 30 28 7 6
PP5V_S5
1
TDFN
ON
SHDN*
PG
NO STUFF
4.7UF
10%
6.3V
X5R-CERM 2
603
P1V5S0FET_GATE
5%
1/16W
MF-LF
402
SC70-6L
Q7801
R7801
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
SI7108DN
P1V5S0FET_GATE_R
PP3V3_S5
SI7108DN
CHANNEL
N-TYPE
RDS(ON)
6 mOhm @4.5V
LOADING
3.2 A (EDP)
0.01UF
1K
P3V3GPU_SS
5%
1/16W
MF-LF
402
D 3
PP1V2_ENET
MOSFET
SI2306BDS-GE3
CHANNEL
N-TYPE
RDS(ON)
65 mOhm @4.5V
LOADING
1 G
S 2
5.0V S0 FET
CRITICAL
Q7860
TPCP8102
0.124 A (EDP)
PP5V_S0
IN
ON
CRITICAL
SHDN*
D 5
G
R7850
1
P1V2S0_GATE
PG
R7862
P1V2S0_GATE_R
NC
X5R
2
R7860
P5V0S0_EN_L
47K
1
TPCP8102
CHANNEL
P-TYPE
RDS(ON)
18 MOHM @4.5V
LOADING
3.5 A (EDP)
C7860
402
0.01UF
P5V0S0_SS
5%
MOSFET
6 7 87
THRM
PAD
GND
6 7 23 42 47 52 54 68 69 70 72
86 88
5.0V S0 FET
10%
16V
MF-LF
402
0.033UF
5%
SOT23
PP1V2_S0
C7861
1/16W
SI2306BDS-GE3
S
47K
Q7850
5%
1/16W
MF-LF
402
PP5V_S3
CRITICAL
P1V2S0_EN
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82
376S0748
U7850
2 3
23V1K-SM
SLG5AP020
73
0.8 A (EDP)
LOADING
23 mOhm @4.5V
EG_RAIL2_EN
VCC
TDFN
P-TYPE 8V/5V
SiA417
CHANNEL
10%
16V
CERM
402
0.1UF
20%
10V
CERM
402
MOSFET
RDS(ON)
C7870
R7870
1
SOD-VESM-HF
IN
1.2V S0 FET
PP5V_S5
C7850
Q7872
87 73
72 66 23 7 6
10%
10V
X5R
402
P3V3GPU_EN_L
SSM3K15FV
MOSFET
1UF
51K
6 7 13 16 31 42 73 99
5%
1/16W
MF-LF
402
1.2V S0 FET
C7871
R7872 1
PP1V5_S3RS0
1.5V S3/S0 FET
71 37 7 6
6 7 74 79 80 81 82 84
3.3V S0 GPU FET
1 2 3
NC
THRM
PAD
GND
PP3V3_S0GPU
PWRPK-1212-8-HF
7 8
C7802
CRITICAL
D 5
CRITICAL
5 6
P1V5CPU_EN
CRITICAL
Q7870
SIA417DJ
4 7
SLG5AP020
IN
APN 376S0651
VCC
U7801
20%
10V
CERM
402
31
3.3V S0 GPU FET
0.1UF
C7801
72 66 23 7 6
Q7865
SSM3K15FV
1/16W
10%
MF-LF
16V
402
CERM
402
D 3
SOD-VESM-HF
1
73 72 49
IN
PM_SLP_S3_L_R
S 2
1.8V S0 GPU_IFPX FET

87 71 58 24 23 21 16 12 7 6
88
52 47 42 23 7 6
86 72 70 69 68 54
PP1V8_S0
PP5V_S0
1.8V S0 GPU_IFPX FET

C7880
20%
10V
CERM
402
VCC
376S0683
U7880
IN
EG_RAIL4_EN
N-TYPE
TDFN
ON
SHDN*
CRITICAL
D
D
PG
CRITICAL
Q7880
P1V8GPUIFPXFET_GATE 1
LOADING
31 mOhm @4.5V
0.3 A (EDP)
Power FETs
SOT23
DRAWING NUMBER
2
GND
PAGE TITLE
SI2312BDS
NC
PP1V8_GPUIFPX
Apple Inc.
6 7 81
THRM
PAD

SIZE
<SCH_NUM> D
REVISION
87 86 73
SI2312BDS
CHANNEL
RDS(ON)
SLG5AP020
2
MOSFET
1
0.1UF
<E4LABEL>
BRANCH
<BRANCH>
PAGE
78 OF 132
SHEET
72 OF 101
5
State
3.3V S5 ENABLE
SMC_PM_G2_ENABLE
PM_SLP_S4_L
PM_SLP_S3_L
Run (S0)
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
SMC_PM_G2_EN
100
73 66
OUT
3.3V,5V S3 ENABLE
73 72 46 45 43 31 18
(PM_S4_STATE_L)
PM_SLP_S4_L
IN
R7911
5%
1/16W
MF-LF
402
73 66
P5VS3_EN
P5VS3_EN
OUT
66 73
DDRREG_EN
OUT
67 73
MAKE_BASE=TRUE
C7940 1
10%
10V
CERM
402
18 31 43 45 46 72 73
R7912
5.1K
5%
1/16W
MF-LF
402
PP3V42_G3H
0.068UF
2
PM_SLP_S4_L OUT
MAKE_BASE=TRUE
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
NO STUFF
66 73
C7902
100K
5%
1/16W
MF-LF
402
S5 rail PWRGD
P3V3S5_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
R79581
P3V3S5_EN
0.1uF
CRITICAL
VDD
5 SENSE
73 67
20%
10V
CERM 2
402
PP3V3_S5
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
IN
R7902
66 45
R7940
5%
1/16W
MF-LF
2 402
C7910
0.47UF
2
RSMRST_PWRGD
U7940 RESET*
NO STUFF
100K
DDRREG_EN
MAKE_BASE=TRUE
C7912
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
45
TPS3808G33DBVRG4
S5_PGOOD_CT
SOT23-6
4 CT
MR* 3
(IPU)
GND
C7941 1
0.001UF
20%
50V
CERM 2
402
Other S0 RAILS
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
PP3V3_S0
S0 ENABLE
(PM_SLP_S3_L)
R7978
85 73 45 31 18 6
IN
100
73 72 49
5%
1/16W
MF-LF
402
PM_SLP_S4_L
IN
R7979 1
18 31 43 45 46 72 73
R7933
5%
1/16W
MF-LF
402
20K
5%
1/16W
MF-LF
402
PM_SLP_S3_L_R
OUT
49 72 73
PM_SLP_S3_L_R
OUT
49 72 73
PM_SLP_S3_L_R
OUT
49 72 73
R7986
5.1K
73 66
46
6
23
53
P1V8S0_EN
OUT
PP3V42_G3H
73 72
73 70
CPUVTTS0_EN
NO STUFF
2
D 3
C7985
1UF
0.47UF
65
OUT
C7981
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
5%
1/16W
MF-LF
402
P5V3V3_PGOOD
5%
1/16W
MF-LF
402
67
IN
DDRREG_PGOOD
69
IN
GFXIMVP_PGOOD
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R7988
0
PP3V3_S0
R7994
CRITICAL
NOTE: S3 term is guaranteed by source of R7920 & Q7920, MUST BE S3 RAIL.
NTR4101P
EXT GPU PWRGD Pullup
C7989
0.1UF
2
2
20%
10V
CERM
402
10K
R7991
5%
1/16W
MF-LF
402
PM_ALL_GPU_PGOOD 1
87 86 82 73 8
OUT
2
1
ALL_GFX_PGOOD_R
SOT665
U7980Y
ALL_SYS_PWRGD OUT
25 27 45 87
5%
1/16W
MF-LF
402
26
Q7995
SSM3K15FV
5 TC7SZ08AFEAPE
NO STUFF
R7999
CK505_27MHZ_EN_L
3.3V ENET FET
1
1
0
5%
1/16W
MF-LF
402
S0_PWR_PGOOD
(Need to confirm if SMC can provide 1 pin for control)
"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")
85 99
6 7 17 18 19 20 21 23 27 31
35 57 66 71 72 73 83
PP3V3_S5
NO STUFF
27MHZ OE EN Generation
ENET Enable Generation
PM_ALL_GFX_PGOOD
HIGH
PM_ALL_GPU_PGOOD
R7997
1
R7998
70 73
IN
10%
6.3V
CERM-X5R
402
S 2
VFRQ_EN_GATE
66
IG
EG
5%
1/16W
MF-LF
402
0
G
OUT
C7986
R7935
SOD-VESM-HF
P1V8S0_PGOOD
0.47UF
10%
2 6.3V
CERM
402
10%
6.3V
CERM-X5R
402
72 73
IN
Q7931
OUT
71
NO STUFF
CPUVTTS0_EN
CHGR VFRQ Generation
5%
1/16W
MF-LF
402
P1V2S0_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R7931
CHGR_VFRQ
SSM3K15FV
P1V2S0_EN
71 73
5%
1/16W
MF-LF
402
R7996
P1V8S0_EN
73 71
S0PGOOD_PWROK
PLACE_NEAR=U1800.P12:5mm
10K
R7995
73
MAKE_BASE=TRUE
5%49214817477
45 43
1/16W
65 64
MF-LF
402
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 PLACE_NEAR=U7720.5:6mm
R7932
0
0
5%
1/16W
MF-LF
402
10K
R7985
33K
5%
1/16W
MF-LF
402 2
VFRQ_SLPS4 VFRQ_SLPS3
R7981
100K
R7992 1
PM_SLP_S3_L_R
MAKE_BASE=TRUE
PM_SLP_S3_L
D 3
SOD-VESM-HF
Q7922
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
SOT-23-HF
R7920
R7921
10K
OUT
5%
1/16W
MF-LF
402 2
R7922
100K 2
1
PM_ENET_EN
Q7921
P3V3ENET_SS
IN
87 86 82 73 8
IN
0.01UF
87 86 82 73 8
IN
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PM_ALL_GPU_PGOOD
PM_ALL_GPU_PGOOD
PM_ALL_GPU_PGOOD
PM_ALL_GPU_PGOOD
Q7921
IN
PM_SLP_S3_L
Q7920
2N7002DW-X-G
SOT-363
PM_WLAN_EN_L
IN
WOL_EN
S
4
OUT
33
AP_PWR_EN
IN
20 33
87 86 73
SOT-363
Q7925
3 V2MON
MR*
5 V3MON CRITICAL
6 V4MON
RST*
PP1V5_S3RS0
PP1V05_S0
GND
GT216 GPU requires rails to come

up in the following order:
1) 1.05V 2) GPU 3V3 3) GPU Vcore 4) GDDR3 1V8
V2MON THRESHOLD IS 3.0V

NC
S0PGOOD_PWROK
73
THRM_PAD
87 86 73 72
EG_RAIL2_EN
EG_RAIL1_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL3_EN
EG_RAIL4_EN
SYNC_MASTER=K17_REF
72 73 87
PAGE TITLE
Power Control
73 82 87
DRAWING NUMBER
EG_RAIL4_EN
Apple Inc.
72 73 86 87

SIZE
<SCH_NUM> D
REVISION
73 86 87
MAKE_BASE=TRUE
SOT-363
(PM_SLP_S3_L)
EG_RAIL1_EN
MAKE_BASE=TRUE
2N7002DW-X-G
PP3V3_S0
GPU Rail Sequencing
MAKE_BASE=TRUE
(AC_EN_L)
3
2N7002DW-X-G
SMC_ADAPTER_EN
U7971
MAKE_BASE=TRUE
87 82 73
IN
Q7925
46 45 18
20%
10V
CERM
402
2N7002DW-X-G
87 73 72
AC_EN_L
Q7920
0.1uF
SOT-363
5
C7971
VDDA
SOT-363
20
8 73 82 86 87
86 70 40 26 25 24 23
21 20 18 17 15 13 12 10 7 6
2N7002DW-X-G
85 73 45 31 18 6
OUT
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
RAIL_MON
ISL88042IRTJJZ
TDFN
WLAN Enable Generation
PP3V3_S0
VDD
MAKE_BASE=TRUE
PM_ENET_EN_L
87 86 82 73 8
10%
16V
CERM
402
SOT-363
10%
10V
CERM 2
402
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
100K
C7922
2
S 2
5%
1/16W
MF-LF
402 2
2N7002DW-X-G
0.22UF
6 7 27 37
10%
16V
2 X5R
402
5%
1/16W
MF-LF
402
C7920 1
C7921
0.033UF
10K
5%
1/16W
MF-LF
402 2
71 8
R7990 1
PP3V3_ENET
36 35 34 33 32 31 20 17 8 7 6
101 87 72 55 54 53 50 48
PP3V3_S3
<E4LABEL>
BRANCH
<BRANCH>
PAGE
79 OF 132
SHEET
73 OF 101
OMIT
Page Notes
U8000
NV-GT216

- =PP1V2_GPU_PEX_PLLXVDD
- =PP1V2_GPU_PEX_IOVDDQ
91 9 8
IN
PEG_R2D_C_P<0>
- =PP1V2_GPU_PEX_IOVDD
91 8
IN
PEG_R2D_C_N<0>
(NONE)
91 9 8
IN
(NONE)
91 8
D
PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
86 81 79 76 74 7 6
86 81 79 76 74 7 6
86 81 79 76 74 7 6
1UF
NO_TEST=TRUE
NV-GT216
H32
M7
P6
A5
U7
V6
AB7
AD6
AF6
AG6
AJ5
AK15
AL7
E7
A2
A7
B7
C5
C7
D5
D6
D7
E5
F4
G5
J18
J19
J25
J26
AA4
AB4
AC5
Y4
AG20
D35
P7
E35
R7
A4
C8000
20%
2 6.3V
CERM-X5R
805
BGA
(2 OF 9)
PEX_IOVDD1
PEX_IOVDD2
PEX_IOVDD3
PEX_IOVDD4
PEX_IOVDD5
C8003
1UF
10%
2 6.3V
CERM
402
AK16
AK17
AK21
AK24
AK27
C8004
0.1UF
20%
2 10V
CERM
402
IN
PEG_R2D_C_P<3>
C8026
0.1uF
91 9 8
IN
IN
IN
IN
IN
IN
PEG_R2D_C_N<3>
PEG_R2D_C_P<4>
PEG_R2D_C_N<4>
PEG_R2D_C_P<5>
PEG_R2D_C_N<5>
PEG_R2D_C_P<6>
NC
VDD_SENSE PEX_PLLVDD
GND_SENSE
BUFRST*
C8008
1UF
10%
2 6.3V
CERM
402
4.7UF
20%
2 6.3V
CERM
603
C8009
1UF
C8006
22UF
C8010
20%
2 6.3V
X5R
603
0.1UF
PP1V1_GPU_PEX_PLLVDD_F
10%
6.3V
2 CERM
402
GPU_VDD_SENSE 82
GPU_GND_SENSE 82
0.1uF
0.1uF
PEG_R2D_C_P<7>
C8034
0.1uF
IN
PEG_R2D_C_N<7>
C8035
0.1uF
IN
PEG_R2D_C_P<8>
C8036
0.1uF
91 9 8
IN
PEG_R2D_C_N<8>
C8037
0.1uF
91 8
IN
PEG_R2D_C_P<9>
C8016 C8015 1
4.7UF
20%
2 6.3V
CERM
603
0.1uF
PEG_R2D_C_N<9>
C8039
0.1uF
IN
IN
PEG_R2D_C_P<10>
C8040
0.1uF
91 9 8
IN
PEG_R2D_C_N<10>
C8041
0.1uF
91 8
IN
PEG_R2D_C_P<11>
C8042
0.1uF
91 9 8
91 9 8
C8038
91 8
91 8
IN
IN
IN
PEG_R2D_C_N<11>
PEG_R2D_C_P<12>
PEG_R2D_C_N<12>
IN
91 8
IN
PEG_R2D_C_P<13>
PEG_R2D_C_N<13>
C8043
C8044
C8045
C8046
C8047
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
4.7UF
20%
6.3V 2
CERM
603
AG14
AD19
IN
0603
C8017
1UF
AD20
0.1uF
91 9 8
100NH-700MA-0.14OHM
120 mA: GT216 A01 DG v3 01/09
GND_SENSE
91 8
VDD_SENSE
C8032
0.1uF
0.1uF
L8015
C8031
C8033
91 9 8
VOLTAGE=1.1V
C8030
0.1uF
PEG_R2D_C_N<6>
C8011
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C8029
IN
C8018
10UF
20%
2 6.3V
CERM-X5R
805
0.1UF
10%
2 6.3V
CERM
402
C8028
0.1uF
0.1UF
20%
2 10V
CERM
402
C8007
C8027
91 8
91 9 8
AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16
0.1uF
0.1uF
1500mA
PEX_IOVDDQ1
PEX_IOVDDQ2
PEX_IOVDDQ3
PEX_IOVDDQ4
PEX_IOVDDQ5
PEX_IOVDDQ6
PEX_IOVDDQ7
PEX_IOVDDQ8
PEX_IOVDDQ9
PEX_IOVDDQ10
PEX_IOVDDQ11
PEX_IOVDDQ12
PEX_IOVDDQ13
PEX_IOVDDQ14
PEX_IOVDDQ15
PEX_IOVDDQ16
PEX_IOVDDQ17
PEX_IOVDDQ18
PEX_IOVDDQ19
PEX_IOVDDQ20
PEX_IOVDDQ21
PEX_IOVDDQ22
PEX_IOVDDQ23
PEX_IOVDDQ24
PEX_IOVDDQ25
C8025
91 8
C8005
0.1uF
PEG_R2D_C_N<2>
22UF
20%
2 6.3V
CERM
603
IN
91 9 8
OMIT
U8000
4.7UF
10%
2 6.3V
CERM
402
NC_GPU_DFM
C8001
0.1uF
91 8
91 8
C8024
91 9 8
C8002
C8023
0.1uF
PEG_R2D_C_P<2>
91 8
C8022
IN
91 9 8
250mA
PEG_R2D_C_N<1>
C8021
BGA
(1 OF 9)
0.1uF
91 9 8
91 8
PEX 1.1V Current = 2A
IN
PEG_R2D_C_P<1>
C8020
91 9 8
IN
PEG_R2D_C_P<14>
C8048
0.1uF
0.1uF
0.1uF
91 8
IN
PEG_R2D_C_N<14>
C8049
91 9 8
IN
PEG_R2D_C_P<15>
C8050
91 8
IN
94 17
IN
94 17
IN
87 8
IN
PEG_R2D_C_N<15>
C8051
0.1uF
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<0>
PEG_R2D_N<0>
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<1>
PEG_R2D_N<1>
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<2>
PEG_R2D_N<2>
AR19
AR20
PEX_RX2
PEX_RX2*
PEX_TX2
PEX_TX2*
AL19
AK19
91
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<3>
PEG_R2D_N<3>
AP20
AN20
PEX_RX3
PEX_RX3*
PEX_TX3
PEX_TX3*
AL20
AM20
91
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<4>
PEG_R2D_N<4>
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<5>
PEG_R2D_N<5>
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<6>
PEG_R2D_N<6>
AP23
AN23
PEX_RX6
PEX_RX6*
PEX_TX6
PEX_TX6*
AL23
AM23
91
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<7>
PEG_R2D_N<7>
AN25
AP25
PEX_RX7
PEX_RX7*
PEX_TX7
PEX_TX7*
AM24
AM25
91
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<8>
PEG_R2D_N<8>
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<9>
PEG_R2D_N<9>
AP26
AN26
PEX_RX9
PEX_RX9*
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<10>
PEG_R2D_N<10>
AN28
AP28
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<11>
PEG_R2D_N<11>
AR28
AR29
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<12>
PEG_R2D_N<12>
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<13>
PEG_R2D_N<13>
R8020
BI
AR22
AR23
AR25
AR26
AP29
AN29
AN31
AP31
PEX_RX1
PEX_RX1*
PEX_TX1
PEX_TX1*
PEX_RX4
PEX_RX4*
PEX_TX4
PEX_TX4*
PEX_RX5
PEX_RX5*
PEX_TX5
PEX_TX5*
PEX_RX8
PEX_RX8*
PEX_TX8
PEX_TX8*
AL17
AM17
91
91
AM18
AM19
91
91
91
91
AM21
AM22
91
91
AL22
AK22
91
91
91
91
AL25
AK25
91
91
PEX_TX9
PEX_TX9*
AL26
AM26
91
PEX_RX10
PEX_RX10*
PEX_TX10
PEX_TX10*
AM27
AM28
91
PEX_RX11
PEX_RX11*
PEX_TX11
PEX_TX11*
AL28
AK28
91
PEX_RX12
PEX_RX12*
PEX_TX12
PEX_TX12*
PEX_RX13
PEX_RX13*
PEX_TX13
PEX_TX13*
91
91
91
AK29
AL29
91
91
AM29
AM30
91
91
AR31
AR32
PEX_RX14
PEX_RX14*
PEX_TX14
PEX_TX14*
AM31
AM32
91
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_R2D_P<15>
PEG_R2D_N<15>
AR34
AP34
PEX_RX15
PEX_RX15*
PEX_TX15
PEX_TX15*
AN32
AP32
91
91
91
PEG_D2R_C_P<0>
PEG_D2R_C_N<0>
PEG_D2R_C_P<1>
PEG_D2R_C_N<1>
PEG_D2R_C_P<2>
PEG_D2R_C_N<2>
PEG_D2R_C_P<3>
PEG_D2R_C_N<3>
PEG_D2R_C_P<4>
PEG_D2R_C_N<4>
PEG_D2R_C_P<5>
PEG_D2R_C_N<5>
PEG_D2R_C_P<6>
PEG_D2R_C_N<6>
PEG_D2R_C_P<7>
PEG_D2R_C_N<7>
PEG_D2R_C_P<8>
PEG_D2R_C_N<8>
PEG_D2R_C_P<9>
PEG_D2R_C_N<9>
PEG_D2R_C_P<10>
PEG_D2R_C_N<10>
PEG_D2R_C_P<11>
PEG_D2R_C_N<11>
PEG_D2R_C_P<12>
PEG_D2R_C_N<12>
PEG_D2R_C_P<13>
PEG_D2R_C_N<13>
PEG_D2R_C_P<14>
PEG_D2R_C_N<14>
PEG_D2R_C_P<15>
PEG_D2R_C_N<15>
PEX_REFCLK
PEX_REFCLK*
AM16
PEX_RST*
AR13
PEX_CLKREQ*
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT*
AJ17
AJ18
PEX_TERMP
AG21
PEX_SVDD_3V3
PEX_CLKREQ_L
PEX_TSTCLK_P
PEX_TSTCLK_N
PEX_TERMP_PD
PP3V3_S0GPU
C8013
10%
6.3V
2 X5R-CERM
603
R8021
84 82 81 80 79 72 7 6
10K
86 81 79 76 74 7 6
PP1V05_S0GPU
R8012
NO STUFF
0 2
1
R8013
C8058
0.1uF
C8059
0.1uF
C8060
0.1uF
C8061
0.1uF
C8062
0.1uF
C8063
0.1uF
C8064
0.1uF
C8065
0.1uF
C8066
0.1uF
C8067
0.1uF
C8068
0.1uF
C8069
0.1uF
C8070
0.1uF
C8071
0.1uF
C8072
0.1uF
C8073
0.1uF
C8074
0.1uF
C8075
0.1uF
C8076
0.1uF
C8077
0.1uF
C8078
0.1uF
C8079
0.1uF
C8080
0.1uF
C8081
0.1uF
C8082
0.1uF
C8083
0.1uF
C8084
0.1uF
C8085
0.1uF
C8086
0.1uF
1
1
1
1
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<0>
OUT
8 9 91
PEG_D2R_N<0>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<1>
OUT
8 9 91
PEG_D2R_N<1>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<2>
OUT
8 9 91
PEG_D2R_N<2>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<3>
OUT
8 9 91
PEG_D2R_N<3>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<4>
OUT
8 9 91
PEG_D2R_N<4>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<5>
OUT
8 9 91
PEG_D2R_N<5>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<6>
OUT
8 9 91
PEG_D2R_N<6>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<7>
OUT
8 9 91
PEG_D2R_N<7>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<8>
OUT
8 9 91
PEG_D2R_N<8>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<9>
OUT
8 9 91
PEG_D2R_N<9>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<10>
OUT
8 9 91
PEG_D2R_N<10>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<11>
OUT
8 9 91
PEG_D2R_N<11>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<12>
OUT
8 9 91
PEG_D2R_N<12>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<13>
OUT
8 9 91
PEG_D2R_N<13>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<14>
OUT
8 9 91
PEG_D2R_N<14>
OUT
8 91
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<15>
OUT
8 9 91
PEG_D2R_N<15>
OUT
8 91
200
1%
1/16W
MF-LF
402
R8050
2.49K2
C8012
0.1UF
10%
2 16V
X5R
402
SYNC_MASTER=K17_REF
PP3V3R1V1_GPU_PEX_SVDD
PAGE TITLE
NV GT216 PCI-E
DRAWING NUMBER
Apple Inc.
5%
1/16W
MF-LF
402
C8057
0.1uF
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
0.1uF
1%
1/16W
MF-LF
402
AG19
F7
4.7UF
OUT
0.1uF
C8056
R8060
AR16
AR17
NC_GPU_BUFRST_L
C8055
NO STUFF
5%
1/16W
MF-LF
402
87 8
AN22
AP22
PEX_TX0
PEX_TX0*
PEG_R2D_P<14>
PEG_R2D_N<14>
GPU_RESET_R_L
AN19
AP19
PEX_RX0
PEX_RX0*
2
91
10% 16V X5R 40291
2
10% 16V X5R 402
PEG_CLK100M_P
PEG_CLK100M_N
EG_RESET_L
AP17
AN17

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
80 OF 132
SHEET
74 OF 101
Page Notes
U8000
U8000
- =PPVCORE_GPU
NV-GT216
BGA
(8 OF 9)
NV-GT216
- =PP1V8_GPU_FBVDDQ
BGA
(9 OF 9)
82
7 6
49
(NONE)
PPVCORE_GPU
???A @ ???/???MHz Core/Mem Clk for VDD

(NONE)
C8100
1UF
C8103
0.022UF
10%
16V
2 CERM-X5R
402
C8113
C8109
C8110
10%
16V
2 X7R
402
C8115
10%
16V
2 X7R
402
C8111
0.015UF
10%
16V
2 X7R
402
0.01UF
10%
25V
2 X7R
402
C8106
0.047UF
0.015UF
10%
25V
2 X7R
402
10%
16V
2 X7R
402
0.01UF
C8118
C8105
0.047UF
C8114
0.0068UF
C8116
0.022UF
C8112
0.01UF
10%
25V
2 X7R
402
0.01UF
10%
25V
2 X7R
402
C8107
10%
16V
2 CERM-X5R
402
C8117
0.01UF
10%
25V
2 X7R
402
C8119
0.0047UF
10%
2 25V
CERM
402
78 77 76 56 50 8 7 6
10%
16V
2 CERM-X5R
402
10%
25V
2 X7R
402
C8104
0.022UF
0.01UF
0.22UF
10%
16V
2 X7R
402
C8108
C8102
10%
6.3V
2 CERM-X5R
402
0.047UF
10%
16V
2 X7R-CERM
402
10%
6.3V
2 CERM-X5R
402
0.1UF
C8101
0.22UF
10%
10V
2 X5R
402
10%
2 25V
CERM
402
Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF
???A @ ???MHz 1.8V GDDR3
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19
P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
OMIT
VDD
VDD
B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F5
F31
F34
J2
J5
J31
J34
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V2
V5
V9
V12
V14
V16
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
AD24
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
W20
C8150 1
4.7UF
20%
6.3V 2
CERM
603
OMIT
C8156 1 C8157 1 C8158 1 C8159 1 C8160 1

4.7UF
20%
6.3V
CERM 2
603
0.1UF
20%
10V
CERM 2
402
C8162 1 C8163
0.047UF
10%
16V
X7R 2
402
0.047UF
10%
16V
X7R 2
402
0.1UF
20%
10V
CERM 2
402
C8164
0.01UF
10%
25V
X7R 2
402
0.1UF
20%
10V
CERM 2
402
C8165
0.01UF
10%
25V
X7R 2
402
U8000
0.047UF
NV-GT216
10%
16V
X7R 2
402
BGA
(7 OF 9)
B18
J17
U27
AB27
AB29
AC27
AD27
AE27
AJ28
E21
G8
G9
G17
G18
G22
H29
J14
J15
J16
C8166 1
0.01UF
10%
25V
X7R 2
402
FBVDDQ
FBVDDQ
J20
J21
J22
J23
J24
J29
N27
P27
R27
T27
U29
V27
V29
V34
W27
Y27
AA27
AA29
AA31
OMIT
GND
GND
V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AP33
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
K9
AK14
SYNC_MASTER=K17_REF
PAGE TITLE
NV GT216 CORE/FB POWER

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
81 OF 132
SHEET
75 OF 101
Page Notes
- =PP1V2_GPU_FBPLLAVDD
- =PP1V8_GPU_FBIO
OMIT
U8000
NV-GT216
(NONE)
BGA
(4 OF 9)

(NONE)
OMIT
U8000
NV-GT216
BGA
(3 OF 9)
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
98 77
BI
FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<22>
FB_A_DQ<23>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>
FB_A_DQ<33>
FB_A_DQ<34>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<44>
FB_A_DQ<45>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<57>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<63>
L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35
NCP29
NCR29
NCL29
NCM29
AD29
NC
AE29
NC
AG29
NC
AH29
NC
FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
NC
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
V32
W31
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29
FB_A_LMA<4>
OUT
FB_A_RAS_L
OUT
FB_A_LMA<5>
OUT
FB_A_BA<1>
OUT
FB_A_UMA<2>
OUT
FB_A_UMA<4>
OUT
FB_A_UMA<3>
OUT
FB_A_UCKE
FB_A_UCS0_L
OUT
FB_A_MA<11>
OUT
FB_A_LCAS_L
OUT
FB_A_WE_L
OUT
FB_A_BA<0>
OUT
FB_A_UMA<5>
OUT
FB_A_MA<12>
OUT
FB_A_DRAM_RST
FB_A_MA<7>
OUT
FB_A_MA<10>
OUT
FB_A_LCKE
FB_A_MA<0>
OUT
FB_A_MA<9>
OUT
FB_A_MA<6>
OUT
FB_A_LMA<2>
OUT
FB_A_MA<8>
OUT
FB_A_LMA<3>
OUT
FB_A_MA<1>
OUT
NC_FBA_MA<13> OUT
FB_A_BA<2>
OUT
NC_FB_A_UCS1_L 80
FB_A_LCS0_L
77 98
NC_FB_A_LCS1_L 80
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
T32
T31
AC31
AC30
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
P32
H34
J30
P30
AF32
AL32
AL34
AF35
L35
G35
H31
N32
AD32
AJ31
AJ35
AC34
OUT
BI
98 78
BI
77 98
98 78
BI
77 98
98 78
BI
77 98
98 78
BI
98 78
BI
98 78
BI
98 78
BI
77 98
OUT
77 98
77
R8203
77 98
10K
77 98
5%
1/16W
MF-LF
2 402
77 98
77 98
77 98
77 98
OUT
77 98
77 98
R8200
77 98
OUT
10K
77 98
5%
1/16W
MF-LF
2 402
77 98
77 98
77 98
77 98
77 98
R8201
10K
5%
1/16W
MF-LF
2 402
77 98
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
77 98
98 78
BI
80
98 78
BI
77 98
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
77 98
BI
77 98
BI
77 98
BI
77 98
BI
77 98
BI
77 98
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
77 98
77 98
77 98
IN
77 98
IN
77 98
IN
77 98
86 81 79 74 7 6
PP1V05_S0GPU
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
77 98
IN
77 98
IN
77 98
IN
77 98
CRITICAL
L8200
300-OHM-0.5A
1
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
L34
H35
J32
N31
AE31
AJ32
AJ34
AC33
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
FB_DLLAVDD
FB_PLLAVDD
AG27
AF27
PP1V1_GPU_FBPLLAVDD_F
FBA_DEBUG
T30
FB_A_UCAS_L
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
K27
L27
M27
FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
OUT
77 98
OUT
77 98
77 98
OUT
77 98
OUT
77 98
OUT
77 98
OUT
77 98
OUT
77 98
2
0603-1
C8202 1 C8200
1UF
10%
2 6.3V
CERM
402
4.7UF
C8201
4.7UF
10%
2 6.3V
X5R-CERM
603
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
98 78
BI
FB_B_DQ<0>
FB_B_DQ<1>
FB_B_DQ<2>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<10>
FB_B_DQ<11>
FB_B_DQ<12>
FB_B_DQ<13>
FB_B_DQ<14>
FB_B_DQ<15>
FB_B_DQ<16>
FB_B_DQ<17>
FB_B_DQ<18>
FB_B_DQ<19>
FB_B_DQ<20>
FB_B_DQ<21>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<28>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<31>
FB_B_DQ<32>
FB_B_DQ<33>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<36>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<40>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<43>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<47>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<51>
FB_B_DQ<52>
FB_B_DQ<53>
FB_B_DQ<54>
FB_B_DQ<55>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_DQ<58>
FB_B_DQ<59>
FB_B_DQ<60>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<63>
10%
2 6.3V
X5R-CERM
603
78 77 76 75 56 50 8 7 6
R82901
VOLTAGE=1.1V
B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25
NCG11
NCG12
NCG14
NCG15
NCG24
NCG25
NCG27
NCG28
56.2
1%
1/16W
MF-LF
402 2
77 98
FBC_D00
FBC_D01
FBC_D02
FBC_D03
FBC_D04
FBC_D05
FBC_D06
FBC_D07
FBC_D08
FBC_D09
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FB_B_LMA<4>
OUT
FB_B_RAS_L
OUT
FB_B_LMA<5>
OUT
FB_B_BA<1>
OUT
FB_B_UMA<2>
OUT
FB_B_UMA<4>
OUT
FB_B_UMA<3>
OUT
FB_B_UCKE
FB_B_UCS0_L
OUT
FB_B_MA<11>
OUT
FB_B_LCAS_L
OUT
FB_B_WE_L
OUT
FB_B_BA<0>
OUT
FB_B_UMA<5>
OUT
FB_B_MA<12>
OUT
FB_B_DRAM_RST
FB_B_MA<7>
OUT
FB_B_MA<10>
OUT
FB_B_LCKE
FB_B_MA<0>
OUT
FB_B_MA<9>
OUT
FB_B_MA<6>
OUT
FB_B_LMA<2>
OUT
FB_B_MA<8>
OUT
FB_B_LMA<3>
OUT
FB_B_MA<1>
OUT
NC_FBB_MA<13> OUT
FB_B_BA<2>
OUT
NC_FB_B_UCS1_L 80
FB_B_LCS0_L
78 98
NC_FB_B_LCS1_L 80
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
C17
B19
D18
F21
A23
D21
B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
B20
A20
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
E17
D17
D23
E23
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
A16
D10
F11
D15
D27
D34
A34
D28
FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
B14
B10
D9
E14
F26
D31
A31
A26
FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<4>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
C14
A10
E10
D14
E26
D32
A32
B26
FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>
78 98
78 98
78 98
78 98
78 98
78 98
78 98
OUT
R8252
78 98
10K
78 98
5%
1/16W
MF-LF
2 402
78 98
78 98
78 98
78 98
OUT
78 98
78 98
R8250
78 98
OUT
10K
78 98
5%
1/16W
MF-LF
2 402
78 98
R8251
78 98
10K
78 98
5%
1/16W
MF-LF
2 402
78 98
78 98
78 98
78 98
80
78 98
OUT
78 98
OUT
78 98
OUT
78 98
OUT
78 98
BI
78 98
BI
78 98
BI
78 98
BI
78 98
BI
78 98
BI
78 98
BI
78 98
BI
78 98
78
78 98
IN
78 98
IN
78 98
IN
78 98
IN
78 98
IN
78 98
IN
78 98
IN
78 98
IN
78 98
OUT
78 98
OUT
78 98
OUT
78 98
OUT
78 98
OUT
78 98
OUT
OUT
78 98
50 8 7 6
78 77 76 75 56
78 98
OUT
78 98
B
R82951
1.07K
FBC_DEBUG
G19
FB_VREF
J27
FB_B_UCAS_L
1%
1/16W
MF-LF
402 2
OUT
78 98
GPU_FB_VREF
NC
R82961
2.49K
1%
1/16W
MF-LF
402 2
R82921
40.2
1%
1/16W
MF-LF
402 2
BI
98 78
77 98
OUT
BI
98 78
77 98
BI
OUT
98 78
77 98
77 98
IN
BI
BI
OUT
IN
BI
98 78
BI
OUT
FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>
BI
98 78
98 78
77 98
BI
98 78
98 78
77 98
BI
BI
77 98
OUT
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>
98 78
R82911
31.6
1%
1/16W
MF-LF
402 2
SYNC_MASTER=K17_REF
PAGE TITLE
NV GT216 FRAME BUFFER I/F

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
82 OF 132
SHEET
76 OF 101
OMIT
CRITICAL
78 77 76 75 56 50 8 7 6
10UF
C8401
0.1uF
20%
6.3V 2
X5R
603
C8402
0.1uF
10%
2 16V
X5R
402
C8403
0.1uF
10%
2 16V
X5R
402
C8404
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
K1 VDDA0
K12 VDDA1
D
1
C8410
C8415
0.1uF
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
U8400.J1
U8400.J12
Connect to designated pin, then GND
76 75 56 50 8 7 6
78 77
C8420 1
10UF
77 32 8
C8421
0.1uF
20%
6.3V 2
X5R
603
10%
2 16V
X5R
402
C8422
0.1uF
10%
2 16V
X5R
402
C8423
0.1uF
10%
2 16V
X5R
402
C8424
0.1uF
10%
2 16V
X5R
402
C8425
0.1uF
C8426
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
GPU_FB_A_VREF_DIV
1
R8430
R8433
549
549
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
FB_A0_VREF
R84311 R84321
1.33K
931
1%
1/16W
MF-LF
402 2
C8431 R84341
0.01UF
R84351
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
1.33K
10%
2 16V
CERM
402
1%
1/16W
MF-LF
402 2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VSS3
VSS4
VSS5
VSS6
VSS7
C8450 1
10UF
G12
L1
L12
V3
V10
C8451
20%
6.3V 2
X5R
603
C8452
0.1uF
10%
2 16V
X5R
402
C8453
10%
2 16V
X5R
402
C8454
0.1uF
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
C8460
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
U8400.J1
U8400.J12
78 77 76 75 56 50 8 7 6
C8470 1
10UF
77 32 8
C8471
0.1uF
20%
6.3V 2
X5R
603
10%
2 16V
X5R
402
C8472
0.1uF
C8473
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C8474
0.1uF
10%
2 16V
X5R
402
C8475
0.1uF
C8476
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
GPU_FB_A_VREF_DIV
R84801
R84831
549
549
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
FB_A1_VREF
R84811 R84821
1.33K
10%
2 16V
CERM
402
931
1%
1/16W
MF-LF
402 2
C8481 R84841
0.01uF
R84851
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
1.33K
10%
2 16V
CERM
402
1%
1/16W
MF-LF
402 2
98 77 76
IN
98 77 76
IN
98 76
IN
98 76
IN
98 76
IN
98 76
IN
98 77 76
IN
98 77 76
IN
98 77 76
IN
98 77 76
IN
98 77 76
IN
98 77 76
IN
98 76
IN
98 77 76
IN
98 76
IN
98 76
IN
98 76
IN
98 77 76
IN
98 76
IN
98 77 76
IN
R8445
121
1%
1/16W
MF-LF
2 402
98 76
OUT
98 76
OUT
98 76
98 76
98 76
IN
OUT
OUT
IN
98 76
IN
98 76
IN
98 76
IN
98 77 76
IN
98 77 76
IN
98 77 76
IN
5 G
S 1
1K
5%
1/16W
MF-LF
402 2
S 4
J11
J10
F4
H4
F9
H10
A4
A9
V4
V9
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_RDQS<0>
D3
D10
P10
P3
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_WDQS<0>
D2
D11
P11
P2
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>
R8494
121
1%
1/16W
MF-LF
402 2
U8400
DM0
BGA
(1 OF 2)
DM1
A2
A3
A6
A7
A8/AP
A9
A10
A11
CKE
A12/CS1*
CK
CK*
CS0*
WE*
CAS*
RAS*
DM2
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
ZQ
DQ15
DQ16
MF
DQ17
SEN
DQ18
DQ19
RESET
RDQS0
DQ20
DQ21
RDQS1
RDQS2
DQ22
RDQS3
DQ23
DQ24
WDQS0
WDQS1
DQ25
WDQS2
DQ26
DQ27
WDQS3
DQ28
DQ29
DQ30
DQ31
E3
E10
N10
N3
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQM_L<0>
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
FB_A_DQ<11>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<13>
FB_A_DQ<10>
FB_A_DQ<12>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<19>
FB_A_DQ<22>
FB_A_DQ<18>
FB_A_DQ<20>
FB_A_DQ<23>
FB_A_DQ<21>
FB_A_DQ<26>
FB_A_DQ<24>
FB_A_DQ<28>
FB_A_DQ<25>
FB_A_DQ<29>
FB_A_DQ<27>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<0>
FB_A_DQ<4>
FB_A_DQ<1>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
IN
76 98
98 77 76
IN
IN
76 98
98 77 76
IN
IN
76 98
98 76
IN
IN
76 98
98 76
IN
98 76
IN
BI
76 98
BI
76 98
BI
76 98
BI
98 76
IN
98 77 76
IN
98 77 76
IN
98 77 76
IN
98 77 76
IN
98 77 76
IN
76 98
BI
76 98
BI
76 98
BI
76 98
98 77 76
IN
98 76
IN
98 77 76
IN
BI
76 98
BI
76 98
BI
76 98
BI
76 98
98 76
IN
BI
76 98
98 76
IN
BI
76 98
76
IN
BI
76 98
98 77 76
IN
BI
76 98
98 76
IN
BI
76 98
98 77 76
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
IN
98 77 76
IN
98 76
OUT
98 76
OUT
98 76
76 98
OUT
OUT
BI
76 98
98 76
BI
76 98
98 76
IN
BI
76 98
98 76
IN
BI
76 98
98 76
IN
76 98
BI
76 98
BI
76 98
SSM6N15FEAPE
121
10%
16V
CERM 2
402
1%
1/16W
MF-LF
402 2
VRAM4
VRAM4
R8495
121
1%
1/16W
MF-LF
2 402
98 77 76
IN
IN
98 77 76
IN
98 77 76
IN
SOT563
0.01UF
243
1%
1/16W
MF-LF
402 2
VSSA0 J1
VSSA1 J12
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
79 78 77
80
D 3
Q8450
SSM6N15FEAPE
SOT563
FB_VREF_UNTERM
2 G
5 G
S 1
S 4
R8497
243
OMIT
CRITICAL
1%
1/16W
MF-LF
2 402
FB_A_MA<0>
FB_A_MA<1>
FB_A_UMA<2>
FB_A_UMA<3>
FB_A_UMA<4>
FB_A_UMA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
FB_A_UCKE
FB_A_MA<12>
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
H9
J3
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_A_UCS0_L
FB_A_WE_L
FB_A_UCAS_L
FB_A_RAS_L
J11
J10
F4
H4
F9
H10
A4
A9
V4
V9
FB_A_DRAM_RST
FB_A_RDQS<6>
FB_A_RDQS<7>
FB_A_RDQS<5>
FB_A_RDQS<4>
D3
D10
P10
P3
FB_A_WDQS<6>
FB_A_WDQS<7>
FB_A_WDQS<5>
FB_A_WDQS<4>
D2
D11
P11
P2
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>
A0
U8450
DM0
A1
BGA
(1 OF 2)
DM1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
CKE
A12/CS1*
CK*
CS0*
WE*
CAS*
RAS*
NC
DM2
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
CK
DQ11
DQ12
DQ13
DQ14
ZQ
DQ15
DQ16
MF
DQ17
SEN
DQ18
DQ19
RESET
RDQS0
DQ20
DQ21
RDQS1
RDQS2
DQ22
RDQS3
DQ23
DQ24
WDQS0
WDQS1
DQ25
WDQS2
DQ26
DQ27
WDQS3
DQ28
G9 BA0
G4 BA1
H3 BA2
J2 RFU
IN
D 6
FB_A1_ZQ
FB_A1_MF
FB_A1_SEN
98 76
BI
Q8450
C8496 1
R8496
1%
1/16W
MF-LF
2 402
A1
A4
A5
VRAM4
VOLTAGE=0.9V
1
121
A0
G9 BA0
G4 BA1
H3 BA2
NC
VRAM4
1
R8492
OMIT
CRITICAL
1%
1/16W
MF-LF
2 402
FB_A_DRAM_RST
R8490
SOT563
FB_VREF_UNTERM
2 G
243
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_LCS0_L
FB_A_WE_L
FB_A_LCAS_L
FB_A_RAS_L
1%
1/16W
MF-LF
402 2
VRAM4
1
R8493
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
H9
J3
243
D 3
R8447
FB_A_MA<0>
FB_A_MA<1>
FB_A_LMA<2>
FB_A_LMA<3>
FB_A_LMA<4>
FB_A_LMA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
FB_A_LCKE
FB_A_MA<12>
R84481
IN
Q8400
SSM6N15FEAPE
FB_A0_ZQ
FB_A0_MF
FB_A0_SEN
98 77 76
79 78 77
80
D 6
K4J10324QD-HC11
1%
1/16W
MF-LF
2 402
FB_A3_VREF_UNTERM_L
FB_A1_VREF_UNTERM_L
MFHIGH
121
VRAM4
VSS6
VSS7
(NONE)
10%
2 16V
CERM
402
32MX32-900MHZ-MFH
R8443
10%
16V
CERM 2
402
VSS5
C8482
MFHIGH
0.01UF
VSS3
VSS4
- =PP1V8_S0_FB_VREFA
G12
L1
L12
V3
V10
0.01uF
931
DQ29
DQ30
MFHIGH
VRAM4
243
1%
1/16W
MF-LF
402 2
SOT563
K4J10324QD-HC11
121
1%
1/16W
MF-LF
402 2
C8446 1
32MX32-900MHZ-MFH
121
1%
1/16W
MF-LF
402 2
R8446
MFHIGH
1K
5%
1/16W
MF-LF
402 2
R8444
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
- =PP1V8_S0_FB_VDD
VSS1 A10
VSS2 G1
BGA
(2 OF 2)
FB_A_CLK1_TERM
Q8400
SSM6N15FEAPE
MFHIGH
R8442
MFHIGH
R8440
VSS0 A3
U8450
H1 VREF0
H12 VREF1
FB_A3_VREF
C8432
VOLTAGE=0.9V
VRAM4
1
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
C8465
0.1uF
FB_A_CLK0_TERM
VRAM4
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
K1 VDDA0
K12 VDDA1
FB_A2_VREF_UNTERM_L
FB_A0_VREF_UNTERM_L
A2
A11
F1
F12
M1
M12
V2
V11
VSSA0 J1
VSSA1 J12
0.01UF
931
0.1uF
H1 VREF0
H12 VREF1
FB_A2_VREF
VSS1 A10
VSS2 G1
BGA
(2 OF 2)
Page Notes
CRITICAL
VSS0 A3
U8400
K4J10324QD-HC11
C8400 1
A2
A11
F1
F12
M1
M12
V2
V11
32MX32-900MHZ-MFH
76 75 56 50 8 7 6
78 77
OMIT
K4J10324QD-HC11
32MX32-900MHZ-MFH
DQ31
E3
E10
N10
N3
FB_A_DQM_L<6>
FB_A_DQM_L<7>
FB_A_DQM_L<5>
FB_A_DQM_L<4>
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
FB_A_DQ<48>
FB_A_DQ<51>
FB_A_DQ<55>
FB_A_DQ<54>
FB_A_DQ<52>
FB_A_DQ<50>
FB_A_DQ<53>
FB_A_DQ<49>
FB_A_DQ<57>
FB_A_DQ<62>
FB_A_DQ<63>
FB_A_DQ<60>
FB_A_DQ<58>
FB_A_DQ<56>
FB_A_DQ<59>
FB_A_DQ<61>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<44>
FB_A_DQ<41>
FB_A_DQ<45>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<40>
FB_A_DQ<35>
FB_A_DQ<34>
FB_A_DQ<33>
FB_A_DQ<32>
FB_A_DQ<39>
FB_A_DQ<36>
FB_A_DQ<38>
FB_A_DQ<37>
IN
76 98
IN
76 98
IN
76 98
IN
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76
98
BI
SYNC_MASTER=K17_REF
PAGE TITLE
GDDR3 Frame Buffer A (Top)
BI
BI
DRAWING NUMBER
76
98
Apple Inc.
J2 RFU
R
<E4LABEL>
R8449
100
R8498
5%
1/16W
MF-LF
2 402
243
1%
1/16W
MF-LF
402 2
R8499

100
5%
1/16W
MF-LF
2 402
SIZE
<SCH_NUM> D
REVISION
BRANCH
<BRANCH>
PAGE
84 OF 132
SHEET
77 OF 101
OMIT
CRITICAL
78 77 76 75 56 50 8 7 6
10UF
C8501
0.1uF
20%
6.3V 2
X5R
603
C8502
0.1uF
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C8503
C8504
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
K1 VDDA0
K12 VDDA1
D
1
C8510
0.1uF
C8515
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
U8500.J1
U8500.J12
76 75 56 50 8 7 6
78 77
C8520 1
10UF
78 32 8
C8521
0.1uF
10%
2 16V
X5R
402
20%
6.3V 2
X5R
603
C8522
0.1uF
10%
2 16V
X5R
402
C8523
0.1uF
10%
2 16V
X5R
402
C8524
0.1uF
10%
2 16V
X5R
402
C8525
0.1uF
10%
2 16V
X5R
402
C8526
0.1uF
10%
2 16V
X5R
402
GPU_FB_B_VREF_DIV
1
R8530
R85331
549
1%
1/16W
MF-LF
402 2
549
1%
1/16W
MF-LF
402 2
FB_B0_VREF
R85311 R85321
1.33K
931
1%
1/16W
MF-LF
402 2
C8531 R85341
0.01uF
R85351
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
1.33K
10%
2 16V
CERM
402
1%
1/16W
MF-LF
402 2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VSS3
VSS4
VSS5
VSS6
VSS7
C8550 1
10UF
G12
L1
L12
V3
V10
C8551
20%
6.3V 2
X5R
603
C8552
0.1uF
10%
2 16V
X5R
402
C8553
10%
2 16V
X5R
402
C8554
0.1uF
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
C8560
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
U8500.J1
U8500.J12
78 77 76 75 56 50 8 7 6
C8570 1
10UF
78 32 8
C8571
0.1uF
10%
2 16V
X5R
402
20%
6.3V 2
X5R
603
C8572
0.1uF
10%
2 16V
X5R
402
C8573
0.1uF
10%
2 16V
X5R
402
C8574
0.1uF
10%
2 16V
X5R
402
C8575
0.1uF
C8576
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
GPU_FB_B_VREF_DIV
R85801
R85831
549
1%
1/16W
MF-LF
402 2
549
1%
1/16W
MF-LF
402 2
FB_B1_VREF
C8532
R85811 R85821
1.33K
931
1%
1/16W
MF-LF
402 2
C8581 R85841
0.01uF
R85851
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
1.33K
10%
2 16V
CERM
402
1%
1/16W
MF-LF
402 2
IN
98 76
IN
98 76
IN
98 76
IN
98 78 76
IN
98 78 76
IN
98 78 76
IN
98 78 76
IN
98 78 76
IN
98 78 76
IN
98 76
IN
98 78 76
IN
98 76
IN
98 76
IN
98 76
IN
98 78 76
IN
98 76
IN
98 78 76
IN
121
1%
1/16W
MF-LF
2 402
98 76
OUT
98 76
OUT
98 76
98 76
98 76
IN
OUT
OUT
IN
98 76
IN
98 76
IN
98 76
IN
98 78 76
IN
98 78 76
IN
98 78 76
IN
5 G
S 1
1K
5%
1/16W
MF-LF
402 2
S 4
J11
J10
F4
H4
F9
H10
A4
A9
V4
V9
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<0>
D3
D10
P10
P3
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<0>
D2
D11
P11
P2
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>
U8500
DM0
A1
BGA
(1 OF 2)
DM1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
CKE
A12/CS1*
CK
CK*
CS0*
WE*
CAS*
RAS*
DM2
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
ZQ
DQ15
DQ16
MF
DQ17
SEN
DQ18
DQ19
RESET
RDQS0
DQ20
DQ21
RDQS1
RDQS2
DQ22
RDQS3
DQ23
DQ24
WDQS0
WDQS1
VRAM4
VSSA0 J1
VSSA1 J12
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
121
1%
1/16W
MF-LF
402 2
DQ25
WDQS2
DQ26
DQ27
WDQS3
DQ28
DQ29
DQ30
DQ31
E3
E10
N10
N3
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<0>
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
FB_B_DQ<15>
FB_B_DQ<9>
FB_B_DQ<14>
FB_B_DQ<11>
FB_B_DQ<13>
FB_B_DQ<12>
FB_B_DQ<10>
FB_B_DQ<8>
FB_B_DQ<16>
FB_B_DQ<19>
FB_B_DQ<21>
FB_B_DQ<17>
FB_B_DQ<22>
FB_B_DQ<18>
FB_B_DQ<23>
FB_B_DQ<20>
FB_B_DQ<29>
FB_B_DQ<27>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<30>
FB_B_DQ<28>
FB_B_DQ<31>
FB_B_DQ<26>
FB_B_DQ<4>
FB_B_DQ<3>
FB_B_DQ<0>
FB_B_DQ<2>
FB_B_DQ<1>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<5>
IN
76 98
98 78 76
IN
IN
76 98
98 78 76
IN
IN
76 98
98 76
IN
IN
76 98
98 76
IN
98 76
IN
BI
76 98
BI
76 98
BI
76 98
BI
98 76
IN
98 78 76
IN
98 78 76
IN
98 78 76
IN
98 78 76
IN
98 78 76
IN
76 98
BI
76 98
BI
76 98
BI
76 98
98 78 76
IN
98 76
IN
98 78 76
IN
BI
76 98
BI
76 98
BI
76 98
BI
76 98
98 76
IN
BI
76 98
98 76
IN
BI
76 98
76
IN
BI
76 98
98 78 76
IN
BI
76 98
98 76
IN
BI
76 98
98 78 76
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
IN
SSM6N15FEAPE
VRAM4
VRAM4
R8595
121
1%
1/16W
MF-LF
2 402
10%
16V
CERM 2
402
IN
98 76
OUT
98 76
OUT
98 76
98 76
76 98
OUT
OUT
BI
76 98
98 76
BI
76 98
98 76
IN
BI
76 98
98 76
IN
BI
76 98
98 76
IN
BI
76 98
BI
76 98
BI
76 98
98 78 76
IN
IN
98 78 76
IN
98 78 76
IN
100
J11
J10
F4
H4
F9
H10
A4
A9
V4
V9
FB_B_DRAM_RST
FB_B_RDQS<5>
FB_B_RDQS<7>
FB_B_RDQS<4>
FB_B_RDQS<6>
D3
D10
P10
P3
FB_B_WDQS<5>
FB_B_WDQS<7>
FB_B_WDQS<4>
FB_B_WDQS<6>
D2
D11
P11
P2
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>
5%
1/16W
MF-LF
2 402
A0
U8550
DM0
A1
BGA
(1 OF 2)
DM1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
CKE
A12/CS1*
CK*
CS0*
WE*
CAS*
RAS*
NC
DM2
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
CK
DQ11
DQ12
DQ13
DQ14
ZQ
DQ15
DQ16
MF
DQ17
SEN
DQ18
DQ19
RESET
RDQS0
DQ20
DQ21
RDQS1
RDQS2
DQ22
RDQS3
DQ23
DQ24
WDQS0
WDQS1
DQ25
WDQS2
DQ26
DQ27
WDQS3
DQ28
G9 BA0
G4 BA1
H3 BA2
1%
1/16W
MF-LF
402 2
5 G
S 1
S 4
OMIT
CRITICAL
1%
1/16W
MF-LF
2 402
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FB_B_UCS0_L
FB_B_WE_L
FB_B_UCAS_L
FB_B_RAS_L
SOT563
FB_VREF_UNTERM
2 G
243
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
H9
J3
243
IN
D 3
Q8550
SSM6N15FEAPE
R8597
FB_B_MA<0>
FB_B_MA<1>
FB_B_UMA<2>
FB_B_UMA<3>
FB_B_UMA<4>
FB_B_UMA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
FB_B_UCKE
FB_B_MA<12>
R85981
R8549
79 78 77
80
D 6
FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
98 78 76
SOT563
0.01UF
243
1%
1/16W
MF-LF
402 2
J2 RFU
Q8550
C8596 1
R8596
121
1%
1/16W
MF-LF
402 2
VOLTAGE=0.9V
1
R8594
1%
1/16W
MF-LF
2 402
121
A0
G9 BA0
G4 BA1
H3 BA2
NC
VRAM4
1
R8592
OMIT
CRITICAL
1%
1/16W
MF-LF
2 402
FB_B_DRAM_RST
R8590
SOT563
FB_VREF_UNTERM
2 G
243
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_LCS0_L
FB_B_WE_L
FB_B_LCAS_L
FB_B_RAS_L
1%
1/16W
MF-LF
402 2
VRAM4
1
R8593
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
H9
J3
243
D 3
R8547
FB_B_MA<0>
FB_B_MA<1>
FB_B_LMA<2>
FB_B_LMA<3>
FB_B_LMA<4>
FB_B_LMA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
FB_B_LCKE
FB_B_MA<12>
R85481
Q8500
SSM6N15FEAPE
FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
98 78 76
IN
D 6
K4J10324QD-HC11
IN
98 76
R8545
FB_B3_VREF_UNTERM_L
FB_B1_VREF_UNTERM_L
MFHIGH
IN
98 78 76
79 78 77
80
VRAM4
1
VSS6
VSS7
(NONE)
10%
2 16V
CERM
402
32MX32-900MHZ-MFH
1%
1/16W
MF-LF
2 402
10%
16V
CERM 2
402
VSS5
C8582
MFHIGH
121
0.01UF
243
1%
1/16W
MF-LF
402 2
VSS3
VSS4
- =PP1V8_S0_FB_VREF_B
G12
L1
L12
V3
V10
0.01uF
931
DQ29
DQ30
MFHIGH
R8543
SOT563
K4J10324QD-HC11
VRAM4
1
98 78 76
R8546
121
1%
1/16W
MF-LF
402 2
SSM6N15FEAPE
32MX32-900MHZ-MFH
121
1%
1/16W
MF-LF
402 2
Q8500
C8546 1
MFHIGH
1K
5%
1/16W
MF-LF
402 2
R8544
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
- =PP1V8_S0_FB_VDD
VSS1 A10
VSS2 G1
BGA
(2 OF 2)
FB_B_CLK1_TERM
VOLTAGE=0.9V
1
VSS0 A3
U8550
H1 VREF0
H12 VREF1
FB_B3_VREF
10%
2 16V
CERM
402
MFHIGH
R8542
MFHIGH
R8540
VRAM4
1
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
C8565
0.1uF
FB_B_CLK0_TERM
VRAM4
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
K1 VDDA0
K12 VDDA1
FB_B2_VREF_UNTERM_L
FB_B0_VREF_UNTERM_L
A2
A11
F1
F12
M1
M12
V2
V11
VSSA0 J1
VSSA1 J12
0.01uF
931
0.1uF
H1 VREF0
H12 VREF1
FB_B2_VREF
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
VSS1 A10
VSS2 G1
BGA
(2 OF 2)
Page Notes
CRITICAL
VSS0 A3
U8500
K4J10324QD-HC11
C8500 1
A2
A11
F1
F12
M1
M12
V2
V11
32MX32-900MHZ-MFH
76 75 56 50 8 7 6
78 77
OMIT
K4J10324QD-HC11
32MX32-900MHZ-MFH
DQ31
E3
E10
N10
N3
FB_B_DQM_L<5>
FB_B_DQM_L<7>
FB_B_DQM_L<4>
FB_B_DQM_L<6>
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<47>
FB_B_DQ<43>
FB_B_DQ<42>
FB_B_DQ<40>
FB_B_DQ<41>
FB_B_DQ<44>
FB_B_DQ<59>
FB_B_DQ<56>
FB_B_DQ<60>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<57>
FB_B_DQ<63>
FB_B_DQ<58>
FB_B_DQ<36>
FB_B_DQ<38>
FB_B_DQ<37>
FB_B_DQ<39>
FB_B_DQ<35>
FB_B_DQ<34>
FB_B_DQ<32>
FB_B_DQ<33>
FB_B_DQ<48>
FB_B_DQ<50>
FB_B_DQ<54>
FB_B_DQ<49>
FB_B_DQ<51>
FB_B_DQ<55>
FB_B_DQ<52>
FB_B_DQ<53>
IN
76 98
IN
76 98
IN
76 98
IN
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
BI
76 98
SYNC_MASTER=K17_REF
PAGE TITLE
BI
GDDR3 Frame Buffer B (Top)
BI
BI
DRAWING NUMBER
76 98
Apple Inc.
J2 RFU
R
R8599
100
5%
1/16W
MF-LF
2 402

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
85 OF 132
SHEET
78 OF 101
Page Notes
NV-GT216
- =PP3V3_GPI_MIO
BGA
(6 OF 9)
- =PP1V2_GPU_PLLVDD
84 82 81 80 79 74 72 7 6
- =PP1V2_GPU_H_PLLVDD
PP3V3_S0GPU
J9
J10
J11
J12
J13
- =PP1V2_GPU_VID_PLLVDD
C8694
0.1UF
(NONE)
20%
2 10V
CERM
402
C8696
1UF
C8698
4.7UF
10%
2 6.3V
X5R
402
20%
6.3V
2 X5R-CERM1
402
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
VDD33
(NONE)
NC_GPU_ROM_CS_L
80 GPU_ROM_SCLK
80 GPU_ROM_SI
80 GPU_ROM_SO
C3
D4
D3
C4
80
R8696
40.2K
1%
1/16W
MF-LF
2 402
84 82 81 80 79 74 72 7 6
84 82 81 80 79 74 72 7 6
R86201
R8697
40.2K
1%
1/16W
MF-LF
2 402
GPU_STRAP_REF_3V3_PDN9
GPU_STRAP_REF_MIOB_PD
M9
C8610 1
C8611 1
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
1UF
R8621
49.9
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
R86161
GPU_MIOA_PD_VDDQ
GPU_MIOB_PD_VDDQ
GPU_MIOA_PU_GND
GPU_MIOB_PU_GND
R86221
49.9
49.9
1%
1/16W
MF-LF
402 2
R8618
10K
79
79
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
GPU_TESTMODE_PD
79
1
C8617 R8619
10K
0.1uF
5%
1/16W
MF-LF
402 2
10%
2 16V
X5R
402
5%
1/16W
MF-LF
2 402
C8619 R8660
10K
0.1uF
10%
2 16V
X5R
402
79
79
5%
1/16W
MF-LF
2 402
79
79
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
AA9
AB9
W9
Y9
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4
N5
AF1
GPU_MIOA_PD_VDDQ
GPU_MIOA_PU_GND
U5
T5
GPU_MIOB_PD_VDDQ
GPU_MIOB_PU_GND
AA7
AA6
65mA
TESTMODE
MIOA_VREF
MIOB_VREF
MIOA_CAL_PD_VDDQ
MIOA_CAL_PU_GND
MIOB_CAL_PD_VDDQ
MIOB_CAL_PU_GND
AF9
SP_PLLVDD
AE9
PLLVDD
AD9
VID_PLLVDD
L8635
PP1V05_S0GPU
100NH-700MA-0.14OHM
1
2
PP1V1_GPU_H_PLLVDD_F
0603
C8637 1
VOLTAGE=1.2V
C8635 1
4.7UF
4.7UF
20%
6.3V 2
CERM
603
20%
6.3V 2
CERM
603
98 80 27
25mA
8
IN
OUT
GPU_CLK27M
NC_GPU_XTALOUT
B1
B2
XTAL_IN
XTAL_OUT
C8636
1UF
80
10%
6.3V
2 X5R
402
98 80
OUT
IN
GPU_XTALOUTBUFF
GPU_CLK27M_SS
D1
D2
XTAL_OUTBUFF
XTAL_SSIN
L8640
PP1V05_S0GPU
100NH-700MA-0.14OHM
1
2
PP1V1_GPU_VID_PLLVDD_F
0603
C8643 1
VOLTAGE=1.2V
C8640 1
4.7UF
4.7UF
20%
6.3V 2
CERM
603
GPU_VCORE_VID3
BI
DP_EG_HPD
BI
GPU_VCORE_VID4
BI
EG_LCD_PWR_EN
BI
EG_BKLT_EN
BI
GPU_VCORE_VID0
BI
GPU_VCORE_VID1
BI
GPU_VCORE_VID2
BI
SMC_GFX_OVERTEMP_R_L
BI
TP_GPU_GSTATE<0>
BI
FB_VREF_UNTERM
BI
GPU_GPIO_11
BI
SMC_GFX_THROTTLE_R_L
BI
FBVDD_ALTVO
BI
NC_GPU_GPIO_14
BI
NC_GPU_GPIO_15
BI
GPU_GPIO_16
BI
NC_GPU_GPIO_17
BI
NC_GPU_GPIO_18
BI
NC_GPU_GPIO_19
BI
NC_GPU_GPIO_20
BI
NC_GPU_GPIO_21
BI
NC_GPU_GPIO_22
BI
NC_GPU_GPIO_23
BI
80 82
80 84
80 82
80 87
80 87
80 82
80 82
80 82
80
6 80
77 78 80
80
80
80 86
80
80
80
80
80
80
80
80
80
80
MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GND
P9
R9
T9
U9
AP35
GPU_MIOA_VREF
GPU_MIOB_VREF
79
10K
1%
1/16W
MF-LF
2 402
1UF
R86171
R8623
K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
PP3V3_S0GPU
49.9
ROM_CS*
ROM_SCLK
ROM_SI
ROM_SO
PP3V3_S0GPU
86 81 79 76 74 7 6
U8000
- =PP3V3_GPU_VDD33
86 81 79 76 74 7 6
OMIT
110mA
20%
6.3V 2
CERM
603
50mA
C8641
1UF
C8631
0.1uF
10%
6.3V
2 X5R
402
10%
2 16V
X5R
402
80
BI
80
BI
80
BI
GPU_STRAP<0>
GPU_STRAP<1>
GPU_STRAP<2>
W5
W7
V7
C
AP14
AN14
AN16
AR14
AP16
TP_GPU_JTAG_TCK
IN
TP_GPU_JTAG_TDI
IN
TP_GPU_JTAG_TDO
OUT
TP_GPU_JTAG_TMS
IN
TP_GPU_JTAG_TRST_L IN
MIOA_CLKIN
MIOA_CLKOUT
MIOA_CLKOUT*
MIOA_CTL3
MIOA_DE
MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14
MIOA_HSYNC
MIOA_VSYNC
N4
R4
T4
P5
N2
N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
N3
L3
NC_GPU_MIOA_CLKIN IN
NC_GPU_MIOA_CLKOUT_P
BI
NC_GPU_MIOA_CLKOUT_N
BI
NC_GPU_MIOA_CTL3
BI
TP_GPU_MIOA_DE
BI
TP_GPU_MIOA_D<0>
BI
TP_GPU_MIOA_D<1>
BI
TP_GPU_MIOA_D<2>
BI
TP_GPU_MIOA_D<3>
BI
TP_GPU_MIOA_D<4>
BI
TP_GPU_MIOA_D<5>
BI
TP_GPU_MIOA_D<6>
BI
TP_GPU_MIOA_D<7>
BI
TP_GPU_MIOA_D<8>
BI
TP_GPU_MIOA_D<9>
BI
GPU_MIOA_D<10>
BI
GPU_MIOA_D<11>
BI
GPU_MIOA_D<12>
BI
GPU_MIOA_D<13>
BI
GPU_MIOA_D<14>
BI
NC_GPU_MIOA_HSYNC BI
NC_GPU_MIOA_VSYNC BI
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT*
MIOB_CTL3
MIOB_DE
MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8
MIOB_D9
MIOB_D10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14
AE1
V4
W4
W3
Y5
Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6
NC_GPU_MIOB_CLKIN IN
NC_GPU_MIOB_CLKOUT_P
BI
NC_GPU_MIOB_CLKOUT_N
BI
NC_GPU_MIOB_CTL3
BI
NC_GPU_MIOB_DE
BI
NC_GPU_MIOB_D<0>
BI
NC_GPU_MIOB_D<1>
BI
NC_GPU_MIOB_D<2>
BI
NC_GPU_MIOB_D<3>
BI
NC_GPU_MIOB_D<4>
BI
NC_GPU_MIOB_D<5>
BI
NC_GPU_MIOB_D<6>
BI
NC_GPU_MIOB_D<7>
BI
NC_GPU_MIOB_D<8>
BI
NC_GPU_MIOB_D<9>
BI
NC_GPU_MIOB_D<10> BI
MIOB_HSYNC
MIOB_VSYNC
W1
W2
NC_GPU_MIOB_HSYNC
NC_GPU_MIOB_VSYNC
THERMDP
THERMDN
B5
B4
GPU_TDIODE_P
GPU_TDIODE_N
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
80
80
80
80
80
80
80
80
80
6 80
6 80
6 80
6 80
6 80
6 80
6 80
6 80
6 80
6 80
6 80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
STRAP0
STRAP1
STRAP2
SYNC_MASTER=K17_REF
BI
80
BI
80
PAGE TITLE
NV GT216 GPIO/MIO/MISC
DRAWING NUMBER
IN
51 80 99
OUT
51 80 99
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
86 OF 132
SHEET
79 OF 101
Renamed signals
Native Func
82
79
80
GPU_VCORE_VID3
GP
84
79
80
DP_EG_HPD
HPDC
82
79
80
LCD0_BL_PWM
GPU_VCORE_VID4
GPU_VCORE_VID3
GPU_VCORE_VID4
EG_BKLT_EN
LCD0_BL_EN
EG_LCD_PWR_EN
EG_BKLT_EN
MAKE_BASE=TRUE
82
79
80
GPU_VCORE_VID0
82
79
80
GPU_VCORE_VID1
VID1
82
79
80
GPU_VCORE_VID2
GPU_VCORE_VID0
MAKE_BASE=TRUE
GPU_VCORE_VID1
MAKE_BASE=TRUE
VID2/MEM_VID
GPU_VCORE_VID2
MAKE_BASE=TRUE
THERM
86
79
80
79
80
HPDE
GPU_GPIO_16
DVI_MODE0
80 79
GPIOs
NC_GPU_GPIO_15
98 80 79 27
79 80
80
NC_GPU_GPIO_17
79 80
99 80 79 51
GPU_TDIODE_P
79 80
99 80 79 51
GPU_TDIODE_N
98 80 79
GPU_CLK27M_SS
HDMI_DETECT0
NC_GPU_GPIO_17
MAKE_BASE=TRUE
80 79
NC_GPU_GPIO_18
79 80 87
80 79
HDMI_DETECT1
NC_GPU_GPIO_19
NC_GPU_GPIO_18
FAN_PWM
TP_GPU_GSTATE<0>
TP_GPU_GSTATE<0>
MEM_VREF
GPU_GPIO_11
SLI_SYNC
FB_VREF_UNTERM
MAKE_BASE=TRUE
NC_GPU_GPIO_19
TP_GPU_GSTATE<1>
79 80 82
80 79
NC_GPU_GPIO_20
80 79
NC_GPU_GPIO_21
HPDF
79 80 82
80 79
NC_GPU_GPIO_22
SWAPRDY_A
79 80 82
80 79
NC_GPU_GPIO_23
NC_GPU_GPIO_20
MAKE_BASE=TRUE
NC_GPU_GPIO_21
MAKE_BASE=TRUE
NC_GPU_GPIO_22
MAKE_BASE=TRUE
GP
NC_GPU_GPIO_23
MAKE_BASE=TRUE
NO_TEST=TRUE
79 80
84 81 80
LVDS_EG_DDC_CLK
79 80
84 81 80
LVDS_EG_DDC_DATA
PWR_CTL1
MAKE_BASE=TRUE
80 79
51 79 80 99
LVDS_EG_DDC_CLK
80 81 84
NC_FBA_MA<13>
LVDS_EG_DDC_DATA
80 81 84
NC_FBB_MA<13>
DP_EG_DDC_CLK
80 81 84
DP_EG_DDC_DATA
80 81 84
TP_GPU_JTAG_TMS
79 80
TP_GPU_JTAG_TRST_L
79 80
MAKE_BASE=TRUE
79 80
84 81 80
DP_EG_DDC_CLK
79 80
84 81 80
DP_EG_DDC_DATA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
76 80
NC_FBB_MA<13>
76 80
NO_TEST=TRUE
Unused I2C Buses

80 76
81 80
NC_GPU_I2CC_SCL
81 80
NC_GPU_I2CC_SDA
MAKE_BASE=TRUE
NC_GPU_I2CC_SCL
80 81
NC_GPU_I2CC_SDA
80 81
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
76
80
NC_FB_B_UCS1_L
MAKE_BASE=TRUE
NC_FB_B_LCS1_L
MAKE_BASE=TRUE
76 80
NC_FB_B_LCS1_L
76 80
NO_TEST=TRUE
79 80 86
80 76
NC_FB_A_UCS1_L
80 76
NC_FB_A_LCS1_L
79 80
NC_FB_B_UCS1_L
NO_TEST=TRUE
FBVDD_ALTVO
MAKE_BASE=TRUE
NC_FBA_MA<13>
NO_TEST=TRUE
NC_GPU_ROM_CS_L
NC_GPU_GPIO_14
79 80
TP_GPU_JTAG_TMS
80 79
OUT
79 80
TP_GPU_JTAG_TDO
TP_GPU_JTAG_TRST_L
79 80
MAKE_BASE=TRUE
NC_GPU_GPIO_14
80 79
51 79 80 99
GPU_TDIODE_N
TP_GPU_JTAG_TDO
SMC_GFX_THROTTLE_R_L OUT
MAKE_BASE=TRUE
PWR_CTL0
GPU_TDIODE_P
MAKE_BASE=TRUE
79 80
OUT
MAKE_BASE=TRUE
FBVDD_ALTVO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 80
TP_GPU_JTAG_TDI
MAKE_BASE=TRUE
79 80
MAKE_BASE=TRUE
HPDD
77 78 79 80
MAKE_BASE=TRUE
80 79
79 80 98
6 79 80
MAKE_BASE=TRUE
FB_VREF_UNTERM
GPU_CLK27M_SS
MAKE_BASE=TRUE
TP_GPU_JTAG_TCK
TP_GPU_JTAG_TDI
80 79
27 79 80 98
MAKE_BASE=TRUE
EG_DP_CA_DET
TP_GPU_JTAG_TCK
MAKE_BASE=TRUE
GPU_CLK27M
MAKE_BASE=TRUE
80 79
79 80 87
GPU_CLK27M
MAKE_BASE=TRUE
AC_DET
79
80
NC_GPU_GPIO_15
DVI_MODE1
MAKE_BASE=TRUE
VID0
79
79 80 84
79 80 82
MAKE_BASE=TRUE
87
79
80
79
IN
MAKE_BASE=TRUE
EG_LCD_PWR_EN
79
77
78
80
80 79
MAKE_BASE=TRUE
DP_EG_HPD
87
79
80
80 79 6
79 80 82
MAKE_BASE=TRUE
LCD0_VDD
79
80
Native Func
GPIOs
Unused signals
NC_GPU_ROM_CS_L
MAKE_BASE=TRUE
79 80
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FB_A_UCS1_L
76 80
NC_FB_A_LCS1_L
76 80
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
Config Straps
Physical
Strapping Pin
84 82 81 80 79 74 72 7 6
PP3V3_S0GPU
ROM_SO
OMIT
NO STUFF
1
NO STUFF
4.99K
15.0K
R87071 R8709
2.0K
5%
1/16W
MF-LF
402 2
Strapping Bit 3
1%
1/16W
MF-LF
402 2
XCLK_417
ROM_SCLK
OUT
GPU_ROM_SI
79
IN
GPU_ROM_SO
79
IN
GPU_ROM_SCLK
FB_0_BAR_SIZE
PCI_DEVID[4]
SUB_VENDOR
Strapping Bit 1
SMB_ALT_ADDR
SLOT_CLK_CFG
81 80
NC_GPU_I2CH_SCL
81 80
NC_GPU_I2CH_SDA
NC_GPU_I2CH_SCL
MAKE_BASE=TRUE
Strapping Bit 0
NC_GPU_I2CH_SDA
MAKE_BASE=TRUE
VGA_DEVICE
80 81
NO_TEST=TRUE
NO_TEST=TRUE
80
81
R87111
ROM_SI
RAMCFG[3]
STRAP 2
1%
1/16W
MF-LF
402 2
RAMCFG[2]
PCI_DEVID[3]
RAMCFG[1]
PCI_DEVID[2]
81 80
NC_LVDS_EG_B_CLK_P
81 80
NC_LVDS_EG_B_CLK_N
PEX_PLL_EN_TERM
98 81 80
NC_LVDS_EG_A_DATA_P<3>
98 81 80
NC_LVDS_EG_A_DATA_N<3>
MAKE_BASE=TRUE
3GIO_PADCFG[3]
3GIO_PADCFG[2]
3GIO_PADCFG[1]
PCI_DEVID[0]
USER[2]
USER[1]
NC_LVDS_EG_B_DATA_P<3>
R8708
R8710
R8712
45.3K
10K
15.0K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
Strap S1/S2 Bit[3:0] PU/PD Rval

8 1000 PU 5k
9 1001 PU 10k
A 1010 PU 15k
B 1011 PU 20k
C 1100 PU 25k
D 1101 PU 30k
E 1110 PU 35k
F 1111 PU 45k
NO_TEST=TRUE
80 79
80 79
MAKE_BASE=TRUE
80 79
NC_GPU_MIOA_CTL3
MAKE_BASE=TRUE
80 79 6
45.3K
34.8K
1%
1/16W
MF-LF
402 2
BI
GPU_STRAP<0>
BI
GPU_STRAP<1>
BI
1%
1/16W
MF-LF
402 2
R87051
79 6
TP_GPU_MIOA_D<9..0>
R8702
CRITICAL
BOM OPTION
80 79
NC_GPU_MIOA_VSYNC
QTY
DESCRIPTION
REFERENCE DES
RES,MTL FILM,1/16W,24.9K,1,0402,SMD,LF
R8708
114S0368
R8708
VRAM_512_HYNIX
80 79
NC_GPU_MIOB_CLKIN
114S0343
R8708
VRAM_256_SAMSUNG
80 79
114S0331
R8708
VRAM_256_HYNIX
80 79
80 79
NC_GPU_MIOB_CTL3
80 79
NC_GPU_MIOB_DE
VRAM_512_SAMSUNG
2.0K
5%
1/16W
MF-LF
402 2
10K
24.9K
1%
1/16W
MF-LF
402 2
PP3V3_S0
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 73 72 69
84 82 81 80 79 74 72 7 6
5%
1/16W
MF-LF
402 2
2.2K
5%
1/16W
MF-LF
402 2
4.7K
5%
1/16W
MF-LF
402
84 81 80
84 82 81 80 79 74 72 7 6
DP_EG_DDC_CLK
BI
DP_EG_DDC_DATA
PP3V3_S0GPU
DP_CA_DET_EG_FET
DP_CA_DET_EG_FET
Q8742
R87421
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
IN
DP_IG_DDC_CLK
BI
DP_IG_DDC_DATA
EG_DP_CA_DET
DP_CA_DET
IN
79 80
79 80
79 80
NC_GPU_MIOB_CTL3
79 80
NC_GPU_MIOB_DE
79 80
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_D<14..0>
MAKE_BASE=TRUE
NC_GPU_MIOB_VSYNC
NC_GPU_MIOB_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_GPU_MIOB_VSYNC
79 80
NC_GPU_MIOB_HSYNC
79 80
NO_TEST=TRUE
MAKE_BASE=TRUE
GPU_MIOB_D<14..0>
NO_TEST=TRUE
Unused Clocks
84 82 81 80 79 74 72 7 6
PP3V3_S0GPU
79
GPU_CLK27M_SS
GPU_XTALOUTBUFF
GPU_SS_INT
1
R8796 R8797
2.2K
2.2K
5%
1/16W
MF-LF
402
80 79
80 79
R87801
R87811
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
10K
5%
1/16W
MF-LF
402
R8798
R8799
SSM3K15FV
80
84 18 8
NC_GPU_MIOB_CLKIN
NO_TEST=TRUE
MAKE_BASE=TRUE
98 80 79
SOD-VESM-HF
1%
1/16W
MF-LF
402 2
84 18 8
79 80
NO_TEST=TRUE
80 79
10K
NO STUFF
0
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
SMC_GFX_OVERTEMP_L
OUT
45
SMC_GFX_THROTTLE_L
OUT
45
EG_LCD_PWR_EN
OUT
79 80 87
EG_BKLT_EN
OUT
79 80 87
FBVDD_ALTVO
OUT
79 80 86
FB_VREF_UNTERM
OUT
77 78 79 80
100K
IN
79 80
NC_GPU_MIOA_VSYNC
4.7K
84 81 80
79
NC_GPU_MIOA_HSYNC
NO_TEST=TRUE
R87501 R87511 R87521 R87531

2.2K
79 80
GPU_MIOA_D<14..10>
NO_TEST=TRUE
80 79
PP3V3_S0GPU
NC_GPU_MIOA_CLKIN
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79
1%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R8706
6 79 80
NO_TEST=TRUE
NC_GPU_MIOA_HSYNC
NO STUFF
R8704
79 80
TP_GPU_MIOA_DE
NO_TEST=TRUE
80 79
GPU_STRAP<2>
NO STUFF NO STUFF
1
1
NC_GPU_MIOA_CTL3
GPU_MIOA_D<9..0>
MAKE_BASE=TRUE
114S0353
1%
1/16W
MF-LF
402 2
79 80
MAKE_BASE=TRUE
NC_GPU_MIOA_CLKIN
PART NUMBER
10K
79 80
MAKE_BASE=TRUE
NC_GPU_MIOA_D<14..10>
R87011 R87031
NO_TEST=TRUE
TP_GPU_MIOA_DE
MAKE_BASE=TRUE
79
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
PP3V3_S0GPU
84 82 81 80 79 74 72 7 6
80 81
98
PCI_DEVID[4:0]=0x14
80 79
79
80 81 98
NC_LVDS_EG_B_DATA_N<3>
G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.
Strap S1/S2 Bit[3:0] PU/PD Rval

0 0000 PD 5k
1 0001 PD 10k
2 0010 PD 15k (HYN 256)
3 0011 PD 20k (SAM 256)
4 0100 PD 25k (SAM 512)
5 0101 PD 30k
6 0110 PD 35k (HYN 512)
7 0111 PD 45k
OMIT
79
80 81 98
NO_TEST=TRUE
MAKE_BASE=TRUE
USER[0]
80 81 98
NO_TEST=TRUE
MAKE_BASE=TRUE
3GIO_PADCFG[0]
98 81 80
USER[3]
80 81
NO_TEST=TRUE
MAKE_BASE=TRUE
98 81 80
STRAP 1
80 81
MAKE_BASE=TRUE
RAMCFG[0]
PCI_DEVID[1]
NC_LVDS_EG_B_CLK_P
NC_LVDS_EG_B_CLK_N
MAKE_BASE=TRUE
I2CS ties into SMBus connection page

(I2CS requires pullups even if not used)
STRAP 0
79
Strapping Bit 2
84 85 87
SYNC_MASTER=K17_REF
PAGE TITLE
R8743
1
DP_CA_DET_EG
GT216 GPIOS & STRAPS
NO STUFF
1
R8792 R8793R8794 R8795

IN
10K
87
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402
10K
10K
5%
1/16W
MF-LF
402
DRAWING NUMBER
5%
1/16W
MF-LF
402
Apple Inc.
R
DP_CA_DET_EG_PLD

Isolation FETs for DP MUX inputs

8
SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
87 OF 132
SHEET
80 OF 101
Page Notes
- =PP1V8_GPU_IFPX
72 7 6
PP1V8_GPUIFPX
?mA peak per diff pair

?mA peak for all pairs
PP1V8_GPU_IFPAB_IOVDD_F
VOLTAGE=1.8V
0603-1
C8800
C8801
4.7UF

(NONE)
PP1V05_S0GPU
GPU_IFPEF_RSET 81
GPU_IFPC_RSET 81
GPU_IFPAB_RSET 81
GPU_IFPD_RSET 81
OMIT
0.1UF
20%
10V
CERM 2
402
20%
10V
CERM 2
402
Place at AG9
81 79 76 74 7 6
86
C8803
0.1UF
20%
6.3V
CERM 2
603
(NONE)
U8000
NV-GT216
Place at AG10
L8805
80mA peak
PP1V1_GPU_IFPAB_PLLVDD_F
0603
C8805 1
C8806 1
1K
1K
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
81
PP1V1_GPU_IFPEF_IOVDD_F
VOLTAGE=1.1V
10%
6.3V 2
CERM
402
81
81
R8855 R8850 R8851 R8858
1%
1/16W
MF-LF
2 402
PP1V1_GPU_IFPCD_IOVDD_F
1UF
20%
6.3V 2
CERM
603
1K
81
180-OHM-1.5A
4.7UF
1
81
1K
1%
1/16W
MF-LF
2 402
81
81
AG9
AG10
AJ8
AK8
AE7
AD7
AK9
AJ11
GPU_IFPAB_RSET
PP3V3_GPU_IFPC_PLLVDD_F
GPU_IFPC_RSET
AJ9
AK7
PP1V8_GPU_IFPEF_PLLVDD_F
GPU_IFPEF_RSET
AJ6
AL1
L8810
180-OHM-1.5A
86 81 79 76 74 7 6
PP1V05_S0GPU
?mA peak per diff pair

?mA peak for all pairs
PP1V1_GPU_IFPCD_IOVDD_F
0603
C8810
4.7UF
20%
6.3V 2
CERM
603
C8811
C8813
0.1UF
20%
10V
CERM 2
402
20%
10V
CERM 2
402
84 80
BI
84 80
BI
L8815
81
LVDS_EG_DDC_CLK
LVDS_EG_DDC_DATA
G1
G4
BGA
(5 OF 9)
IFPA_IOVDD
IFPA_TXC
IFPB_IOVDD
IFPA_TXC*
IFPC_IOVDD
IFPA_TXD0
IFPD_IOVDD
IFPA_TXD0*
IFPE_IOVDD
IFPA_TXD1
IFPF_IOVDD
IFPA_TXD1*
IFPAB_PLLVDD
IFPA_TXD2
IFPAB_RSET
IFPA_TXD2*
IFPA_TXD3
IFPC_PLLVDD
IFPA_TXD3*
IFPC_RSET
IFPB_TXC
IFPEF_PLLVDD
IFPB_TXC*
IFPEF_RSET
IFPB_TXD4
IFPB_TXD4*
IFPB_TXD5
IFPB_TXD5*
IFPB_TXD6
I2CA_SCL
IFPB_TXD6*
I2CA_SDA
IFPB_TXD7
IFPB_TXD7*
Place at AK8
80
BI
80
BI
I2CS must be pulled up if not used
CRITICAL
VOLTAGE=1.1V
0.1UF
Place at AJ8
I2CS addr fixed at 0x9E,0x9F
NC_GPU_I2CC_SCL
NC_GPU_I2CC_SDA
E3
E4
AM11
AM12
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11
LVDS_EG_A_DATA_P<0>
OUT
LVDS_EG_A_DATA_N<0>
OUT
LVDS_EG_A_DATA_P<1>
OUT
LVDS_EG_A_DATA_N<1>
OUT
LVDS_EG_A_DATA_P<2>
OUT
LVDS_EG_A_DATA_N<2>
OUT
NC_LVDS_EG_A_DATA_P<3>OUT
NC_LVDS_EG_A_DATA_N<3>OUT
AP13
AN13
NC_LVDS_EG_B_CLK_P
NC_LVDS_EG_B_CLK_N
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11
LVDS_EG_B_DATA_P<0>
OUT
LVDS_EG_B_DATA_N<0>
OUT
LVDS_EG_B_DATA_P<1>
OUT
LVDS_EG_B_DATA_N<1>
OUT
LVDS_EG_B_DATA_P<2>
OUT
LVDS_EG_B_DATA_N<2>
OUT
NC_LVDS_EG_B_DATA_P<3>OUT
NC_LVDS_EG_B_DATA_N<3>OUT
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA*
AP2
AN3
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
IFPC_L0
IFPC_L0*
IFPC_L1
IFPC_L1*
IFPC_L2
IFPC_L2*
IFPC_L3
IFPC_L3*
AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2
DP_EG_ML_P<0>
DP_EG_ML_N<0>
DP_EG_ML_P<1>
DP_EG_ML_N<1>
DP_EG_ML_P<2>
DP_EG_ML_N<2>
DP_EG_ML_P<3>
DP_EG_ML_N<3>
I2CC_SCL
I2CC_SDA
300-OHM-0.5A
84 82 81 80 79 74 72 7 6
PP3V3_S0GPU
160mA peak
PP3V3_GPU_IFPC_PLLVDD_F
0603-1
PP1V1_GPU_IFPEF_IOVDD_F
PP1V8_GPU_IFPEF_PLLVDD_F
VOLTAGE=1.8V
C8815 1
C8816 1
20%
6.3V 2
CERM
603
10%
6.3V 2
CERM
402
4.7UF
81
VOLTAGE=1.1V
VOLTAGE=3.3V
1UF
81
97 51 48 45
BI
97 51 48 45
BI
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
E2
E1
I2CS_SCL
I2CS_SDA
I2CS must be pulled up if not used.

I2CS addr fixed at 0x9E,0x9F
81
80
BI
80
BI
84 80
BI
84 80
BI
Power inputs must be pulled down if not used
NC_GPU_I2CH_SDA
NC_GPU_I2CH_SCL
F6
G6
I2CH_SCL
I2CH_SDA
DP_EG_DDC_CLK
DP_EG_DDC_DATA
G3
G2
I2CB_SCL
I2CB_SDA
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA*
AP4NC
AN4NC
IFPD_L0
IFPD_L0*
IFPD_L1
IFPD_L1*
IFPD_L2
IFPD_L2*
IFPD_L3
IFPD_L3*
AR8NC
AR7NC
AP7NC
AN7NC
AN5NC
AP5NC
AR5NC
AR4NC
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA*
AE4NC
AD4NC
IFPE_L0
IFPE_L0*
IFPE_L1
IFPE_L1*
IFPE_L2
IFPE_L2*
IFPE_L3
IFPE_L3*
AH6NC
AH5NC
AH4NC
AG4NC
AF4NC
AF5NC
AE6NC
AE5NC
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA*
AF3NC
AF2NC
IFPF_L0
IFPF_L0*
IFPF_L1
IFPF_L1*
IFPF_L2
IFPF_L2*
IFPF_L3
IFPF_L3*
AL2NC
AL3NC
AJ3NC
AJ2NC
AJ1NC
AH1NC
AH2NC
AH3NC
DACA_RED
DACA_GREEN
DACA_BLUE
AM15
NC
AM14
NC
AL14
NC
DACA_HSYNC
DACA_VSYNC
AM13
NC
AL13
NC
DACB_RED
DACB_GREEN
DACB_BLUE
AK4NC
AL4NC
AJ4NC
R8856 1R8857
10K
5%
1/16W
MF-LF
2 402
L8800
300-OHM-0.5A
1
- =PP3V3_GPU_IFPCD_IOVDD
CRITICAL
Sum of peak currents: 240mA
10K
5%
1/16W
MF-LF
2 402
AJ12
DACA_VDD
AK12 DACA_VREF
NC
AK13 DACA_RSET
NC
OUT
87 98
OUT
87 98
87 98
87 98
87 98
87 98
87 98
87 98
80 98
80 98
OUT
80
OUT
80
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
87 98
87 98
87 98
87 98
87 98
87 98
80 98
80 98
NO STUFF
R88611
1K
5%
1/16W
MF-LF
402 2
OUT
84 98
OUT
84 98
NO STUFF
1
R8860
1K
5%
1/16W
MF-LF
2 402
PP3V3_S0GPU
6 7 72 74 79 80 81 82 84
R8859
GPU_DACA_VDD
GPU_DACB_VDD
PP1V8_GPU_IFPD_PLLVDD
AG7
NCAK6
NCAH7
VOLTAGE=1.8V
R8852 1R8853 1R8854
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
10K
AC6
5%
1/16W
MF-LF
2 402
DACB_VDD
DACB_VREF
DACB_RSET
CEC
AB5
10K
5%
1/16W
MF-LF
2 402
GPU_CEC
SYNC_MASTER=K17_REF
IFPD_PLLVDD
PAGE TITLE
NV GT216 VIDEO INTERFACES

DRAWING NUMBER
81
GPU_IFPD_RSET
AB6
IFPD_RSET
DACB_HSYNC
DACB_VSYNC
AM1NC
AM2NC
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
88 OF 132
SHEET
81 OF 101
8
72 67 66
54 46 44
31 7 6
43 42 33
61 58 56
101
6
5
GPU VCore Regulator
VOLTAGE=5V
C8902 1
10
0.01uF
86 70 69 67 66 65 49 40 7 6
89
10%
2 16V
CERM
402
CRITICAL
20%
16V
POLY-TANT 2
D3L
PP5V_S3_GFXIMVP6_VDD
1
16
1uF
VDD
R8905
2
GFXIMVP6_RBIAS
50
87 86 73 8
OUT
82
82
R8910
82
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
82
82
87 73
IN
R8924
100
1%
1/16W
MF-LF
402 2
VOLTAGE=0V
20
C8920
10%
2 50V
CERM
402
5%
1/16W
MF-LF
402 2
U8900
VIN
14
UGATE
18
BOOT
17
GFXIMVP6_VIN
28
31
23
24
25
26
27
29
30
32
8
9
C8923
R8909
7.15K
330PF
GFXIMVP6_COMP_RC
1
R8950
150K
SOFT
MLP5X6-LFPAK-Q5A
GFXIMVP6_BOOT
10%
16V 2
X7R
603
PGOOD
VID0
VID1
VID2
VID3
VID4
VR_ON
AF_EN
FDE
PHASE
LGATE
84 82 81 80 79 74 72 7 6
VW
10%
6.3V
2 X5R-CERM
603
C8943
330UF
20%
3 2 2.0V
POLY-TANT
D2T-SM2
COMP
VO
1%
1/16W
MF-LF
402 2
GFXIMVP6_VO
12
R8900
C8952
OCSET
FB
ISP
ISN
13
1%
1/16W
MF-LF
402
R8902
ICOMP
VDIFF
THRM_PAD
15
VSS
20
PGND
1%
1/16W
MF-LF
402
Max Batt
C8906 1
VID2
1
VID1
0
VID0
1
0.74675V
K18
Balanced
5%
50V 2
COG
402
0.82400V
K18
0.90125V
Max perf
K18
R8901
9.09K
68PF
1
(PPVCORE_GPU_REG)
1%
1/16W
MF-LF
2 402
C8971
1
GFXIMVP6_DROOP
5%
50V
CERM
402-1
C8972 1
0.001UF
10%
50V
CERM 2
402
VOLTAGE=0V
XW8900
SM
1
VID3
9.76K
10
33
Voltage
330PF
GFXIMVP6_DFB
1%
1/16W
MF-LF
2 402
GFXIMVP6_VDIFF
VID4
11
3.01K
10%
25V
CERM
402
GFXIMVP6_VSUM
6
GPU VCore Setpoints
7.32K2
GFXIMVP6_OCSET
K18 Default Vcore Setpoints
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
GPUVID_0P75V
GPUVID4_1,GPUVID3_0,GPUVID2_1,GPUVID1_0,GPUVID0_1
GPUVID0_1
GPUVID1_1
GPUVID2_1
GPUVID3_1
GPUVID4_1
R89871
R89841
R89821
R89951
R89911
GPUVID_0P82V
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
GPUVID_0P90V
2.2K
2.2K
2.2K
2.2K
2.2K
TABLE_BOMGROUP_ITEM
GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4
82
82
82
82
82
PAGE TITLE
GPUVID0_0
GPUVID1_0
GPUVID2_0
GPUVID3_0
GPUVID4_0
R89881
R89851
R89831
R89961
R89921
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
2.2K
2.2K
2.2K
2.2K
GPU (GT216) CORE SUPPLY

DRAWING NUMBER
Apple Inc.
2.2K

SIZE
<SCH_NUM> D
REVISION
5%
1/16W
MF-LF
402
GFXIMVP6_PHASE_VSUM
R8998
GPU_VCORE_VID4
CRITICAL
10UF
20%
2 6.3V
X5R
603
1K
R8953
5%
1/16W
MF-LF
402
IN
C8965
TABLE_BOMGROUP_ITEM
R8994
80 79
TABLE_BOMGROUP_ITEM
5%
1/16W
MF-LF
402
IN
C8967
R89031
R8993
80 79
MLP5X6-LFPAK-Q5
330UF
20%
2.0V
POLY-TANT 2 3
D2T-SM2
C8953
10%
2 50V
CERM
402
5%
1/16W
MF-LF
402
20%
6.3V 2
X5R
603
C8942 1
20%
6.3V 2
X5R
603
10UF
6 7 49 75 82
30A max output

(L8920 limit)
CRITICAL
10UF
C8968 1
10%
50V 2
X7R
402
1 2 3
PP3V3_S0GPU
R8990
GPU_VCORE_VID3
C8969 1
0.001UF
Q8951
VSEN
RTN
330PF
C8951
5%
1/16W
MF-LF
402
C8966 1
GATE_NODE=TRUE
R8986
GPU_VCORE_VID2
PPVCORE_GPU
1
3
CSD58857Q5
GND_GFXIMVP6_AGND
IN
2
4
GFXIMVP6_LGATE
21
353S2289
80 79
VOLTAGE=1.2V
680pF
10%
50V
CERM
402
R8951
PPVCORE_GPU_REG_R
C8922
GFXIMVP6_COMP
0.0068UF
2
GFXIMVP6_VDIFF_RC 1
1%
1W
MF-1
0612
CRITICAL
10%
50V
2 CERM
402
1%
1/16W
MF-LF
402
2
GPU_VCORE_VID1
2
FDU1040D-SM
SWITCH_NODE=TRUE
DIDT=TRUE
Vout = 0.75V - 0.90V
0.001
0.56UH-31A
GFXIMVP6_PHASE
19
R8940
CRITICAL
L8920
10%
2 50V
X7R
402
150
IN
1 2 3
0.22UF
80 79
CRITICAL
C8956 1
IMON
GFXIMVP6_FB
CSD58856Q5A
10%
50V
CERM 2
402
GPU_VCORE_VID0
Q8950
0.001UF
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
IN
CRITICAL
GFXIMVP6_UGATE
C8921 1
1
100
80 79
DIDT=TRUE
GFXIMVP6_IMON
GFXIMVP6_VW
1K
QFN
10%
2 50V
CERM
402
(GFXIMVP6_AGND)
C8950
2
R89301
0.001UF 0.001UF
5%
1/16W
MF-LF
402
R8925
1%
1/16W
MF-LF
402
GFXIMVP6_SOFT
GFXIMVP6_VSEN_P
GFXIMVP6_VSEN_N
0.001UF
R8908
1
20%
2 16V
TANT
SM
5%
1/16W
MF-LF
402
GPU_GND_SENSE
15UF
4.7UF
R8920
1
C8935
DIDT=TRUE
GPU_VDD_SENSE
CRITICAL
1
20%
2 16V
TANT
SM
10%
50V
2 X7R
402
PVCC
ISL6263C
PM_ALL_GPU_PGOOD
GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4
EG_RAIL3_EN
GFXIMVP6_AF_EN
GFXIMVP6_FDE
OUT
PP3V3_S0GPU
10K
RBIAS
0.033UF
10%
16V
X5R
402
R89071
C8904
2
VOLTAGE=1.25V
C8931
15UF
0.001UF
10%
25V 2
X5R
603-1
CRITICAL
150K 1
1%
1/16W
MF-LF
402
20
C8934
C8901
10%
2 10V
X5R
402
PPVCORE_GPU
CRITICAL
1
1UF
X5R
603-1
VOLTAGE=5V
1%
1/16W
MF-LF
402
C8932
1UF
10% C8933 1
2 25V
C8930 1
68UF
PPBUS_G3H
22
74
C8903
2.2UF
R8904
74
PP5V_S3_GFXIMVP6_PVCC
20%
10V
X5R-CERM 2
402
82 75 49 7 6
R8911
PP5V_S3
5%
1/16W
MF-LF
402
84 82
79 74 72 7 6
81 80
<E4LABEL>
BRANCH
<BRANCH>
PAGE
89 OF 132
SHEET
82 OF 101
D
87
LCD_PWR_EN
IN
R90941
10K
LCD (LVDS) INTERFACE
5%
1/16W
MF-LF
402 2
CRITICAL
U9000
CRITICAL
FPF1009
1 ON
31 27 23 21 20 19 18 17 7 6
99 85 73 72 71 66 57 35
PP3V3_S5
C9009
0.1UF
L9000
MFET-2X2
FERR-250-OHM
2 VIN_1
VOUT_1 4
3 VIN_2
VOUT_2 5
GND
6
THRM
PAD
7
PP3V3_SW_LCD_UF
C9011
0.1UF
SM
C9001 1
C9012
C9002 1
0.1UF
10UF
10%
2 16V
X5R
402
10%
16V
2 X5R
402
VOLTAGE=3.3V
0.001UF
10%
16V 2
X5R
402
20%
2 6.3V
X5R
603
10%
50V 2
X7R
402
CRITICAL
J9000
20474-040E-11
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 80 73 72 69
F-RT-SM
41
42
PP3V3_S0
R90101
100K pull-ups are for
100K
5%
1/16W
MF-LF
402 2
no-panel case (development).

Panel has 2K pull-ups
84 6
84 6
R9011
100K
PP3V3_SW_LCD
VOLTAGE=3.3V
5%
1/16W
MF-LF
2 402
NC
LVDS_DDC_CLK
LVDS_DDC_DATA
98 84 6
C9010 1
98 84 6
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_DATA_P<0>
0.001UF
10%
50V 2
X7R
402
98 84 6
98 84 6
CRITICAL
L9010
90-OHM-100MA
98 84 6
DLP11S
SYM_VER-1
98 84 6
98 84
LVDS_CONN_A_CLK_N
98 84
LVDS_CONN_A_CLK_P
98 6
98 6
Place close to the connector
98 84 6
98 84 6
98 84 6
98 84 6
CRITICAL
L9011
90-OHM-100MA
98 84 6
DLP11S
SYM_VER-1
98 84 6
98 84
LVDS_CONN_B_CLK_N
98 84
LVDS_CONN_B_CLK_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_CLK_F_P
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
98 6
98 6
88 6
Place close to the connector
88 6
88 6
88 6
88 6
88 6
NC
88 56 6
PPVOUT_S0_LCDBKLT
C9000
0.001UF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
518S0651
43
44
10%
50V
CERM 2
402
SYNC_MASTER=K19_MLB
PAGE TITLE
LVDS Display Connector

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
90 OF 132
SHEET
83 OF 101
DisplayPort Mux
R9320
IN
LVDS_A_CLK_P
357
LVDS_CONN_A_CLK_P
OUT
93 8
IN
93 8
IN
93 8
IN
93 8
IN
93 8
IN
93 8
IN
83 98
1%
1/16W
MF-LF
402
R9322
98 87
IN
LVDS_A_CLK_N
357
98 87
IN
LVDS_CONN_A_CLK_N
1%
1/16W
MF-LF
402
OUT
83 98
93 18 8
BI
357
OUT
6 83 98
18 8
1%
1/16W
MF-LF
402
OUT
98 87
IN
LVDS_A_DATA_N<0>
IN
LVDS_A_DATA_P<1>
357
OUT
5%
1/16W
MF-LF
402 2
6 83 98
OUT
PLACE_NEAR=U9600.C10:7mm
98 87
IN
LVDS_A_DATA_N<1>
R9332
1
357
1%
1/16W
MF-LF
402
98 87
IN
LVDS_A_DATA_P<2>
IN
LVDS_A_DATA_N<2>
IN
LVDS_B_CLK_P
IN
LVDS_B_CLK_N
IN
IN
A8
A9
DIN1_3+
DIN1_3-
H9
DAUX1+
DAUX1-
357
6 83 98
OUT
83 98
IN
98 81
IN
98 81
IN
98 81
IN
98 81
IN
98 81
IN
98 81
IN
98 81
BI
98 81
BI
81 80
IN
81 80
BI
LVDS_B_DATA_N<1>
R9305
87
IN
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
DP_EG_ML_P<1>
DP_EG_ML_N<1>
D8
D9
DIN2_1+
DIN2_1-
DP_EG_ML_P<2>
DP_EG_ML_N<2>
E8
E9
DIN2_2+
DIN2_2-
DP_EG_ML_P<3>
DP_EG_ML_N<3>
F8
F9
DIN2_3+
DIN2_3-
H6
DAUX2+
DAUX2-
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
0.1uF
2 98 DP_EG_AUX_CH_C_P
10% 16V X5R 402
J6
2 98 DP_EG_AUX_CH_C_N
10% 16V X5R 402
H5
J5
DP_MUX_SEL_EG
IN
R9303
87
IN
DP_MUX_EN
1%
1/16W
MF-LF
402 2
10K
OUT
CRITICAL
DOUT_0+
DOUT_0-
B2
B1
DP_ML_P<0>
DP_ML_N<0>
OUT
85 98
OUT
85 98
DOUT_1+
DOUT_1-
D2
DP_ML_P<1>
DP_ML_N<1>
OUT
85 98
D1
OUT
85 98
DOUT_2+
DOUT_2-
E2
E1
DP_ML_P<2>
DP_ML_N<2>
OUT
85 98
OUT
85 98
DOUT_3+
DOUT_3-
F2
DP_ML_P<3>
DP_ML_N<3>
OUT
85 98
OUT
85 98
AUX+
AUX-
H2
F1
DP_AUX_CH_C_P
DP_AUX_CH_C_N
H1
BI
85 98
BI
85 98
PLACE_NEAR=U9320.J1:3mm
R9307
HPDIN
J1
DP_HPD_R
1K
DP_HOTPLUG_DET
84
IN
357
357
HPD_2
LO=PORT1
HI=PORT2
GPU_SEL
B7
XSD*
LO=AUX_CH
HI=DDC
DDC_AUX_SEL
C2
TST0
G2
GND
DP_CA_DET
IN
80 85 87
DP_HOTPLUG_DET
MAKE_BASE=TRUE
LVDS_CONN_B_CLK_N
OUT
83 98
OUT
6 83 98
357
OUT
6 83 98
R93701
1%
1/16W
MF-LF
402
OUT
6 83 98
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
20K
PP3V3_S0
5%
1/16W
MF-LF
402 2
C9370
R93721
20K
20%
10V
CERM 2
402
R9352
357
LVDS_B_DATA_P<2>
OUT
6 83 98
OUT
6 83 98
R9355
1
357
LVDS_B_DATA_N<2>
VCC
IN
LVDS_DDC_SEL_EG
13
87
IN
LVDS_DDC_SEL_IG
OUT
6 83 98
5%
1/16W
MF-LF
402 2
14
87
1%
1/16W
MF-LF
402
357
PP3V3_S0GPU
82 81 80 79 74 72 7 6
1%
1/16W
MF-LF
402
LVDS DDC MUX
U9370
QFN1
C1
C2
C3
R9371
20K
5%
1/16W
MF-LF
2 402
R9373
20K
5%
1/16W
MF-LF
2 402
LVDS_EG_DDC_CLK
IN
80 81
LVDS_IG_DDC_CLK
LVDS_DDC_CLK
IN
18
OUT
A1 2
B1
A2 3
B2
8
LVDS_EG_DDC_DATA
11
LVDS_IG_DDC_DATA
LVDS_DDC_DATA
A3
9
B3
A4
B4 10
GND THRM
CRITICAL
7
15
C4
BI
6 83
80 81
BI
18
BI
6 83
SYNC_MASTER=K17_REF
1%
1/16W
MF-LF
402
PAGE TITLE
Muxed Graphics Support

DRAWING NUMBER
Apple Inc.
SIZE
<SCH_NUM> D
REVISION
85 87
5%
1/16W
MF-LF
402
10%
2 6.3V
CERM-X5R
402
1%
1/16W
MF-LF
402 2
87 85 84
402
BGA
A1
1UF
20%
U9320
DDC_CLK2
DDC_DAT2
C9301
0.1UF
2 10V
CERM
CBTL06141EE
DPMUX_EN_HPD
R93011
12
IN
0.1uF
C9336
10K
R9357
98 87
C9335
DP_EG_DDC_CLK
DP_EG_DDC_DATA
PP3V3_S0
R9347
HPD_1
DIN2_0+
DIN2_0-
DP_MUX_XSD_L
DPMUX_EN_HPD
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
98 87
J2
B9
0.1UF
IN
J8
DDC_CLK1
DDC_DAT1
C9321
R9345
1
98 87
H8
DP_EG_ML_P<0>
DP_EG_ML_N<0>
R93021
OUT
J9
2 99 DP_IG_AUX_CH_C_N
10% 16V X5R 402
B8
DPMUX_EN_S0&DPMUX_EN_PLD
0.1uF
2 99 DP_IG_AUX_CH_C_P
10% 16V X5R 402
H3
DPMUX_EN_PLD
LVDS_B_DATA_N<0>
0.1uF
DP_IG_DDC_CLK
DP_IG_DDC_DATA
IN
98 81
5%
1/16W
MF-LF
402 2
LVDS_CONN_B_CLK_P
R9350
98 87
357
DP_IG_ML_P<3>
DP_IG_ML_N<3>
1
R9342
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
6 83 98
DIN1_2+
DIN1_2-
C9330
C9320
20%
2 10V
CERM
402
VDD
5%
1/16W
MF-LF
402
IN
OUT
A6
DP_EG_HPD
1%
1/16W
MF-LF
402
98 87
OUT
B6
100K
1%
1/16W
MF-LF
402
98 87
1%
1/16W
MF-LF
402
98 87
80 79
R9337
R9340
98 87
357
1%
1/16W
MF-LF
402
357
6 83 98
R9335
98 87
OUT
BI
DP_IG_ML_P<2>
DP_IG_ML_N<2>
DP_IG_AUX_CH_P
6 83 98
1%
PLACE_NEAR=U9600.A9:7mm 1/16W
MF-LF
402
80 18 8
98 81
1%
1/16W
MF-LF
402
R9330
98 87
357
IN
DIN1_1+
DIN1_1-
DP_IG_HPD
100K
R9327
80 18 8
B5
A5
C9331
R93041
BI
DP_IG_ML_P<1>
DP_IG_ML_N<1>
DP_IG_AUX_CH_N
R9325
LVDS_A_DATA_P<0>
93 18 8
A4
DIN1_0+
DIN1_0-
B3
98 87
IN
B4
SN74LV4066A
93 8
0.1UF
DP_IG_ML_P<0>
DP_IG_ML_N<0>
H7
All emulated LVDS outputs require this termination
IN
C8
93 8
J4
A2
LVDS Transmitter Termination
PP3V3_S0
G8
H4
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
<E4LABEL>
BRANCH
<BRANCH>
PAGE
93 OF 132
SHEET
84 OF 101
Port Power Switch
31 27 23 21 20 19 18 17 7 6
99 83 73 72 71 66 57 35
73 45 31 18 6
IN
L9400
SOT23
PP3V3_S5
PM_SLP_S3_L
IN
EN
OUT
PP3V3_S0_DPILIM
OC*
VOLTAGE=3.3V
TP_DPPWR_OC_L
0603
1
C9481
C9485 1
0.1UF
0.1UF
20%
2 10V
CERM
402
20%
6.3V 2
X5R
603
5 IO
C9486
22UF
20%
6.3V
2 X5R-CERM
603
20%
10V
CERM 2
402
2 IO
9 NC
IO 4
NC 7
6 NC
20%
2 50V
CERM
603
CRITICAL
1
10UF
VOLTAGE=3.3V
0.01UF
C9480
C9400
SLP2510P8
SLP2510P8
FERR-120-OHM-3A
1
2
PP3V3_S0_DPPWR
GND
RCLAMP0524P
3
3
CRITICAL
1
C9487
100UF
20%
POLY-TANT
CASE-B2-SM
2 6.3V
R94201
100K
5%
1/16W
MF-LF
402 2
NO STUFF
R9401
CRITICAL
HDMI_CEC
0
DP_ML_P<3>
C9414
98 84
IN
DP_ML_N<3>
C9415
98 84
BI
DP_AUX_CH_C_P
BI
DP_AUX_CH_C_N
2 98 DP_ML_C_P<3>
10% 16V X5R 402
0.1uF
1
SYM_VER-2
TOP ROW
TH PINS
SM PINS
1/16W MF-LF 402

2
4
6
1
98
DP_ML_CONN_P<3>
98
DP_ML_CONN_N<3>
12
14
16
18
98 84
99 88 87 85 84
58 54 52 51 50 48 47 46
25 24 23 21 20 19 18 17 7 6
42 40 37 34 30 28 27 26
83 80 73 72 69 68 63 62
20
DP_ESD
CRITICAL
PP3V3_S0
R94431
87 84 80
OUT
DP_CA_DET
5%
1/16W
MF-LF
402 2
2 IO
Q9440
GND
AUX_CHP
AUX_CHN
DP_PWR
13
98
1/16W MF-LF 402
1/16W MF-LF 402
5%
1/16W MF-LF 402
CRITICAL
98
DP_ML_CONN_P<1>
12-OHM-100MA
TCM1210-4SM
SYM_VER-2
GND
ML_LANE2P
ML_LANE2N
RETURN
15
98
DP_ML_CONN_N<1>
SYM_VER-2
9
11
12-OHM-100MA
TCM1210-4SM
FL9402
12-OHM-100MA
CRITICAL
DP_ML_CONN_P<2>
98
98
DP_ML_CONN_N<2>
TCM1210-4SM
SYM_VER-2
17
19
DP_ML_C_P<0> C9410 1
0.1uF
1
98 DP_ML_C_N<0> C9411
0.1uF
98 DP_ML_C_P<1>
C9412 1
0.1uF
98 DP_ML_C_N<1>
C9413 1
0.1uF
98 DP_ML_C_P<2>
C9416 1
0.1uF
98 DP_ML_C_N<2>
C9417 1
0.1uF
98
FL9401
21
2
DP_ML_P<0>
10% 16V X5R 402
IN
84 98
2
DP_ML_N<0>
10% 16V X5R 402
IN
84 98
2
DP_ML_P<1>
10% 16V X5R 402
IN
84 98
2
DP_ML_N<1>
10% 16V X5R 402
IN
84 98
2
DP_ML_P<2>
10% 16V X5R 402
IN
84 98
2
DP_ML_N<2>
10% 16V X5R 402
IN
84 98
R9432
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
NO STUFF
1
D9411
RCLAMP0504F
SC70-6-1
NO STUFF
R9402
DP_ESD
CRITICAL
D9400
RCLAMP0524P
SLP2510P8
5
MF-LF
402 2
1
2
6
5 IO
IO 4
NC 7
6 NC
PP3V3_S0
R9445 1
R9444 1
10K
5%
1/16W
MF-LF
402
87 84
5%
DP_ML_CONN_P<0>
DP_ML_CONN_N<0>
DP_ESD
CRITICAL
DP_CA_DET_Q
DP to DVI/HDMI
4
R94221 Cable Adapter
1M
(CA) has 100k
5%
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
1/16W
pull-up to DP_PWR.
88 87 85 84 83 80 73
52 51 50 48 47 46 42
25 24 23 21 20 19 18 17 7 6
40 37 34 30 28 27 26
72 69 68 63 62 58 54
99
22
2N7002DW-X-G
SOT-363
1/16W MF-LF 402
5%
SHIELD PINS
CRITICAL
GND
DP_CA_DET_L_Q
5%
IO 1
NC 10
9 NC
100K
2N7002DW-X-G
SOT-363
SLP2510P8
R94211
5%
1/16W
MF-LF
402 2
Q9440
NO STUFF
RCLAMP0524P
100K
5%
1/16W
MF-LF
402 2
98
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
D9411
R94421
100K
FL9400
BOT ROW
10
2 98 DP_ML_C_N<3>
10% 16V X5R 402
0.1uF
12-OHM-100MA
TCM1210-4SM
R9430
GND
IN
98 84
5%
FL9403
1M
1/16W MF-LF 402
CRITICAL
R9425
5%
1/16W
MF-LF
2 402
NO STUFF
R9400
F-RT-THSM
NO STUFF
R9413
NO STUFF
DSPLYPRT-M97-1
5%
R9431
J9400
NO STUFF
R9403
IO 1
NC 10
GND
U9480
TPS2051B
D9410
D9410
RCLAMP0524P
GND
DP_ESD
CRITICAL
DP_ESD
CRITICAL
CRITICAL
OUT
10K
5%
1/16W
MF-LF
402
DP_HOTPLUG_DET
Q9441
2N7002DW-X-G
SOT-363
DP_HPD_L_Q
3
Q9441
2N7002DW-X-G
SOT-363
DP_HPD_Q
R9423 1
100K
5%
1/16W
MF-LF
402
SYNC_MASTER=K17_REF
DP Source must pull

down HPD input with
greater than or equal
to 100K (DPv1.1a).
PAGE TITLE
DisplayPort Connector
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
94 OF 132
SHEET
85 OF 101
1V05 S0 GPU FET
D
70 69 68 54 52 47 42 23 7 6
88 86 72
PP1V05_S0
21 20 18 17 15 13 12 10 7 6
73 70 40 26 25 24 23
PP5V_S0
C9550
20%
10V
CERM
402
1.05V FB FET
0.1UF
2
VCC
U9550
EG_RAIL1_EN
IN
TDFN
ON
CRITICAL
SHDN*
D 5
G
PG
Q9550
AON6400L
MOSFET
AON6400L
CHANNEL
N-TYPE
1.8 mOhm @4.5V
RDS(ON)
DFN5X6
LOADING
P1V05_FB_GATE
3.83 A (EDP)
S
1 2 3
THRM
PAD
9
GND
CRITICAL
SLG5AP020
87 73
376S0827
PP1V05_S0GPU
PM_ALL_GPU_PGOOD
OUT
6 7 74 76 79 81
8 73 82 86 87
1V8 / 1V55 / 1V35 S0 FRAMEBUFFER REGULATOR
DESCRIPTION
CRITICAL
RES,1/16W,16.9K,1%,0402,LF
R9588
RES,1/16W,27.4K,1%,0402,LF
R9589
10%
2 25V
X5R
603-1
20%
16V 2
POLY-TANT
CASE-D2E-SM
FB1V35
C9595
1UF
68UF
FB1V35
TABLE_5_ITEM
114S0357
C9590 1
BOM OPTION
TABLE_5_ITEM
RJK0384DPA
R9580
FB_1V8_S0_VBST
PP5V_S0
1.35 / 1.55 V
1.80 V
20%
10V
X5R 2
603
EG_RAIL4_EN
IN
FB_1V8_S0_VFB
FB1V55
FB_1V8_S0_TRIP
R9589 1
1K
PGOOD 1
2.2UH-8.0A
G2
0.1UF
10%
50V
X7R
2 603-1
DRVH 9
2
PCMB065T-SM
S2
PM_ALL_GPU_PGOOD
2
SW 8
5 TRAN
DRVL 6
OUT
8 73 82 86 87
DIDT=TRUE
PP1V8R1V55_S0GPU_ISNS_R 6
Vout = 1.806V
10UF
7 50
7A max output
(Q9560 limit?)
f = 340 kHz
FB_1V8_S0_LL
SWITCH_NODE=TRUE DIDT=TRUE
C9565
20%
2 6.3V
X5R
603
XW9565
SM
FB_1V8_S0_DRVH
GATE_NODE=TRUE
2 TRIP
FB_1V8_S0_TRAN
CRITICAL
C9560
330UF
C9586
FB_1V8_S0_VFB_R
Q9581
FB1V55
D 3
R9588
SOD-VESM-HF
13K
1%
1/16W
MF-LF
2 402
80 79
3 EN
353S2739
FBVDD_ALTVO
DSC
4 VFB
1%
1/16W
MF-LF
402
L9560
CRITICAL
CRITICAL
6
TPS51217
P1V8FB_EN_R
5%
1/16W
MF-LF
402
51.1K
U9500
R9587
87 73 72
SSM3K15FV
152S0518
S1/D2
10UF
WPAK
G1
R9585
40.2K
47PF
CERM
5%
50V
402
20%
2.0V
POLY-TANT 2
B2-SM
FB_1V8_S0_DRVL
THRM
PAD
GATE_NODE=TRUE
DIDT=TRUE
11
V5IN 7
C9501
Regulator Output
FB_1V8_S0_VBST_RC
C9580
FB VDD
FBVDD_ALTVO
5%
1/16W
MF-LF
402
VBST 10
70 69 68 54 52 47 42 23 7 6
88 86 72
CRITICAL
Q9560
D1
QTY
114S0336
PART#
PPBUS_G3H
CRITICAL
82 70 69 67 66 65 49 40 7 6
89
TABLE_5_HEAD
FB_1V8_S0_VFB_XW
1%
1/16W
MF-LF
2 402
FB_1V8_S0_TRAN_R
R9586
R9571
1K
S 2
20.5K
5%
1/16W
MF-LF
2 402
IN
GND
1%
1/16W
MF-LF
2 402
(GND)
C9570
1000PF
5%
25V
402
2 NP0-C0G
(FB_1V8_S0_VFB)
PAGE TITLE
1V8 / 1V55 FB Power Supply

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
95 OF 132
SHEET
86 OF 101
8
87 85 84
68 63 62
48 47 46
28 27 26
19 18 17 7
24 23 21
40 37 34
54 52 51
80 73 72
99
83
58
42
25
6
20
30
50
69
88
PP3V3_S0
C9610
0.1UF
C9621
C9622
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C9623
0.1UF
C9624
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C9625
0.1UF
20%
2 10V
CERM
402
C9626
0.1UF
20%
2 10V
CERM
402
C9627
0.1UF
20%
2 10V
CERM
402
C9628
0.1UF
20%
2 10V
CERM
402
PP1V8_S0
C9629
VOLTAGE=3.3V
0.1UF
20%
2 10V
CERM
402
5%
1/16W
MF-LF
402
C9611
0.1UF
C9612
0.1UF
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
C9613
C9614
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
C9615
0.1UF
C9616
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
93 87 18
93 87 18
R9612
2
93 87 18
5%
1/16W
MF-LF
402
L9621
VOLTAGE=3.3V
C9617
93 87 18
93 87 18
0.1UF
20%
2 10V
CERM
402
98 87 81
98 87 81
98 87 81
FERR-220-OHM
PP3V3R1V8_S0_GMUX_LRC_VCCPLL
PP1V2_S0
VOLTAGE=3.3V
C9600 1
4.7UF
20%
4V
X5R 2
402
C9604
0.1UF
C9605
0.1UF
20%
10V
2 CERM
402
C9606
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
C9607
0.1UF
20%
10V
2 CERM
402
C9608
0.1UF
20%
2 10V
CERM
402
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_P<2>
98 87 81
98 87 81
0402
LVDS_EG_A_CLK_P
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_P<2>
98 87 81
L9620
72 7 6
98 87 81
C9609
20%
10V
2 CERM
402
0.1UF
20%
2 10V
CERM
402
GMUX_CFG0
10K
88 87 6
OUT
87 84
OUT
87 84
OUT
84
OUT
1%
1/16W
MF-LF
2 402
OUT
OUT
OUT
87 73 72
OUT
87 82 73
OUT
87 86 73 72
OUT
17 8
OUT
80
OUT
87 83
OUT
CRITICAL
J9600
BI
94 47 45 17 6
BI
94 47 45 17 6
BI
94 47 45 17 6
BI
17 6
50 51 52 54 58 62 63 68 69 72 47 45 94
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48 94 47 27 6
73 80 83 84 85 87 88 99
BI
1909782
M-RT-SM
7
GMUX_JTAG_CONN
1
2
3
4
PP3V3_S0
JTAG_GMUX_TDO
JTAG_GMUX_TDI
JTAG_GMUX_TMS
IN
27
IN
20
OUT
19 87
19 87
5
6
JTAG_GMUX_TCK
93 87 18
IN
93 87 18
IN
20 25 87
R96471
10K
1%
1/16W
MF-LF
402 2
IN
IN
IN
93 87 18
IN
93 87 18
IN
93 87 18
IN
93 87 18
IN
93 87 18
IN
93 87 18
IN
93 87 18
IN
93 87 18
93 87 18
8
IN
IN
OUT
88 87
IN
88 87
86 82 73 8
IN
74 8
IN
(Tie/strap low if EGPU doesnt provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)
K12
PT9B
PB27B
PB28A
PB28B
PP3V3_S0
PT14A
PT14B
PT15A
PT15B
PT16A
PT16B
PT17A
PT17B
PT18A
PT18B
PT19A
PT19B
PT20A
PT20B
PT28A
PT28B
PL2A
PL2B
PR2A
PR2B
PL6A
PR6A
PL6B
PR6B
PL7A
PL7B
PR7A
PR7B
PL8A
PR8A
PL8B
PL9A
PR8B
PR9A
PR9B
PL9B
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
PL14A
PL14B
PL15A
PL15B
PL25A
PL25B
PR10A
PR10B
PR11A
PR11B
PR12A
PR12B
PR14A
PR14B
PR24A
PR24B
A2
A3
A1
B3
C5
A5
B6
C7
A6
A7
C8
C9
A8
B9
A9
C10
B10
A10
A11
B12
B13
A13
LVDS_B_DATA_P<0>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_N<1>
LVDS_B_DATA_P<2>
LVDS_B_DATA_N<2>
EG_PWRSEQ_EN
GMUX_DEBUG_RESET_L
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_A_DATA_P<0>
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_N<1>
LVDS_A_DATA_P<2>
LVDS_A_DATA_N<2>
GND
GND
GND
GND
A14
B14
D12
D13
D14
E14
E12
F12
F14
G14
G12
G13
H13
H12
H14
J12
L14
M13
N14
N13
DP_CA_DET
DP_HOTPLUG_DET
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_N<2>
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_DATA_N<2>
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_IG_PANEL_PWR
EG_LCD_PWR_EN
LVDS_IG_BKL_ON
EG_BKLT_EN
101 73
17 8 7 6
72 55 54 53 50 48 36 35 34 33 32 31 20
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
100
100
100
R9660
R9661
R9662
R9663
R9664
R9665
R9666
2
2
402
1/16W
MF-LF
402
1/16W
MF-LF
402
1/16W
MF-LF
402
1/16W
MF-LF
402
1/16W
MF-LF
402
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>
PLACE_NEAR=U9600.J12:5mm LVDS_EG_A_CLK_N
1%
1/16W MF-LF 402
PLACE_NEAR=U9600.D13:5mm LVDS_EG_A_DATA_N<0>
1%
1/16W MF-LF 402
PLACE_NEAR=U9600.E14:5mm LVDS_EG_A_DATA_N<1>
1%
1/16W MF-LF 402
PLACE_NEAR=U9600.F12:5mm LVDS_EG_A_DATA_N<2>
1/16W
MF-LF
402
LVDS_EG_B_DATA_N<0>
PLACE_NEAR=U9600.G13:5mm LVDS_EG_B_DATA_N<1>
1%
1/16W MF-LF 402
PLACE_NEAR=U9600.H12:5mm LVDS_EG_B_DATA_N<2>
402
PLACE_NEAR=U9600.G3:5mm
1%
1%
1
MF-LF
1%
1%
EG_PWRSEQ_EN
R9684
1K
OUT
87 84
87 84
87 84
84 98
IN
87
IN
87
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
18 87 93
18 87 93
18 87 93
18 87 93
18 87 93
18 87 93
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
PP3V3_S0
10K
1%
1/16W
MF-LF
402 2
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
OUT
84 98
IN
80 84 85
IN
84 85
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
81 87 98
IN
8 18
IN
79 80
IN
8 18
IN
79 80
R9676
10K
LVDS_DDC_SEL_IG
R9682
10K
LVDS_DDC_SEL_EG
R9683
10K
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
87 83
NO STUFF
87 74 8
EG_RESET_L
R9691
100K
88 87 6
LCD_BKLT_PWM
R9693
100K
87 86 73
EG_RAIL1_EN
87 73 72
EG_RAIL2_EN
87 82 73
EG_RAIL3_EN
87 86 73 72
EG_RAIL4_EN
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
LCD_PWR_EN
1
R9672
R9674
4.7K
4.7K
4.7K
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
402 2
4.7K
5%
1/16W
MF-LF
2402
1
R9671
R9678 1
5%
1/16W
MF-LF
402
R9673 2
4.7K
5%
1/16W
MF-LF
2402
GMUX_S3_PD_GND
Q9607
1
R9681
DP_MUX_SEL_EG
D 3
NO STUFF
1
SSM6N15FEAPE
R9675
SOT563
100K
5%
1/16W
MF-LF
2402
5 G
5%
1/16W
MF-LF
2402
S 4
GMUX_S3_PD_EN
R9670
SYNC_MASTER=K17_REF
10K
Q9607
1%
1/16W
MF-LF
2 402
PAGE TITLE
D 6
Graphics MUX (GMUX)
SSM6N15FEAPE
SOT563
GMUX_VSYNC 87
18 87 93
(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rails source is valid)
PP3V3_S3
NO STUFF
DRAWING NUMBER
Apple Inc.
88
2 G
73 45 27 25
MF-LF
1K
100
100
100
100
1%
1%
1/16W
A4
P11
ULC_VCCPLL
LRC_VCCPLL
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
PT9A
J1
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
VCCIO1
PT8A
PT8B
GND
B5
B7
A12
C14
F13
M12
M9
M3
N5
M1
C3
F2
C11
J2
J14
M8
PT7B
PB14A
PB14B
PB15A (OD)
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PB18B (OD)
PB19A
PB19B
PB20A
PB20B
BANK6
27
B1
B2
C2
D3
D1
E1
D2
E3
F1
G1
F3
G2
H2
G3
H1
H3
L1
L3
K3
L2
N1
P1
1/16W
1%
Required Pulldowns
PT7A
CSBGA
BANK7
NO STUFF
93 87 18
93 87 18
93 87 18
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
GMUX_PL10A
TP_GMUX_PL10B
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
TP_LVDS_MUX_SEL_EG
GMUX_VSYNC
GMUX_RESET_L
GMUX_VSYNC
PM_ALL_GPU_PGOOD
PEX_CLKREQ_L
100
100
100
PLACE_NEAR=U9600.H3:5mm
1%
R96791
PB7B
PB27A
R9680
SILK_PART=GMUX_RST
XP25-5
PB26A
PB26B
GMUX_DEBUG_RESET_L
U9600
BANK4
94 47 45 17 6
PB7A
BANK5
87 84
87 74 8
87 86 73
CFG0
P2
N2
P4
N4
N3
M4
P5
M5
P6
M6
P7
M7
N7
N8
P9
N9
P10
M10
P12
P13
N12
P14
BANK0
10K
1%
1/16W
MF-LF
402 2
K1
BANK1
R9646
LCD_BKLT_EN
LCD_BKLT_PWM
LVDS_DDC_SEL_EG
LVDS_DDC_SEL_IG
DP_MUX_EN
DP_MUX_SEL_EG
EG_RESET_L
EG_RAIL1_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL4_EN
PEG_CLKREQ_L
DP_CA_DET_EG
LCD_PWR_EN
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
LPCPLUS_RESET_L
LPC_CLK33M_GMUX
GMUX_INT
BANK2
OUT
BANK3
R96411
89 8
ULC_GNDPLL
LRC_GNDPLL
NO STUFF
NO STUFF
B4
M11
NO STUFF
GNDIO7
VCCJ
OMIT
CRITICAL
GNDIO6
87 19
GNDIO5
87 20
VCCIO0
87 19
GNDIO3
GNDIO4
1%
1/16W
MF-LF
2 402
VCCAUX
TCK
TDI
TDO
TMS
TOE
GNDIO2
1%
1/16W
MF-LF
402 2
K14
L13
K13
L12
K2
GNDIO1
10K
JTAG_GMUX_TCK
JTAG_GMUX_TDI
JTAG_GMUX_TDO
JTAG_GMUX_TMS
GMUX_TOE
GNDIO0
10K
87 25 20
B8
C6
C12
C13
E13
M14
N10
N6
P3
M2
C1
E2
R9645
Required Pullups
87
VCC
1
SIGNAL_MODEL=EMPTY
PP3V3_S0
R96401
0.1UF
B11
C4
J3
J13
N11
P8
87
54
28
6
21
46
72
100
100
100
100
C9630
87
99 88
69 68 63 62 58
42 40 37 34 30
20 19 18 17 7
27 26 25 24 23
52 51 50 48 47
85 84 83 80 73
R9650
R9651
R9652
R9653
R9654
R9655
R9656
0402
C9631
0.1UF
20%
10V
2 CERM
402
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<2>
93 87 18
FERR-220-OHM
PP3V3R1V8_S0_GMUX_ULC_VCCPLL
VOLTAGE=1.8V
LVDS_IG_A_CLK_P
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2>
93 87 18
GMUXPLL_3V3
1
PP3V3R1V8_S0_GMUX
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
99
88 87
80 73
63 62
51 50
42 40
28 27
23 21
17 7 6
20 19 18
26 25 24
37 34 30
48 47 46
58 54 52
72 69 68
85 84 83
PP3V3_S0
PP1V8_S0_GMUX_R
R9610
87 72 71
16 12 7 6
58 24 23 21
LVDS Receiver Termination
R9611
PP1V8_S0
PP3V3_S0_GMUX_R
1
GMUXPLL_1V8
72 71 58 24 23 21 16 12 7 6
87
0.1UF
20%
2 10V
CERM
402
GMUX CPLD
5%
1/16W
MF-LF
402
R9600
IN
S 1
ALL_SYS_PWRGD

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
96 OF 132
SHEET
87 OF 101
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
*PPVOUT_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
D
R9701
PP5V_S0
70 69 68 54 52 47 42 23 7 6
86 72
5%
1/16W
MF-LF
402
VOLTAGE=5V
1
R9702
0
5%
1/16W
MF-LF
2 402
CRITICAL
89 88
PPBUS_S0_LCDBKLT_PWR
CRITICAL
L9701
XW9700
SM
D9701
SOD-123
22UH-2.5A
PPVIN_BKL
CRITICAL
1
C9712
VOLTAGE=8.4V
C9713
IHLP2525CZ-SM
0.1UF
10UF
NO STUFF
10%
2 25V
X5R
402
10%
2 25V
X5R
805
PPBUS_S0_LCDBKLT_PWR_SW
VOLTAGE=50V
SWITCH_NODE=TRUE
PPVOUT_S0_LCDBKLT
CRITICAL CRITICAL
RB160M-60G
1
C9796
220PF
R9703
10%
2 50V
X7R-CERM
402
5%
1/16W
MF-LF
2 402
C9797
10UF
10%
50V
2 X5R
1210-1
6 56 83
VOLTAGE=50V
C9799
10UF
10%
50V
2 X5R
1210-1
BKL_VLDO
PPVIN_BKL_R
PP3V3_S0
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 87 85 84 83 80 73 72 69
1
C9714
0.01UF
C9710
1UF
10%
2 16V
CERM
402
10%
2 25V
X5R
603-1
C9711
0.1UF
10%
2 16V
X5R
402
NO STUFF
C9741
1UF
VOLTAGE=5V
10%
6.3V
X5R
402
47.0K2
20%
6.3V
X5R
603
BKL_FLTR_RC
VDDIO
10K
BKL_FSET
5%
1/16W
MF-LF
402
BKL_FLTR
BKL_ISET
2
5%
301K
NO STUFF
1
OUT2
13
BKL_ISEN2
OUT3
14
BKL_ISEN3
BKL_SDA
11 SDA
OUT4
16
BKL_ISEN4
2 PWM
OUT5
17
BKL_ISEN5
TP_BKL_FAULT
7 FAULT
OUT6
18
BKL_ISEN6
BKLT_EN
4 EN
VSYNC
19
C9723
0.1UF
10%
25V
2 X5R
402
R9715
100K
1%
1/16W
MF-LF
402
(EEPROM should set EN_I_RES=1)
R97141
16.2K
R9704
IN
BKL_ISEN1
LCD_BKLT_PWM
R9704 SHOULD BE 47K IF RC FILTER IS USED
R97161
90.9K
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
I_LED=23.2Ma
I_LED=369/Riset
NO STUFF
1
R9755
10K
5%
1/16W
MF-LF
2 402
THRM
PAD
1
R9754
BKL_SGND
LED_RETURN_2
5%
1/16W
MF-LF
2 402
10.2 2
LED_RETURN_3
0.1%
1/16W
TF
402
6 83
OUT
6 83
OUT
6 83
OUT
6 83
OUT
6 83
OUT
6 83
R9720
1
10.2 2
LED_RETURN_4
0.1%
1/16W
TF
402
R9721
1
XW9710
SM
33PF
10.2 2
0.1%
1/16W
TF
402
C9704
OUT
R9719
Fpwm=9.62KhZ
details in spec
5%
50V
2 CERM
402
LED_RETURN_1
R9718
BKL_VSYNC_R
1
10.2 2
0.1%
1/16W
TF
402
NO STUFF
1%
1/16W
MF-LF
402 2
87 6
OUT1
R9717
1%
1/16W
MF-LF
402
89 88
21
12
3 ISET
1/16W MF-LF 402
R9731
24
FB
10 SCLK
LVDS_BKL_PWM_RC
5%
SW
BKL_SCL
1/16W MF-LF 402
CRITICAL
25
R9757
20 FILTER
15 GND_L
SMBUS_PCH_DATA
5 FSET
9 GND_S
48 47 42 32 30 28 26 25 17
94 63
R9753
SMBUS_PCH_CLK
6 GD
1 GND_SW
63 48 47 42 32 30 28 26 25 17
94
VIN
LLP
NC
VLDO
U9701
1%
1/16W
MF-LF
402
R9741
1
23
R9740
22
10UF
LP8545SQX
C9740
NO STUFF
8
NO STUFF
10.2 2
LED_RETURN_5
0.1%
1/16W
TF
402
R9722
1
GMUX_VSYNC
IN
10.2 2
LED_RETURN_6
0.1%
1/16W
TF
402
87
SYNC_MASTER=K18_BKLT
PAGE TITLE
LCD BACKLIGHT DRIVER

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
97 OF 132
SHEET
88 OF 101
CRITICAL
Q9806
FDC638APZ_SBMS001
CRITICAL
1 2 5 6
F9800
IN
2
0402-HF
PPBUS_S0_LCDBKLT_FUSED
VOLTAGE=12.6V
R9808
301K
C9802
0.1UF
1%
1/16W
MF-LF
2 402
MOSFET
FDC638APZ
CHANNEL
P-TYPE
RDS(ON)
LOADING
10%
16V
2 X5R
402
43 mOhm @4.5V
0.4 A (EDP)
PPBUS_G3H
2AMP-32V
82 70 69 67 66 65 49 40 7 6
86
PPBUS S0 LCDBkLT FET
SSOT6-HF
PBUS_S0_LCDBKLT_EN_DIV
R9809
147K
1%
1/16W
MF-LF
2 402
PBUS_S0_LCDBKLT_EN_L
Q9807
D 3
SSM6N15FEAPE
SOT563
89 87 8
IN
5 G
LCD_BKLT_EN
S 4
OUT
VOLTAGE=12.6V
BKLT_EN_L
Q9807
88
D 6
SSM6N15FEAPE
SOT563
C
27
IN
2 G
BKLT_PLT_RST_L
S 1
LCD_BKLT_EN 8
87 89
R9840
4.7K
5%
1/16W
MF-LF
2 402
SYNC_MASTER=K19_MLB
PAGE TITLE
LCD Backlight Support

DRAWING NUMBER
Apple Inc.
R
<E4LABEL>

SIZE
<SCH_NUM> D
REVISION
BRANCH
<BRANCH>
PAGE
98 OF 132
SHEET
89 OF 101
Blank Page, was 1.2V/1.8V in K19
PAGE TITLE
Misc Power Supplies

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
99 OF 132
SHEET
90 OF 101
CPU Signal Constraints
CPU Net Properties

TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
CPU_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CPU_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
PHYSICAL
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
CPU_AGTL
DMI_S2N
DMI_S2N
DMI_N2S
DMI_N2S
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
FDI_DATA
FDI_DATA
PCIE_85D
PCIE_85D
CPU_50S
CPU_50S
PCIE
PCIE
CPU_AGTL
CPU_AGTL
FDI_DATA_P<7:0>
FDI_DATA_N<7:0>
FDI_FSYNC<1..0>
FDI_LSYNC<1..0>
CPU_50S
CPU_AGTL
FDI_INT
CPU_PECI
FSB_CPURST_L
PM_SYNC
PM_MEM_PWRGD
CPU_50S
CPU_50S
CPU_50S
CPU_50S
PCIE
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_PECI
FSB_CPURST_L
PM_SYNC
PM_MEM_PWRGD
CPU_VTT_S0_PGOOD
XDP_XPU_PWRGOOD
XDP_BDRESET_L
CPU_50S
CPU_50S
CPU_50S
CPU_AGTL
CPU_ITP
CPU_ITP
CPUVTTS0_PGOOD
XDP_CPUPWRGD
XDP_DBRESET_L
XDP_PRDY_L
XDP_PREQ_l
CPU_50S
CPU_50S
CPU_ITP
CPU_ITP
XDP_PRDY_L
XDP_PREQ_L
CPU_50S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_50S
CPU_50S
CPU_50S
CPU_AGTL
CPU_AGTL
CPU_COMP
CPU_COMP
CPU_COMP
CPU_ITP
CPU_AGTL
CPU_AGTL
PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
CPU_SM_RCOMP0
CPU_SM_RCOMP1
CPU_SM_RCOMP2
CPU_CFG<17..0>
CPU_CATERR_L
TP_CPU_VTT_SELECT
CPU_PROCHOT_L
CPU_PWRGD
CPU_50S
CPU_50S
CPU_AGTL
CPU_AGTL
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
PM_THRMTRIP_L
FSB_CLK_CPU
FSB_CLK_CPU
FSB_CLK_ITP
FSB_CLK_ITP
PCIE_CLK100M_CPU
PCIE_CLK100M_CPU
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
FSB_CLK133M_CPU_P
FSB_CLK133M_CPU_N
FSB_CLK133M_ITP_P
FSB_CLK133M_ITP_N
PCIE_CLK100M_CPU_P
PCIE_CLK100M_CPU_N
PM_DPRSLPVR
CPU_55S
CPU_50S
CPU_8MIL
CPU_AGTL
CPU_PSI_L
PM_DPRSLPVR
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_PEG_COMP
CPU_PEG_RBIAS
CPU_COMP3
CPU_COMP2
CPU_COMP1
CPU_COMP0
(FSB_CPURST_L)
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<6..0>
XDP_BPM_L<7>
XDP_CPURST_L
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_55S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_8MIL
CPU_AGTL
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VID<6..0>
CPUIMVP_IMON
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VTTSENSE_P
CPU_VTTSENSE_N
CPU_27P4S
CPU_27P4S
CPU_55S
CPU_50S
CPU_50S
CPU_50S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
GFX_VSENSE_P
GFX_VSENSE_N
GFX_VID<6..0>
GFX_DPRSLPVR
GFX_VR_EN
GFXIMVP_IMON
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>
CPU_AGTL
TOP,BOTTOM
9 18
9 18
9 18
9 18
9 18
9 18
9 18
9 18
CPU_8MIL
8 MIL
9 18
CPU_COMP
20 MIL
CPU_ITP
=2:1_SPACING
CPU_VCCSENSE
25 MIL
Most CPU signals with impedance requirements are 50-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.
SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8
PCI-Express
10 20
10 25
10 18
10 18 31
10 70
10 25
10 25 27
10 25
10 25
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_CFG
CPU_CATERR_L
CLK_PCIE_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=3X_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
=4X_DIELECTRIC
PCIE
PCIE
TOP,BOTTOM
10 46
10 46
10
10
10
8 9 25
10
8 12
CLK_PCIE
20 MIL
SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.1 and Table 4-184.
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L
XDP_BPM_L
CPU_VCCSENSE
CPU_VCCSENSE
PM_DPRSLPVR
PEG_R2D
PEG_D2R
10 46 68
10 20 25
10 20 46
10 20
10 20
10 25
10 25
10 17
10 17
12 15 68
12 15 68
9
9
10
10
10
10
25
25
10 25
10 25
10 25
10 25
10 25
25
8 12 15
12 50 68
12 68
12 68
12 70
12 70
13 69
13 69
8 13
13 69
13 69
13 69
74
74
8 9 74
8 74
8 9 74
8 74
74
74
SYNC_MASTER=K17_REF
PAGE TITLE
CPU Constraints
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
100 OF 132
SHEET
91 OF 101
Memory Bus Constraints
Memory Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_37S
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=STANDARD
=STANDARD
MEM_40S
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MEM_A_CLK
MEM_A_CLK
MEM_72D
MEM_72D
MEM_CLK
MEM_CLK
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
MEM_A_CNTL
MEM_A_CNTL
MEM_A_CNTL
MEM_37S
MEM_37S
MEM_37S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK
MEM_B_CLK
MEM_72D
MEM_72D
MEM_CLK
MEM_CLK
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CNTL
MEM_B_CNTL
MEM_B_CNTL
MEM_37S
MEM_37S
MEM_37S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
DQ/DM signals should be matched within 0.508mm of associated DQS pair.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
11 28
11 28
MEM_72D
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
MEM_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
11 28
11 28
11 28
MEM_85D
SPACING_RULE_SET
LAYER
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
WEIGHT
MEM_CLK2MEM
=4:1_SPACING
11 28
11 28
11 28
11 28
11 28
MEM_CTRL2CTRL
=3:1_SPACING
MEM_CTRL2MEM
=2.5:1_SPACING
MEM_CMD2CMD
=1.5:1_SPACING
?
MEM_CMD2MEM
=3:1_SPACING
MEM_DATA2DATA
=1.5:1_SPACING
MEM_DATA2MEM
=3:1_SPACING
11 29
11 29
11 29
11 29
11 28 29
11 29
11 29
11 29
MEM_DQS2MEM
=3:1_SPACING
MEM_2OTHER
25 MILS
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
MEM_CLK2MEM
MEM_CMD
MEM_CLK
MEM_CMD2MEM
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_CMD
MEM_DATA
MEM_CMD2MEM
MEM_DQS
MEM_CLK2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CMD
MEM_DQS
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
MEM_CTRL2MEM
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_CTRL
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
MEM_DQS2MEM
MEM_DATA
MEM_DQS
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_2OTHER
MEM_CTRL
MEM_DQS2MEM
MEM_CTRL
MEM_2OTHER
MEM_DQS
MEM_CMD
MEM_DQS2MEM
MEM_CMD
MEM_2OTHER
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_DQS
MEM_DQS
MEM_DQS2MEM
MEM_DATA
MEM_2OTHER
MEM_DQS
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR3:
11 29
11 29
11 29
11 29
11 29
11 29
11 28 29
11 28 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 30
11 30
MEM_DQS
11 29
MEM_CLK
11 28 29
11 30
11 30
11 30
11 30
11 30
11 30
11 30
11 30
11 29
11 29
11 29
11 29
11 29 30
11 29
11 29
11 29
11 29 30
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29 30
11 29 30
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
SYNC_MASTER=K17_REF
PAGE TITLE
Memory Constraints
11 29
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
101 OF 132
SHEET
92 OF 101
Digital Video Signal Constraints

LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
DP_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
LVDS_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
=3x_DIELECTRIC
LVDS
=3x_DIELECTRIC
NET_TYPE
PHYSICAL
SPACING
DP_ML
DP_ML
DP_AUX_CH
DP_AUX_CH
DP_85D
DP_85D
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
LVDS_IG_A_CLK
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_IG_A_DATA3
LVDS_IG_A_DATA3
LVDS_IG_B_CLK
LVDS_IG_B_CLK
LVDS_IG_B_DATA
LVDS_IG_B_DATA
LVDS_IG_B_DATA3
LVDS_IG_B_DATA3
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_B_CLKN
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
SATA_HDD_R2D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA_HDD_R2D_C_P
17 42
SATA_HDD_R2D_C_N
17 42
SATA_HDD_R2D_P
6 42
SATA_HDD_R2D_N
6 42
SATA_HDD_D2R_P
17 42
SATA_HDD_D2R_N
17 42
SATA_HDD_D2R_C_P
6 42
SATA_HDD_D2R_C_N
6 42
SATA_ODD_R2D_C_P
17 42
SATA_ODD_R2D_C_N
17 42
SATA_ODD_R2D_P
6 42
SATA_ODD_R2D_N
6 42
SATA_ODD_D2R_P
17 42
SATA_ODD_D2R_N
17 42
SATA_ODD_D2R_C_P
6 42
SATA_ODD_D2R_C_N
6 42
SATA_HDD_R2D_RDRV_IN_P 42
SATA_HDD_R2D_RDRV_IN_N 42
SATA_HDD_R2D_RDRV_OUT_P 42
SATA_HDD_R2D_RDRV_OUT_N 42
SATA_HDD_D2R_RDRV_IN_P 42
SATA_HDD_D2R_RDRV_IN_N 42
SATA_HDD_D2R_RDRV_OUT_P 42
SATA_HDD_D2R_RDRV_OUT_N 42
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
SATA_ICOMP
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
PCH_SATAICOMP
USB_HUB1_UP_P
USB_HUB1_UP_N
USB_HUB2_UP_P
USB_HUB2_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_P
USB_EXTB_N
USB_EXTC_P
USB_EXTC_N
USB_EXTD_P
USB_EXTD_N
USB_MINI_P
USB_MINI_N
USB_WM_P
USB_WM_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_SDCARD_P
USB_SDCARD_N
USB_BRCRYPT_P
USB_BRCRYPT_N
8 84
8 84
8 18 84
8 18 84
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
PCH Net Properties
PHYSICAL_RULE_SET
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
SATA Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SATA_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
18 87
18 87
18 87
18 87
8 18
8 18
6 8 18
6 8 18
18 87
18 87
8 18
8 18
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
=3x_DIELECTRIC
SATA
=4x_DIELECTRIC
SATA
TOP,BOTTOM
SATA_HDD_D2R
SATA_ICOMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
USB 2.0 Interface Constraints
SATA_ODD_R2D
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCH_USB_RBIAS
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
SPACING_RULE_SET
LAYER
SATA_ODD_D2R
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
=4x_DIELECTRIC
USB
=2x_DIELECTRIC
SATA_HDD_R2D
USB
TOP,BOTTOM
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8
SATA_HDD_D2R
PCH_SATA_ICOMP
USB_HUB1_UP
USB_HUB2_UP
USB_EXTA
USB_EXTB
USB_EXTC
USB_EXTD
USB_MINI
USB_WM
USB_CAMERA
USB_BT
USB_TPAD
USB_IR
USB_SDCARD
USB_BRCRYPT
PCH_USB_RBIAS
PCH_USB_RBIAS
PCH_USB_RBIAS
PCH_CLK100M_PCH
PCH_CLK100M_SATA
PCH_CLK100M_SATA
GFX_CLK_DPLLSS
GFX_CLK_DPLLSS
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CPU_50S
CPU_50S
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
FSB_CLK133M_PCH_P
FSB_CLK133M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
17
19 35
19 35
19 36
19 36
36 43
36 43
35 43
35 43
8 35
8 35
6 33
6 33
33 36
33 36
36 53
36 53
35 44
35 44
8 34 36
8 34 36
19 101
19 101
19
17 26
17 26
17 26
17 26
17 26
17 26
17 26
17 26
17 26
17 27
10 17
10 17
SYNC_MASTER=K17_REF
PAGE TITLE
PCH Constraints 1
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
102 OF 132
SHEET
93 OF 101
LPC Bus Constraints

LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
LPC_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
PCH Net Properties
PHYSICAL_RULE_SET
4
NET_TYPE
PHYSICAL
SPACING
SPACING_RULE_SET
LAYER
WEIGHT
6 MIL
LPC
LPC_AD
LPC_FRAME_L
LPC_RESET_L
LPC_50S
LPC_50S
LPC_50S
LPC
LPC
LPC
LPC_AD<3..0>
LPC_FRAME_L
LPCPLUS_RESET_L
MCP_LPC_CLK0
CLK_LPC_50S
CLK_LPC_50S
CLK_LPC_50S
CLK_LPC
CLK_LPC
CLK_LPC
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_PCH_1_CLK
SMBUS_PCH_1_DATA
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB
SMB
SMB
SMB
SMB
SMB
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
HDA_BIT_CLK
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R
PM_SUS_CLK
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK
SPI_CLK
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
CONN_PCIE_AP_D2R_P
CONN_PCIE_AP_D2R_N
CONN_PCIE_AP_R2D_P
CONN_PCIE_AP_R2D_N
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
PEG_CLK100M_P
17
PEG_CLK100M_N
17
PCIE_CLK100M_ENET_P
17
PCIE_CLK100M_ENET_N
17
PCIE_CLK100M_AP_P
17
PCIE_CLK100M_AP_N
17
PCIE_CLK100M_FW_P
17
PCIE_CLK100M_FW_N
17
NC_PCIE_CLK100M_EXCARD_P
NC_PCIE_CLK100M_EXCARD_N
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<5>
TP_PCH_VSS_NCTF<7>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<22>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>
CLK_LPC
8 MIL
SMBus Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SMB_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
HDA_SYNC
SMB
=2x_DIELECTRIC
HDA_RST_L
HD Audio Interface Constraints
HDA_SDIN0
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
HDA_SDOUT
HDA_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
6 17 45 47 87
6 17 45 47 87
6 27 47 87
19 27
27 45
6 27 47
17 25 26 28 30 32 42 47 48 63
88
17 25 26 28 30 32 42 47 48 63
88
17 48
17 48
17 48
17 48
17 58
17
17 58
17
17
17 58
17 58
58
17 58
17
18 46
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
HDA
SPI_MOSI
SIO Signal Constraints
SPI_MISO
SPI_CS0
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
17 47
47
17 47
47
17 47
17 47
47
CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PCIE_ENET_R2D
SPACING_RULE_SET
LAYER
WEIGHT
CLK_SLOW
8 MIL
PCIE_ENET_D2R
SPI Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PCIE_AP_R2D
PCIE_AP_D2R
SPACING_RULE_SET
LAYER
WEIGHT
37
37
17 37
17 37
17 37
17 37
37
37
6 33
6 33
17 33
17 33
6 17 33
6 17 33
SPI
8 MIL
PCIE_FW_R2D
PCIE_FW_D2R
PCIE_AP_D2R
PCIE_AP_R2D
B
MCP_PE0_REFCLK
PCIE_CLK100M_ENET
MCP_PE1_REFCLK
MCP_PE2_REFCLK
MCP_PE3_REFCLK
I235
I236
I237
I238
I239
I240
I241
I242
I243
I244
I245
I246
I247
I248
I249
I250
39
39
17 39
17 39
17 39
17 39
39
39
B
74
74
37
37
33
33
39
39
8 17
8 17
6 20
6 20
6 20
20
6 20 94
6 20 94
6 20
6 20
6 20
6 20
6 20
6 20
20
6 20
SYNC_MASTER=K17_REF
PAGE TITLE
PCH Constraints 2
6 20
6 20
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
103 OF 132
SHEET
94 OF 101
CAESAR II (Ethernet) Constraints
Ethernet Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
SPACING_RULE_SET
LAYER
WEIGHT
ENET_50S
ENET_50S
ENET_50S
ENET_3X
ENET_3X
ENET_3X
ENET_RESET_L
ENET_100D
ENET_100D
ENET_MDI
ENET_MDI
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
27 37
27 37
27 37
ENET_3X
=3:1_SPACING
ENET_MDI
SOURCE: Broadcom 5764-DS04-RDS Page 38
37 38
37 38
CAESAR II (Ethernet PHY) Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
0.6 MM
ENET_MDI
SOURCE: Broadcom 5764-DS04-RDS Page 38
SYNC_MASTER=K17_REF
PAGE TITLE
Ethernet Constraints
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
104 OF 132
SHEET
95 OF 101
FireWire Interface Constraints
FireWire Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
FW_P0_TPA
FW_P0_TPA
FW_P0_TPB
FW_P0_TPB
FW_P1_TPA
FW_P1_TPA
FW_P1_TPB
FW_P1_TPB
SPACING_RULE_SET
LAYER
WEIGHT
FW_TP
=3:1_SPACING
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
NC_FW0_TPAP
NC_FW0_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
FW_PORT1_TPA_P
FW_PORT1_TPA_N
FW_PORT1_TPB_P
FW_PORT1_TPB_N
6 39 41
39 41
6 39 41
6 39 41
39 40 41
39 40 41
39 40 41
39 40 41
D
Port 2 Not Used
SYNC_MASTER=K17_REF
PAGE TITLE
FireWire Constraints
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
105 OF 132
SHEET
96 OF 101
SMC SMBus Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
PHYSICAL
SPACING
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
6 33 45 48 54
6 33 45 48 54
45 48 51
45 48 51
45 48 51 81
45 48 51 81
6 45 48 64 65
6 45 48 64 65
45 48 56
45 48 56
SMBus Charger Net Properties

NET_TYPE
PHYSICAL
SPACING
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO_P
CHGR_CSO_N
65
65
65
65
SYNC_MASTER=K17_REF
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
106 OF 132
SHEET
97 OF 101
GDDR3 Frame Buffer Signal Constraints
GDDR3 FB A/B Net Properties
GDDR3 FB C/D Net Properties
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

GDDR3_40R55SE
=55_OHM_SE
=40_OHM_SE
0.095 MM
12.7 MM
=STANDARD
=STANDARD
GDDR3_40SE
=40_OHM_SE
=40_OHM_SE
0.095 MM
=40_OHM_SE
=STANDARD
=STANDARD
=85_OHM_DIFF
=85_OHM_DIFF
0.095 MM
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
SPACING
GDDR3_CLK
GDDR3_CLK
GDDR3_CLK
GDDR3_CLK
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD_PD
FB_AB_CMD_PD
FB_AB_CS0
FB_AB_CMD_PD
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
FB_A_MA<1..0>
FB_A_MA<12..6>
FB_A_BA<2..0>
FB_A_RAS_L
FB_A_UCAS_L
FB_A_WE_L
FB_A_UCKE
FB_A_LCKE
FB_A_LCS0_L
FB_A_DRAM_RST
FB_A_CMD
FB_B_CMD
GDDR3_40SE
GDDR3_40SE
GDDR3_CMD
GDDR3_CMD
FB_A_LMA<5..2>
FB_A_UMA<5..2>
FB_A_WDQS0
FB_A_WDQS1
FB_A_WDQS2
FB_A_WDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_RDQS0
FB_A_RDQS1
FB_A_RDQS2
FB_A_RDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_DQ_BYTE0
FB_A_DQ_BYTE1
FB_A_DQ_BYTE2
FB_A_DQ_BYTE3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_A_DQ<7..0>
FB_A_DQ<15..8>
FB_A_DQ<23..16>
FB_A_DQ<31..24>
FB_A_DQM0
FB_A_DQM1
FB_A_DQM2
FB_A_DQM3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_B_WDQS0
FB_B_WDQS1
FB_B_WDQS2
FB_B_WDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
FB_B_RDQS0
FB_B_RDQS1
FB_B_RDQS2
FB_B_RDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>
FB_B_DQ_BYTE0
FB_B_DQ_BYTE1
FB_B_DQ_BYTE2
FB_B_DQ_BYTE3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_A_DQ<39..32>
FB_A_DQ<47..40>
FB_A_DQ<55..48>
FB_A_DQ<63..56>
FB_B_DQM0
FB_B_DQM1
FB_B_DQM2
FB_B_DQM3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>
PHYSICAL
GDDR3_80D
GDDR3_80D
GDDR3_80D
GDDR3_80D
FB_A_CLK
GDDR3_80D
NET_TYPE
NET_TYPE
FB_B_CLK
GDDR3_CLK
GDDR3_CLK
GDDR3_CLK
GDDR3_CLK
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD_PD
FB_CD_CMD_PD
FB_CD_CS0
FB_CD_CMD_PD
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
FB_B_MA<1..0>
FB_B_MA<12..6>
FB_B_BA<2..0>
FB_B_RAS_L
FB_B_UCAS_L
FB_B_WE_L
FB_B_UCKE
FB_B_LCKE
FB_B_LCS0_L
FB_B_DRAM_RST
FB_C_CMD
FB_D_CMD
GDDR3_40SE
GDDR3_40SE
GDDR3_CMD
GDDR3_CMD
FB_B_LMA<5..2>
FB_B_UMA<5..2>
FB_C_WDQS0
FB_C_WDQS1
FB_C_WDQS2
FB_C_WDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_C_RDQS0
FB_C_RDQS1
FB_C_RDQS2
FB_C_RDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_C_DQ_BYTE0
FB_C_DQ_BYTE1
FB_C_DQ_BYTE2
FB_C_DQ_BYTE3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_B_DQ<7..0>
FB_B_DQ<15..8>
FB_B_DQ<23..16>
FB_B_DQ<31..24>
FB_C_DQM0
FB_C_DQM1
FB_C_DQM2
FB_C_DQM3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_D_WDQS0
FB_D_WDQS1
FB_D_WDQS2
FB_D_WDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>
FB_D_RDQS0
FB_D_RDQS1
FB_D_RDQS2
FB_D_RDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_B_RDQS<4>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>
FB_D_DQ_BYTE0
FB_D_DQ_BYTE1
FB_D_DQ_BYTE2
FB_D_DQ_BYTE3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_B_DQ<39..32>
FB_B_DQ<47..40>
FB_B_DQ<55..48>
FB_B_DQ<63..56>
FB_D_DQM0
FB_D_DQM1
FB_D_DQM2
FB_D_DQM3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>
FB_AB_CMD
FB_CD_CMD
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_CMD
GDDR3_CMD
FB_A_LCAS_L
FB_B_LCAS_L
76 77
FB_D_CLK
76 77
SPACING
GDDR3_80D
GDDR3_80D
GDDR3_80D
GDDR3_80D
FB_C_CLK
76 77
PHYSICAL
76 77
76 78
76 78
76 78
76 78
SPACING_RULE_SET
LAYER
WEIGHT
GDDR3_CLK
=2.5:1_SPACING
GDDR3_CMD
=2.5:1_SPACING
GDDR3_DATA
=2.5:1_SPACING
GDDR3_DQS
=2.5:1_SPACING
Digital Video Signal Constraints
I205
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
I204
76 77
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
DIFFPAIR NECK GAP

DP_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
LVDS_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
76 77
76 77
76 78
76 78
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
=3x_DIELECTRIC
LVDS
=3x_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
LVDS intra-pair matching should be 0.127 mm. Pairs should be within 0.508mm of entire channel.
DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm.
DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.
Max length of LVDS/DisplayPort/TMDS traces: 13 inches.
SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
Max Length 241.3mm.
MUXGFX Net Properties
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
G96 Net Properties
I210
NET_TYPE
I148
I149
I199
I198
LVDS_A_CLK
LVDS_A_CLK
LVDS_A_DATA
LVDS_A_DATA
NET_TYPE
PHYSICAL
SPACING
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS
LVDS
LVDS
LVDS
LVDS_A_CLK_P
LVDS_A_CLK_N
84 87
(CK505_DOT96)
84 87
LVDS_A_DATA_P<2..0>
LVDS_A_DATA_N<2..0>
84 87
84 87
I206
I207
I152
I153
LVDS_B_CLK
LVDS_B_CLK
LVDS_85D
LVDS_85D
LVDS
LVDS
LVDS_B_CLK_P
LVDS_B_CLK_N
84 87
84 87
I208
I209
I201
I200
LVDS_B_DATA
LVDS_B_DATA
LVDS_85D
LVDS_85D
LVDS
LVDS
LVDS_B_DATA_P<2..0>
LVDS_B_DATA_N<2..0>
84 87
I142
84 87
I144
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
I183
I182
I184
I185
I190
I191
I192
I193
I194
I195
I196
I197
I161
DP_ML
I160
I155
DP_ML
I157
I202
DP_ML
I203
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
LVDS_CONN_A_CLK_F_P
6 83
LVDS_CONN_A_CLK_F_N
6 83
LVDS_CONN_B_CLK_F_P
6 83
LVDS_CONN_B_CLK_F_N
6 83
LVDS_CONN_A_CLK_P
83 84
LVDS_CONN_A_CLK_N
83 84
LVDS_CONN_A_DATA_P<2..0> 6 83
LVDS_CONN_A_DATA_N<2..0> 6 83
LVDS_CONN_B_CLK_P
83 84
LVDS_CONN_B_CLK_N
83 84
LVDS_CONN_B_DATA_P<2..0> 6 83
LVDS_CONN_B_DATA_N<2..0> 6 83
DP_ML_C_P<3..0>
DP_ML_C_N<3..0>
DP_ML_P<3..0>
DP_ML_N<3..0>
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
I145
I143
CK505_CLK27MSS
LVDS_EG_A_CLK
LVDS_EG_A_CLK
LVDS_EG_A_DATA
LVDS_EG_A_DATA
LVDS_EG_A_DATA3
LVDS_EG_A_DATA3
LVDS_EG_B_DATA
LVDS_EG_B_DATA
LVDS_EG_B_DATA3
LVDS_EG_B_DATA3
DP_ML
DP_ML
DP_AUX_CH
DP_AUX_CH
I139
I138
PHYSICAL
CLK_SLOW_55S
CLK_SLOW_55S
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
I211
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 77
76 78
SPACING
CLK_SLOW
CLK_SLOW
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
GPU_CLK27M
GPU_CLK27M_SS
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_P<2..0>
LVDS_EG_A_DATA_N<2..0>
LVDS_EG_B_DATA_P<2..0>
LVDS_EG_B_DATA_N<2..0>
DP_EG_ML_P<3..0>
DP_EG_ML_N<3..0>
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
DP_EG_AUX_CH_C_P
DP_EG_AUX_CH_C_N
27 79 80
79 80
81 87
81 87
81 87
81 87
80 81
80 81
81 87
81 87
80 81
80 81
81 84
81 84
81 84
81 84
84
84
84
84
84
84
85
SYNC_MASTER=K17_REF
85
PAGE TITLE
84 85
GPU (GT216) CONSTRAINTS
84 85
DRAWING NUMBER
85
85
Apple Inc.
I158
DP_AUX_CH
DP_AUX_CH
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DP_AUX_CH_C_P
DP_AUX_CH_C_N
<E4LABEL>
BRANCH
<BRANCH>
84 85

84 85
SIZE
<SCH_NUM> D
REVISION
I159
76 78
76 78
PAGE
107 OF 132
SHEET
98 OF 101
5
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
K18 Specific Net Properties
K18 Specific Net Properties
NET_TYPE
NET_TYPE
SENSE_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
THERM_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
PHYSICAL
SPACING
ENET_100D
ENETCONN
ENET_100D
ENETCONN
ENETCONN_P<3..0>
ENETCONN_N<3..0>
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
=1:1_DIFFPAIR
PHYSICAL
SPACING
38
38
DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
NET_SPACING_TYPE1
SPACING_RULE_SET
LAYER
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
WEIGHT
CPU_COMP
SENSE
=2:1_SPACING
THERM
=2:1_SPACING
GND
GND_P2MM
CPU_VCCSENSE
GND
GND_P2MM
42
42
42
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
PCIE_CLK100M_AP_CONN_P
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
USB_85D
USB
USB_85D
USB
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB_85D
USB
USB_85D
USB
51 79 80
USB_85D
USB
51 79 80
USB_85D
USB
PCIE_CLK100M_AP
42
42
42
42
42
6 33
6 33
65
65
49 65
49 65
AUDIO
=2:1_SPACING
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
SPACING_RULE_SET
LAYER
WEIGHT
I287
ENETCONN
25 MILS
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
ENET_MDI
GND
GND_P2MM
SENSE_DIFFPAIR
I288
?
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
SPACING_RULE_SET
LAYER
WEIGHT
SENSE_DIFFPAIR
GND
=STANDARD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_PCIE
GND
GND_P2MM
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
GPUTHMSNS_D_P
GPUTHMSNS_D_N
GPU_TDIODE_P
GPU_TDIODE_N
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
51
51
PCIE
GND
GND_P2MM
SATA
GND
GND_P2MM
SENSE_DIFFPAIR
SPACING_RULE_SET
LAYER
WEIGHT
0.20 MM
1000
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
USB
GND
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
GND_P2MM
PWR_P2MM
0.20 MM
6 43
6 43
9 51
51
51
USB_85D
USB
USB_85D
USB
CONN_USB2_BT_P
CONN_USB2_BT_N
6 33
6 33
USB_LT2_P
USB_LT2_N
6 43
6 43
50
50
GND_P2MM
CPUVTTISNS_R_N
CPUVTTISNS_R_P
USB2_LT1_P
USB2_LT1_N
9 51
43
43
SENSE_DIFFPAIR
1000
CLK_PCIE
SB_POWER
PWR_P2MM
SATA
SB_POWER
PWR_P2MM
CPUVTTS0_CS_N
CPUVTTS0_CS_P
DDRISNS_R_N
DDRISNS_R_P
50 70
DP_85D
DISPLAYPORT
50 70
DP_85D
DISPLAYPORT
DP_IG_AUX_CH_C_P
DP_IG_AUX_CH_C_N
84
84
50
50
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
USB
MEM_CLK
GND
GND_P2MM
MEM_CMD
GND
GND_P2MM
SB_POWER
PWR_P2MM
SENSE_DIFFPAIR
SENSE_DIFFPAIR
MEM_CTRL
GND
GND_P2MM
MEM_DATA
GND
GND_P2MM
SENSE_DIFFPAIR
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
GND
SENSE_DIFFPAIR
GND_P2MM
LVDS
GND
GND_P2MM
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SENSE_DIFFPAIR
MEM_40S
OVERRIDE
OVERRIDE
0.09 MM
OVERRIDE
OVERRIDE
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
I249
OVERRIDE
SENSE_DIFFPAIR
MEM_72D
OVERRIDE
OVERRIDE
PCIE_85D
OVERRIDE
OVERRIDE
I250
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
0.09 MM
10 mm
I251
OVERRIDE
I253
OVERRIDE
I252
OVERRIDE
SENSE_DIFFPAIR
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
SENSE_DIFFPAIR
USB_85D
TOP
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
I254
OVERRIDE
I256
OVERRIDE
SENSE_DIFFPAIR
CPU_27P4S
BOTTOM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.23 MM
100 MIL
OVERRIDE
OVERRIDE
I255
OVERRIDE
OVERRIDE
I281
SENSE_DIFFPAIR
I282
I283
SENSE_DIFFPAIR
I284
I285
SENSE_DIFFPAIR
I286
SENSE_DIFFPAIR
SENSE_DIFFPAIR
I292
SENSE_DIFFPAIR
I291
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
GFXIMVP_CS_N
GFXIMVP_CS_P
GFXIMVP_CS_R_N
GFXIMVP_CS_R_P
GFX_ISNS_R_N
GFX_ISNS_R_P
GPUISENS_N
GPUISENS_P
ISNS_1V5_S3_N
ISNS_1V5_S3_P
ISNS_AIRPORT_N
ISNS_AIRPORT_N
ISNS_AIRPORT_P
ISNS_AIRPORT_P
ISNS_AIRPORT_R_N
ISNS_AIRPORT_R_P
ISNS_CPU_N
ISNS_CPU_P
ISNS_HDD_N
ISNS_HDD_P
ISNS_HDD_R_N
ISNS_HDD_R_P
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
ISNS_ODD_N
ISNS_ODD_P
ISNS_ODD_R_N
ISNS_ODD_R_P
ISNS_P1V8GPU_N
ISNS_P1V8GPU_P
ISNS_P1V8GPU_R_N
ISNS_P1V8GPU_R_P
69
69
50 69
50 69
50
50
SPK_OUT
50
50
SPK_OUT
50 67
50 67
SPK_OUT
99
99
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
6 61 62
6 61 62
6 61 62
6 61 62
6 61 62
6 61 62
99
99
56
56
49
49
USB_85D
USB
USB_85D
USB
USB_TPAD_R_P
USB_TPAD_R_N
53
53
56
56
SB_POWER
SB_POWER
SB_POWER
GND
56
PP3V3_S5
PP3V3_S0
PP1V5_S3RS0
6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85
50 51 52
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
54 58 62
6 7 13 16 31 42 72 7363 68 87
69 72
73 84
80 88
83
85
GND
56
50
50
50
50
Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
LVDS_85D
BGA
LVDS_85D
DP_85D
BGA
100_DIFF_BGA
SATA_90D
BGA
100_DIFF_BGA
CLK_PCIE_90D
BGA
100_DIFF_BGA
TABLE_PHYSICAL_ASSIGNMENT_ITEM
A Memory Constraint Relaxations
SYNC_MASTER=K17_REF
PAGE TITLE
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.
Project Specific Constraints
PHYSICAL_RULE_SET
LAYER
MEM_72D
BOTTOM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
0.127 MM
6.35 MM
DIFFPAIR NECK GAP
DRAWING NUMBER
Apple Inc.
TOP
MEM_85D
0.1 MM

<E4LABEL>
6.35 MM
SIZE
<SCH_NUM> D
REVISION
BRANCH
<BRANCH>
PAGE
108 OF 132
SHEET
99 OF 101
K18 Board-Specific Spacing & Physical Constraints

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
15.5.1
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPACING_RULE_SET
LAYER
WEIGHT
DEFAULT
=50_OHM_SE
=50_OHM_SE
10 MM
0 MM
0 MM
DEFAULT
0.1 MM
=DEFAULT
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BGA
BGA_P1MM
STANDARD
NET_SPACING_TYPE1
STANDARD
=DEFAULT
BGA_P1MM
=DEFAULT
MEM_CLK
BGA
BGA_P2MM
CLK_PCIE
BGA
BGA_P2MM
CLK_SLOW
BGA
BGA_P2MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
55_OHM_SE
TOP,BOTTOM
0.090 MM
0.090 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
BGA_P2MM
=DEFAULT
55_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
SPACING_RULE_SET
=STANDARD
WEIGHT
1.5:1_SPACING
LAYER
*
0.15 MM
2:1_SPACING
0.2 MM
WEIGHT
2X_DIELECTRIC
SPACING_RULE_SET
LAYER
0.140 MM
3X_DIELECTRIC
0.210 MM
4X_DIELECTRIC
0.280 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
50_OHM_SE
TOP,BOTTOM
0.110 MM
0.095 MM
50_OHM_SE
0.090 MM
0.090 MM
2.5:1_SPACING
0.25 MM
=STANDARD
=STANDARD
=STANDARD
3:1_SPACING
0.3 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
4:1_SPACING
0.4 MM
DIFFPAIR NECK GAP

40_OHM_SE
TOP,BOTTOM
0.165 MM
0.095 MM
40_OHM_SE
0.135 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
37_OHM_SE
TOP,BOTTOM
0.185 MM
0.095 MM
37_OHM_SE
0.155 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
0.310 MM
0.095 MM
27P4_OHM_SE
0.250 MM
0.1 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
C
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
72_OHM_DIFF
=STANDARD
=STANDARD
72_OHM_DIFF
ISL3,ISL4
0.154 MM
0.154 MM
72_OHM_DIFF
ISL9,ISL10
0.154 MM
72_OHM_DIFF
TOP,BOTTOM
0.175 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
85_OHM_DIFF
=STANDARD
=STANDARD
85_OHM_DIFF
ISL3,ISL4
0.110 MM
0.090 MM
85_OHM_DIFF
ISL9,ISL10
0.110 MM
85_OHM_DIFF
TOP,BOTTOM
PHYSICAL_RULE_SET
LAYER
90_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
0.200 MM
0.200 MM
0.154 MM
0.200 MM
0.200 MM
0.175 MM
0.200 MM
0.200 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
0.180 MM
0.180 MM
0.090 MM
0.180 MM
0.180 MM
0.125 MM
0.090 MM
0.190 MM
0.190 MM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4
0.102 MM
0.090 MM
0.220 MM
0.220 MM
90_OHM_DIFF
ISL9,ISL10
0.102 MM
0.090 MM
0.220 MM
0.220 MM
90_OHM_DIFF
TOP,BOTTOM
0.115 MM
0.090 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
DIFFPAIR NECK GAP
1:1_DIFFPAIR
=STANDARD
=STANDARD
0.1 MM
=STANDARD
0.1 MM
MAXIMUM NECK LENGTH
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_DIFF_BGA
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
100_DIFF_BGA
ISL3,ISL4
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_DIFF_BGA
ISL9,ISL10
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4
0.080 MM
0.080 MM
0.200 MM
0.200 MM
100_OHM_DIFF
ISL9,ISL10
0.080 MM
0.080 MM
0.200 MM
0.200 MM
100_OHM_DIFF
TOP,BOTTOM
0.089 MM
0.089 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
110_OHM_DIFF
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4
0.075 MM
110_OHM_DIFF
ISL9,ISL10
110_OHM_DIFF
TOP,BOTTOM
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
0.220 MM
0.220 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
0.075 MM
0.330 MM
0.330 MM
0.075 MM
0.075 MM
0.330 MM
0.330 MM
0.075 MM
0.075 MM
0.330 MM
0.330 MM
NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.
SYNC_MASTER=K17_REF
PAGE TITLE
PCB Rule Definitions

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
109 OF 132
SHEET
100 OF 101
56 54 46 44 43 42 33 31 7 6
82 72 67 66 61 58
PP5V_S3
T57
T57
CD230 1
ZTD200
0.01uF
STDOFF-3.6OD3.4H-SM
20%
16V
CERM 2
402
T57
ZTD201
STDOFF-3.6OD3.4H-SM
36 35 34 33 32 31 20 17 8 7 6
87 73 72 55 54 53 50 48
PP3V3_S3
T57
T57
CRITICAL
CD225 1
0.01uF
JD201
20%
16V
CERM 2
402
AXK720427G
F-ST-SM
21
NC
93 19
93 19
BI
BI
USB_BRCRYPT_P
USB_BRCRYPT_N
17
IN
NC
BRCRYPT_RESET
10
11
12
13
14
15
16
17
18
19
20
BRCRYPT_PWR_EN
IN
17
NC
NC
NC
NC
22
6 VBUS
NC
IO
NC
IO
2 5 3 4
1 GND
DD220
RCLAMP0502N
SLP1210N6
CRITICAL
T57
SYNC_MASTER=K17_REF
PAGE TITLE
BluRay Decrypter Card Connector

DRAWING NUMBER
Apple Inc.
R

SIZE
<SCH_NUM> D
REVISION
<E4LABEL>
BRANCH
<BRANCH>
PAGE
132 OF 132
SHEET
101 OF 101

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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

NOTICE OF PROPRIETARY PROPERTY:

FAN CONN AND CONTROL

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

K17 POWER SYSTEM ARCHITECTURE

SMC AVREF SUPPLY

IBEX PEAK MPM_PWRBTN_L

Power Block Diagram

(PAGE 70) PGOOD

NOTICE OF PROPRIETARY PROPERTY:

NOTICE OF PROPRIETARY PROPERTY:

Murata alt to Samsung

Delta alt to TDK Magnetics

MAG LAYERS ALT TO CYNTEC

MAG LAYERS ALT TO MURATA

Hynix 900M alt to 1000M

Molex alt to Foxconn

Mag layer alt to Vishay

K18 DEVELOPMENT BOM

Fairchild wafer option

Samsung I die alt to H

Sanyo alt to Kemet

Panasonic alt to Sanyo

A02 alt to A03 GPU

6.3V alt to 11V Sanyo

K18 BOM GROUPS

Bar Code Labels / EEE #s

IC,GPU,NV GT216 LP++,969BGA,40NM,A03

IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12

IR,ENCORE II, CY7C63833-LFXC

IC,SGRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550

IC,SDRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550

IC,SGRAM,GDDR3,16MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550

NOTICE OF PROPRIETARY PROPERTY:

K18 MLB DEVELOPMENT

THE INFORMATION CONTAINED HEREIN IS THE

Functional Test Points

J5650 (LEFT FAN CONN)

J5660 (RIGHT FAN CONN)

J6780 (MIC CONN)

J3401 & J3402 (AIRPORT/BT/CAMERA CONN) I1120

J6781 & J6782 (SPEAKERS CONN)

J5815 (KBD BACKLIGHT CONN)

J6995 (BAT LED CONN)

Functional / ICT Test

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

J6950 (MAIN BATT CONN)

J6900 (DC POWER CONN)

J4501 (SATA HDD CONN)

J5800 (IPD FLEX CONN)

ICT Test Points

J4500 (SATA ODD CONN)

J9000 (LVDS CONN)

J5713 (KEY BOARD CONN) 73 87 101

"G3Hot" (Always-Present) Rails

Chipset "VCore" Rails

THE INFORMATION CONTAINED HEREIN IS THE

NOTICE OF PROPRIETARY PROPERTY:

PEG LANES REVERSED. ARD STRAP REQD.