VLSI PROJECT 2014-15

1. PERFORMANCE EVALUATION OF FFT PROCESSOR USING VEDIC ALGORITHM

2. AN EFFICIENT SQRT ARCHITECTURE OF CARRY SELECT ADDER DESIGN BY COMMON BOOLEAN
LOGIC.
3. AN EFFICIENT HIGH SPEED WALLACE TREE MULTIPLIER
4. DESIGN AND IMPLEMENTATION OF 32 BIT UNSIGNED MULTIPLIER USING CLAA AND CSLA
5. REAL TIME COMMUNICATION BETWEEN MULTIPLE FPGA SYSTEMS IN MULTITASKING
ENVIRONMENT USING RTOS
6. LUT OPTIMIZATION FOR MEMORY BASED COMPUTATION USING MODIFIED OMS
TECHNIQUE
7. DESIGN MULTIPURPOSE CIRCUITS WITH MINIMUM GARBAGE OUTPUTS USING CMVMIN
GATE
8. AN EFFICIENT IMPLEMENTATION OF THE NON RESTORING SQUARE ROOT ALGORITHM IN
GATE LEVEL
9. DS-CDMA IMPLEMENTATION WITH ITERATIVE MULTIPLE ACCESS INTERFERENCE
CANCELLATION
10. IMPLEMENTATION OF SERIAL COMMUNICATION USING UART WITH CONFIGURABLE BAUD
RATE
11. IMPLEMENTATION OF ADAPTIVE VITERBI DECODER FOR WIRELESS COMMUNICATION
12. DESIGN OF HIGH RESOLUTION DPWM FOR POWER CONVERTERS USING GENERAL-PURPOSE
FPGAS
13. DESIGN OF EFFICIENT REVERSIBLE MULTIPLY ACCUMULATE (MAC) UNIT
14. 6-BIT ARITHMETIC AND LOGIC UNIT DESIGN USING MIXED TYPE OF MODELING IN VHDL
15. DESIGN OF A LOW POWER DOUBLE TAIL COMPARATOR USING GATED CLOCK AND POWER
GATING TECHNIQUES
16. A FAST-LOCKING ANALOG PLL WITH DESKEW BUFFER
17. GLITCH-FREE NAND-BASED DIGITALLY CONTROLLED DELAY-LINES
18. RESOURCEFUL FAST DHT ALGORITHM FOR VLSI IMPLEMENTATION BY SPLIT RADIX
ALGORITHM
19. DESIGN OF A SELF-ADAPTIVE ON-CHIP PERMUTATION NETWORK FOR MULTIPROCESSOR
SYSTEM-ON-CHIP
20. THE LUT-SR FAMILY OF UNIFORM RANDOM NUMBER GENERATORS FOR FPGA
ARCHITECTURES
21. RADIX-8 BOOTH ENCODED MODULO 2^N 1 MULTIPLIERS WITH PARALLEL PREFIX ADDER
FOR HIGH DYNAMIC RANGE RESIDUE NUMBER SYSTEM
22. TRIPLE MODULAR REDUNDANCY LOW DELAY SINGLE ERROR CORRECTION CODE FOR
PROTECTING DATA BITS
23. ACCUMULATOR BASED 3-WEIGHT TEST PATTERN GENERATION
24. OPTIMIZED MODULO MULTIPLIER BASED ON R.N.S
25. DESIGN OF ROUTER ARCHITECTURE BASED ON WORMHOLE SWITCHING MODE FOR NOC
26. A LOW POWER SINGLE PHASE CLOCK DISTRIBUTION MULTIBAND NETWORK
27. HARDWARE IMPLEMENTATION OF A DIGITAL WATERMARKING SYSTEM FOR VIDEO
AUTHENTICATION
28. TEACHING HW/SW CO-DESIGN WITH A PUBLIC KEY CRYPTOGRAPHY APPLICATION
29. DESIGN AND IMPLEMENTATION OF AN FPGA-BASED REAL-TIME FACE RECOGNITION SYSTEM
30. A LOW-COMPLEXITY IMPLEMENTATION OF QC-LDPC ENCODER IN RECONFIGURABLE LOGIC











STANDBY PROJECT
1. ROUND RESCHEDULING FOR HASH FUNCTION BLAKE
2. MULTIPLICATION ACCELERATION THROUGH TWIN PRECISION
3. HIGH SPEED LOW COMPLEXITY REED-SOLOMON CODES
4. DESIGN OF MD5 HASH ALGORITHM
5. COMPOSITE FIELD ALGORITHM FOR S BOX
6. SIMULATION AND SYNTHESIS OF LOW DENSITY PARITY CHECK CODE
7. DESIGNING OF REVERSIBLE MULTIPLEXERS AND DE MULTIPLEXERS WITH NEW
REVERSIBLE GATE
8. A LOW POWER STRUCTURE DESIGN OF 2D LFSR AND ENCODING TECHNIQUE FOR BIST
9. KECCAK SHA3 CRYPTO CORE
10. IMPLEMENTATION OF THE LMS ALGORITHM
11. 2D-DWT LIFTING BASED IMPLEMENTATION USING VLSI ARCHITECTURE
12. MODIFIED GRADIENT SEARCH FOR LEVEL SET BASED IMAGE SEGMENTATION
13. EDGED DETECTION ALGORITHM IMPLEMENTED IN SOBEL OPERATOR IN HARDWARE
14. RECONFIGURABLE PROCESSOR FOR BINARY IMAGE PROCESSING
15. HK-MEANS CLUSTERING IN MULTIMEDIA APPLICATIONS FOR PATTERN RECOGNITION