Assignment 2 Xinwei Xu 870209

ASSIGNMENT 2 XINWEI XU 870209-9311
1. FULLY SERIAL FIR

Adder:1
Multiplier:1
Register:2
2. FULLY PARALLEL FIR
Adder: 11
Multiplier:12
Register:1
3.PARTIALY PARALLEL(2 macs)

Adder :2
Mutiplier:2
Register:2
Answer the questions:
1. Gate count estimation
A 1bit full adder can be realized by 9 NAND gates and A m*n bit multiplier
can be realized by m*(n-1) adder and m*n *2 NAND gate. So,
Fully serial needs about 1300 NAND gates
Fully parallel needs about 13000 NAND gates
Partially parallel (2 MACS a cycle) needs about 2500 NAND gates
2. VHDL code for each FIR (in the appendix)

3. Estimate the critical path
In fully parallel and serial, the longest path is from c0(x0) to the
final result, and the shortest one is from x11(c11) to the final result.
In the partially parallel, the shortest way is from x5or x6 to the
final result.
4. Are there any paths cross the component boundary?

YES, paths crossing the component boundary exist in all the three
kinds of FIR.
5 . What is the best and worst case utilization factor?

APPENDIX:
VHDL CODE:
FULLY SERIAL:
FSM(control other components by 23 states):
library IEEE; end entity;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_signed.all; architecture behave of fsm is
Use IEEE.std_logic_arith.all; subtype state is integer range 0 to 22;
signal pres_state, next_state: state;
entity fsm is signal temp_dav: std_logic;
port (clk: in std_logic;
reset: in std_logic; begin
ctrl_arith: out std_logic_vector(1 downto 0); dav<=temp_dav;
ctrl_corom_en: out std_logic; process(pres_state)
ctrl_corom_adr: out std_logic_vector(3 downto 0); begin
ctrl_regfile_adr: out std_logic_vector(3 downto 0); case pres_state is
ctrl_regfile_rden:out std_logic; when 0 => ----c0*x0
dav:out std_logic); ctrl_arith<="00";

ctrl_corom_adr<="0000"; --c0 ctrl_regfile_rden<='1';
ctrl_corom_en<='1'; ctrl_regfile_adr<="0010";
ctrl_regfile_adr<="0000"; temp_dav<='0';
ctrl_regfile_rden<='1'; next_state<=pres_state+1;
temp_dav<='0';
next_state<=pres_state+1; when 4=> ------sum+t2
ctrl_arith<="11";
ctrl_corom_en<='0';
when 1 => ------c1*x1 ctrl_regfile_rden<='0';
ctrl_arith<="01"; temp_dav<='0';
ctrl_corom_adr<="0001"; --c1 next_state<=pres_state+1;
ctrl_corom_en<='1';
ctrl_regfile_adr<="0001"; when 5=> ------c3*x3
ctrl_regfile_rden<='1'; ctrl_arith<="00";
temp_dav<='0'; ctrl_corom_en<='1';
next_state<=pres_state+1; ctrl_corom_adr<="0011";
ctrl_regfile_rden<='1';
when 2=> ------sum+t1 ctrl_regfile_adr<="0011";
ctrl_corom_en<='0'; next_state<=pres_state+1;
temp_dav<='0'; when 6=> ------sum+t3
next_state<=pres_state+1; ctrl_arith<="11";
ctrl_corom_en<='0';
when 3=> ------c2*x2 ctrl_regfile_rden<='0';
ctrl_corom_adr<="0010";
ctrl_regfile_rden<='1'; when 11=> ------c6*x6
ctrl_regfile_adr<="0100"; ctrl_arith<="00";
ctrl_corom_en<='0';
ctrl_corom_en<='0';
ctrl_corom_en<='0';
when 21=> ------c11*x11 end process;
ctrl_arith<="00";
ctrl_corom_en<='1'; process(clk,reset)
ctrl_corom_adr<="1011"; begin
ctrl_regfile_rden<='1'; if reset='1' then
ctrl_regfile_adr<="1011"; pres_state<=0;
temp_dav<='0'; else
next_state<=pres_state+1; if rising_edge(clk) then
when 22=> ------sum+t11 pres_state<=next_state;
ctrl_arith<="11"; end if;
ctrl_corom_en<='0'; end if ;
ctrl_regfile_rden<='0'; end process;
temp_dav<='1'; end behave;
next_state<=0;
end case;
co-rom:
library IEEE; end co_rom;
use ieee.std_logic_1164.all;
Architecture behave of co_rom is
entity co_rom is type romtype is array (11 downto 0) of

std_logic_vector(9 downto 0);
port (co_rom_adr: in std_logic_vector(3 downto 0);
procedure conv_adr ( adr: in std_logic_vector(3
co_rom_en: in std_logic; downto 0); adr_int:out integer range 0 to 11)
co_rom_output: out std_logic_vector( 9 downto is

0));
variable result : natural;
begin
result:=0; rom(0):="0000000101";
for i in adr'range loop rom(1):="0000000110";
result := result * 2; -- converting rom(2):="0000010101";
if adr(i)='1' then -- std_logic_vector rom(3):="0001000100";
result := result + 1; rom(4):="0000100100";
end if; rom(5):="1000000100";
adr_int:=result; rom(6):="1100000101";
end loop; rom(7):="0110000101";
end procedure; rom(8):="0000101001";
rom(9):="0011011101";
rom(10):="1010000101";
begin rom(11):="0010000100";
if co_rom_en='1' then
conv_adr(co_rom_adr,conv);
process(co_rom_en,co_rom_adr) co_rom_output<=rom(conv);
variable conv: integer range 0 to 12; end if;
variable rom: romtype; end process;
begin end behave;
delayline:
library IEEE; rd: out std_logic_vector(11 downto 0);
USE IEEE.std_logic_1164.all; rd_en: in std_logic);
end entity;
entity delayline is
port (wr:in std_logic_vector(11 downto 0); Architecture behave of delayline is
wr_en: in std_logic; type memtype is array(11 downto 0) of

adr: in std_logic_vector(3 downto 0);
signal mem : memtype:=(others=>"000000000000");
procedure conv_adr ( adr: in std_logic_vector(3 begin
downto 0); adr_int:out integer range 0 to 11)
if rising_edge(wr_en) then
is
mem(0)<=wr;
variable result : natural;
for i in 10 downto 0 loop
begin
mem(i+1)<=mem(i);
result:=0;
end loop;
for i in adr'range loop
end if;
result := result * 2; -- converting
end process;
if adr(i)='1' then -- std_logic_vector
result := result + 1;
process( adr,rd_en)
end if;
variable conv: integer range 0 to 12;
adr_int:=result;
begin
if rd_en='1' then
end loop;
conv_adr(adr,conv);
end procedure;
rd<=mem(conv);
end if;
end process;
begin
process(wr_en)
end behave;
Arithmetic:
library IEEE; Entity arithmetic is
use IEEE.std_logic_1164.all; port(input_co: in std_logic_vector(9 downto 0);
use IEEE.std_logic_signed.all; input_x: in std_logic_vector(11 downto 0);
ctrl: in std_logic_vector(1 downto 0);

dav_ctrl: in std_logic; --if ctrl='0' then
clk: in std_logic; -- temp:=input_co*input_x;
output: out std_logic_vector(25 downto 0)); -- else sum:=sum+temp;
end entity; -- end if;
Architecture behave of arithmetic is if dav_ctrl='1' then
output<=sum;
begin end if;
process(clk) end if;
variable sum: std_logic_vector(25 downto

0):=(others=>'0');
variable temp, temp2: std_logic_vector(21

downto 0):=(others=>'0');
variable extend: std_logic_vector(25 downto

0):=(others=>'0');
begin
extend:=(others=>'0');
if clk'event and clk='1' then

FIR_SERIAL
case ctrl is
library IEEE;
when "00"=>
use IEEE.std_logic_1164.all;
temp:=input_co*input_x;
use IEEE.std_logic_signed.all;
when "01"=>
temp2:=input_co*input_x;
Entity arithmetic is
when "10"=>
port(input_co: in std_logic_vector(9 downto 0);
sum:=temp+temp2+extend;
input_x: in std_logic_vector(11 downto 0);
when "11" =>
ctrl: in std_logic_vector(1 downto 0);
sum:=sum+temp;
dav_ctrl: in std_logic;
when others=>
clk: in std_logic;
sum:=sum;
output: out std_logic_vector(25 downto 0));
end case;
end entity;
-- else sum:=sum+temp;
-- end if;
Architecture behave of arithmetic is if dav_ctrl='1' then
output<=sum;
begin end if;
process(clk) end if;
variable sum: std_logic_vector(25 downto end process;

0):=(others=>'0');
variable temp, temp2: std_logic_vector(21

downto 0):=(others=>'0'); end behave;
variable extend: std_logic_vector(25 downto

0):=(others=>'0');
begin
extend:=(others=>'0');
if clk'event and clk='1' then
case ctrl is
when "00"=>
temp:=input_co*input_x;
when "01"=>
temp2:=input_co*input_x;
when "10"=>
sum:=temp+temp2+extend;
when "11" =>
sum:=sum+temp;
when others=>
sum:=sum;
end case;
--if ctrl='0' then
-- temp:=input_co*input_x;
output5: out std_logic_vector(11 downto 0);
output11: out std_logic_vector(11 downto 0));
end entity;
Architecture behave of reg is
type regtype is array(0 to 11) of std_logic_vector(11

downto 0);
begin
process(reset, clk)
FULLY PARALLEL:
Parallel_shiftreg:
library IEEE;
use ieee.std_logic_1164.all; variable reg : regtype:=(others=>"000000000000");
begin
Entity reg is if reset='1' then
port (input: in std_logic_vector(11 downto 0); reg:=(others=>"000000000000");
clk,reset: in std_logic; else
output0: out std_logic_vector(11 downto 0); if rising_edge(clk) then
output1: out std_logic_vector(11 downto 0); for i in 10 downto 0 loop
output2: out std_logic_vector(11 downto 0); reg(i+1):=reg(i);
output3: out std_logic_vector(11 downto 0); end loop;
output4: out std_logic_vector(11 downto 0); reg(0):=input;

end if; output4: out std_logic_vector(11 downto 0);
end if; output5: out std_logic_vector(11 downto 0);
output0<=reg(0); output6: out std_logic_vector(11 downto 0);
output5<=reg(5); output11: out std_logic_vector(11 downto 0));
output6<=reg(6); end entity;
output7<=reg(7);
output8<=reg(8); Architecture behave of reg is
output9<=reg(9); type regtype is array(0 to 11) of std_logic_vector(11

downto 0);
output10<=reg(10);
output11<=reg(11);
begin
end process;
process(reset, clk)
end behave;
variable reg :
regtype:=(others=>"000000000000");
Arithmetic: begin
library IEEE; if reset='1' then
use ieee.std_logic_1164.all; reg:=(others=>"000000000000");
else
Entity reg is if rising_edge(clk) then
port (input: in std_logic_vector(11 downto 0); for i in 10 downto 0 loop
clk,reset: in std_logic; reg(i+1):=reg(i);
output0: out std_logic_vector(11 downto 0); end loop;
output1: out std_logic_vector(11 downto 0); reg(0):=input;
output2: out std_logic_vector(11 downto 0); end if;
output3: out std_logic_vector(11 downto 0); end if;

output4<=reg(4); output11: out std_logic_vector(9 downto 0)
output5<=reg(5); );
output6<=reg(6); end entity;
output7<=reg(7);
output8<=reg(8); Architecture behave of rom is
output9<=reg(9);
output10<=reg(10); begin
output11<=reg(11);
end process;
end behave; output0<="0000000101";
output1<="0000000110";
output2<="0000010101";
Parallel co_rom:
output3<="0001000100";
library IEEE;
output4<="0000100100";
output5<="1000000100";
output6<="1100000101";
output7<="0110000101";
entity rom is
output8<="0000101001";
port( output0: out std_logic_vector(9 downto 0);
output9<="0011011101";
output10<="1010000101";
output11<="0010000100";

end behave;

Parallel_fir:
library ieee; output6: out std_logic_vector(11 downto 0);
use ieee.std_logic_1164.all; output7: out std_logic_vector(11 downto 0);
entity parallel_fir is output9: out std_logic_vector(11 downto 0);
port (input: in std_logic_vector(11 downto 0); output10: out std_logic_vector(11 downto 0);
clk,enable,reset : in std_logic; output11: out std_logic_vector(11 downto 0));
output: out std_logic_vector(21 downto 0)); end component;
end entity;
component rom is
port( output0: out std_logic_vector(9 downto 0);
Architecture behave of parallel_fir is output1: out std_logic_vector(9 downto 0);
component reg is output2: out std_logic_vector(9 downto 0);
port (input: in std_logic_vector(11 downto 0); output3: out std_logic_vector(9 downto 0);
clk,reset: in std_logic; output4: out std_logic_vector(9 downto 0);
output0: out std_logic_vector(11 downto 0); output5: out std_logic_vector(9 downto 0);
output11: out std_logic_vector(9 downto 0) co11: in std_logic_vector(9 downto 0);
); enable,clk: in std_logic;
end component; output: out std_logic_vector(21 downto 0)
);
component arithmetic is end component ;
port( x0: in std_logic_vector(11 downto 0);
x1: in std_logic_vector(11 downto 0); signal

reg_arith0,reg_arith1,reg_arith2,reg_arith3,reg_arith4
x2: in std_logic_vector(11 downto 0); ,reg_arith5,reg_arith6,reg_arith7,reg_arith8,reg_arith
9,reg_arith10,reg_arith11:std_logic_vector(11
x3: in std_logic_vector(11 downto 0);
downto 0);
signal
x5: in std_logic_vector(11 downto 0); rom_arith0,rom_arith1,rom_arith2,rom_arith3,rom_a
rith4,rom_arith5,rom_arith6,rom_arith7,rom_arith8,r
x6: in std_logic_vector(11 downto 0); om_arith9,rom_arith10,rom_arith11:std_logic_vector
(9 downto 0);
begin
label1: component reg port map
( input=>input,clk=>clk,
x10:in std_logic_vector(11 downto 0); reset=>reset,output0=>reg_arith0,output1=>reg_arith
1,output2=>reg_arith2,
x11:in std_logic_vector(11 downto 0);
co0:in std_logic_vector(9 downto 0);

output3=>reg_arith3,output4=>reg_arith4,output5=>
co1:in std_logic_vector(9 downto 0); reg_arith5,output6=>reg_arith6,output7=>reg_arith7,
co2: in std_logic_vector(9 downto 0);

output8=>reg_arith8,output9=>reg_arith9,output10=
co3: in std_logic_vector(9 downto 0); >reg_arith10,output11=>reg_arith11);
co5: in std_logic_vector(9 downto 0); label2: component rom port map

(output0=>rom_arith0,output1=>rom_arith1,output2
co7: in std_logic_vector(9 downto 0); =>rom_arith2,output3=>rom_arith3,output4=>rom_a
rith4,

output5=>rom_arith5,output6=>rom_arith6,output7=
co10:in std_logic_vector(9 downto 0);
>rom_arith7,output8=>rom_arith8,output9=>rom_ari
th9, x11=>reg_arith11,co0=>rom_arith0,co1=>rom_arith
1,co2=>rom_arith2,co3=>rom_arith3,co4=>rom_arit
h4,co5=>rom_arith5,
output10=>rom_arith10,output11=>rom_arith11);
co6=>rom_arith6,co7=>rom_arith7,co8=>rom_arith8
,co9=>rom_arith9,co10=>rom_arith10,co11=>rom_a
label3: component arithmetic port map
rith11);
(enable=>enable,
clk=>clk,output=>output,x0=>reg_arith0,x1=>reg_ar
ith1,x2=>reg_arith2,x3=>reg_arith3,
x4=>reg_arith4,x5=>reg_arith5,x6=>reg_arith6,x7=>
reg_arith7,x8=>reg_arith8,x9=>reg_arith9,x10=>reg end behave;
_arith10,
Partially Parallel:
FSM:
library ieee; ctrl_rom_ad1: out std_logic_vector(3 downto 0);
use ieee.std_logic_1164.all; ctrl_rom_ad2: out std_logic_vector(3 downto 0);
ctrl_reg_en: out std_logic;
ctrl_reg_ad1: out std_logic_vector(3 downto 0);
entity partial_fsm is ctrl_reg_ad2: out std_logic_vector(3 downto 0);
port(clk,reset:in std_logic; dav: out std_logic);
ctrl_arith: out std_logic_vector(1 downto 0);
ctrl_rom_en: out std_logic; end entity;

ctrl_rom_ad1<="0000";
Architecture behave of partial_fsm is ctrl_rom_ad2<="1011";
subtype state is integer range 0 to 6; ctrl_reg_en<='1';
signal pres_state,next_state: state; ctrl_reg_ad1<="0000";
signal temp_dav: std_logic; ctrl_reg_ad2<="1011";
--signal counter: integer range 0 to 5; next_state<=pres_state+1;
begin when 1=>
-- process (clk,reset) ctrl_arith<="00";
--begin ctrl_rom_en<='1';
-- if reset='1'or counter>=5 then ctrl_rom_ad1<="0001";
--counter<=0; ctrl_rom_ad2<="1010";
-- else counter<=counter+1; ctrl_reg_en<='1';
-- end if; ctrl_reg_ad1<="0001";
--end process; ctrl_reg_ad2<="1010";
next_state<=pres_state+1;
-- process(counter)
-- begin
when 2=>
dav<=temp_dav; ctrl_arith<="00";
ctrl_rom_en<='1';
process(pres_state) ctrl_rom_ad1<="0010";
begin ctrl_rom_ad2<="1001";
temp_dav<='0'; ctrl_reg_en<='1';
case pres_state is ctrl_reg_ad1<="0010";
when 0=> ctrl_reg_ad2<="1001";
ctrl_arith<="01"; next_state<=pres_state+1;
ctrl_rom_en<='1';
when 3=> next_state<=pres_state+1;
ctrl_arith<="00"; --temp_dav<='1';
ctrl_rom_en<='1';
ctrl_rom_ad1<="0011"; when 6=>
ctrl_rom_ad2<="1000"; ctrl_arith<="11";
ctrl_reg_en<='1'; ctrl_rom_en<='1';
ctrl_reg_ad1<="0011"; ctrl_rom_ad1<="0101";
ctrl_reg_ad2<="1000"; ctrl_rom_ad2<="0110";
next_state<=pres_state+1; ctrl_reg_en<='1';
ctrl_reg_ad1<="0101";
when 4=> ctrl_reg_ad2<="0110";
ctrl_arith<="00"; next_state<=0;
ctrl_rom_en<='1'; temp_dav<='1';
ctrl_rom_ad1<="0100";
ctrl_rom_ad2<="0111"; end case;
ctrl_reg_en<='1'; end process;
ctrl_reg_ad2<="0111"; process(clk, reset)
next_state<=pres_state+1; begin
if reset='1' then
when 5=> pres_state<=0;
ctrl_arith<="00"; else
ctrl_rom_en<='1'; if rising_edge(clk) then
ctrl_rom_ad1<="0101"; pres_state<=next_state;
ctrl_rom_ad2<="0110"; end if;
ctrl_reg_en<='1'; end if;
ctrl_reg_ad1<="0101"; end process;
end behave;
Reg
library IEEE; result:=0;
use ieee.std_logic_1164.all; for i in adr'range loop
if adr(i)='1' then -- std_logic_vector
entity partial_reg is result := result + 1;
port (write: in std_logic_vector(11 downto 0); end if;
wr_en,rd_en: in std_logic; adr_int:=result;
ad1,ad2: in std_logic_vector(3 downto 0); end loop;
rd1,rd2: out std_logic_vector(11 downto 0)); end procedure;
end entity; signal mem: regtype:=(others=>"000000000000");
Architecture behave of partial_reg is begin
type regtype is array(0 to 11) of process(ad1,ad2,rd_en)

variable conv1,conv2: integer range 0 to 12;
downto 0); adr_int:out integer range 0 to 11) begin
is if rd_en='1' then
variable result : natural; conv_adr(ad1,conv1);
begin conv_adr(ad2,conv2);
rd1<=mem(conv1); mem(i+1)<=mem(i);
rd2<=mem(conv2); end loop;
end if; mem(0)<=write;
end process; end if;
process(wr_en) end process;
begin
if rising_edge(wr_en) then end behave;
for i in 10 downto 0 loop
ROM:
library ieee; begin
use ieee.std_logic_1164.all; result:=0;
for i in adr'range loop
Entity partial_rom is if adr(i)='1' then -- std_logic_vector
port( rom_enable: in std_logic; result := result + 1;
ad1: in std_logic_vector(3 downto 0); end if;
ad2: in std_logic_vector(3 downto 0); adr_int:=result;
co_low: out std_logic_vector(9 downto 0); end loop;
co_high: out std_logic_vector(9 downto 0)); end procedure;
end entity;
begin
Architecture behave of partial_rom is
type romtype is array(0 to 11) of std_logic_vector(9 process(ad1,ad2,rom_enable)

downto 0);
variable conv1,conv2:integer range 0 to 11;
downto 0); adr_int:out integer range 0 to 11) variable rom: romtype;
is begin
variable result : natural; rom(0):="0000000101";
rom(1):="0000000110";
rom(2):="0000010101"; rom(11):="0010000100";
rom(3):="0001000100"; if rom_enable ='1' then
rom(4):="0000100100"; conv_adr(ad1,conv1);
rom(5):="1000000100"; conv_adr(ad2,conv2);
rom(6):="1100000101"; co_low<=rom(conv1);
rom(7):="0110000101"; co_high<=rom(conv2);
rom(8):="0000101001"; end if;
rom(9):="0011011101"; end process;
rom(10):="1010000101"; end behave;
Arithmetic:
library ieee; Architecture behave of partial_arithmetic is
use ieee.std_logic_signed.all; begin
process(clk)
entity partial_arithmetic is variable sum1,sum2: std_logic_vector(21 downto

0);
port( ctrl: in std_logic_vector(1 downto 0);
clk: in std_logic;
begin
dav_ctrl:in std_logic;
case ctrl is
co1,co2: in std_logic_vector(9 downto 0);
when "01"=>
x1,x2: in std_logic_vector(11 downto 0);
sum1:=co1*x1;
sum2:=co2*x2;
end entity;
when "00"=>
sum1:=sum1+co1*x1;
sum2:=sum2+co2*x2; if dav_ctrl='1' then
output<=sum1;
when "11"=> end if;
sum1:=sum1+sum2; end process;
when others=>
end case; end behave;
Parital_fir
dav: out std_logic);
library ieee; end entity;
entity partial_fir is Architecture behave of partial_fir is
port(clk,reset: in std_logic;
sample_in : in std_logic_vector(11 downto 0); component partial_fsm is
output: out std_logic_vector(21 downto 0); port(clk,reset:in std_logic;
dav: out std_logic); ctrl_arith: out std_logic_vector(1 downto 0);
end entity; ctrl_rom_en: out std_logic;
ctrl_rom_ad1: out std_logic_vector(3 downto 0);
{library ieee; ctrl_rom_ad2: out std_logic_vector(3 downto 0);
use ieee.std_logic_1164.all; ctrl_reg_en: out std_logic;
ctrl_reg_ad1: out std_logic_vector(3 downto 0);
entity partial_fir is ctrl_reg_ad2: out std_logic_vector(3 downto 0);
port(clk,reset: in std_logic; dav: out std_logic);
sample_in : in std_logic_vector(11 downto 0);
output: out std_logic_vector(21 downto 0); end component;

signal corom_fsm_en,regfile_fsm_en,wr_dav:
std_logic;
component partial_reg is
signal
port (write: in std_logic_vector(11 downto 0); corom_fsm_adr1,corom_fsm_adr2,regfile_fsm_adr1,
regfile_fsm_adr2: std_logic_vector(3 downto 0);
wr_en,rd_en: in std_logic;
signal co1,co2: std_logic_vector(9 downto 0);
ad1,ad2: in std_logic_vector(3 downto 0);
signal x1,x2: std_logic_vector (11 downto 0);
rd1,rd2: out std_logic_vector(11 downto 0));
signal arith_fsm:std_logic_vector(1 downto 0);
end component;
begin
label1: component partial_fsm port map

component partial_rom is
(clk=>clk,
port( rom_enable: in std_logic;
reset=>reset,ctrl_arith=>arith_fsm,ctrl_rom_en=>cor
ad1: in std_logic_vector(3 downto 0); om_fsm_en,ctrl_rom_ad1=>corom_fsm_adr1,ctrl_ro
m_ad2=>corom_fsm_adr2,
ad2: in std_logic_vector(3 downto 0);
ctrl_reg_en=>regfile_fsm_en,
co_low: out std_logic_vector(9 downto 0); ctrl_reg_ad1=>regfile_fsm_adr1,ctrl_reg_ad2=>regfi
le_fsm_adr2,dav=>wr_dav);
co_high: out std_logic_vector(9 downto 0));
end component;
label2: component partial_rom port map
(ad1=>corom_fsm_adr1,ad2=>corom_fsm_adr2,rom
_enable=>corom_fsm_en,co_low=>co1,co_high=>co
component partial_arithmetic is
2);
port( ctrl: in std_logic_vector(1 downto 0);
clk: in std_logic;
label3: component partial_reg port map
dav_ctrl:in std_logic;
(write=>sample_in,
co1,co2: in std_logic_vector(9 downto 0); wr_en=>wr_dav,ad1=>regfile_fsm_adr1,ad2=>regfil
e_fsm_adr2,rd1=>x1,rd2=>x2,rd_en=>regfile_fsm_e
x1,x2: in std_logic_vector(11 downto 0); n);
label4: component partial_arithmetic port map
end component;
(co1=>co1,co2=>co2,x1=>x1,x2=>x2,ctrl=>arith_fs
m,dav_ctrl=>wr_dav,clk=>clk,output=>output);
port( rom_enable: in std_logic;
dav<=wr_dav; ad1: in std_logic_vector(3 downto 0);
ad2: in std_logic_vector(3 downto 0);
end behave;} co_low: out std_logic_vector(9 downto 0);
Architecture behave of partial_fir is co_high: out std_logic_vector(9 downto 0));
end component;
component partial_fsm is
port(clk,reset:in std_logic;
ctrl_arith: out std_logic_vector(1 downto 0); component partial_arithmetic is
ctrl_rom_en: out std_logic; port( ctrl: in std_logic_vector(1 downto 0);
ctrl_rom_ad1: out std_logic_vector(3 downto 0); clk: in std_logic;
ctrl_rom_ad2: out std_logic_vector(3 downto 0); dav_ctrl:in std_logic;
ctrl_reg_en: out std_logic; co1,co2: in std_logic_vector(9 downto 0);
ctrl_reg_ad1: out std_logic_vector(3 downto 0); x1,x2: in std_logic_vector(11 downto 0);
ctrl_reg_ad2: out std_logic_vector(3 downto 0); output: out std_logic_vector(21 downto 0));
dav: out std_logic);
end component;
end component;
signal corom_fsm_en,regfile_fsm_en,wr_dav:
std_logic;
component partial_reg is
signal
port (write: in std_logic_vector(11 downto 0); corom_fsm_adr1,corom_fsm_adr2,regfile_fsm_adr1,
regfile_fsm_adr2: std_logic_vector(3 downto 0);
wr_en,rd_en: in std_logic;
signal co1,co2: std_logic_vector(9 downto 0);
ad1,ad2: in std_logic_vector(3 downto 0);
signal x1,x2: std_logic_vector (11 downto 0);
rd1,rd2: out std_logic_vector(11 downto 0));
signal arith_fsm:std_logic_vector(1 downto 0);
end component;
begin
label1: component partial_fsm port map

component partial_rom is
(clk=>clk, (write=>sample_in,
reset=>reset,ctrl_arith=>arith_fsm,ctrl_rom_en=>cor wr_en=>wr_dav,ad1=>regfile_fsm_adr1,ad2=>regfil
om_fsm_en,ctrl_rom_ad1=>corom_fsm_adr1,ctrl_ro e_fsm_adr2,rd1=>x1,rd2=>x2,rd_en=>regfile_fsm_e
m_ad2=>corom_fsm_adr2, n);
ctrl_reg_en=>regfile_fsm_en,
ctrl_reg_ad1=>regfile_fsm_adr1,ctrl_reg_ad2=>regfi
le_fsm_adr2,dav=>wr_dav); label4: component partial_arithmetic port map
(co1=>co1,co2=>co2,x1=>x1,x2=>x2,ctrl=>arith_fs
label2: component partial_rom port map m,dav_ctrl=>wr_dav,clk=>clk,output=>output);
(ad1=>corom_fsm_adr1,ad2=>corom_fsm_adr2,rom
_enable=>corom_fsm_en,co_low=>co1,co_high=>co dav<=wr_dav;
2);
end behave;
label3: component partial_reg port map

Assignment 2 Xinwei Xu 870209

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Assignment 2 Xinwei Xu 870209

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ASSIGNMENT 2 XINWEI XU 870209-9311

1. FULLY SERIAL FIR

3.PARTIALY PARALLEL(2 macs)

Fully serial needs about 1300 NAND gates

Fully parallel needs about 13000 NAND gates

Partially parallel (2 MACS a cycle) needs about 2500 NAND gates

2. VHDL code for each FIR (in the appendix)

4. Are there any paths cross the component boundary?

5 . What is the best and worst case utilization factor?

library IEEE; end entity;

Use IEEE.std_logic_signed.all; architecture behave of fsm is

Use IEEE.std_logic_arith.all; subtype state is integer range 0 to 22;

signal pres_state, next_state: state;

entity fsm is signal temp_dav: std_logic;

port (clk: in std_logic;

reset: in std_logic; begin

ctrl_arith: out std_logic_vector(1 downto 0); dav<=temp_dav;

ctrl_corom_en: out std_logic; process(pres_state)

ctrl_corom_adr: out std_logic_vector(3 downto 0); begin

ctrl_regfile_adr: out std_logic_vector(3 downto 0); case pres_state is

ctrl_regfile_rden:out std_logic; when 0 => ----c0*x0

dav:out std_logic); ctrl_arith<="00";

next_state<=pres_state+1; when 4=> ------sum+t2

when 1 => ------c1*x1 ctrl_regfile_rden<='0';

ctrl_corom_adr<="0001"; --c1 next_state<=pres_state+1;

ctrl_regfile_adr<="0001"; when 5=> ------c3*x3

when 2=> ------sum+t1 ctrl_regfile_adr<="0011";

temp_dav<='0'; when 6=> ------sum+t3

when 3=> ------c2*x2 ctrl_regfile_rden<='0';

ctrl_regfile_rden<='1'; when 11=> ------c6*x6

when 8=> ------sum+t4 ctrl_regfile_adr<="0110";

temp_dav<='0'; when 12=> ------sum+t6

when 9=> ------c5*x5 ctrl_regfile_rden<='0';

ctrl_regfile_rden<='1'; when 13=> ------c7*x7

when 10=> ------sum+t5 ctrl_regfile_adr<="0111";

when 14=> ------sum+t7 ctrl_regfile_adr<="1001";

temp_dav<='0'; when 18=> ------sum+t9

when 15=> ------c8*x8 ctrl_regfile_rden<='0';

ctrl_regfile_rden<='1'; when 19=> ------c10*x10

when 16=> ------sum+t8 ctrl_regfile_adr<="1010";

temp_dav<='0'; when 20=> ------sum+t10

when 17=> ------c9*x9 ctrl_regfile_rden<='0';

ctrl_regfile_rden<='1'; if reset='1' then

next_state<=pres_state+1; if rising_edge(clk) then

when 22=> ------sum+t11 pres_state<=next_state;

ctrl_arith<="11"; end if;

ctrl_regfile_rden<='0'; end process;

temp_dav<='1'; end behave;

Architecture behave of co_rom is

entity co_rom is type romtype is array (11 downto 0) of

co_rom_output: out std_logic_vector( 9 downto is

for i in adr'range loop rom(1):="0000000110";

result := result * 2; -- converting rom(2):="0000010101";

if adr(i)='1' then -- std_logic_vector rom(3):="0001000100";

result := result + 1; rom(4):="0000100100";

end if; rom(5):="1000000100";

end loop; rom(7):="0110000101";

end procedure; rom(8):="0000101001";

variable conv: integer range 0 to 12; end if;

variable rom: romtype; end process;

begin end behave;

USE IEEE.std_logic_1164.all; rd_en: in std_logic);

port (wr:in std_logic_vector(11 downto 0); Architecture behave of delayline is