module etaa(a,b,cin,s0,s1,s2,s3,s4,s5,s6,s7,cout);

input [7:0]a,b;
input cin;
output s0,s1,s2,s3,s4,s5,s6,s7;
output cout;
reg s0,s1,s2,s3;
wire w1,w2,w3,w4,w5,w6,w7;

assign w1=a[3] & b[3];/* in accurate part*/

assign w2=a[2] & b[2];
assign w3=a[1] & b[1];
assign w4=a[0] & b[0];
always @(a or b or w1 or w2 or w3 or w4)

if (w1 == 1)
begin
s3=1'b1;
s2=1'b1;
s1=1'b1;
s0=1'b1;
end
else
if (w2 == 1)
begin
s3=a[3] | b[3];

s2=1'b1;
s1=1'b1;
s0=1'b1;
end

else

if (w3 == 1)
begin
s3=a[3] | b[3];
s2=a[2] | b[2];
s1=1'b1;
s0=1'b1;
end

else

if (w4 == 1)
begin
s3=a[3] | b[3];
s2=a[2] | b[2];
s1=a[1] | b[1];
s0=1'b1;
end

else
begin
s3=a[3] | b[3];
s2=a[2] | b[2];
s1=a[1] | b[1];
s0=a[0] | b[0];
end

fa f1(a[4],b[4],cin,s4,w5);/* accurate part*/

fa f2(a[5],b[5],w5,s5,w6);
fa f3(a[6],b[6],w6,s6,w7);
fa f4(a[7],b[7],w7,s7,cout);

endmodule

module fa(a,b,c,s,x);
input a,b,c;
output s,x;
assign s= a^b^c;
assign x=(a&b)|(b&c)|(c&a);

endmodule