Exp. No.

6 (a) : 1x2 DEMULTIPLEXER in GATE LEVEL

Code

`timescale 1ns / 1ps

module Demux1x2_GL(Out0,Out1,S,In);

output Out0,Out1;
input S,In;

not (Sbar,S);
and (Out0,Sbar,In);
and (Out1,S,In);

endmodule

Test bench

`timescale 1ns / 1ps

module tb_Demux1x2_GL;

reg S,In;
wire Out0,Out1;

// Instantiate the Unit Under Test (UUT)

Demux1x2_GL uut (Out0,Out1,S,In);

initial
begin
S = 0;
In = 0;
#40 S=1;
#40 $finish;
end

always

#2 In=~In;

endmodule
 Exp. No. 6 (b) : 1x2 DEMULTIPLEXER in DATAFLOW

Code

`timescale 1ns / 1ps

module Demux1x2_DF(Out0,Out1,S,In);

output Out0,Out1;
input S,In;

assign Out0=(~S)&In;
assign Out1=S&In;

endmodule

Test bench

`timescale 1ns / 1ps

module tb_Demux1x2_DF;

reg S,In;
wire Out0,Out1;

// Instantiate the Unit Under Test (UUT)

Demux1x2_DF uut (Out0,Out1,S,In);

initial
begin
S = 0;
In = 0;
#40 S=1;
#40 $finish;
end

always
 #2 In=~In;

endmodule

Exp. No. 6 (c) : 1x2 DEMULTIPLEXER using CONDITIONAL OPERATOR

Code

`timescale 1ns / 1ps

module Demux1x2_CondOper(Out0,Out1,S,In);

output Out0,Out1;
input S,In;

assign Out0=S? 0 : In;

assign Out1=S? In : 0;

endmodule

Test bench

`timescale 1ns / 1ps

module tb_Demux1x2_ CondOper;

reg S,In;
wire Out0,Out1;

// Instantiate the Unit Under Test (UUT)

Demux1x2_ CondOper uut (Out0,Out1,S,In);

initial
begin
 S = 0;
In = 0;
#40 S=1;
#40 $finish;
end

always

#2 In=~In;

endmodule

Exp. No. 6 (d) : 1x2 DEMULTIPLEXER using CASE

Code

`timescale 1ns / 1ps

module Demux1x2_Case(Out0,Out1,S,In);

output reg Out0,Out1;

input S,In;

always @ (In,S)
begin
case(S)
0 : begin Out0=In; Out1=0; end
1 : begin Out0=0; Out1=In; end
default : begin Out0=1’bx; Out1=1’bx; end

endcase
end

endmodule

Test bench
`timescale 1ns / 1ps

module tb_Demux1x2_ Case ;

reg S,In;
wire Out0,Out1;

// Instantiate the Unit Under Test (UUT)

Demux1x2_ Case uut (Out0,Out1,S,In);

initial
begin
S = 0;
In = 0;
#40 S=1;
#40 $finish;
end

always

#2 In=~In;

endmodule

Exp. No. 6 (e) : 1x2 DEMULTIPLEXER using IF-ELSE

Code

`timescale 1ns / 1ps

module Demux1x2_IF(Out0,Out1,S,In);

output reg Out0,Out1;

input S,In;

always @ (In,S)
begin
if (S)
begin
Out0=0;
Out1=In;
 end
else
begin
Out0=In;
Out1=0;
end
end

endmodule

Test bench

`timescale 1ns / 1ps

module tb_Demux1x2_ IF ;

reg S,In;
wire Out0,Out1;

// Instantiate the Unit Under Test (UUT)

Demux1x2_ IF uut (Out0,Out1,S,In);

initial
begin
S = 0;
In = 0;
#40 S=1;
#40 $finish;
end

always #2 In=~In;

endmodule

Exp. No. 6 (f) : 1x4 DEMULTIPLEXER using 1x2 DEMULTIPLEXERS

Code

`timescale 1ns / 1ps

module Demux1x4_Struct(Out0,Out1,Out2,Out3,S,In);
output Out0,Out1,Out2,Out3;
input In;
input [1:0] S;

Demux1x2_GL DM11 (W1,W2,S[1],In);

Demux1x2_GL DM21 (Out0,Out1,S[0],W1);
Demux1x2_GL DM22 (Out2,Out3,S[0],W2);

endmodule

Test bench

`timescale 1ns / 1ps

module tb_Demux1x4_Struct;

reg [1:0] S;
reg In;
wire Out0,Out1,Out2,Out3;

Demux1x4_Struct uut (Out0,Out1,Out2,Out3,S,In);

initial
begin
S = 0;
In = 0;
#40 S=1;
#40 S=2;
#40 S=3;
#40 $finish;
end

always

#2 In=~In;

endmodule

Exp. No. 7 (a) : 8x3 ENCODER with ENABLE

Code

`timescale 1ns / 1ps

module Enc8x3(Y,En,A);
output reg [2:0] Y;
input En;
input [7:0] A;

always @ (En,A)
begin
if (En==1)
begin
case(A)
8'b0000_0001 : Y=3'b000;
8'b0000_0010 : Y=3'b001;
8'b0000_0100 : Y=3'b010;
8'b0000_1000 : Y=3'b011;
8'b0001_0000 : Y=3'b100;
8'b0010_0000 : Y=3'b101;
8'b0100_0000 : Y=3'b110;
8'b1000_0000 : Y=3'b111;
default : Y=3'b000;
endcase
end
else Y=3'bz;
end

endmodule

Test bench

`timescale 1ns / 1ps

module tb_Enc8x3;

reg En;
reg [7:0] A;
wire [2:0] Y;

Enc8x3 uut (Y,En,A);

initial begin
En = 1;A = 0;
#20 A=1; #20 A=2; #20 A=4; #20 A=8; #20 A=16; #20 A=32;
 #20 A=64;#20 A=8'bx11; #20 En=0; #20 A=4; #20 A=8; #20 A=16;
#20 $finish;
end

endmodule

Exp. No. 7 (b) : 3X8 DECODER with ENABLE

Code

`timescale 1ns / 1ps

module Dec3x8(Y,En,A);

output reg [7:0] Y;

input En;
input [2:0] A;

always @ (En,A)
begin
if (En==1)
begin
case(A)
3'b000 : Y=8'b0000_0001;
3'b001 : Y=8'b0000_0010;
3'b010 : Y=8'b0000_0100;
3'b011 : Y=8'b0000_1000;
3'b100 : Y=8'b0001_0000;
3'b101 : Y=8'b0010_0000;
3'b110 : Y=8'b0100_0000;
3'b111 : Y=8'b1000_0000;
default : Y=8'b0000_0000;
endcase
end
else Y=8'bz;
end
endmodule

Test bench

`timescale 1ns / 1ps

module tb_Dec3x8;

reg En;
reg [2:0] A;
wire [7:0] Y;

Dec3x8 uut (Y,En,A);

initial begin
En = 1;A = 0;
#20 A=1; #20 A=2; #20 A=3; #20 A=4; #20 A=5; #20 A=6;
#20 A=7; #20 A=3'b11x; #20 En=0; #20 A=4; #20 A=5; #20 A=6;
#20 $finish;
end

endmodule

Exp. No. 7 (c) : 4x2 PRIORITY ENCODER with ENABLE

Code

`timescale 1ns / 1ps

module PriorityEnc4x2(Y,En,A);

output reg [1:0] Y;

input En;
input [3:0] A;

always @ (A,En)
begin
if (En==1)
begin
casex(A)
4'bxxx1 : Y=2'b00;
4'bxx1x : Y=2'b01;
4'bx1xx : Y=2'b10;
4'b1xxx : Y=2'b11;
default : Y=2'bx;
endcase
end
else Y=2'bz;
end

endmodule

Test bench

`timescale 1ns / 1ps

module tb_PriorityEnc4x2;

reg En;
reg [3:0] A;
wire [1:0] Y;

PriorityEnc4x2 uut (Y,En,A);

initial begin
En = 1;A = 0;
#20 A=4'b1100;
#20 A=4'b0111;
#20 A=4'b11x0;
#20 A=4'b0011;
#20 $finish;
end

endmodule

Exp. No. 8 : 4 – bit COMPARATOR

Code

`timescale 1ns / 1ps

module Comp4bit(AgtB,AeqB,AltB,A,B);

output reg AgtB,AeqB,AltB;

input [3:0] A,B;

always @ (A,B)
begin
AgtB=0;AeqB=0;AltB=0;
if (A>B)
AgtB=1;
else if (A==B)
AeqB=1;
else if (A<B)
AltB=1;
else
begin
AgtB=1'bx;
AeqB=1'bx;
AltB=1'bx;
end
end
endmodule

Test bench

`timescale 1ns / 1ps

module tb_Comp4bit;

reg [3:0] A,B;

wire AgtB,AeqB,AltB;

Comp4bit uut (AgtB,AeqB,AltB,A,B);

initial begin
A = 0;B = 0;
#20 A=5; B=7;
#20 A=7;
#20 A=10;
#20 B=4'b111x;
#20 $finish;
end

endmodule

Exp. No. 9 : ALU with 8 INSTRUCTIONS

Code

`timescale 1ns / 1ps

module ALU(Y,S,A,B);

output reg [7:0] Y;

input [2:0] S;
input [3:0] A,B;

always @ (A or B or S)
begin
case(S)
3'b000 : Y=A+B;
3'b001 : Y=A-B;
3'b010 : Y=B-A;
3'b011 : Y=A*B;
 3'b100 : Y=A&B;
3'b101 : Y=A|B;
3'b110 : Y=A;
3'b111 : Y=B;
default : Y=8'bx;
endcase
end
endmodule

Test bench

`timescale 1ns / 1ps

module tb_ALU;

reg [2:0] S;
reg [3:0] A,B;
wire [7:0] Y;

ALU uut (Y,S,A,B);

initial begin
S = 0;A = 4;B = 2;
#20 S=1;
#20 S=2;
#20 S=3;
#20 S=4;
#20 S=5;
#20 S=6;
#20 S=7;
#20 $finish;
end
endmodule