1 2 3 4 5 6

C224
U19A U19B Place twisted pair Tx and Rx termination close to DP83843 U19F
DP83843 DP83843 DP83843
MII Interface PMD Interface 10p Power and Ground Pins
R69 R70 J9
49.9 49.9 +5V
L8
MDC 35 74 C225 1 72 54
MDC TPTD+ CD_VDD0 CPTW_DVDD +5V
2 FB
+5V R108 39 34 73 3 C231 C235
MDIO TPTD- 10p L9
D C228 4 0.1u 71 53 0.0033u D
R67 CD_GND0 CPTW_DVSS
67 5 +5V FB
+5V TPRD+
C8 1.5k 6 76 TW_AVDD
10p 7 CD_VDD1 L10
0.1u 65 68
24

TPRD- R71 49.9 R72 49.9 TW_AVDD +5V

U20 8 JP6 C264 FB
SN74CBT3384 66 0.1u 75 64 C236 C237
VCM_CAP 1 CD_GND1 TW_AGND 0.0033u
3 2 0.1u
VCC

1A1 1B1 R103 39 RJ45-SI 2 L11

RXD0 4 5 18 C226 C227 10 70
1A2 1B2 RX_CLK PCS_VDD SUB_GND1
RXD1 7 6 0.1u 0.0033u HEADER 2 FB
1A3 1B3 RA15 TW_AVDD
RXD2 8 9 12 43 C265
1A4 1B4 RXD[3] FXTD+/AUITD+ L12
RXD3 11 10 1 8 0.1u 11 52
1A5 1B5 PCS_VSS CP_AVDD +5V
1 2 7 13 44 FB
1OE RXD[2] FXTD-/AUITD- R76 R77 R78 R79 R80 R81
3 6 J11 +5V C238 C239
RX_CLK 14 15 4 5 14 49 82 82 130 82 91 91 6 51 0.001u 0.1u
2A1 2B1 RXD[1] FXRD-/AUIRD- IO_VDD1 CP_AGND
RX_DV 17 16 9
2A2 2B2 Veet
MDIO 18 19 39 15 50 C234
2A3 2B3 RXD[0] FXRD+/AUIRD+
TX_CLK 21 20 8 0.001u 7 79
2A4 2B4 R68 TD+ IO_VSS1 TR_AVDD +5V
22 23 23 47
GND

2A5 2B5 +5V RX_EN FXSD-/CD-

13 10k 7 16 C240
2OE TD- IO_VDD2
NC 19 48 C2290.1u 80 0.1u
RX_ER FXSD+/CD+ TR_AGND
6 C266
R125 Vcct
20 0.001u 17
12

RX_DV IO_VSS2
39 5 46
Vccr AUIFX_VDD +5V
26
C R109 IO_VDD3 C
33 78 NC C2300.0033u 4 C241
TX_CLK TXAR100 SD
C267 45 0.1u
39 AUIFX_GND
FPGA inputs TXD3 28 60 R74 69.8k 3 0.001u 27
TXD[3] TWREF RD- IO_VSS3
RXD[0-3] - Receive Data
RX_DV - Receive Data Valid TXD2 29 61 R75 4.87k 2 36 57
TXD[2] BGREF RD+ IO_VDD5 ATP_GND
FPGA outputs TXD1 30 1 C268
TXD[1] R82 R83 R84 R85 R86 R87 Veer
MDC - Management Data Clock 0.001u 37 77
130 130 360 130 115 115 IO_VSS5 SUB_GND2
TX_CLK - Transmit Clock TXD0 31 32
TXD[0] Optek OPF5101 IO_VSS4
TXD[0-3] - Transmit Data C233
TX_EN - Transmit Enable TX_EN 25 JP7 2
TX_EN NC
R102 10k 24 1 0.1u
FPGA bidirectional 55
TX_ER 2 NC
MDIO - Management Data I/O
Place Tx termination near Optek transceiver HEADER 2 C232 56
NC
FPGA clock input Place Rx and CD termination near DP83843
RX_CLK - Receive Clock 58
10u NC
59
NC
JP3
U19C 62
3 +5V NC
DP83843
2
+5V Clock Interface & Reset
1
B JP8 X2 B
HEADER 3
2
1 3 9 U19D U19E
1 OE Output X1
JP4 DP83843 DP83843
HEADER 2 R5 NC 8 Device Configuration Interface LED Interface/PHY Address Interface
10k L13 X2 3 +5V
2 4
GND Vcc FB +5V 2
1 R97 10k
C243 1 4 42
0.0033u RESET AN0 LED_COL/PHYAD[0] +5V
CTS CB3 25.00000 MHz HEADER 3
DigiKey CTX276CT 3 41 R98 10k
AN1 LED_TX/PHYAD[1]
40 R99 10k
R73 LED_RX/PHYAD[2]
63
THIN R10010k
10k 39
LED_LINK/PHYAD[3]
NC 22
SYMBOL R10110k
U21 38
LED_FDPLO/PHYAD[4]
Ethernet_clk_enable 2 6 NC 69
RESIN RST SERIAL10
7 5 JP5 5 NC
+5V SENSE RESET SPEED10 D13 D14 D15 D16 D17
21
2 COL LED LED LED LED LED
8 4
VCC GND 1
3 1 22
CT REF R89 R88 R91 CRS
10k HEADER 2
C242 TL7705A C244 10k 10k
2.2u 0.1u
A 100base-FX: JP3=23 JP4=open JP5=closed A
100base-TX: JP3=23 JP4=12 JP5=open R92 R93 R94 R95 R96
10baseT JP3=12 JP4=12 JP5=open 1k 1k 1k 1k 1k Title

Size Number Revision

+5V
B
Date: 6-Apr-2007 Sheet of
File: C:\ppham\sequencer\sequencer2.ddb Drawn By:
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