{

} }

FPGA {

wishbone bus } .~ } FPGA ~|I/O ~

} ~ Slave Master { } { }| } BUS } ~ }
.
.}
~ }} BUS
} } ~ } BUS ~ BUS { $Data BUS
~|~.} |~ BUS . } ~|} ~ ~IC .~| WR/RD ~|~
STB (strobe) ,CYC (cycle),ACK(acknowledge) ~ .~ ~ ~|} { } BUS
~} ~|} ~} } | handshaking ~ } }} high ~| ~ $time reset
wishbone ~|~ }| Slave .| } ~|} } ~ } ~IC ~ |
. } BUS
} high CYC_I STB_I ~
. } ~|~ } ~} FPGA }} }
{ }.} ~ } }} high
. ~ } WE(write enable ) ~ Master
} Slave ~|} } } (high) |} ~ ~ ~} ~ }| } ~}
Master } } ~ low ~ } } $} | ~ } ~ ~ . BUS ~|}
} } $Slave .} } Slave ~|} } | ~ } $| RUN ~
~|~ ACK (high) ~ ~ { ~ ~~ ~|} ~} } | handshaking
$| low } STB ~ Master .| set } { } ~ }~} .
LOW } ACK ~ ~ Slave { }.}|{ FPGA ~ } |
.~| wishbone bus } BUS ~|
~ | ~ HAND SHAKING } .
$ set } ACK ~ }| Slave |~ bus | ~|} } ~
<http://www.opencore.com> ~ }| wishbone

~ ~~ 34

255;
BEGIN
sel<= 1when ADR_IN=x8000" else 0;

~ . Master | Slave
~ ~ } } ~|} ~} }|
} ~ ~} | Slave }
.} ~

PROCESS (CLK,RESET)
BEGIN
if (RESET=1') then
OUTPUT <=11111111";
else
if (CLKevent and CLK=1') then
if (sel=1' and WE_IN=1' and STB_IN=1'
and CYC_IN=1') then OUTPUT<=DAT_IN;
end if;
end if;
end if;
END PROCESS;

Master } ~ Slave BUS

| ~ Slave . } } } ~
~~ } . ~ | ~~ ~ ACK ~
~. } handshaking ~ |
} extention { ~ } BUS { sel
.~| 0X8000 { } ~` } ..| ~ } }
~|sel=1 ~ { | ~ valid {
~|~ $} ~} ~ write
~ ~|} } STB=1 ,CYC=1, WE=1
~ |~ ~ ~| } DAT_I
.| |
~ | ~ } } } ~ }20000 } ~

bus } Master } } 8051 ~`

.} ~} wishbone

Entity Declaration
ENTITY wish_output IS
{{ALTERA_IO_BEGIN}} DO NOT
REMOVE THIS LINE!
PORT
(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
WE_IN : IN STD_LOGIC;
STB_IN : IN STD_LOGIC;
CYC_IN : IN STD_LOGIC;
DAT_IN
:
IN
STD_LOGIC_VECTOR(7 downto 0);
ADR_IN
:
IN
STD_LOGIC_VECTOR(15 downto 0);
DAT_O
:
OUT
STD_LOGIC_VECTOR(7 downto 0);
ACK_O : OUT STD_LOGIC;
OUTPUT
:
OUT
STD_LOGIC_VECTOR(7 downto 0)
);
{{ALTERA_IO_END}} DO NOT
REMOVE THIS LINE!

~ } { } hand shaking ~} } ~
. ~ }| ~ ~ END wish_output;
#include <8052.h>
#include stdio.h
void main (void)
{
35 ~ ~~

Architecture Body
ARCHITECTURE wish_output_architecture
OF wish_output IS
SIGNAL sel,ACK_OK : STD_LOGIC;
SIGNAL COUNT : INTEGER RANGE 0 TO

OUT_SIGNAL : OUT STD_LOGIC

);
END COMPONENT;
COMPONENT OR_2IN
PORT
(
A,B : IN STD_LOGIC;
OUT_SIGNAL : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL IN1,IN2,IN3,IN4 : STD_LOGIC;
SIGNAL AND1_OUT,AND2_OUT, OR_OUT
: STD_LOGIC;
BEGIN
IN1 <= SWITCH1;
IN2 <= SWITCH2;
IN3 <= SWITCH3;
IN4 <= SWITCH4;
inst1 : AND_2IN
PORT MAP
(
A => IN1,
B => IN2,
OUT_SIGNAL => AND1_OUT
);
inst2 : AND_2IN
PORT MAP
(
A => IN3,
B => IN4,
OUT_SIGNAL => AND2_OUT
);
inst3 : OR_2IN
PORT MAP
(
A => AND1_OUT,
B => AND2_OUT,
OUT_SIGNAL => OR_OUT
);
LED1 <= AND1_OUT;
LED2 <= OR_OUT;
LED3 <= AND2_OUT;

__xdata unsigned long count;

__xdata unsigned char * __data p;// Pointer (in
internal RAM) pointing to unsigned char stored
in external RAM
__xdata unsigned char * __data p2;// Pointer
(in internal RAM) pointing to unsigned char
stored in external RAM
xdata unsigned char buffer[128];
// volatile xdata __at 0xf000 test;
unsigned char LED;
LED=0x01;
p = (__xdata unsigned char*) (0x8000);
p2 = (__xdata unsigned char*) (0x0500);
for (count=0;count <sizeof (buffer);count++)
buffer[count]=(unsigned char) (count);
while (1) {
for (count=0;count<200000;count++)
{
//
test = LED;
*p = LED;
*p2 = LED;
}
LED = LED <<1;
if (LED==0) LED=1;
};
}

}} $" } }}$ ~ }
} ~Slave } ~ ~Slave
~} ~ | } ~} ~ BUS
~Slave } { }} }}
handshaking ~| } ~.~| ~
~` $ ~ wishbone bus | ~
. ~ error ~|~ ~ }| BUS
~ }| ~|} ~
} ~ } . ~ } w w w. o p e n c o r e . c o m
|~{ } } ~ | ~ VHDL
}| VHDL } ~` ~
.} {
PORT
(
SWITCH1, SWITCH2, SWITCH3,
SWITCH4 : IN STD_LOGIC;
LED1, LED2, LED3 : OUT STD_LOGIC
);
END;
PORT
(
A,B : IN STD_LOGIC;

END;
~ ~~ 36