203

4.0
2014


/203,

.

,VHDL,
, Digilent
Xilinx Spartan 3
.
fanin/fanout,
onehot, ()
,datapathcontrolpath,
, ,
controlpath.(ripplecarry,carryselect,
carrysave,.),(Wallace,Daddamultipliers),(restoring,non
restoring),.
, ,
,.
VHDL,
(designflow),,,,
(place and route), .
datapathcontrolpath
.

. ,
. ABEL
Wakerly ,
.
Wakerly
(.. group ripple carry adder
MSITTLgroupripplecarryadder).
,
.
!
..

1.

,,

.
(
), /,
, .
..
Beethoven
,
,
.

.
1. .
,
,
,
. ,
, (..

.
2.
.,6NAND
74LS00 NAND ,

.
,
(topdowndesign),

(bottomupdesign).,AirbusA320
,(airframe),
(), (avionics).
.

.
Karnaugh ,
PCI
.
(Computer Aided Design CAD),
.
,
(designflow).,VHDL,
:
2

.VHDL
VHD

BEHAVIORALMODEL

.MODELSIM
ISESIMULATOR

SIMULATION

.VHDL
VHD

/
BEHAVIORAL/STRUCTURALMODEL

.MODELSIM
ISESIMULATOR

SIMULATION

.SYNOPSIS
ISESYNTHESISTOOL
NETLIST

SYNTHESIS

.MODELSIM
ISESIMULATOR

SIMULATION

.XILINX
.BIT

.MODELSIM
ISEPOSTPLACEANDROUTESIMULATOR

PLACEANDROUTE

SIMULATION

1. .
.
,
, .
, ()
,
.
,
,
,.
2.
.
( testbenches)
.
3. / .
(.. )
(.. )
. .
,(pipelineregisters)
.
4.
.
5..flipflops,
( ) ,
(Floating Point) .
(netlist),
,.
frontenddesign
backenddesign,
.
(.. FPGA Xilinx),
.
3.,.
4. (place and route),
(.. FPGA).
(..FPGAVLSI)
FPGA . ,
,
,
.
(,FPGAXilinx.bit),
.
,,.
5 ,

.
4

 ,

.
, ,
.
, .. place and
routeFPGA,(..
FPGA)
(.. ).

,
.

2.

o
o TTL
o (tristatebuffers)
o Flipflops(Latches)
o (FSM) FlipFlop
,FlipFlop
o n
o MSI:,.
o ,
o ; (.
2**)
o BCD,GrayCode,.

, , (
totem pole TTL), , Gray,
Karnaugh.MealyMoore.
.
flip flops (D,JK,T). MSI/LSI, ,
, , ,
(.. whatif ).
,RCLoad.
, .. (ring counters) Johnson
.(**).
. BCD.
(). topdown bottomup, (decomposition)
(partitioning).

2.1 01
1()
0, 0
1.:0
.,TTL
0(
TTL1
),.
.
0 1
, .
TTL<0.8V0>1.6V1,
:


0:()<0,8V
1:()>1,6V
0,8V<x<1,6V
.

2.2

,(..01).
0,1,(,),
(),
01.
..2.5VoltTTL,,
.
.
,
,01(10)
.2.1.

2.1


2.3 TTL

2.2NANDTTLLS
2.2 NAND TTL LS.
.
totempole()
, 1 0 .
0 1 .
..

TTL1.

2.4 TotemPole(OpenCollector)

HTTLTotempole.transistor,()
1 ( 4V ) () 0 (
0.2V ).
.
, 1
.,
.
totempole.
2.5 (tristatebuffers)

. transistor
transistor ,
.


IN

OUT

21

2.6 Flipflops(Latches)
Flip Flop ,
,
(GateEnable)
.
, ,
FlipFlop.

10

2.7 n(n)
n,:
1.n2n
2.()nbits.
bit.
3.1bit.
n
Boole Bits .
,

,(..4,
01011100010111011100).
(n+1):
1. n
2. (MSB)
01.
3.
.

n1

n2

11

n3

n4

00
01
11
10

00
(0000)
(0100)
(1100)
(1000)

01
(0001)
(0101)
(1101)
(1001)

11
(0011)
(0111)
(1111)
(1011)

10
(0010)
(0110)
(1110)
(1010)

Karnaugh4

Karnaugh 4 , ( ) 4
,.
12

 1 1.
1bit
, 1
BooleAx+Ax=A,
.
,,.

2.8 MSI:,.

Multiplexer

Demultiplexer:n=log2k

13

Encoder
:()
.

2.9 ,

Decoder
nkk
2n.

2.10 ; (.
2**)

,
(..4bitBCDsegments7segmentLEDdisplay)
.
2.11

BCD,GrayCode,.

Gray:

Gray
0000

0000

0001
0011

0001
0010

0010
0110

0011
0100

0111
0101

0101
0110

0100

0111

14

1100
1101

1000
1001

1111
1110

1010
1011

1010
1011

1100
1101

1001
1000

1110
1111

2.12

(EN_CTR = 1) , MSB Q7
IN Q0 .
(
SR, SL), ( , .. IN7IN0).
S1,S0
:

S1
0
0
1
1

S0
0
1
0
1

,Q7<=SR
,Q0<=SL

15

TTL74LS194
(4bit)74LS198(8bit).
TTL(..PRESETCLEARFlipFlopPRCLR0,
PRCL)
. ,
PRCLR,.

,:
FLIPFLOP

101011 ( Flip Flop).
1FlipFlop
.FlipFlop
1 0 , AND
. ,
FlipFlop.

o Wakerly,/5.2,394ff
o

Wakerly,/8.1.4,789ff

TTL
o Wakerly,/3.9.23.10.2,175ff
o

Wakerly,/3.11,197ff
16

(tristatebuffers)
o Wakerly,/3.7.3,148ff
o

Wakerly,/5.6,456ff

Flipflops(Latches)
o Wakerly,/7.2,632ff(
FF)

(FSM) FlipFlop
,FlipFlop
o Wakerly,/7.4,667ff(
)

n
o Wakerly,/2.14,67

MSI: , .
MSI
; (.
2**)
o Wakerly,/5.4,419ff

17

3.

o /RC(TCO)
o
o (ring)
o Johnson
o BCD
o , (..
)

3.1

.
,
, . TTL 1960
,
.
:

IN/OUT

CKCLOCK
To ,
,
, ..
LD
IN
IN_n1..IN_0
,n
(_D_A)
Bits ( TTL n=4
_..._D).

LD.

LD
, 0.

ENABLE,,

, ,
LD.
IN
UP/DN

(U/D=1)(U/D=0).
IN
ENABLE(..ENT, .
ENP,ENQ)
(.. ENABLE, EN), 1
0 (
, .. ENQ).
ENABLE

, (
)
.ENABLE
.
OUT
OUT_n1..OUT..0 ,OUT_0=LSB.
18

OUT

(Q_D..Q_A)
RC(TCO)

,

(1...1),
,(0...0),
, .
1()0.

.3.1/

. ,
U/D . ,
LD(
RESET , 0...0).
ENABLERC.

3.2

.
.

,
. Flip Flop
,:bit
.,
. Bits
(..8),..
.,8Bit
01001111 01010000 (
) 01001111 > 01001110 > 01001100 > 01001000 > 01000000 >
01010000.

.3.1

3.3 RC(TCO)

RC
(cascade).ENABLE
RC
1,,(RC1
19

LD 0) . ,
4Bit90
9(BCD),
RC LD, 0000
1001(9)1111.

3.4 ;

FlipFlop,
Bits1,Bits0
. T Flip
Flops D FlipFlop FlipFlop.

Flip Flop ENABLE

Q.

FlipFlopnable

bit:

Qn
Dn

Qn

Clk

Qn1Qn2..Q0

UpCounternable

(ENABLE)
,(
10),
bit:

20

Qn
Dn

Qn

Clk
Qn1Qn2..Q0

EnT
EnP
En

EnQ

UpCounterEnable

,,
LD,w:

Qn
Dn

1
2
3

Qn

LD
Clk

Qn1Qn2..Q0
EnT
EnP
EnQ

En

UpCounterEnableLoad

, ,
Flip Flop
FlipFlop0,:

21

Qn
Dn

1
2
3

Qn

Clk

LD

Qn1Qn2..Q0

Qn1Qn2..Q0

U/D
EnT
EnP
En

EnQ

Up/DownCounterEnableLoad

,3Bit:

Q2

D2

1
2

Q1Q0

LD

Q0

U/D

Q0

U/D

EnT
EnP
En

Q0

Clk

LD

Q1Q0

Q1

Clk

LD

U/D

EnT
EnP
EnQ

Q0
D0

Q2

Clk

EnQ

Q1
D1

EnT
EnP

En

EnQ

En

3bitCounter

3.5

RC ENABLE ,
LD, U/D, ENABLE

22

LE,(ENP
):

LD
En

U/D
LD

U/D
EnT
EnP
EnQ

U/D

LD

EnT
RC

EnQ

RC

Clk

8bitcounter24bitcounters

3.6 /LD

(
),

.
LD (. 0) 0 5
3..0=0000LDNANDQ2Q0,
5(.Q3..Q0=0101)NAND0,
000004.
LD6,NANDQ2
Q1.

3.7

EN3
11 (0011 1011) LD.
3..0=0011(3),U/D=1(),LD=
(Q3Q1Q0) ( LD 0 1011 Q2
101111dd),
1.

RESET 1
3,(LD
0) RESET AND
,NANDRESET0

23

0011.LD:LD=(Q3Q1Q0)RESET
DeMorganLD=(Q3Q1Q0+RESET).

3.8

,
Bits.
1 ,
Bit.
waitstates,
Motherboard
, .
4.3.

3.9

:
0000
1000
0100
0010
0001

()1
FlipFlop.
4Bits5FlipFlop,
0000.Q0Q3:

24

Q4
0
1
0
1

Q4
1
0
1
0

Reset
0
0
1
1

PR/CL
0
0
1
1

, .
Q0Q3FlipFlopBits:

flipflop.

3.10 Johnson
Johnson:

0000
1000
1100
1110
1111
0111
0011
0001

Gray, 16
4Bit.HLSB01
MSB0.bit1flipflop.

25

Johnson

3.11 BCD

BCD 0 9 RC
0, +1.
,.
BCD:

BCD4Bit,9
0RC:

(reset0LD)

26

Q3Q0=111001(910)0000.
0000.

3.12

,31,28(
29), 31, 30, 31, 30, 31, 31, 30, 31, 30, 31. ,

.,112,
31
1,282,.(5Bit)
1
.

:
3.13
/RC(TCO)
Wakerly, / 8.4, 827ff (

)
3.14

Wakerly,/8.5.5,863
3.15
(ring)
Wakerly,/8.5.6,864
3.16
Johnson
Wakerly,/8.5.7,867
3.17
BCD
, 4 Bits
,00001001RC
.
27

3.18
, (..
)

.

link
http://en.wikipedia.org/wiki/Counter

1BCD
BCD, 4bit ,
,12bits,
12bit.
: Clock, Up/Down, EnT, EnP, EnQ, Ld, IN3..0
(EnTEnP1EnQ
0 ). Ld
,3..0
.OUT3..0,RC(1).
BCD.
,
, Up/Down 12 Bits.
Clock, Up/Down, En ( Enable ,
1). Q11 Q0.
,
.
,()
BCDbinary,/
(50 ) () (
)12Bits.
:Karnaugh.
: BCD Binary (),
;

2BCD
4bit,,
BCD(),12bit.
: Clock, Up/Down, EnT, EnP, EnQ, Ld, IN3..0
(EnTEnP1EnQ
0 ). Ld
28

,3..0
.OUT3..0,RC(1).
,
Up/DownBCD(BinaryCodedDecimal).
Clock,Up/Down,En(Enable).
C3..0(MSD),B3..0,A3..0(LSD).
.
:Karnaugh.

3
7 30
FSM '1' 1 1
. FSM D flip flops Preset,
ClearDQ,Q.
.FSM()
. Onehot.
Dflipflops,
.

29

4.

(FSM)
o FSMOneHot
o

Wakerly2.16,.
80ff
(FSM).
.
, (
0F0,.).

bit, FlipFlop,
.

FlipFlopFSM.
1(onehot)
log2#STATESFlipFlop(FlipFlop)
log22=1FlipFlop.

:
165stateslog2165=7,358FlipFlop.

4.2FSMONEHOT
flipflop1
1.

30

4.3
:

CPU,
waitstates.:

31

14 (wait
states).waitstates.

FSM (..
)
32

FSM
o

FSMOneHot
o ,,
o

http://en.wikipedia.org/wiki/One_hot_encoding

:MercuryCougar68
o Wakerly,/7.5,694ff
o

Wakerly,/7.7,706ff

33

5.

(FSM)
o 01011011101111...
o

01011011101111...
( FSM).
FlipFlop.

:
FSM

01
011 0111 01111011.1.
11 21 31 41
4931

010110111011110.11..1010110111.

493

:
493+(493+1)(493/2)1=122017(216217)
17bits.

:
2:
1.1(9bits)
2.1(9bits)

34

RC=11.
0.
ParallelLoad:
EN=Enable

(handshake)
FSM.
,,
,
.

35

FSM
o Wakerly,/7.8,714ff

1
, OUT1,
OUT2, . 100MHz ( ),
10nsec.

IN

1
OUT1
2
OUT2

=1OUT1=OUT2=0.10.
OUT1 0 1
1=50nsec (. ). 1
1().OUT21
2=80nsec OUT1
1,1()OUT21
2=80nsec1(OUT21
80nsecINOUT11).0
OUT2(=1,OUT1=0,OUT2=0).
DFlipFlop
,
FSM,1(
FSM),2
.
FSM,
, .
DFlipFlopPresetClear(0).
OUT1
OUT2.FSM.

36

 , OUT1,
OUT2, . 100MHz ( ),
10nsec.

IN

1
OUT1
2
OUT2

=1OUT1=OUT2=0.10.
OUT1 0 1
1=70nsec. 1 1 (
). OUT2 1
2=30nsecOUT11,
1()OUT212=30nsec
1(OUT2130nsec
IN OUT1 1). 0 OUT2
(=1,OUT1=0,OUT2=0).
D Flip Flop
,FSM,
1, 2
.
FSM,
, .
DFlipFlopPresetClear(0).
OUT1OUT2.

, =
+ , = 20. ..
()=(9+6)20=300.
FSM:
01

011

11 21

0111

01111011.1.

31 41

37

 , ,
4931.

6 Bits,
U/D (Up/Down), LD (Load active low), IN5IN0 (Parallel Input,
IN5=MSB),OUT5OUT0(Output,OUT5=MSB),RC(RippleCarry=ActiveHigh),EN(Enable=
ActiveHigh),,(
).,.

, RC,
Wakerly.,
bit , (.. 12
bit,18bit,24bit,.).
,
..

:
1. RESET ( 1
)
2. FSM, (
RESE).
3. FSM ,
().
buffers.
4. FSM()RESET
( ): 1,,,0,1,,,0, ( 1,,,0
).OUT.
5. FSM()RESET
( ): ,,1,,,,1,, . ( ,,1,
).OUT.
1,,1,0.

FSM,JK
FlipFlop()DFlipFlop.:
1. toplevelRESETOUT,
(A),RESET
OUT.
38

2. ,,
( Karnaugh, ).
.
tristatebuffers,,
0 1.
tristatebuffers1.
:2bit,
,
buffer.
Karnaugh.

39

6.

(FSM)
o
o RS232

6.1

, ,
,.
,
, .
, RS 232.
1, 0
8 Bits 0 1, Stop Bit
1.
7 Bit ASCII 1 2 Stop Bits,
Byte.

RS232

RS232

40

 ,
16 .
, 8 ( )
16 ,
.

6.2

,
10.
.
NewTransmission.

FSM
, ( Process)
Done.
Process
,Done
FSM .
handshake
.

41


Karnaugh
newtransmissionDone 00
Process
0
1

0
1

01

11

10

0
0

1
1

1
1

FSM
:

Process=New_Transmission+Process*Done
New_Transmission

D
Q

Done
Q'

12,
Bits (Bit Counter)
(Period Counter).
0000 1111 1111
0000. periodcounter0111
(710)
bit .
LD0000
1111.

ProcessbitFSM.

42

 periodcounter 16 enable bitcounter

8
. , 1000 (8)
0000,9,
start bit, ,
,
.

8 Bit,
4Bit.

FSM:

FSM (..
)
FSM
o Wakerly,/7.8,714ff

43

Wakerly,/7.8,714ff

FSM
o Wakerly,/7.8,714ff

:RS232.,,
o Wakerly,/7.5,694ff
o

Wakerly,/7.7,706ff

1
,debounced,
.
( , ).

,101
( ). ,
,
49,0
. ,
(..
,01,.).
(..,.).
2
. : Clock, Up/Down,
EnT,EnP,EnQ,Ld,IN3..0(EnTEnP1
EnQ0
). Ld ,
3..0.
OUT3..0,RC(1).
,
D Flip Flop ,
4Bit:
0,0,...0,(16 0 ),1,2,3,4,...,13,14,15,14,13,12,11,10,9,...,2,1,
. : 0 16 (
17)151,LD.
1601,2,3,...,15,14,13,..2,1,0.
,
.

44

7.

,
(),FaninFanoutTrees

o ()
o

FaninFanout
o faninfanout
o fanin/fanout
trees

().Fanin Fanout trees. ,

, .
.narytrees,
,
fanintreefanouttree
ripple carry, full adder.
CLA
fanin, / fanout. fanin
fanout.
fanin/fanout . FullLookahead Adder
fanin fanout.
45Bits.24bit.
,faninn
fanink logk(n) (n1)/(k1)
.fanouttrees,k
fanoutnfanout.

a. fanin fanout,

Wakerly, / 3.10.3, 190 fanout

().

45

8.

Hardware:

,hardware,preincrement/postdecrementpost
increment/predecrement. RAM .
stackfull/stackempty,Push/Pop.

H
..
(Push),
(Pop)(isEmptyisFull).
HWN+1Wbit
(stack pointer SP)
. o SP (0)10 (.1),
SP(1)10(.2).
SP ()10,
(.3).

Push
(.4)(.5):

46

Pop
(.6)(.7):

47

9.

o RippleCarry
o FullLookahead,GnPn
o GroupRippleCarry
o CarrySelect
o

.fulllookaheadaddition,GiPi
Ci 4 Bit.
ripple carry, (n),
/ . Carry Lookahead Adder (CLA),
Gi, Pi, Ci. Carry Select Group
Ripple Carry,
(group size),
fulllookaheadaddersripplecarryadders.CarrySave
.

9.1FullAdder1Bit
criticalpathFullAdderHalfAdders
OR3Cout.

FullAdders,,
..:

48


FA
OR.
9.2(RippleCarryAdder)4Bits
Bit 1td carry Sum
2td Carry .
Cout9td

:9

:(2+1)
49

:4x5=20

:5

9.2Carrylookaheadadder(CLA)

Gi Ai Bi (Generate)
Pi Ai Bi (Propagate)

S i Pi Cin,i
C 0 G0 P0 C in
C1 G1 P1 C 0 G1 P1 G0 P1 P0 C in
C 2 G2 P2 C1 G2 P2 G1 P2 P1 G0 P2 P1 P0 C in

C i Gi Pi C i 1 Gi Pi Gi 1 Pi Pi 1 Gi 2 Pi Pi 1 P1 G0 Pi Pi 1 P0 C in

CLAfanin4fanout.

C120=G120+P120G119+P120P119G118+...+P120P119......P1G0+P120P119.....P1P0Cin

P120P119.....P1P0Cin122.

50

, : log4122=4. 4
fanin4.

(1)=>,.

9.3CarrySelectAdder
(MUX)21,
43td:
21

:3,:4

51

carry select adder

bits,Cin0
1. Cin
() , Carry Out .
LSBCin.

8bitcarryselectadder

52

H , n LSB
(..RippleCarry),Cin.
R.C.Adder,
k bits (2k+1)T bits n bits
((nk)/k)x3T,.

:[(2x4+1)+3x3]T
2x4+1:4bitr.c.adder
3x3:CarrySelect

Carry Select
, Bits,
CarryIn.

Bit

5
25
6
30
7
35
9
45
2bit
16bitadder

53

10
12
14
18


32bitadder

:
Wakerly,/5.10,508ff
a. RippleCarry
Wakerly,/5.10.2,509ff
http://en.wikipedia.org/wiki/Ripple_carry_adder#Ripple_carry_adder
b. FullLookahead,GnPn
Wakerly,/5.10.4,512ff
http://en.wikipedia.org/wiki/Carry_lookahead_adder
Co Cin bits
A,B[4..1] ,[n..0] Cin carry
, C,S[n..0]
.Wakerlybits.
.
c. GroupRippleCarry
Wakerly,/5.10.5,514ff
Wakerly,/5.10.7,519ff
()
http://en.wikipedia.org/wiki/Lookahead_Carry_Unit
groups
,.
54

d. CarrySelect
,
http://en.wikipedia.org/wiki/Carry_select_adder
e. CarrySave
http://en.wikipedia.org/wiki/Carrysave_adder
Wakerly,/,
f.

1
AND,NAND,OR,NOR,NOT,XOR
fanin/fanout(fanin=1).
1. carrylookahead
8bits,fanin3fanout10.
2. carry look ahead
8bits,fanin3fanout10.

kbit,.
group ripple carry
24bit.
4Bit.carrylookaheadadder(CLA)
fanin8fanout.
.
1. CLA.
,().
2. CLA group ripple carry
adder.
3.
23..0,23..0,Cin.
4. ripplecarryadder
(:3).

55

5.
.
23/.

3CarrySelectAdders
32bit,carryselect.
.blockbits
bit ( 4 6
).:
1. full adder,
SumCarry.
2. 21
.
3. carry select adder, bit
.
carry.
4. ripple
carryadder.
5. .;
.

4CarrySelectAdders
32bit,carryselect.
.blockbits
bit ()
carrylookaheadadders(Bit)RippleCarryadders.
:
1. carry lookahead adder bit (A3..0, B3..0, Cin),
fanin=3fanout.
2. 21
.
3. carryselectadder4
Bitcarrylookahead
adder 1 ripple carry adder.
.
4. carryselect
lookahead adders 1.
carry.

56

5. carry select
bit ripple carry adder (
Fulladder3carry2Sum).
6. .;
.

5CarrySelectAdders
, =
+...()=
15.
(),
.
811 Bit , carry in,
carryselectadders,datapathBits.
1. ripple carry adder.
RCA.
2. carry select adder
()Bits.CSA_X
3. .
4. carryselectadder(,
)
; :
. ,
(2)

..

57

10.

o
o
o carrysaveadders
o WallaceTree
o Dadda
o Booth(:0111=10000001)

, 4bit
full adder FSM.
. Booth,
Booth, . Wallace.
WallaceDadda,
. Carry Save Adders
/((n2)(2n)).

10.1(Unsigned
BinaryMultiplication)

.
AND bit
,
.
11
6,66:

1011
x0110

0000
1011
1011
+0000

1000010

58

10.2

(n2),
. n bit
n,n
bit .
,ripplecarryadders(
), ripple carry adders 4 bits .
(n1)n
, (n2).
ripple carry adders, (2n),
nbits
ripplecarryaddern.
MSB.

(n+1) bits
n bits ,
2nbitsnbits.

10.3CarrySaveAdders

carry save adders ,

.carrysaveadderripple
carry adder,
Flip Flop bit.
n bits , n ,
Full Adder Tsetup
TholdFlipFlop.64bits
64(Tadder + Tsetup + Thold). ripple carry adder
FlipFlopCarry.

10.1CarrySaveAdderDatapath4Bits

Carry Save Adders /

,.DFlipFlop
,
59

n,
,
.

1011

x0110

10.4WallaceDaddaTreeMultiplier

Wallace bits
.Dadda,2Bit,
HalfAdders.

60

6fulladder.

10.5Booth

BOOTHMULTIPLIER:
999=10001(:0111=10000001)

999x15=(1000x15)15

00010

x00011

00000

0
Res 0
0
0
0
0
0
0
0
1
1
0
sub
sub 1
1
1
1
0
0
0
0
1
1
0

shift 1
1
1
1
1
0
0
0
0
1
1
Donothing
shift 1
1
1
1
1
1
0
0
0
0
1
add
add 0
0
0
0
1
1
0
0
0
0
1

shift 0
0
0
0
0
1
1
0
0
0
0
Donothing
shift 0
0
0
0
0
0
1
1
0
0
0
Donothing
shift 0
0
0
0
0
0
0
1
1
0
0
Donothing

2bit

10
SUB

01
ADD

11,00 DONOTHING
().

a.
Wakerly,/2.8,54ff
Wakerly,/5.11,525ff

61

b.
,BFS
c. WallaceTree
d. Dadda
WallaceDadda
,
Wallace (half
adders)Dadda.
e. Booth(:0111=10000001)

1Dadda
Dadda
6bit 12bit.
HalfAdders(HA)FullAdders(FA).HA,S,C,
2 . FA
,,Cin,S,Cout2S3Cout,
5.datapath
,FA,()
. fanin = 3, 1 ()
().50(0=LSB),50
(0=LSB)C11C0(C0=LSB).
1.
FA.
2.
3. .

2WallaceDadda
( Wallace Dadda) 4 bit
(3..0, 3..0), Full Adders (5 , =3
S)HalfAdders(2,=1).

()
()()
()()

3Booth

= ,
= 20, (
15 300 = 4500)
, Booth. .
,
,0MSB().

4CarrySaveAdders
62


carrysaveadders,,
.
TsetupThold,
,
(.
/).
datapath,
(1) (1). control path
.

carry save,
ripple carry adders
,
().FlipFlop
( ) 16 , bit
,
,(bits
).

1.
( bits , ),
16 bits, 32 bits 64 bits ( ,
,)(30)
2. carrysaveadders(bits
,),16bits,32bits64bits (
,,)
(30)
3. CarryLookaheadAdder(CLA)4bits
27 6, bits
(
carry save adder) carry save flip flop ,

(bits,),16bits,32
bits 64 bits ( ,
,)(30)
4. .
(163264bits);

: (.
Wallace,Dadda,.)datapath,
, bit
.

5CarrySaveAdders

carrysaveadders.8
it , 16 Bit
.,:

63

=
(..
:96=54)

,
, Flip Flop ( ) ,
( ),
. ,

; ,

6Dadda

Dadda
6bit 12bit.
HalfAdders(HA)FullAdders(FA).HA,S,C,
2 . FA
,,Cin,S,Cout2S3Cout,
5.datapath
,FA,()
. fanin = 3, 1 ()
().50(0=LSB),50
(0=LSB)C11C0(C0=LSB).

()
FA.
()
().

64

11.

()
o
o

11.1

,
=,=,=,=.:
=+,<
1
bit=*21bit=/2.

.

,
LSB 0,
.

,
2 MSB
.
,
( ),
,:

1. MSB
1 ( 1
).
2. MSB
1(1
).

MSB
1. (
),.
3. (+1).

, = 00011100 =00000101.
1 : =11100000, =00101000. 2 :
=10100000 =2.
+1=3.

65

11.2(RestoringDivision)

:
,
() , ,
,
(
).

10/3=31.

101011
11
011
1100,
+11
1010
- 11
0100
- 11
+0001

11.3(NonRestoringDivision)

:
2,
,
, , (
)
.
.(
+/2=/2,

).

101011
1100 011
1110,
+11
0100
- 11
+0001

11.3
145/5=29,.
,
16 Bit. =0000000010010001 =0000000000000101. MSB
0(),
, 10010001 (
66

1001000100000000).
00000101 ( 0000010100000000),
MSB=0. MSB=1,
n . n=5
=101 ( =1010000000000000). n 1 ,
n=6 , bits
(MSB0).
11.3.1
145 5, 6, .
6,,
,.

10010001101
101 011101
111,
+101
1001
- 101
1000
- 101
0110
101
0010
101
1101,
+101
0101
- 101
0000

11.3.2

, .
,
.

67


10010001101
101 011101
1111,,
+101
1000
- 101
00110
- 101
0010
101
1011,,
+101
0000

n,6,
.

11.4

,bit
MSB.
,()
MSB0(borrow)
1.
bit01.

.,LSB
0 .

,
.

, (
)
. 64 / 4 = 16
4(10)64(100000)
,
( 1000).
,
().

68

1

12Bit.
,
8Bit (..
1990=9010,,010110102)

). 114 Booth,
( Bit)
8Bit.16Bit

) / . ,
,.

.
(2).

2
1000
/ 25. ,
,.

()
()

3
8bit = 00111011 = 00001110.
:
1. () Booth ,
.
..
2. (/) ,
,
. ()
()..

.
(..142bits
, ). MSB
,
. .
datapath ,
.

69

12. (
)

()
o
o debounceNANDNAND
o
o
o
(races),criticalracesnoncriticalraces
o (A,B,C,D00,.)races

, ,
FSM , , Karnaugh,
, . debounce
NANDNAND. ,
(;).
: ,

(critical races)
:

(criticalraces)

Fundamentalmode

SPDT

70


:
,
,.
PULSEMODE

A,B

00

01

11

10

OUT_A,OUT_B
00
00

01

00

10

71

01

00

01

01

01

11

00

00

00

00

10

00

10

10

10

_
A,B

00

01

11

10

OUT_A,OUT_B
00
0

01

11

10

00

00

01

11

10

OUT_A,OUT_B
00
0

01

_
A,B

72

11

10

00

_=OUT_A*OUT_B*B+OUT_B*A*B
_B=OUT_A*OUT_B*A+OUT_A*A*B

73

x=(A*OUT_B)
OUT_B=(A*OUT_A)
X=(A*(A*OUT_A))

a
b
c
d
e
f
g
h

00
a
b
h
a
g
a
d
h

01
c
(f)(c)h
c
c
(h)c
e
g
(a)c

11
d
(g)e
(b)e
e
e
f
e
b

10
(e)d
b
(b)a
d
d
g
a
(a)c

.
dontcare.

2 2
(races).
Boole=1races.
: 2.

74

Races

ab,cd.
(c,d)criticalrace,
noncriticalrace.

x1x2 00
y1y2
00
00

01

11

10

01

10

11

01

00

01

(10)00

11

11

01

11

11

11

10

10

10

10

11

75

:
Wakerly(7.97.10)
:
Wakerly,/7.1,628ff
Wakerly,/7.9,717ff
a.
,
.
Wakerly,
7.10.6742ff.
b. debounceNANDNAND
Wakerly,/8.2.2,8.2.3,795ff
c.
Wakerly,/7.9.2,723
d. (races),
criticalracesnoncriticalraces
Wakerly,/7.9.3,726
e. (A,B,C,D00,.)races

Wakerly,/7.9.4,727
Wakerly,/7.10.4,737
f.
Wakerly,/7.10,731

1
1. ( 5 ) critical race non
criticalrace.

76

2. (5)
races.
3. FSM
criticalnoncriticalraces,
. (:
5
).

2
(
).
.
,001,
0.100.
011
100
.

IN
OUT

3
(
).
./reset.

)FSM(,,...).
.Moore.

)(:
Grey),
(races).

)Karnaugh.

)FSM.

77

IN
OUT

4
, 1 2, debounced, OUT1 OUT2.
1=0,2=0,OUT1=0OUT2=0.
FSM
(OUT1,OUT2) = 10 1 (OUT1,OUT2) = 01
2 .
,
(OUT1,OUT2)=
00.

5
.
: (
'1')
('1').

.2(2)

.1(1)

.3(3)
.4(4)

FSM
.
(OUT=0 OUT = 1
).

78

6
FSM
.:
()()
()criticalnoncriticalraces,=00,=01,=11=10
() critical races (
)
races
() FSM.
00.

00

01

11

10

7FlipFlop
FlipFlop .
JK Flip Flop,
. : FlipFlop ,
(CK=Clock)
0
1.

Qn J K Qn+1
0
0 0 0
0
0 1 0
0
1 0 1
0
1 1 1
1
0 0 1
1
0 1 0
1
1 0 1
1
1 1 0

(),
( Karnaugh, .) Flip
Flop.(races),
.

()(..NORNOR,NANDNAND),
,,
(.. MUX) JK Flip Flop (
MasterSlave).
79

13.

(CriticalPath)
o
o BreadthFirstSearchcriticalpath

, , , .
, XOR,
, Breadth First Search
(criticalpath),,
, .
.
(criticalpath).

13.1

13.1

.
. ,
, . 13.1
.n
.

,
.

80


(Directed Acyclical Graph DAG).

.

(travellingsalesmanproblem)
,
.
,..
. ,
( )
()
.
, ,

, (,
).

:

FSM (..
,,C,000,001,010,011,...)

(..
FPGA;)

(CriticalPath)
:

81

1
Full Adder ( , , Cin, S, Cout),
HalfAdder().
AND, NAND, OR, NOR
(XOR),=10nsec,fanin=2(
NOTfanin=1)fanout.
1. HalfAdderFullAdder
.(XOR)
(:
Half Adder
Karnaugh
).
2. Full Adder

.
;
3. XOR(fanin=2)
_XOR = 15nsec,
FullAdder(HalfAdders).
FullAdder(Karnaugh).

82

4. Full Adder 3

.
;
5. FullAdders;
:
. (
)
.

83

14.

7segment LED. CA CC LED, ,

7segments,
7segmentLED.
(bitslice/bitserialaddition).
8BitsFullAdderFlipFlop
.

14.17SegmentLED
:.ToLED
..14.1.
IN=10LED.
330.LED
(V_forward_bias)1.61.9Volts,
LED 10mA ( 0.2V
).

14.1LED

14.2CommonAnode7SegmentLED
84


14.3CommonCathode7SegmentLED

14.214.37segmentLED.
o'0' LEDCA1CC(
.

a b c d e f g

0 0 0 0 0 0 0 1
1 1 0 0 1 1 1 1
2 0 0 1 0 0 1 0
3 0 0 0 0 1 1 0
4 1 0 0 1 1 0 0
5 0 1 0 0 1 0 0
6 0 1 0 0 0 0 0
7 0 0 0 1 1 1 1
8 0 0 0 0 0 0 0
9 0 0 0 0 1 0 0
14.4LED09
14.4LED09Common
Anode7SegmentLED(0).segmentsa
,
f,g.

10(..90)70(107),
.
.a,b,.,
(common) .
85

7017(7segments10).
,(1
CC 0 CA). 7segment LED
segments .
.FSM
.
1.
(4bits10)
,
1711.
2:
(ringcounter)
.

14.2BitSliceAdders
nbit,
(n+1)bit(Cout),FFCout
,FullAdder(FA),
, n bits (..
ripplecarryadder)(FullAdder
bit ). ,, ( rotate)
1bitS,CFullAdder

86

15.

,,,
, offset, (normalization),
(alignment), (, ),
bit

15.1
15.2

Sign

Mantissa

Exponent

Sm

Se

10
4
000011010110111
011010110000100

(Mx)(F/)
(Mx)(2e/23)=(M<<3)(2e3)

32
((16)(+15))
5bits2scomplement

Offset16

0,125x25+0,5x23

Mantissa

011010000000101
011101011110011
000111010110101

87

011010000000101
011101011110011
mantissa.

mantissa.

offset,
offset.

:
Wakerly,/6.1.2,556ff
, ,
,,.

1
.2,
bit , mantissa ( ) 16 Bits,
2scomplement8Bits.mantissa.
1. ,
,.(20)
2. ,
,.
3. 1 ,
mantissa
.
, ,
.
4. 1 2,
. ,
, .
(..,
5. 12,
. (..
88

,.).,,
.

2
1 Bit , .12 Bits
,6Bits.
()(mantisa).
01()
0.375 ( 0.375 1/4 + 1/8 ) 125
():
1. 2 2s complement, MSB

2. 2 2s complement, MSB

3. 2 2s complement, MSB
(:
Bit
).
4. 8 2s complement
()(:
+/1 mantisa
1).

89

16.

RAM/ROM/PAL/GAL/FPGA

RAM/LUT/ROM/PLA/FPGA
o
o PAL/GAL
o Sxed;iashmeROM
o (LUT)
o PAL/GAL()
o

RAM/ROM/LUT/PLA/GAL/FPGAs. PAL/GAL
ROM.
PAL/GAL , PAL/GAL .
RAM/ROM/LUT/PLA/GAL/FPGAs.
DRAM. ROM.
FPGA CAD
(LUT).

:
Wakerly,/5.3,403ff(PAL/GAL/PLD)
Wakerly,/8.3,814ff

((GAL)
(FPGA))
g. (LUT)
(LUT)
h. PAL/GAL()
( PAL/GAL
).
i. DRAM
bits
,Bit
.

90

17.

. TTL (totem pole, open

collector,tristate),,Bus
Master Bus Slave, hardware
BREQ BGRANT ( daisy chain), BREQ,
BGRANT,ACKN,BBUSY,BHOLD.
(handshake).

:
91

: Mercury Cougar 68, RS232,

(bus)
,,
o

Wakerly,/7.5,694ff

Wakerly,/7.7,706ff

92

.1(FSM)Flip
Flop,FlipFlop
: (
.)

MooreFSMflipflop.

FSM3FlipFlop.

A
B
C
D
E

Q2
0
0
0
0
1

Q1
0
0
1
1
1

Q0
0
1
0
1
1
93

=Q0

JKflipflop()
J

Qn

Qn+1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
0
1
1
1
0

0
0
0
0
1
1
1
1
(QnJ=K=1)

JKFlipFlop:

Qn
0
0
1
1

Qn+1
0
1
0
1

J
0
1
x
x

K
x
x
1
0

flip flop 2 Karnaugh, 6

.

J2
Q2 00
Q1Q0
0
0
1
d

01

11

10

0
d

1
d

0
d

Q2 00
Q1Q0
0
d
1
d

01

11

10

d
d

d
1

d
d

11

10

K2

J1
Q2 00 01
Q1Q0
94

0
1

0
d

1
d

d
d

d
d

01

11

10

d
d

0
1

0
d

01

11

10

d
d

d
d

1
d

01

11

10

1
d

0
1

d
d

K1
Q2 00
Q1Q0
0
d
1
d

J0
Q2 00
Q1Q0
0
1
1
d

K0
Q2 00
Q1Q0
0
d
1
d

J2=Q0Q1

K2=1

J1=0

K1=Q2

J0=1

K2=Q1+Q2

100

110

101

001

001

010

.2

95

:
( Mealy
dontcare
)



.
(..
CE CE
).
Mealy
(),Moore
.

1:FSM

INX
K

D,1

D,1

C,1

C,0

B,1

B,1

A,1

C,0

B
X

C
BD
X

D
X
AC
X

A
B
C

A<=AC
(AC)
B<=BD
(BD)

,FSM:

96

INX

B,1

B,1

A,1

A,0

2:FSM

IN
K

00

01

10

E,1

C,0

B,1

C,0

F,1

E,1

B,1

A,0

D,1

C,0

F,1

E,1

A,0

F,1

B,1

C,0

E,1

C,1

B
X

C
BD
BE
D
X
E

A<=AC

X
BD

AC

X
B

(AC)
97

AC
BE
X

B<=BDE

(B,DE)
F<=F

,FSM:

IN
K

00

01

10

B,1

A,0

B,1

A,0

F,1

B,1

A,0

B,1

A,1

98


(SEC,SECDED)

Single Error Correction Double Error Detection (SECDED)

WakerlyHammingcodes
o itsnBits
o Bits
o paritybits

.1SEC(SingleErrorCorrection)

.
,.
SEC(Hamming)Bits
(parity, XOR) .
,01001101,XOR8bit0
18Bits.

XOR

010011010

a3

a2

a1

a0 k

,nbitskbits

k= log2(n+k+1)

nbit
kbit
1(00)

n=1024BitsSEC;
99

n=1024
+

+k=11

1036

10bit,
11 Bits. k Bits
k= log2(n) 2k
n+k+1.,
1.

kbits2:

k0

k1

a0

k2

a1

a2

a3

bits k0 k2 1,2, 4
2.

k bits XOR bits poy

k
XOR().

k0=a0a1a3

(2obit)

k1=a0a2a3

(2bit,22...)

k2=a1a2a3

(2bit,44...)

bitsk0k2.,kbits.
kbits.XORk
bitskbits.
1bit,XOR.
000.
100

:
a3

a2

a1

a0

k0

k1

a0

k2

a1

a2

a3

kbits:

k0=1 k1=0 k2=0

5 Bit, a1,
:

error

k0

k1

a0

k2

a1

a2

a3

k bits , k bits
:
k0=1

k0=0

k1=0

k1=0

k2=0

k2=1

XORk0k0,k1k1,k2k2101bit
.

.2SECDED(SingleErrorCorrectionDoubleErrorDetection)
SECDED
bit ,
bits.

101

SECSECDED1bitparity
. bit ( )
kbits,.

:
( SECDED, ) Wakerly,
/2.15.12.15.3,68ff,
j. itsnBits
Wakerly,/2.15.3,72
k. Bits
Wakerly,/2.15.3,74
l.

parity bits

Wakerly,/,
m.
(parity)
Wakerly,/2.15.6,79

1SECDED
()q3q2q1q0=0101.bitsk0k1k2SEC.
bit q1
.
()SECDED;
SECDED(,).
()Bits4bits2037.

102


VHDL

,
.
Wakerly,.9,951ff.

1
VHDL (architecture)

00, 11, 01.

10.CASE.
ENTITYsimpleIS

PORT(clock :INSTD_LOGIC;

rst :INSTD_LOGIC;
eisodos

:INSTD_LOGIC_VECTOR(1DOWNTO0);

eksodos

:OUTSTD_LOGIC);

ENDsimple;

2
VHDL FSM .
CASE
2bit (,,C). FSM
.

103

resetn
= 1 w

A z = 0

B z = 0
=

C z = 1

= 1 w

3
entities
counter4bit.
1.(entityarchitecture)toplevelentity
counter(30)
2.counterreset=1;(10)
3. simple x y counter
(20)
4. 10 CLOCK, RST, X,
COUNT_OUT(20)
5. 3 4
(20).
ENTITYsimpleIS

PORT(clock :INSTD_LOGIC;
rst :INSTD_LOGIC;

x:OUTSTD_LOGIC);
ENDsimple;
ARCHITECTUREBehaviorOFsimpleIS

TYPEState_typeIS(A,B,C);
104


SIGNALy:State_type;
BEGIN

PROCESS

BEGIN

Waituntilclkeventandclk=1;
IFreset='1'THEN

y<=A;

ELSE

CASEyIS

WHENA=>

y<=;

x<=;

WHENB=>

y<=;

x<=;

WHENC=>

y<=;

x<=;

ENDCASE;
ENDIF;

ENDPROCESS;

ENDBehavior;

ENTITYsimple2IS

PORT(clock :INSTD_LOGIC;
rst :INSTD_LOGIC;

x
:INSTD_LOGIC;
count_out:OUTSTD_LOGIC_VECTOR(3downto0)
);
ENDsimple;

ARCHITECTUREBehaviorOFsimpleIS

TYPEState_typeIS(A,B,C);

SIGNALy:State_type;

SIGNALxyz:STD_LOGIC_VECTOR(3downto0);
BEGIN

PROCESS

BEGIN

Waituntilclkeventandclk=1;
IFreset='1'THEN

y<=A;
xyz<=(others=>1);

ELSE

Ifx=1then
xyz<=xyz+1;

else
105

xyz<=xyz;

ENDIF;

ENDPROCESS;

count_out<=xyz;
ENDBehavior;

endif;

37SegmentLED
VHDL module
_DATA4bitsIN_CTL2bits.IN_CTL
4SevenSegmentLEDDisplayIN_DATA
Display.
_DATA 1 5.
moduleA,B,C,D,E,F,G,AN3,AN2,AN1,AN0.7Segment
LED ( ).
module.

4()
(architecture) entity

ENTITYmuxIS
PORT(A,B,C,D:INSTD_LOGIC_VECTOR(7downto0);
select:INSTD_LOGIC_VECTOR(1downto0);
Q:OUTSTD_LOGIC_VECTOR(7downto0)
);
ENDmux;
106