Operational Amplifier

EE3408E: Integrated Analog Design

Design of an Operational Amplifier

Prepared for: Prof Xu Yong Ping

Prepared by: Kyaw Soe Hein (A0103612Y)
Demo Date: 18 Nov 2014

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Objective & Introduction

The objective of this project is to design an operational amplifier (Op-amp) based on the given
specifications. The Op-amp has two inputs (differential) and a single-ended output, as shown
below. The design will be based on a 0.35m CMOS process. The device models will be given.
This is an individual project. The design of project will be started off with modelling the NMOS
and PMOS, extracting
- Vth, threshold voltage
- K, product of charge carrier effective mobility & gate oxide capacitance per unit area
- , channel length modulation factor
- , body effect parameter
Then, calculations are done to obtain the theoretical value which can be useful for tuning of the
values to meet the specification on the LTSPICE.

Design Specification
The table below summarizes the project practical results achieved regarding to the design
specification.

No Design Specification

Project Result

Supply voltage: 2.5V (Single supply)

Supply Voltage: 2.5V (Single Supply)

Open-loop gain: > 80dB

Open-loop gain: 81 dB

Gain peaking: < 3 dB (ratio of maximum gain to gain at DC)

Gain Peaking: 0.9 dB

Unity gain bandwidth: > 10MHz

Unity gain bandwidth: 60.4MHz

Phase Margin: > 55 degree

Phase Margin: 66 degree

CMRR : > 70dB

CMRR: 93.9 dB

Output voltage swing: > 1.0 V (Peak-to-Peak)

Output voltage swing: 1.5V (Peak-toPeak)

Offset voltage: < 5mV

Offset Voltage is: -1.067 V

Supply current: < 800 A

Supply current: 685 A

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Load (capacitive): 1 pF

Load (capacitive): 1 pF

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Extracting NMOS & PMOS Device Parameters

Due to number of reports pages constraint, the details of extracting of parameters will be
omitted.
NMOS

PMOS

ID vs VDS Simulation result for NMOS Device & PMOS Device

NMOS

PMOS

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Extracting Vth0
Square root of (ID(M1)) vs VGS relation at VDS=1 is simulated at LT spice and these
data are exported to excel.
IDS (VGS-Vth0) 0r (IDS) VGS and thus, VthO is the x-intercept of the linear
graph,y=0.0229x-0.0092
X-intercept, y=0 Thus, 0=0.229x-0.0092 or, 0.0092/0.229=x or, x= 0.4V=Vth0 (NMOS)
Vth0= 0.0077/0.013=0.59V (PMOS)

Extracting K
IDS=(W/L)*(Kn/2)(Vgs-Vth0)^2 ,substituting and solving the equation, kn=ID(M1)/(5*(VGSVTHO)^2)
Kn = 1 E -04, Kp= 6.15 E-05

Extracting
Slope=Lambdha* ID(M1) in ID(M1) vs VDS curve. Thus, by differentiating ID(M1), slope data
is obtained. After export the data to excel, lambdha=Slope/ID is evaluated by taking average.
VGS steps are taken such that VGS>Vth0.
(NMOS) = 0.08, (PMOS) = 0.07

Extracting

Finidng , Vsb = 0.1V in the original circuit and new Vth is calculated using the same procedure
as finding Vth0 earlier. New Vth must be increased as per increment of Vsb. However, in this
project, the body effect is eliminated.
(NMOS) = 0.43,

(PMOS) = 0.30

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Calculation for Parameters

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Circuit Design & Simulation

Circuit Design

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Simulation of Open-loop Gain, Unity Gain Bandwidth & Phase Margin

The output comes through one pair of differential amplifier and one common source
amplifier, thus the phase changes two times. However, the results are as follow.
Open loop gain: 81.09 dB (DC state , 0 Hz)
Phase margin: 66 degree
Unity Gain bandwidth : 60 MHz (-3dB point)
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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Simulation of Gain Peaking, CMRR, Supply Current

Gain peaking here is only 0.9dB which is less than 3dB as specified by requirement.

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

The common mode gain is -11.5 dB and differential gain is 81dB. Applying formula mentioned
above, CMRR (dB) is computed and resulted 93.9dB.

As shown above simulation, the supply current is just 790A. Thus, it meets the requirement of
less than 800A.
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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Simulation of Output Voltage Swing, Offset Voltage

The upper limit of output voltage swing is 1.8V and lower limit of output swing is 0.3V,
thus the output swing is 1.5V while maintain gain @ 80dB as seen in the simulation result.
Therefore, it meets the requirement of output voltage swing must be higher than 1V (Peak-Peak).

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Offset Voltage Specification

The input offset voltage ( ) is a parameter defining the differential DC voltage required
between the inputs of an amplifier, especially an operational amplifier (op-amp), to make the
output zero (for voltage amplifiers, 0 volts with respect to ground or between differential outputs,
depending on the output type).

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Kyaw Soe Hein (A0103612Y)

Operational Amplifier

Simulation of Output waveform

It is concluded that the project is successful and it is working according to specifications. Thus,
by presenting output waveform with respect to the input waveform, it will be crystal clear to
witness the amplifying action of the op-amp that has specifically designed. The output has been
amplified as well as notice of change in phase as the signal gone through one pair of differential
amplifier and common source amplifier.

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Kyaw Soe Hein (A0103612Y)