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Microelectronic Circuit Design

Fourth Edition - Part II


Solutions to Exercises
CHAPTER 6
Page 292
NM L = 0.8V 0.4V = 0.4 V | NM H = 3.6V 2.0V = 1.6 V

Page 294
V10% = VL + 0.1 (V ) = 2.6V + 0.1 0.6 (2.6) = 2.4 V

Checking : V10% = VH 0.9 (V ) = 0.6V 0.9 0.6 (2.6) = 2.4 V

V90% = VH 0.1 (V ) = 0.6V 0.1 0.6 (2.6) = 0.8 V

Checking : V90% = VL + 0.9 (V ) = 2.6V + 0.9 0.6 (2.6) = 0.8 V


V50% =

VH + VL 0.6 2.6
=
= 1.6 V | t r = t 4 t3 = 3 ns | t f = t2 t1 = 5 ns
2
2

Page 295
At P = 1 mW : PDP = 1mW (1ns) = 1 pJ
At P = 3 mW : PDP = 3mW (1ns) = 3 pJ
At P = 20 mW : PDP = 20mW (2ns) = 40 pJ

Page 297
Z = ( A + B)( B + C) = AB + AC + BB + BC = AB + BB + AC + BB + BC
Z = AB + B + AC + B + BC = B( A + 1) + AC + B(C + 1) = B + AC + B
Z = B + B + AC = B + AC

R. C. Jaeger and T. N. Blalock


08/12/10

Page 300
P
0.4mW
V VL 2.5V 0.2V
I DD =
=
= 160 A | R = DD
=
= 14.4 k
VDD
2.5V
I DD
160A
W
A W
0.2
4.44
2
1.6x104 A = 104 2 2.5 0.6
0.2 V =
2
1
V L S
L S

Page 301
V VL 3.3V 0.1V
I DD = DD
=
= 31.4A
R
102k
W
A W
0.1
2.09
31.4x106 A = 6x105 2 3.3 0.75 0.1 V 2 =
2
1
V L S
L S
Page 303

Ron
2.5V Ron = 1.84 k
Ron + 28.8k
W
W
1
2.98
=
=

1
0.15
L S
L S
104 2.5 0.60
(1.84k)
2

0.15V =

Ron =

1
1.03
0.2
6x105
3.3 0.75

2
1

= 6.61 k | VL =

6.61k
3.3V = 0.201 V
6.61k + 102k

1 V2 1 V2
=
=V

=
Kn R A V

Page 305

1.03
6.30
5
Kn R = 6x105
1.02x10 =
V
1

NM H = 3.3 0.75 +

1
3.3
1.63
= 1.45 V
6.30
2(6.30)

NM L = 0.75 +

2(3.3)
1

= 0.318 V
6.30
3(6.30)

R. C. Jaeger and T. N. Blalock


08/12/10

Page 309
Using MATLAB :
fzero(@(vh) ((vh -1.9 - 0.5* sqrt(0.6))^2 - 0.25(vh + 0.6)), 1) | ans = 1.5535
fzero(@(vh) ((vh -1.9 - 0.5* sqrt(0.6))^2 - 0.25(vh + 0.6)), 4) | ans = 3.2710

)]

VH = 5 0.75 + 0.5 VH + 0.6 0.6 VH = 3.61 V


fzero(@(vh) (5- 0.75 - 0.5* (sqrt(vh + 0.6) - sqrt(0.6)) - vh), 1) | ans = 3.6112

(a )

80x106 A = 100x106

W
A W
0.15
6.10
2
1.55 0.60
0.15 V =
2
2
1
V L S
L S

VTNL = 0.6 + 0.5 .15 + 0.6 0.6 = 0.646 V


W 0.551
2 2
100x106 A W
1
=
(2.5 0.15 0.646) V =
2
2
1
1.82
V L L
L L
W
A W
0.1
8.89
(b) 80x106 A = 100x106 2 1.55 0.60 0.1 V 2 =
2
1
V L S
L S
80x106 A =

VTNL = 0.6 + 0.5 .1+ 0.6 0.6 = 0.631 V


W 0.511
2 2
100x10 A W
1
2.5

0.1
0.631
V

=
(
)
2
2
1
1.96
V L L
L L
6

80x106 A =

Page 312
The high logic level is unchanged : VH = 2.11
W
A W
0.1
9.16
60x106 A = 50x106 2 2.11 0.75 0.1 V 2 =
2
1
V L S
L S

VTNL = 0.75 + 0.5 .1+ 0.6 0.6 = 0.781 V


60x106 A =

W 0.410
2 2
50x106 A W
1
=
(3.3 0.1 0.781) V =
2
2
1
2.44
V L L
L L

R. C. Jaeger and T. N. Blalock


08/12/10

Page 314
Using MATLAB :
fzero(@(vh) ((vh -1.9 - 0.5* sqrt(0.6))^2 - 0.25(vh + 0.6)), 1) | ans = 1.5535

= 0 VTN = 0.6V | VH = 2.5 - 0.6 = 1.9 V | I DD = 0 for vO = VH



2
VL
100x106 2
6 10
100x10 1.9 0.6 VL =
(2.5 VL 0.6)
2
2
1
1
10
0.235
6VL2 116.8VL + 3.61 = 0 VL = 0.235V | I DD = 100x106 1.9 0.6
0.235 = 278 A
2
1
2
100x106 2
Checking : I DD =
(2.5 0.235 0.6) = 277 A
2
1

Page 319
VTNL = 1.5 + 0.5 0.2 + 0.6 0.6 = 1.44V

W
W 1.17
0.2
60.6x106 = 100x106 3.3 0.6
0.2 =
2
1
L S
L S
W 0.585
2
100x106 W
1
60.6x106 =
=
(0 1.44) =
2
1
1.71
L L
L L

Page 320

2.22
0.2
I DS = 100x106
2.5 0.6
0.2 = 79.9 A which checks.
2
1

Page 321
The PMOS transistor is still saturated so I DL = 144 A, and VH = 2.5 V.
5
V
144x106 = 100x106 2.5 0.6 L VL VL = 0.158 V
2
1
Page 326

W 2.22
=
in parallel with transistors A and B.
L
1
W 1.81
The W/L ratio of the load transistor remains unchanged : =
1
L L

Place a third transistor with

R. C. Jaeger and T. N. Blalock


08/12/10

Page 327
Place a third transistor in series with transistors A and B.
W
2.22 6.66
The new W/L ratios of transistors A, B and C are
=3
=
.
1
1
L ABC
W 1.81
The W/L ratio of the load transistor remains unchanged : =
1
L L
Page 333

M L1 is saturated for all three voltages. I DD =

2
40x106 1.11

2.5 (0.6) = 80.1 A


2 1 L

The voltages can be estimated using the on - resistance method.


For the 11000 case, RonA =

132mV 64.4mV
64.4mV
= 844 RonB =
= 804
80.1A
80.1A

For the 00101 case, RonE =

64.4mV
= 804 .
80.1A

For the 01110 case, RonC =

203mV 132mV
132mV 64.4mV
= 886 RonD =
= 844
80.1A
80.1A

The voltage across a given conducting device is I D Ron . Small variations in Ron are ignored.

ABCDE

Y (mV)

2 (mV)

3 (mV)

IDD (uA)

ABCDE

Y (mV)

2 (mV)

3 (mV)

IDD (uA)

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
130
2.5 V
130
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
130
200
114

0
0
0
0
0
0
2.5 V
64
0
0
0
0
0
0
64
21

0
0
0
0
2.5 V
64
2.5 V
64
0
0
0
0
2.5 V
64
130
43

0
0
0
0
0
80.1
0
80.1
0
0
0
0
0
80.1
80.1
80.1

10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

2.5 V
2.5 V
2.5 V
200
2.5 V
130
2.5 V
100
130
130
130
110
130
66
110
65

2.5 V
2.5 V
2.5 V
130
2.5 V
130
2.5 V
83
64
64
64
43
64
32
64
32

0
0
2.5 V
64
2.5 V
64
2.5 V
64
0
0
64
22
64
32
87
32

0
0
0
80.1
0
80.1
0
80.1
80.1
80.1
80.1
80.1
80.1
80.1
80.1
80.1

R. C. Jaeger and T. N. Blalock


08/12/10

Page 334
2.5V (80A)
Pav =
= 0.100 mW
2
Page 335
2

(
)
F (2.5V ) (3.2x10 Hz ) = 2x10

PD = 10-12 F (2.5V ) 32x106 Hz = 2x104W = 200 W or 0.200 mW

PD = 10-12

W = 0.02 W or 20 mW

Page 336
The inverter in Fig. 6.38(a) was designed for a power dissipation of 0.2 mW.
To reduce the power by a factor of two, we must reduce the W/L ratios by a factor of 2.
W 1 1
W
1
1 4.71 2.36
| =
=
=
=
1
L L 2 1.68 3.36
L S 2 1

4mW
, we must increase the W/L ratios by a factor of 20.
0.2mW
W
2.22 44.4
| = 20
=
1
L S
1

To increase the power by a factor of


W
1.81 36.2
= 20
=
1
L L
1

To reduce the power by a factor of three, we must reduce the W/L ratios by a factor of 3.
W 1 1.81 0.603
W
W
1
1 3.33 1.11
1 6.66 2.22
=
| =
|
=
=
=
=
=
1
1.66
1
1
L L 3 1
L A 3 1
L BCD 3 1

R. C. Jaeger and T. N. Blalock


08/12/10

Page 339
t r = 2.2RC = 2.2 28.8x103 2x1013 F = 12.7 ns

)(

)(

PLH = 0.69RC = 0.69 28.8x103 2x1013 F = 3.97 ns

t
VH + VL
vO (t ) = VF (VF VI ) exp
| vO ( PHL ) = VH 0.5
= 2.5 1.15 = 1.35 V
RC
2

1.35 = 0.2 (0.2 2.5) exp PHL PLH = RC ln 0.5 = 0.69RC
RC
vO (t1 ) = VH 0.1(VH + VL ) = 2.5 + 0.23 = 2.27 V
t
2.27 = 0.2 (0.2 2.5) exp 1 t1 = RC ln 0.9
RC
vO (t2 ) = VL + 0.1(VH + VL ) = 0.2 + 0.23 = 0.43 V
t
0.43 = 0.2 (0.2 2.5) exp 2 t2 = RC ln 0.1
RC
t f = t2 t1 = RC ln 0.1+ RC ln 0.9 = RC ln 9 = 2.2RC

Page 343
t f = 3.7 2.37x103 2.5x1013 F = 2.19 ns | PHL = 1.2 2.37x103 2.5x1013 F = 0.711 ns
tr

(
)(
)
= 2.2(28.8x10 )(2.5x10 F ) = 15.8 ns

P =

13

| PLH

)(
)
= 0.69(28.8x10 )(2.5x10 F ) = 4.97 ns
3

13

0.711 ns + 4.97 ns
= 2.84 ns
2

Page 346

T = 2N P 0 = 2(401) 109 s = 802 ns | f =

1
1
=
= 1.25 MHz
T 802ns

R. C. Jaeger and T. N. Blalock


08/12/10

Page 347
For our Psuedo NMOS inverter with VL = 0.2 V ,

PHL = 1.2RonS C = 1.2

Cox" WL
L2
= 1.2
W
n (VGS VTN )
nCox"
VGS VTN )
(
L

PHL

(250x10 m) (100cm m) = 0.606 ps


= 1.2
(500cm V s)(3.3 0.825)V
(250x10 m) (100cm m) = 2.63 ps
L
= 1.2R C = 1.2
= 1.2
0.4 (V V )
(125cm V s)(3.1 0.825)V
2

PLH

onL

P =

GS

TN

0.606 ps + 2.63 ps
= 1.62 ps
2

Page 349

The PMOS transistor is saturated for vO = VL.


Pav =

2.5V (1.71mA)
2

I DD =

2
40x106 23.7

2.5 (0.6) = 1.71 mA


2 1 L

2
1
= 2.14 mW | PD = 5x1012 F (2.5V 0.2V )
= 13.2 mW
2x109 s

20 pF 2ns
We must increase the power by a factor of

= 8,
5 pF 1ns
so the W/L ratios must also be increased by a factor of 8.
W
23.7 190
W
47.4 379
2
1
| = 8
| PD = 20x1012 F (2.5V 0.2V ) 9 = 106 mW
= 8
=
=
1
L L
1 1
L S
1
10 s

R. C. Jaeger and T. N. Blalock


08/12/10

CHAPTER 7
Page 370

(a )

20
A
K p = 40x106 = 800 2
V
1

( b) V
(c) V

20
A
mA
| Kn = 100x106 = 2000 2 = 2.00 2
V
V
1

TN

= 0.6 + 0.5 2.5 + 0.6 0.6 = 1.09 V

TP

= 0.6 0.75 2.5 + 0.7 0.7 = 1.31 V

Page 372
(a ) For vI = 1 V , VGSN VTN = 1 0.6 = 0.4V and VGSP VTP = 1.5 + 0.6 = 0.9V
MN is saturated for vO 0.4 V. MP is in the triode region for vO 1.6 V. 1.6 V v O 2.5 V

(b) M
(c) M

is saturated for vO 1.6 V. 0.4 V v O 1.6 V

is in the triode region for vO 0.4 V. MP is saturated for v O 1.6 V. 0 v O 0.4 V

W
10 25
Kn W
=
= 2.5 =
L P K p L N
1 1

Page 373
Both transistors are saturated since VGS = VDS .
K
2
2
Kn
VGSN VTN ) = p (VGSP VTP )
(
2
2
VGSN = VGSP vI = VDD v I v I =

Kn = K p

VTN = VTP

VDD
2

10K p
2
K
2
VGSN VTN ) = p (VGSP VTP ) 10 (VGSN VTN ) = VGSP + VTP
(
2
2
10 (vI 0.6) = 4 v I 0.6 vI = 1.273 V
Kp
2
10K p
2
VGSN VTN ) =
VGSP VTP ) (VGSN VTN ) = 10 (VGSP + VTP )
(
(
2
2
vI 0.6 = 10 (4 v I 0.6) vI = 2.37 V

R. C. Jaeger and T. N. Blalock


08/12/10

Page 375
W
Kn
L N Kn
KR =
=
= 2.5
W
Kp
K p
L P
VIH =

2KR (VDD VTN + VTP )

VOL

(V

DD

KRVTN + VTP )

K 1
( K 1) 1+ 3K
2(2.5)(2.5 0.6 0.6) (2.5 2.5(0.6) 0.6)
=

= 1.22V
2.5
1
2.5
1
1+
3
2.5
(
)
( )
( K + 1)V V K V V = (2.5 + 1)1.22 2.5 2.5(0.6) + 0.6 = 0.174V
=
2K
2(2.5)
2 K (V V + V ) (V K V + V )
=

K 1
( K 1) K + 3
2 2.5 (2.5 0.6 0.6) (2.5 2.5(0.6) 0.6)
=

= 0.902V
2.5
1
2.5
1
2.5
+
3
(
)
( K + 1)V + V K V V = (2.5 + 1)0.902 + 2.5 2.5(0.6) + 0.6 = 2.38V
=
R

VIH

IH

DD

R TN

TP

VIL

DD

VIL
VOH

NM H = VOH

TN

TP

DD

DD

TP

IL

R TN

R TN

TP

2
2
VIH = 2.38 1.22 = 1.16 V | NM L = VIL VOL = 0.902 0.174 = 0.728 V

Page 376

Symmetrical Inverter : P = 1.2RonnC = 1.2

1012 F

( )

2 104 (2.5 0.6)

= 3.16 ns

Page 377

Symmetrical Inverter : Ronn =

P
109 s
=
= 167
1.2C 1.2 5x1012 F

W
1
1
31.5
=
=
=
'
4
1
L N Ronn Kn (VGS VTN ) 167 10 (2.5 0.6)

( )

W
W
78.8
= 2.5 =
1
L P
L N

10

R. C. Jaeger and T. N. Blalock


08/12/10

Page 379
The inverters need to be increased in size by a factor of
W
3.77 4.22
= 1.12
=
1
L N
1

280ps
= 1.12.
250ps

W
9.43 10.6
= 1.12
=
1
L P
1

W
3.77 3.3 0.75 3.43
=

=
1
L N 1 3.3 0.5

W 9.43 3.3 0.75 8.59


| =

=
1
L P 1 3.3 0.5

Page 380

PHL = 2.4RonnC =

2.4C
2.4C
C
=
= 1.26
Kn
Kn (VGS VTN ) Kn (2.5 0.6)

PLH = 2.4RonpC =

2.4C
2.4C
C
=
= 1.26
Kp
K p (VGS VTN ) K p (2.5 0.6)

PHL = 2.4RonnC =

2.4C
2.4C
C
=
= 0.94
Kn
Kn (VGS VTN ) Kn (3.3 0.75)

PLH = 2.4RonpC =

2.4C
2.4C
C
=
= 0.94
Kp
K p (VGS VTN ) K p (3.3 0.75)

Page 381
The inverter in Fig. 7.12 is a symmetrical design, so the maximum current occurs
2
VDD
10-4 2
for vO = v I =
. Both transistors are saturated : iDN =
(1.25 0.6) = 42.3 A
2
2 1
2
4x10-5 5
Checking : iDP =
(1.25 0.6) = 42.3 A
2 1
Page 382

10
CV 2
(a) PDP 5DD =

F (2.5V )

2
10
CVDD
b
PDP

=
()
5

F (3.3V )

2
10
CVDD
c
PDP

=
()
5

F (1.8V )

13

13

13

5
2

5
5

= 0.13 pJ = 130 fJ
= 0.22 pJ = 220 fJ

= 0.065 pJ = 65 fJ

11

R. C. Jaeger and T. N. Blalock


08/12/10

Page 388
Remove the NMOS and PMOS transistors connected to input E, and ground the source of
the NMOS transistor connected to input D. The are now 4 NMOS transistors in series, and
W
2 8
W
5
| =
= 4 =
L N
1 1
L P 1

Page 392
There are two NMOS transistors in series in the AB and CD NMOS paths, and three PMOS
transistors in the ACE and BDE PMOS paths. Therefore :
W
2 4
W
W
5 15
2
= 2 =
|
=
| = 3 =

L N ABCD
1 1
L N E 1
L P
1 1
Page 396
(a) The logic network for F = AB + C is

B
C
A

2
P = CVDD
f = 50x1012 F (5V ) 10 7 Hz = 12.5 mW

12

R. C. Jaeger and T. N. Blalock


08/12/10

Page 400
1

50 pF 2
=
= 31.6
50 fF

P = 31.6 o + 31.6 o = 63.2 o

z = e ln z

( )

| z ln z = e ln z

1
ln z

=e

50 pF 7
=
= 2.683
50 fF
1, 2.68 , 2.6832 = 7.20, 2.6833 = 19.3, 2.6834 = 51.8, 2.6835 = 139, 2.6836 = 373
A6 = (1+ 3.16 + 10 + 31.6 + 100 + 316) Ao = 462 Ao
A7 = (1+ 2.68 + 7.20 + 19.3 + 51.8 + 139 + 373) Ao = 594 Ao

Page 401
From the figure, 10/1 devices give a maximum Ron of 4 k. The W/L ratios must be 4 times
W 10 40
larger in order to reduce the maximum Ron to 1 k. = 4 =
L 1 1

13

R. C. Jaeger and T. N. Blalock


08/12/10

CHAPTER 8
Page 419

(a )

NS =

28 220
= 211 = 2048 segments |
2 7 210

( b)

NS =

230
= 211 = 2048 segments
29 210

Page 422
(a) N = 28 220 = 228 = 268,435,456

( b)

I DD =

0.05W
15.2mA
= 15.2 mA | Current/cell = 28
= 56.4 pA
3.3V
2 cells

Reverse the direction of the substrate arrows, and connect the substrates of the PMOS
transistors to VDD .

Page 426
MA1 : At t = 0 + , VGS VTN = 4 V and VDS = 2.5V , so transistor MA1 is operating in the triode region.
1
2.5
i1 = 60x106 5 1
2.5 = 413 A
2
1
MA2 : At t = 0 + , VGS = VDS , so transistor MA2 is operating in the saturation region.
2
60x106 1
VTN 2 = 1+ 0.6 2.5 + 0.6 0.6 = 1.592V
i2 =
(5 2.5 1.592) = 24.8 A
2 1

Page 428
MA1 : At t = 0 + , VGS = VDS , so transistor MA1 is operating in the saturation region.
2
60x106 1
i1 =
(5 1) = 480 A
2 1
MA2 : At t = 0 + , VGS = VDS , so transistor MA2 is operating in the saturation region.
2
60x106 1
i1 =
(5 1) = 480 A
2 1

14

R. C. Jaeger and T. N. Blalock


08/12/10

Page 431
(a ) At t = 0+ , VGS VTN = 3 - 0.7 = 2.3 V and VDS = 1.9 V , so transistor MA is operating in
the triode region.

1
1.9
i1 = 60x106 3 0 0.7 1.9 = 154 A
2
1

(b) From Table 6.10 :

t f = 3.7RonC = 3.7

50x1015 F
= 1.34 ns
60x106 (3 0.7)

VC = VBL VTN

)]

| VC = 3 0.7 + 0.5 VC + 0.6 0.6 VC = 1.89 V | VC = 3 0.7 = 2.3 V

n=

15
CV 25x10 F (1.89V )
=
= 2.95 x 105 electrons
19
q
1.60x10 C

Page 432

VC VBL 1.9 0.95


V VBL 0 0.95
=
V = 19.0 mV | V = C
=
V = 19.0 mV
CBL
49CC
CBL
49CC
+1
+1
+1
+1
CC
CC
CC
CC

(a )

V =

(b)

= Ron

CC
25 fF
= 5k
= 0.123 ns
CC
1
+1
+1
CBL
49

or

RonCC = 5k(25 fF ) = 0.125 ns

Page 434
At t = 0 + , VGS VTN = (3 - 0) - 0.7 = 2.3 V and VDS = 1.5 V , so transistor MA2 is operating in
the triode region.

2
1.5
iD = 60x106 3 0.7 1.5 = 279 A
2
1

15

R. C. Jaeger and T. N. Blalock


08/12/10

Page 436
In setting the drain currents equal, we see that the change in W/L cancels out, and
the voltages remain the same.
5
2
1
iD = 60x10-6 (1.33 0.7) = 59.5 A | PD = 2(59.5A)(3V ) = 0.357 mW
2
1
5
As a check, the current should scale with W/L : iD = (23.5A) = 58.8 A
2

2
2
2
2
1
1
Equating drain currents :
25x10-6 (2.5 VO 0.6) = 60x10-6 (VO 0.6)
2
2
1
1

1.4VO2 + 0.92VO 2.746 = 0 VO = 1.11V


2
2
1
iD = 25x10-6 (2.5 1.11 0.6) = 15.6 A | PD = 2(15.6A)(2.5V ) = 78.0 W
2
1
2
2
1
Checking :
60x10-6 (1.11 0.6) = 15.6 A
2
1

Page 488

Ron =

1
= 23.8 k | = 23.8k(25 fF ) = 0.595 ns
60x10 (3 1.3 1)
6

Page 440
For all possible input combinations there will be two inverters and 3 output lines in the low state.
PD = 5(0.2mW ) = 1.0 mW
Page 442
W
2 1.81 1.63
=

=
1
L L 2.22 1

16

R. C. Jaeger and T. N. Blalock


08/12/10

Page 444
For a 0 - V input, all transistors will be on and the input nodes will all discharge to 0 V.
For the 3 - V input, the nodes will all charge to 3 V as long as VTN 2 V.

VTN = 0.7 + 0.5 3 + 0.6 0.6 = 1.26 V. Thus the nodes will all be a 3 V.
2 0.7 +

3 + 0.6 0.6 1.158

The output will drop below VDD / 2. For the PMOS device, VGS VTP = 3 1.9 0.7 = 0.4V.
The PMOS transistor will be saturated. For the NMOS device, VGS VTP = 1.9 0.7 = 1.2V.
Assume linear region operation.

2
40x10-6 5
VO
-6 2
(1.1+ 0.7) = 100x10 1.9 0.7 VO
2 1
2
1
VO2 2.4VO + 0.16 = 0 VO = 68.6 mV

17

R. C. Jaeger and T. N. Blalock


08/12/10

CHAPTER 9
Page 462
0.2V
0.3V
0.4V
iC 2
iC 2
iC2
3
5
6
= exp
= exp
= exp
= 2.98 x 10 |
= 1.63 x 10 |
= 8.89 x 10
iC1
0.025V
i
0.025V
i
0.025V

C1
C1

Page 464
The current must be reduced by 5 while the voltages remain the same.
300A
I EE =
= 60 A | RC = 5(2k) = 10 k
5
Page 465
I
IB = E
F + 1

| IB3 =

92.9A
107A
= 4.42 A | I B 4 =
= 5.10 A
21
21

I B3 RC = 4.42A(2k) = 8.84 mV << 0.7 V | I B 4 RC = 5.10A(2k) = 10.2 mV << 0.7 V

Page 467
VH = 0 0.7 = 0.7 V | VL = 0 0.2mA(2k) 0.7V = 1.1 V
VREF =

0.7V + (1.10V )
2

= 0.9 V | V = -0.7V - (1.1V ) 0.4 V

Page 469

NM H = NM L =

0.4

0.4V
0.025V 1+ ln
1 = 0.107 V
2
0.025

18

R. C. Jaeger and T. N. Blalock


08/12/10

Page 471
P = 3.3V (0.3mA + 0.2mA) = 1.65 mW | P = 3.3V (0.357mA + 0.2mA) = 1.84 mW
NM H = NM L =

0.6

0.6V
0.025V 1+ ln
1 = 0.20 V
2
0.025

From the graph, the VTC slope is -1 for VIL = 1.08 V , VOH = 0.71 V and
VIH = 0.91 V , VOL = 1.28 V. NM H = 0.71 (0.91) = 0.20 V. NM L = 1.08 (1.28) = 0.20 V

The voltages remain the same. Thus the currents must be reduced by a factor of 3,
and the resistor values must be increase by a factor of 3.
--REE =

1.7V (5.2V )
0.20mA

= 17.5 k | I E =

1.4V (5.2V )
18 k

= 0.211 mA | RC1 =

0.4V
= 1.90 k
0.211mA

Page 472

For all inputs low : I EE =

1 0.7 (5.2) V
= 299A
11.7
k

V
= VH VREF = 0.7 (1) = 0.3 V | V = 0.6 V |
2
For an inputs high : I EE =

RC 2 =

0.6V
= 2.00 k
299A

0.7 0.7 (5.2) V


0.6V
= 325A | RC1 =
= 1.85 k
11.7
k
325A

Based upon analysis above, RC =

0.6V
= 1.85 k
325A

Page 473

For all inputs low : I EE =

1 0.7 (5.2) V
= 299A
11.7
k

V
= VH VREF = 0.7 (1) = 0.3 V | V = 0.6 V
2

RC =

0.6V
= 2.00 k
299A

Page 474
VE (VEE ) 0 0.7 (5.2V ) V
RE =
=
= 15.0 k
0.3mA
0.3
mA

19

R. C. Jaeger and T. N. Blalock


08/12/10

Page 475

(a )

For I E = 0, vO = 5.2 V. ( b) For I E = 0, vO = - 5.2V

10k
= 2.08 V
10k + 15k

Page 476
The transistor's power dissipation is

50
P = VCB IC + VBE I E = 5V 2.55mA + 0.7V (2.55mA) = 14.3 mW
51

The total power dissipation in the circuit is

50
P = VCC IC + VEE I E = 5V 2.55mA + 5V (2.55mA) = 25.3 mW
51

For vO = 3.7V , I E =

3.7 (5)
1300
0.7 (5)

3.7
= 260 A.
5000

0.7
= 3.17 mA
1300
5000
The transistor's power dissipation is

50
P = VCB IC + VBE I E = 5V 3.17mA + 0.7V (3.17mA) = 17.8 mW
51

--10k
(a ) 4V = 5.2V 10k + R RE = 3.00 k
E
At the Q - point, I E =

( b)

IE =

4 (5.2)
4 (5.2)
5.2V
4
4
= 1.73 mA | I E =

= 0 | IE =
+
= 3.47 mA
3k
3000
10000
3000
10000

Page 478
Increase the value of each resistor by a factor of 10.

Page 481
V
0.6V
RC =
=
= 1.2 k | P = 0.69(1.2k)(2 pF ) = 1.66 ns
I EE 0.5mA
P = 5.2V (0.5 + 0.1+ 0.1)mA = 3.64 mW | PDP = 6.0 pJ

20

R. C. Jaeger and T. N. Blalock


08/12/10

Page 483
RC2 = RC1 =

0 VL
0.4V
=
= 800 | P = I EEVEE = 0.5mA(2.8V ) = 1.40 mW
I EE
0.5mA

PDP = 1.4mW (50 ps) = 70 fJ

I EF =

I EE
= 250 A | P = I EEVEE = 0.25mA(2.8V ) = 0.70 mW
2

VH = 0 | VL = 0.2 V | VBias = 0.1 V | VBH = 0.7 | VBL = 0.9 V | VBiasB = 0.8 V


VAH = 1.4 | VAL = 1.6 V | VBiasA = 1.5 V
VEE = VAH 0.7V 0.7V = 1.4 0.7 0.7 = 2.8 V | VEE = 2.8 V

VH = 0 V , VL = 0.4 V , : The C - level bias is VBiasC =

VH + VL
= 0.2 V
2

Using the level shifter in Fig. 9.27,


VBH = 0.7 | VBL = 1.1 V | VBiasB = 0.9 V
VAH = 1.4 | VAL = 1.8 V | VBiasA = 1.6 V
VEE = VemitterA 0.7V = 0.7 = 2.8 V | VEE = 2.8 V

Page 488
For vO = VH , IC = 0, and P = 0.

P = VDD I DD = 5V (2.43mA) = 12.1 mA

Increase R by a factor of 10 : R = 10(2k) = 20k.


Page 490

0.1
= exp
= 48.2
0.0258

20
1+

10 A 0.1(48.2)
10 A
| IB
= 3.34 A | FOR =
= 3.00
11
20
3.34 A
1

48.2

R =

0.2
1
=
0.2 + 1 6

20
1+

10 A 0.2(54.6)
| IB
= 1.59 A

6
20
1

54.6

Page 491

21

R. C. Jaeger and T. N. Blalock


08/12/10


20
1+

0.15
10 A 0.1(403)
= exp
= 0.769 A
= 403 | I B
11
20
0.025
1

403

VT =

1.38x1023 (273 + 150)


1.60x1019

0.05 + 1
= 36.5 mV | VCEMIN = 36.5mV ln
= 111 mV
0.05

0.1
0.25
1
= exp
=
= 54.6 | R =
1+ 0.25 5
0.025

40
1+

10mA 0.25(54.6)
10mA
IB
= 1.08 mA | FOR =
= 9.24

5
40
1.08mA
1

54.6

22

R. C. Jaeger and T. N. Blalock


08/12/10

Page 494

1mA I

1mA I BR
BR
1ns = 6.4ns ln
I BR = 5.49 mA
| 1.169 =
2.5mA
0.0614mA

I
BR

I BR
40.7

V V
50
2.5mA
iCMAX = CC CE
= 2.5mA | QXS = 6.4ns1mA
= 6.01 pC
F
2500
40.7

QF = iF F = 2.5mA(0.25ns) = 0.625 pC | QXS >> QF

Page 495

5 0.95
= 1.01 mA | VBE2 = VL + VCESAT1
4000
Using the value of VCESAT in Fig. 9.32, VBE2 = 0.15 + 0.04 = 0.19 V
2 + 1
A better estimate is VCESAT1 = 25mV ln
= 10.1 mV
2
VBE2 = 0.15 + 0.010 = 0.16 V
For vI = VL = 0.15 V :

iIL =

Page 496

For vI = VH = 5 V :

5 1.5
= 1.75 mA | VBE2 = 0.8 V
4000
2
0.875mA + 1 (2.4mA)
3
= 0.025V ln
= 0.729 V
1 2
15
10 A + 1
40 3

iIH = 2

Using Eq. (5.29), VBESAT

Page 499

5 1.5
= 0.875mA
4000
3.5V
| R
= 0.2
10(2k)(0.875mA)

5V - N (2k) R I B 1.5V | I B =

3.5V
= 0.4
5(2k)(0.875mA)

Page 500

I B2 = (2 + 1)

5 1.5
= 2.63 mA |
4000

2.43mA + N (1.01mA) 28.3(2.63mA) N 71

23

R. C. Jaeger and T. N. Blalock


08/12/10

Page 501
vI = VL and vO = 0 : I B 4 =

5 VB 4 5 (0 + 0.7 + 0.7)
=
= 2.25 mA | I L = 41I B 4 = 92.3 mA
1600
1600

IL
0.7 0.7 3 I L 15.4 mA
41
5 (3 + 0.7 + 0.7)
IB4 =
= 0.375 mA | I L = 41I B 4 = 15.4 mA
1600
VCE = 5 130IC VO = 5V 130(15.4mA) 3.7 = 0.702 V
5 1600

Oops! - the transistor is not in the forward - active region. Assume saturation with VCESAT = 0.15V.
I L = I B + IC =

5 (0.8 + 0.7 + 3.0)


1600

5 (0.15 + 0.7 + 3)
130

= 9.16 mA

Page 513
(a ) BiCMOS NAND gate : Replace the CMOS NOR - gate with a two - input CMOS
NAND - gate, and connect its output to the bases of Q3 and Q 4.

(b)

BiNMOS NAND gate : Replace the input CMOS NOR - gate with a two - input CMOS

NAND - gate, and connect M6 and M 7 in series instead of parallel.

24

R. C. Jaeger and T. N. Blalock


08/12/10