library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity half_add_subtractor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC;
d : out STD_LOGIC;
bo : out STD_LOGIC);
end half_add_subtractor;

architecture Behavioral of half_add_subtractor is

begin
s <= a xor b ;

c <= a and b;
d <= a xor b;
bo <= (not a ) and b ;

end Behavioral;