VLSI Design

Circuits & Layout

1: Circuits & Layout

EE 447 VLSI Design

Slide 1

Outline

CMOS Gate Design

Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams

1: Circuits & Layout

EE 447 VLSI Design

Slide 2

CMOS Gate Design

A 4-input CMOS NOR gate

A
B
C
D

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EE 447 VLSI Design

Slide 3

Complementary CMOS
Complementary CMOS logic gates
nMOS pull-down network
pMOS pull-up network
inputs
a.k.a. static CMOS
Pull-up OFF

Pull-up ON

Pull-down OFF

Z (float)

Pull-down ON

X (crowbar)

1: Circuits & Layout

EE 447 VLSI Design

pMOS
pull-up
network

output
nMOS
pull-down
network

Slide 4

Series and Parallel

nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON

a
g1
g2

OFF

OFF

OFF

ON

g2

(b)

a
g2

(c)

g2
b

1: Circuits & Layout

EE 447 VLSI Design

ON

OFF

OFF

OFF

OFF

ON

ON

ON

a
g1

(d)

0
b

g1

a
g1

b
(a)

ON

ON

ON

OFF

Slide 5

Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Y
Requires parallel pMOS
A
B

Rule of Conduction Complements

Pull-up network is complement of pull-down
Parallel -> series, series -> parallel

1: Circuits & Layout

EE 447 VLSI Design

Slide 6

Compound Gates
Compound gates can do any inverting function
Ex: Y AgB C gD (AND-AND-OR-INVERT, AOI22)
A

(a)

(b)

B C

(c)

(d)

A
B
C
D

(f)

(e)

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EE 447 VLSI Design

Slide 7

Example: O3AI
Y A B C gD

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EE 447 VLSI Design

Slide 8

Example: O3AI
Y A B C gD

A
B
C

D
D

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EE 447 VLSI Design

Slide 9

Pass Transistors
Transistors can be used as switches
g
s

g
s

1: Circuits & Layout

EE 447 VLSI Design

Slide 10

Pass Transistors
Transistors can be used as switches
g=0

g
s

d
g=1

d
g=0

g
s

1
Input

d
g=1

1: Circuits & Layout

Input g = 1 Output
0
strong 0

EE 447 VLSI Design

g=1

g=0
g=0

degraded 1
Output
degraded 0
strong 1

Slide 11

Signal Strength
Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus NMOS are best for pull-down network
Thus PMOS are best for pull-up network

1: Circuits & Layout

EE 447 VLSI Design

Slide 12

Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well

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EE 447 VLSI Design

Slide 13

Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input
g
a

b
gb

g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1, gb = 0
a
b

g = 1, gb = 0
strong 1
1

g
b
gb
1: Circuits & Layout

g
b

gb

Output

b
gb

EE 447 VLSI Design

Slide 14

Tristates
Tristate buffer produces Z when not enabled
EN

EN
Y

A
EN

A
EN

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EE 447 VLSI Design

Slide 15

Nonrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y (after several stages, the
noise may degrade the signal beyond recognition)

EN
A

Y
EN

1: Circuits & Layout

EE 447 VLSI Design

Slide 16

Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A
EN

EN

1: Circuits & Layout

EE 447 VLSI Design

Slide 17

Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A

A
EN

EN = 0
Y = 'Z'

EN = 1
Y=A

EN

1: Circuits & Layout

EE 447 VLSI Design

Slide 18

Multiplexers
2:1 multiplexer chooses between two inputs

D1

D0

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EE 447 VLSI Design

D0

D1

Slide 19

Multiplexers
2:1 multiplexer chooses between two inputs

D1

D0

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EE 447 VLSI Design

S
D0

D1

Slide 20

Gate-Level Mux Design

Y SD1 SD0 (too many transistors)
How many transistors are needed?

1: Circuits & Layout

EE 447 VLSI Design

Slide 21

Gate-Level Mux Design

Y SD1 SD0 (too many transistors)
How many transistors are needed? 20

D1
S
D0

D1
S
D0
1: Circuits & Layout

2
4

EE 447 VLSI Design

Slide 22

Transmission Gate Mux

Nonrestoring mux uses two transmission gates

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EE 447 VLSI Design

Slide 23

Transmission Gate Mux

Nonrestoring mux uses two transmission gates
Only 4 transistors

S
D0
S

D1
S
1: Circuits & Layout

EE 447 VLSI Design

Slide 24

Inverting Mux
Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
D0
S
S

1: Circuits & Layout

S
D1
S

D0

D1

EE 447 VLSI Design

S
Y

D0

D1

Slide 25

4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects

1: Circuits & Layout

EE 447 VLSI Design

Slide 26

4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
Or four tristates
D0
S0
D0

D1

D2

D3

S1
D1
0
1

Y
D2

D3

1: Circuits & Layout

EE 447 VLSI Design

Slide 27

D Latch
When CLK = 1, latch is transparent
Q follows D (a buffer with a Delay)
When CLK = 0, the latch is opaque
Q holds its last value independent of D
a.k.a. transparent latch or level-sensitive latch

Latch

CLK

1: Circuits & Layout

CLK
D

Q
Q

EE 447 VLSI Design

Slide 28

D Latch Design
Multiplexer chooses D or old Q
CLK
D

1
0

CLK

Q
Q

Q
CLK

CLK

CLK

1: Circuits & Layout

EE 447 VLSI Design

Slide 29

D Latch Operation
Q
D
CLK = 1

Q
D

CLK = 0

CLK
D
Q
1: Circuits & Layout

EE 447 VLSI Design

Slide 30

D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
CLK

CLK
D

Flop

1: Circuits & Layout

EE 447 VLSI Design

Slide 31

D Flip-flop Design
Built from master and slave D latches
CLK

CLK
CLK

CLK
QM

Latch

Latch

CLK
D

QM

D
CLK

CLK

CLK

Q
CLK
A negative level-sensitive latch

1: Circuits & Layout

EE 447 VLSI Design

CLK
A positive level-sensitive latch

Slide 32

D Flip-flop Operation
Inverted version of D

QM

CLK = 0
Hold the last value of NOT D

QM

Inverts NOT(QM) and holds it.

CLK = 1

CLK
D
Q

1: Circuits & Layout

EE 447 VLSI Design

Slide 33

Race Condition
Back-to-back flops can malfunction from clock skew
Second flip-flop fires Early
Sees first flip-flop change and captures its result
Called hold-time failure or race condition
CLK1
CLK2
Q1

1: Circuits & Layout

Flop

Flop

CLK1

CLK2
Q2

Q1
Q2

EE 447 VLSI Design

Slide 34

Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
Industry manages skew more carefully instead
2

1
QM

D
2

Q
1

1
2

1: Circuits & Layout

EE 447 VLSI Design

Slide 35

Gate Layout
Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts

1: Circuits & Layout

EE 447 VLSI Design

Slide 36

Example: Inverter

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EE 447 VLSI Design

Slide 37

Inverter, contd..

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EE 447 VLSI Design

Slide 38

Example: NAND3

Horizontal N-diffusion and p-diffusion strips

Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 by 40

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EE 447 VLSI Design

Slide 39

NAND3, contd.

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EE 447 VLSI Design

Slide 40

Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers

1: Circuits & Layout

EE 447 VLSI Design

Slide 41

Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
VDD

Vin

Vout

GND

1: Circuits & Layout

EE 447 VLSI Design

Slide 42

Wiring Tracks
A wiring track is the space required for a wire
4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track

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EE 447 VLSI Design

Slide 43

Well spacing
Wells must surround transistors by 6
Implies 12 between opposite transistor flavors
Leaves room for one wire track

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EE 447 VLSI Design

Slide 44

Area Estimation
Estimate area by counting wiring tracks
Multiply by 8 to express in

1: Circuits & Layout

EE 447 VLSI Design

Slide 45

Example: O3AI
Sketch a stick diagram for O3AI and estimate area
Y A B C gD

1: Circuits & Layout

EE 447 VLSI Design

Slide 46

Example: O3AI
Sketch a stick diagram for O3AI and estimate area
Y A B C gD

1: Circuits & Layout

EE 447 VLSI Design

Slide 47

Example: O3AI
Sketch a stick diagram for O3AI and estimate area
Y A B C gD

1: Circuits & Layout

EE 447 VLSI Design

Slide 48